Chip packaging structure and manufacturing method thereof

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a plurality of circuit layers and at least one chip. The multi-layer circuit layer has a first surface and a second surface opposite to each other, and comprises a high-density circuit layer, a medium-density circuit layer and a low-density circuit layer. The high-density circuit layer has a first surface. The medium-density circuit layer is located between the high-density circuit layer and the low-density circuit layer. The low-density circuit layer has a second surface. The high-density circuit layer has a first line width, the medium-density circuit layer has a second line width, and the low-density circuit layer has a third line width. The first line width is smaller than the second line width, and the second line width is smaller than the third line width. The chip is arranged on the first surface of the high-density circuit layer and is electrically connected with the multi-layer circuit layer. According to the chip packaging structure and the manufacturing method thereof provided by the invention, assembly is not needed, and working hours and material cost can be effectively saved.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and more particularly to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] In the existing chip packaging structure, the chip is electrically connected to the fine lines on the packaging substrate. For the packaging substrate, usually the fine lines and the thick lines are separately manufactured first, and then the fine lines and the thick lines are structurally and electrically connected by means of solder balls. In this way, due to the need to assemble the fine lines and the thick lines, the manufacturing man-hours cannot be further shortened, and since additional solder balls are required to connect the fine lines and the thick lines, in addition to increasing the material cost, it will also additionally occupy the vertical space of the overall packaging structure, thereby resulting in yield and performance losses. Summary of the Invention

[0003] The present invention is directed to a chip packaging structure and a manufacturing method thereof, which do not require assembly and can effectively save man-hours and material costs.

[0004] According to an embodiment of the present invention, a chip packaging structure includes a multi-layer wiring layer and at least one chip. The multi-layer wiring layer has a first surface and a second surface opposite to each other, and includes a high-density wiring layer, a medium-density wiring layer, and a low-density wiring layer. The high-density wiring layer has a first surface. The medium-density wiring layer is located between the high-density wiring layer and the low-density wiring layer. The low-density wiring layer has a second surface. The high-density wiring layer has a first line width, the medium-density wiring layer has a second line width, and the low-density wiring layer has a third line width. The first line width is less than the second line width, and the second line width is less than the third line width. The chip is disposed on the first surface of the high-density wiring layer and is electrically connected to the multi-layer wiring layer.

[0005] In the chip packaging structure according to an embodiment of the present invention, the above chip packaging structure further includes a multi-layer power board disposed on the second surface of the multi-layer wiring layer of the second structure layer having a high coefficient of thermal expansion. The multi-layer power board is a wireless substrate and is composed of thick copper and an insulating material with a high thickness and an extremely low coefficient of thermal expansion, and the multi-layer power board has a plurality of vias. The vias are electrically connected to the multi-layer wiring layer to achieve power transmission. This third-layer structure, corresponding to the first layer structure of the chip with the same low coefficient of thermal expansion, results in a stable balance effect still being maintained during temperature difference changes. The first peripheral surface of the multi-layer wiring layer is flush with the second peripheral surface of the multi-layer power board.

[0006] In the chip packaging structure according to an embodiment of the present invention, the above chip packaging structure further includes a support board disposed on the first surface of the multi-layer wiring layer. The support board has at least one opening, and the chip is disposed within the opening.

[0007] In the chip packaging structure according to an embodiment of the present invention, the material of the above-mentioned support plate includes copper, stainless steel or alloy.

[0008] In the chip packaging structure according to an embodiment of the present invention, the number of layers of the above-mentioned high-density circuit layer is between 2 and 10, and the line width and line pitch of the high-density circuit layer are between 2 μm and 4 μm.

[0009] In the chip packaging structure according to an embodiment of the present invention, the number of layers of the above-mentioned medium-density circuit layer is between 2 and 15, and the line width and line pitch of the medium-density circuit layer are between 5 μm and 10 μm.

[0010] In the chip packaging structure according to an embodiment of the present invention, the number of layers of the above-mentioned low-density circuit layer is between 0 and 20, and the line width of the low-density circuit layer is between 10 μm and 20 μm.

[0011] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. Form a multi-layer circuit layer on a substrate. The multi-layer circuit layer has a first surface and a second surface opposite to each other, and includes a high-density circuit layer, a medium-density circuit layer, and a low-density circuit layer. The high-density circuit layer has a first surface. The medium-density circuit layer is located between the high-density circuit layer and the low-density circuit layer. The low-density circuit layer has a second surface. The high-density circuit layer has a first line width, the medium-density circuit layer has a second line width, and the low-density circuit layer has a third line width. The first line width is less than the second line width, and the second line width is less than the third line width. The first surface of the multi-layer circuit layer is disposed on the substrate. Remove the substrate to expose the first surface of the multi-layer circuit layer. Dispose at least one chip on the first surface of the high-density circuit layer. The chip is electrically connected to the multi-layer circuit layer.

[0012] In the method for manufacturing a chip packaging structure according to an embodiment of the present invention, the method for manufacturing the chip packaging structure further includes forming a multi-layer power board on the second surface of the multi-layer circuit layer of the second structure layer having a high coefficient of thermal expansion before removing the substrate to expose the first surface of the multi-layer circuit layer. The multi-layer power board is a wireless substrate and is composed of thick copper and an insulating material with a high thickness and an extremely low coefficient of thermal expansion, and the multi-layer power board has a plurality of vias. The vias are electrically connected to the multi-layer circuit layer to achieve power transmission. This third-layer structure, corresponding to the first-layer structure of the chip with the same low coefficient of thermal expansion, achieves a stable balance effect under temperature difference changes. The first peripheral surface of the multi-layer circuit layer is flush with the second peripheral surface of the multi-layer power board.

[0013] In the method for manufacturing a chip packaging structure according to an embodiment of the present invention, the method for manufacturing the chip packaging structure further includes disposing a support plate on the first surface of the multi-layer circuit layer before disposing at least one chip on the first surface of the high-density circuit layer. The support plate has at least one opening, and the chip is disposed within the opening.

[0014] Based on the above, in the chip packaging structure of the present invention, a multi-layer circuit layer with multiple line widths is used to replace the fine lines and thick lines assembled with solder balls in the prior art. Thus, there is no need for assembly, and labor hours and material costs can be effectively saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1A to 1C is a schematic cross-sectional view of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0016] Figures 2A to 2B is a schematic cross-sectional view of partial steps of a method for manufacturing a chip packaging structure according to another embodiment of the present invention;

[0017] Figures 3A to 3B is a schematic cross-sectional view of partial steps of a method for manufacturing a chip packaging structure according to another embodiment of the present invention.

[0018] DESCRIPTION OF THE REFERENCE NUMERALS

[0019] 10: Substrate;

[0020] 100a, 100b, 100c: Chip packaging structure;

[0021] 110: Multi-layer circuit layer;

[0022] 111: First surface;

[0023] 112: High-density circuit layer;

[0024] 112a, 114a, 116a: Dielectric layer;

[0025] 112b, 114b, 116b: Patterned circuit layer;

[0026] 112c, 114c, 116c: Conductive blind via;

[0027] 113: Second surface;

[0028] 114: Medium-density circuit layer;

[0029] 116: Low-density circuit layer;

[0030] 117: Pad;

[0031] 120, 125: Chip;

[0032] 122, 127: Chip pad;

[0033] 130, 160: Solder mask;

[0034] 132, 162: Solder mask opening;

[0035] 140, 145: Solder balls;

[0036] 150: Multi-layer power supply board;

[0037] 152: Dielectric layer;

[0038] 155: Via hole;

[0039] 170: Support board;

[0040] 172: Opening;

[0041] L: Straight line;

[0042] P: Pad;

[0043] P’: Via hole pad;

[0044] S1: First peripheral surface;

[0045] S2: Second peripheral surface;

[0046] W1: First line width;

[0047] W2: Second line width;

[0048] W3: Third line width. Detailed implementation mode

[0049] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0050] Embodiments of the present invention can be understood in conjunction with the accompanying drawings, and the accompanying drawings of the present invention are also regarded as a part of the open description. It should be understood that the drawings of the present invention are not drawn to scale. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0051] Figures 1A to 1C is a cross-sectional schematic view of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Regarding the method for manufacturing the chip packaging structure of this embodiment, first, please refer to Figure 1A, a multi-layer wiring layer 110 is formed on a substrate 10. The multi-layer wiring layer 110 has a first surface 111 and a second surface 113 opposite to each other, and includes a high-density wiring layer 112, a medium-density wiring layer 114, and a low-density wiring layer 116. The high-density wiring layer 112 has the first surface 111. The medium-density wiring layer 114 is located between the high-density wiring layer 112 and the low-density wiring layer 116. The low-density wiring layer 116 has the second surface 113. The high-density wiring layer 112 has a first line width W1, the medium-density wiring layer 114 has a second line width W2, and the low-density wiring layer 116 has a third line width W3. The first line width W1 is less than the second line width W2, and the second line width W2 is less than the third line width W3. The first surface 111 of the multi-layer wiring layer 110 is disposed on the substrate 10.

[0052] In one embodiment, the substrate 10 is, for example, a glass substrate, a prepreg (PP) substrate, a stainless steel substrate, or other smooth substrates with support, but not limited thereto. In one embodiment, the number of layers of the high-density wiring layer 112 is, for example, between 2 and 10 layers, and the line width and line pitch of the high-density wiring layer 112 are, for example, between 2 microns and 4 microns. Further, the high-density wiring layer 112 may include multiple dielectric layers 112a, multiple patterned wiring layers 112b, and a plurality of conductive blind vias 112c. The dielectric layers 112a and the patterned wiring layers 112b are alternately arranged, and the conductive blind vias 112c electrically connect two adjacent patterned wiring layers 112b. In one embodiment, the material of the dielectric layer 112a is, for example, polyimide (PI), Ajinomoto build-up film (ABF), or benzocyclobutene (BCB), but not limited thereto. The materials of the patterned wiring layer 112b and the conductive blind via 112c may be, for example, copper, but not limited thereto.

[0053] In one embodiment, the number of layers of the medium-density wiring layer 114 is, for example, between 2 and 15 layers, and the line width and line pitch of the medium-density wiring layer 114 are, for example, between 5 microns and 10 microns. Further, the medium-density wiring layer 114 may include multiple dielectric layers 114a, multiple patterned wiring layers 114b, and a plurality of conductive blind vias 114c. The dielectric layers 114a and the patterned wiring layers 114b are alternately arranged, and the conductive blind vias 114c electrically connect two adjacent patterned wiring layers 114b. In one embodiment, the material of the dielectric layer 114a is, for example, polyimide (PI), Ajinomoto build-up film (ABF), or prepreg (PP), but not limited thereto. The materials of the patterned wiring layer 114b and the conductive blind via 114c may be, for example, copper, but not limited thereto.

[0054] In one embodiment, the number of layers of the low-density circuit layer 116 is, for example, between 0 and 20 layers, and the line width of the low-density circuit layer 116 is, for example, between 10 micrometers and 20 micrometers. Further, the low-density circuit layer 116 may include multiple dielectric layers 116a, multiple patterned circuit layers 116b, and multiple conductive blind vias 116c. The dielectric layers 116a and the patterned circuit layers 116b are arranged in an interleaved manner, and the conductive blind vias 116c are electrically connected to two adjacent patterned circuit layers 116b. In one embodiment, when the low-density circuit layer 116 is not required, the number of its layers can be 0. In one embodiment, the material of the dielectric layer 116a is, for example, polyimide (PI), Ajinomoto build-up film (ABF), or a prepreg (PP) of a material with a low coefficient of thermal expansion, but not limited thereto. The materials of the patterned circuit layer 116b and the conductive blind vias 116c can be, for example, copper, but not limited thereto.

[0055] In manufacturing, the high-density circuit layer 112 in the multi-layer circuit layer 110 can be formed on a smooth mirror surface plate by coating or lamination. Then, the medium-density circuit layer 114 and the low-density circuit layer 116 can be sequentially formed on the high-density circuit layer 112 by, for example, lamination, thereby completing the manufacturing of the multi-layer circuit layer 110. After that, the multi-layer circuit layer 110 can be transferred to a support substrate. It is easier to start manufacturing from the high-density circuit layer 112, and the high-density circuit layer 112 is required for the application after transfer.

[0056] In short, the multi-layer circuit layer 110 of this embodiment is composed of circuit structure layers with various different densities, line widths, and line spacings, and the circuit layers with different densities are in direct contact with each other without passing through solder balls, so no assembly is required, and labor hours and material costs can be effectively saved.

[0057] Next, please refer to Figure 1B , a solder mask layer 130 is formed on the multi-layer circuit layer 110, wherein the solder mask layer 130 has multiple solder mask openings 132, and the solder mask openings 132 expose the patterned circuit layers 116b of a part of the low-density circuit layer 116, thereby defining multiple pads P.

[0058] Next, please refer to Figure 1B and Figure 1C simultaneously, the substrate 10 is removed to expose the first surface 111 of the multi-layer circuit layer 110.

[0059] Finally, please refer to Figure 1C, at least one chip (two chips 120 are schematically shown) is arranged on the first surface 111 of the high-density circuit layer 112, wherein the chip pad 122 of the chip 120 is electrically connected to the multi-layer circuit layer 110 through the solder ball 140. In one embodiment, the chip 120 may be, for example, a single chip or a multi-chip, wherein the chip 120 is electrically connected to the multi-layer circuit layer 110 in a flip chip manner. In addition, in order to electrically connect to an external circuit, a solder ball 145 may be formed on the pad P, wherein the pad P may be electrically connected to the external circuit through the solder ball 145. At this point, the manufacture of the chip package structure 100a has been completed.

[0060] In terms of structure, please refer to Figure 1C , the chip packaging structure 100a includes a multi-layer circuit layer 110 and a chip 120. The multi-layer circuit layer 110 has a first surface 111 and a second surface 113 opposite to each other, and includes a high-density circuit layer 112, a medium-density circuit layer 114 and a low-density circuit layer 116. The high-density circuit layer 112 has a first surface 111. The medium-density circuit layer 114 is located between the high-density circuit layer 112 and the low-density circuit layer 116. The low-density circuit layer 116 has a second surface 113. The high-density circuit layer 112 has a first line width W1, the medium-density circuit layer 114 has a second line width W2, and the low-density circuit layer 116 has a third line width W3. The first line width W1 is smaller than the second line width W2, and the second line width W2 is smaller than the third line width W3. The chip 120 is disposed on the first surface 111 of the high-density circuit layer 112, and is electrically connected to the multi-layer circuit layer 110.

[0061] In short, the chip package structure 100a of the present embodiment replaces the thin and thick lines assembled by solder balls in the prior art with a multi-layer circuit layer 110 with various line widths, thereby eliminating the need for assembly and effectively saving labor hours and material costs. In addition, since there is no need for assembly by solder balls, the vertical space of the overall package structure can also be saved, which can effectively improve the yield and performance.

[0062] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0063] Figures 2A to 2B is a cross-sectional schematic diagram of a partial step of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Figure 1B as well as Figure 2A The manufacturing method of the chip packaging structure of this embodiment is similar to the manufacturing method of the chip packaging structure described above, but the main difference between the two is that: in this embodiment, Figure 1BBefore the step of forming the solder mask layer 130 on the multilayer circuit layer 110, a multilayer power board 150 is formed on the second surface 113 of the multilayer circuit layer 110 of the second structural layer having a high coefficient of thermal expansion. For example, after filling the through-hole portion of a bonding film with conductive paste after laser perforation, the multilayer power board 150 is attached to the multilayer circuit layer 110 by thermal pressing and docked with the corresponding pads 117 on the multilayer circuit layer 110. The multilayer power board 150 includes a copper layer and a multilayer dielectric layer 152 and has a plurality of vias 155. The vias 155 are electrically connected to the multilayer circuit layer 110 to achieve power transmission. This third-layer structure, corresponding to the first chip layer structure with the same low coefficient of thermal expansion, achieves a stable balance effect during temperature difference changes. That is to say, the multilayer power board 150 of this embodiment does not have a circuit structure, only the vias 155 for transmitting electricity and telecommunications.

[0064] Furthermore, in this embodiment, the vias 155 of the multilayer power board 150 are disposed within the dielectric layer 152 and are electrically connected to each other. In one embodiment, the vias 155 of the multilayer power board 150 may be disposed within the dielectric layer 152 along a straight line L, but this is not limiting. In one embodiment, the material of the dielectric layer 152 is, for example, a prepreg (PP) or other material with a low coefficient of thermal expansion (CTE). Herein, the low coefficient of thermal expansion is, for example, a coefficient of thermal expansion between 1 ppm / K and 3 ppm / K, but this is not limiting. The material of the vias 155 is, for example, copper, but this is not limiting. Preferably, the first peripheral surface S1 of the multilayer circuit layer 110 is flush with the second peripheral surface S2 of the multilayer power board 150. That is to say, the size of the multilayer power board 150 of this embodiment is the same as the size of the multilayer circuit layer 110. Herein, the size may include length, width, and / or area. In one embodiment, the multilayer circuit layer 110 and the multilayer power board 150 can be regarded as coreless substrates.

[0065] Next, please refer to Figure 2A again, a solder mask layer 160 is formed on the multilayer power board 150. The solder mask layer 160 has a plurality of solder mask openings 162, and the solder mask openings 162 expose some of the vias 155 and define a plurality of via pads P'.

[0066] Next, please refer to Figure 2A and Figure 2B simultaneously, the substrate 10 is removed and the structure is turned upside down to expose the first surface 111 of the multilayer circuit layer 110.

[0067] Finally, please refer to Figure 2B, at least one chip 120 (two chips 120 are schematically shown) is disposed on the first surface 111 of the multi-layer circuit layer 110, wherein the chip pad 122 of the chip 120 is electrically connected to the multi-layer circuit layer 110 through the solder ball 140. In one embodiment, the chip 120 may be, for example, a single chip or a multi-chip, wherein the chip 120 is electrically connected to the multi-layer circuit layer 110 in a flip chip manner. In addition, in order to electrically connect to an external circuit, a solder ball 145 may be formed on the via pad P', wherein the via pad P' may be electrically connected to the external circuit through the solder ball 155. At this point, the manufacture of the chip package structure 100b has been completed.

[0068] Since the chip package structure 100b of the present embodiment has a multi-layer power board 100b, wherein the multi-layer power board 120 can transmit telecommunications and power through the vias 125, and can also effectively balance the stress generated after the chip 130 is arranged on the multi-layer circuit layer 110 because it selects a material with a low thermal expansion coefficient. In other words, the present embodiment uses the multi-layer power board 120 with the same size as the multi-layer circuit layer 110 to stress balance the board warping phenomenon generated after the chip 130 is arranged on the multi-layer circuit layer 110. In short, the chip package structure 100b of the present embodiment can effectively reduce the board warping and increase the structural reliability through the arrangement of the multi-layer power board 120.

[0069] Figures 3A to 3B is a cross-sectional schematic diagram of a partial step of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Figure 2A as well as Figure 3A The manufacturing method of the chip packaging structure of this embodiment is similar to the manufacturing method of the chip packaging structure described above, but the main difference between the two is that: in this embodiment, Figure 2A After the step of removing the substrate 10 and flipping the structure upside down to expose the first surface 111 of the multi-layer circuit layer 110, a support plate 170 is disposed on the first surface 111 of the multi-layer circuit layer 110. The support plate 170 has a plurality of openings 172, and the chips 125 are respectively disposed in the openings 172. In one embodiment, the material of the support plate 170 is, for example, copper, stainless steel or alloy, but is not limited thereto.

[0070] Afterwards, please refer to Figure 3B, a plurality of chips 125 are disposed on the first surface 111 of the high-density circuit layer 112 of the multi-layer circuit layer 110, wherein the chips 125 are respectively disposed in the openings 172 of the support plate 170, and the chip pads 127 of the chips 125 are electrically connected to the multi-layer circuit layer 110 through solder balls 140. That is to say, the chips 125 and the support plate 170 are disposed on the same side and the same surface (i.e., the first surface 111) of the multi-layer circuit layer 110. Preferably, the orthographic projection area of the chips 125 on the multi-layer circuit layer 110 plus the orthographic projection area of the support plate 170 on the multi-layer circuit layer 110 is at least greater than 90% of the area of the multi-layer circuit layer 110, which means that the area of the support plate 170 can make up for the insufficient area of the chips 125, thereby effectively reducing board warping and increasing structural reliability. Thus, the fabrication of the chip packaging structure 100c is completed.

[0071] In summary, in the chip packaging structure of the present invention, a multi-layer circuit layer with multiple line widths is used to replace the fine lines and thick lines assembled by solder balls in the prior art, thereby eliminating the need for assembly and effectively saving man-hours and material costs.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that, Comprising: A multi-layer circuit layer having a first surface and a second surface opposite to each other, and including a high-density circuit layer, a medium-density circuit layer, and a low-density circuit layer. The high-density circuit layer has the first surface, the medium-density circuit layer is located between the high-density circuit layer and the low-density circuit layer, and the low-density circuit layer has the second surface. Wherein the high-density circuit layer has a first line width, the medium-density circuit layer has a second line width, the low-density circuit layer has a third line width, and the first line width is less than the second line width, and the second line width is less than the third line width; and At least one chip configured on the first surface of the high-density circuit layer and electrically connected to the multi-layer circuit layer.

2. The chip packaging structure according to claim 1, wherein Further comprising: A multi-layer power board configured on the second surface of the multi-layer circuit layer. The multi-layer power board is a wireless circuit board and has a plurality of vias, and the plurality of vias are electrically connected to the multi-layer circuit layer. Wherein the first peripheral surface of the multi-layer circuit layer is flush with the second peripheral surface of the multi-layer power board.

3. The chip packaging structure according to claim 1, wherein Further comprising: A support board configured on the first surface of the multi-layer circuit layer. The support board has at least one opening, and the at least one chip is configured within the at least one opening.

4. The chip packaging structure according to claim 3, wherein, The material of the support board includes copper, stainless steel, or alloy.

5. The chip package structure according to claim 1, characterized in that, The number of layers of the high-density circuit layer ranges from 2 to 10 layers, and the line width and line pitch of the high-density circuit layer range from 2 microns to 4 microns.

6. The chip packaging structure according to claim 1, wherein The number of layers of the medium-density circuit layer ranges from 2 to 15 layers, and the line width and line pitch of the medium-density circuit layer range from 5 microns to 10 microns.

7. The chip packaging structure according to claim 1, wherein, The number of layers of the low-density circuit layer ranges from 0 to 20 layers, and the line width of the low-density circuit layer ranges from 10 microns to 20 microns.

8. A method for manufacturing a chip packaging structure, characterized in that, Comprising: Forming a multi-layer circuit layer on a substrate. The multi-layer circuit layer has a first surface and a second surface opposite to each other, and includes a high-density circuit layer, a medium-density circuit layer, and a low-density circuit layer. The high-density circuit layer has the first surface, the medium-density circuit layer is located between the high-density circuit layer and the low-density circuit layer, and the low-density circuit layer has the second surface. Wherein the high-density circuit layer has a first line width, the medium-density circuit layer has a second line width, the low-density circuit layer has a third line width, and the first line width is less than the second line width, and the second line width is less than the third line width. The first surface of the multi-layer circuit layer is disposed on the substrate; Removing the substrate to expose the first surface of the multi-layer circuit layer; And Configuring at least one chip on the first surface of the high-density circuit layer, and the at least one chip is electrically connected to the multi-layer circuit layer.

9. The method for manufacturing a chip package structure according to claim 8, wherein, Further comprising: Before removing the substrate to expose the first surface of the multi-layer circuit layer, forming a multi-layer power board on the second surface of the multi-layer circuit layer. The multi-layer power board is a wireless circuit board and has a plurality of vias, and the plurality of vias are electrically connected to the multi-layer circuit layer. Wherein the first peripheral surface of the multi-layer circuit layer is flush with the second peripheral surface of the multi-layer power board.

10. The manufacturing method of the chip packaging structure according to claim 8, characterized in that, Further comprising: Before disposing the at least one chip on the first surface of the high-density circuit layer, dispose a support plate on the first surface of the multi-layer circuit layer, the support plate having at least one opening, and the at least one chip being disposed within the at least one opening.

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