Memory device, semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a memory device, a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps that a base structure is provided, the base structure comprises a substrate and an insulating layer covering the substrate, and the substrate comprises an isolation region; forming a first mask layer on the substrate structure, and etching the insulating layer through the first mask layer to form at least one groove in the isolation region; forming a resistor structure at least covering the groove in the isolation region; the resistor structure comprises a resistor layer and a polycrystalline silicon layer; and forming a metal gate in electrical contact with the resistance layer in the polycrystalline silicon layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor manufacturing technologies, and in particular, to a storage device, a semiconductor device, and a manufacturing method thereof. Background Art

[0002] In semiconductor integrated circuits, polysilicon resistors are a commonly used electronic component. By adding dopants to polysilicon, the resistivity of polysilicon can be controlled to the required value. Generally speaking, the higher the doping concentration, the lower the resistivity of polysilicon. In addition, the size and temperature of the semiconductor resistor also affect its resistance value. In order to obtain polysilicon resistors with different resistivities, it is necessary to adjust the doping process and manufacturing process of the semiconductor resistor, which will lead to an increase in process time and cost.

[0003] Based on this, it is expected to propose a semiconductor resistor that can reduce process time and cost. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a storage device, a semiconductor device, and a manufacturing method thereof to solve at least one technical problem existing in the prior art.

[0005] To achieve the above object, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, embodiments of the present disclosure provide a manufacturing method of a semiconductor device, the method including:

[0007] Providing a substrate structure, the substrate structure including a substrate and an insulating layer covering the substrate, the substrate including isolation regions; forming a first mask layer on the substrate structure, etching the insulating layer through the first mask layer to form at least one groove in the isolation regions; forming a resistor structure at least covering the groove in the isolation regions; the resistor structure including a resistor layer and a polysilicon layer; forming a metal gate in the polysilicon layer that is in electrical contact with the resistor layer.

[0008] In some embodiments, forming a metal gate in the polysilicon layer that is in electrical contact with the resistor layer includes: forming at least two metal gates on the resistor layer; wherein, the grooves are all located between any two of the metal gates.

[0009] In some embodiments, the method further includes: forming a conductive contact structure on the metal gate.

[0010] In some embodiments, the substrate further includes active regions; while forming a polysilicon gate structure in the active regions, forming a resistor structure at least covering the groove in the isolation regions.

[0011] In some embodiments, the method further includes: while forming a first isolation structure on the top and sidewalls of the polysilicon gate structure, forming a second isolation structure on the top and sidewalls of the resistor structure.

[0012] In some embodiments, forming a metal gate in the polysilicon layer that is in electrical contact with the resistor layer includes: etching the second isolation structure and the polysilicon layer to form a first gate trench in the polysilicon layer; depositing a metal electrode material in the first gate trench to form a metal gate in the polysilicon layer that is in electrical contact with the resistor layer.

[0013] In some embodiments, forming a metal gate in the polysilicon layer that is in electrical contact with the resistor layer includes: while replacing the polysilicon gate structure with a metal gate structure, forming a metal gate in the polysilicon layer that is in electrical contact with the resistor layer.

[0014] In some embodiments, the material of the resistor layer includes a metal compound.

[0015] In a second aspect, embodiments of the present disclosure provide a semiconductor device, the semiconductor device including: a substrate, the substrate including an isolation region having at least one groove; a resistor layer located in the isolation region and covering the groove; at least two metal gates in electrical contact with the resistor layer; wherein the grooves are all located between any two of the metal gates.

[0016] In some embodiments, it further includes: a conductive contact structure located on the metal gate.

[0017] In some embodiments, the material of the resistor layer includes a metal compound.

[0018] In a third aspect, embodiments of the present disclosure provide a storage device, the storage device including a storage cell array and a peripheral circuit, wherein the peripheral circuit includes: the semiconductor device as described in the second aspect.

[0019] Embodiments of the present disclosure provide a storage device, a semiconductor device, and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: providing a substrate structure, the substrate structure including a substrate and an insulating layer covering the substrate, the substrate including isolation regions; forming a first mask layer on the substrate structure, etching the insulating layer through the first mask layer to form at least one groove in the isolation regions; forming a resistance structure in the isolation regions, at least covering the groove; the resistance structure including a resistance layer and a polysilicon layer; forming a metal gate in the polysilicon layer in electrical contact with the resistance layer. The resistance structure formed in the present disclosure includes a resistance layer and a polysilicon layer, uses the metal gate as an electrode of the resistance structure, and the metal gate is in direct contact with the resistance layer. The electrode of the resistance structure can be formed by using the process steps of the metal gate, so that the process time and cost can be reduced. Description of the Drawings

[0020] Figure 1 is a schematic flowchart of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure;

[0021] Figures 2A to 2H is a cross-sectional view during the manufacturing process of the semiconductor device provided by the embodiments of the present disclosure;

[0022] Figure 3 is a schematic structural diagram of the storage device provided by the embodiments of the present disclosure;

[0023] Figure 4 is a schematic structural diagram of the storage system provided by the embodiments of the present disclosure. Detailed Embodiments

[0024] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0025] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known to the art are not described; that is, all features of the actual embodiments are not described here, and the well-known functions and structures are not described in detail.

[0026] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals represent the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion. And when discussing a second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0028] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0030] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0031] Reference Figure 1 , Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure. As Figure 1 shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

[0032] Step S101: Provide a substrate structure, where the substrate structure includes a substrate and an insulating layer covering the substrate, and the substrate includes isolation regions;

[0033] Step S102: Form a first mask layer on the substrate structure, and etch the insulating layer through the first mask layer to form at least one groove in the isolation region;

[0034] Step S103: Form a resistance structure in the isolation region that at least covers the groove; the resistance structure includes a resistance layer and a polysilicon layer;

[0035] Step S104: Form a metal gate in the polysilicon layer that is in electrical contact with the resistance layer.

[0036] Reference Figures 2A to 2H , a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure is described in detail.

[0037] As Figure 2A shown, Step S101: Provide a substrate structure, where the substrate structure includes a substrate 210 and an insulating layer 220 covering the substrate 210, and the substrate 210 includes isolation regions 211.

[0038] Specifically, the above-mentioned substrate 210 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate, etc. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., and may also be a stacked structure, such as Si / SiGe, etc., and may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc.

[0039] In the embodiments of the present disclosure, the isolation region 211 may be a shallow trench isolation region. The substrate 210 further includes an active region 212. The isolation region 211 may be formed by a shallow trench isolation structure 211-1, and the shallow trench isolation structure 211-1 is formed in the substrate to isolate the active regions 212 in the substrate 210. For example, a trench may be formed in the substrate 210, and then the trench may be filled to form the shallow trench isolation structure 211-1.

[0040] In the embodiments of the present disclosure, the material of the insulating layer 220 may include, but is not limited to, insulating materials such as silicon dioxide. The material of the shallow trench isolation structure 211-1 may include, but is not limited to, insulating materials such as silicon dioxide. In this example, the material of the insulating layer 220 is the same as that of the shallow trench isolation structure 211-1.

[0041] As Figure 2B shown, step S102: Form a first mask layer 231 on the base structure 200, and etch the insulating layer 220 through the first mask layer 231 to form at least one groove 221 in the isolation region 211.

[0042] In the embodiments of the present disclosure, a first mask material layer and a first photoresist material layer are sequentially formed on the base structure 200; the first photoresist material layer is exposed and developed to form a first photoresist layer. The first photoresist layer has at least one opening exposing the first mask material layer. The first mask material layer is etched through the first photoresist layer to form the first mask layer 231. The first mask layer 231 has at least one opening exposing the insulating layer 220, and the insulating layer 220 is etched through the first mask layer 231 to form at least one groove 221 in the isolation region 211. It should be noted that Figure 2B the number of the grooves 221 schematically shown is only used to describe the embodiments of the present disclosure and is not used to limit the number of the grooves 221, and the number of the grooves 221 may be set according to actual needs.

[0043] In the embodiments of the present disclosure, since the insulating layer 220 of the active region 212 is exposed by the first mask layer 231, when the insulating layer 220 is etched through the first mask layer 231, the insulating layer 220 of the active region 212 is also etched, so that the insulating layer of the active region 212 is thinned, and the thinned insulating layer 220A may be used as the gate dielectric layer of the active region 212.

[0044] After forming at least one groove 221 and the thinned insulating layer 220A, the first mask layer 231 is removed.

[0045] In the embodiments of the present disclosure, the first mask layer 231 may be a hard mask layer, and the material of the first mask layer 231 includes, but is not limited to, silicon oxynitride, silicon oxide, or silicon nitride. In practical applications, a first photoresist material layer may be formed first by a spin coating process, and then a first mask material layer is deposited on the first photoresist material layer. Among them, the process of depositing the first mask material layer includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering, Metal-Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD), etc.

[0046] In the embodiments of the present disclosure, step S103: form a resistance structure in the isolation region 211 that at least covers the groove 221; the resistance structure includes a resistance layer 242A and a polysilicon layer 243A.

[0047] As Figure 2C shown, a first dielectric layer 241 and a resistance layer 242 are deposited and formed. Among them, the first dielectric layer 241 and the resistance layer 242 in the isolation region 211 cover the groove 221, and the first dielectric layer 241 and the resistance layer 242 in the active region 212 cover the thinned insulating layer 220A.

[0048] In the embodiments of the present disclosure, the first dielectric layer 241 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric. One or more thin film deposition processes such as CVD, PVD, ALD, any other suitable process, or a combination thereof may be used to deposit and form the first dielectric layer 241.

[0049] In the embodiments of the present disclosure, the material of the resistance layer 242 is a non-semiconductor material, and the resistance layer 242 may include any suitable metal compound, such as metal compounds like titanium nitride (TiN) and tantalum nitride (TaN).

[0050] As Figure 2D shown, a polysilicon layer 243 is deposited and formed. Among them, the polysilicon layer 243 covers the resistance layer 242. Among them, the polysilicon layer 243 in the isolation region 211 fills the groove 221.

[0051] In an embodiment of the present disclosure, while forming a polysilicon gate structure in the active region, a resistor structure covering at least the groove is formed in the isolation region. The present disclosure forms a resistor structure in the isolation region by using the formation process of the polysilicon gate structure in the active region. In other words, the resistor structure of the present disclosure can be formed by using existing process steps without adding new process steps. Thus, the process time and process cost are greatly reduced.

[0052] As Figure 2E shown, the polysilicon layer 243, the resistor layer 242, and the first dielectric layer 241 are etched to form a polysilicon gate structure in the active region 212 and a resistor structure in the isolation region 211 simultaneously.

[0053] Here, when etching the polysilicon layer 243, the resistor layer 242 serves as an etch stop layer; when etching the resistor layer 242, the first dielectric layer 241 serves as an etch stop layer; when etching the first dielectric layer 241, the insulating layer serves as an etch stop layer.

[0054] In an embodiment of the present disclosure, the resistor structure includes a polysilicon layer 243A and a resistor layer 242A. In some embodiments, the resistor structure further includes a first dielectric layer 241A. The present disclosure forms a three-dimensional resistor structure covering at least the groove in the isolation region, and reduces the occupied area of the resistor layer in the three-dimensional resistor structure via the groove. In other words, by forming a resistor structure covering at least the groove, the occupied area of the resistor structure in the semiconductor device can be reduced while ensuring that the effective area of the semiconductor device remains unchanged. On the other hand, by reducing the occupied area of the resistor structure in the semiconductor device, the integration degree of the storage device can be improved.

[0055] The present disclosure can control the resistance value of the resistor structure of the present disclosure by controlling the size (which can be the area) and thickness of the resistor layer in the resistor structure. Then, by controlling the number and size of the grooves, the adjustment of the occupied area of the resistor structure can be achieved while ensuring that the effective area of the semiconductor device remains unchanged, thereby forming resistor structures that meet different resistance value requirements.

[0056] In an embodiment of the present disclosure, the polysilicon gate structure includes a polysilicon layer 243B, a resistor layer 242B, and a first dielectric layer 241B; wherein, the first dielectric layer 241B and the insulating layer 220A can jointly serve as a gate dielectric layer, and the polysilicon layer 243B serves as a polysilicon gate.

[0057] In an embodiment of the present disclosure, the method further includes: while forming a first isolation structure on the top and sidewalls of the polysilicon gate structure, forming a second isolation structure on the top and sidewalls of the resistor structure.

[0058] As Figure 2EAs shown, while forming the first isolation structure 251 on the top and sidewalls of the polysilicon gate structure in the active region 212, a second isolation structure 252 is formed on the top and sidewalls of the resistance structure in the isolation region 211.

[0059] In an embodiment of the present disclosure, the first isolation structure 251 covers the surface of the polysilicon gate structure composed of the polysilicon layer 243B, the resistance layer 242B, and the first dielectric layer 241B; the second isolation structure 252 covers the surface of the resistance structure composed of the polysilicon layer 243A, the resistance layer 242A, and the first dielectric layer 241A.

[0060] In an embodiment of the present disclosure, the materials of the first isolation structure 251 and the second isolation structure 252 may be the same. In this example, the materials of the first isolation structure 251 and the second isolation structure 252 are silicon nitride.

[0061] As Figure 2E shown, an interlayer dielectric (ILD) layer is deposited and planarized until the tops of the first isolation structure 251 and the second isolation structure 252 are exposed. The planarized ILD layer 261 exposes the tops of the first isolation structure 251 and the second isolation structure 252. Here, a chemical mechanical polishing (CMP) process can be used for planarization.

[0062] In an embodiment of the present disclosure, the first isolation structure 251 and the second isolation structure 252 can serve as the stop layers for the planarization of the ILD layer.

[0063] In an embodiment of the present disclosure, the ILD layer can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

[0064] In an embodiment of the present disclosure, step S104: Form a metal gate in the polysilicon layer in electrical contact with the resistance layer.

[0065] In an embodiment of the present disclosure, forming a metal gate in the polysilicon layer in electrical contact with the resistance layer includes: etching the second isolation structure and the polysilicon layer to form a first gate trench in the polysilicon layer; depositing a metal electrode material in the first gate trench to form a metal gate in the polysilicon layer in electrical contact with the resistance layer.

[0066] In an embodiment of the present disclosure, the metal electrode material is one or more combinations of TiN, TiAl, Al, TaN, TaC, and W.

[0067] Combined Figure 2E and Figure 2F shown, inFigure 2E A second mask layer 232 is formed on the structure shown, and the second isolation structure 252 and the polysilicon layer 243A are etched through the second mask layer 232 to form a first gate trench 243A-1 in the polysilicon layer 243A.

[0068] In the embodiments of the present disclosure, on Figure 2E the structure shown, a second mask material layer and a second photoresist material layer are sequentially formed; the second photoresist material layer is exposed and developed to form a second photoresist layer. The second photoresist layer has at least one opening exposing the second mask material layer. The second mask material layer is etched through the second photoresist layer to form a second mask layer 232. The second mask layer 232 has at least two openings exposing the second isolation structure 252, and the second isolation structure 252 and the polysilicon layer 243A are etched through the second mask layer 232 to form at least two first gate trenches 243A-1 in the polysilicon layer 243A. It should be noted that Figure 2H the number of the first gate trenches 243A-1 shown is only used to describe the embodiments of the present disclosure and is not used to limit the number of the first gate trenches 243A-1, and the number of the first gate trenches 243A-1 can be set according to actual needs.

[0069] In the embodiments of the present disclosure, since the second mask layer 232 does not cover the active region 212, when the second isolation structure 252 and the polysilicon layer 243A are etched through the second mask layer 232, the first isolation structure 251 and the polysilicon layer 243B in the active region 212 are also etched, so that the top of the first isolation structure 251 exposed in the active region 212 and the polysilicon layer 243B are removed. The remaining part of the first isolation structure 251 after the top of the first isolation structure 251 is removed serves as the sidewall 251B of the gate structure. Since the polysilicon layer 243B is removed, a second gate trench 251B-1 is formed between the sidewalls 251B.

[0070] Here, the resistance layer 242B serves as an etch stop layer for etching the polysilicon layer 243B, and the etching of the polysilicon layer 243B stops on the resistance layer 242B.

[0071] In the embodiments of the present disclosure, the first isolation structure 251 and the second isolation structure 252 may be composite structures. For example, the first isolation structure 251 includes a first sidewall and a second sidewall, the first sidewall covers the surface of the polysilicon gate structure, and the second sidewall covers the surface of the first sidewall. Further, each of the first sidewall and the second sidewall includes a first stack and a second stack, the second stack covers the surface of the first stack, and the material of the first stack includes an oxide, and the material of the second stack includes a nitride.

[0072] In an embodiment of the present disclosure, the second mask layer 232 may be a hard mask layer, and the material of the second mask layer 232 includes but is not limited to silicon oxynitride, silicon oxide, or silicon nitride. In practical applications, a second photoresist material layer may be first formed by a spin coating process, and then a second mask material layer is deposited on the second photoresist material layer.

[0073] In an embodiment of the present disclosure, while replacing the polysilicon gate structure with a metal gate structure, a metal gate in electrical contact with the resistance layer is formed in the polysilicon layer.

[0074] Combined Figure 2F and Figure 2G as shown in, where Figure 2G the structure within the square dashed box in is an enlarged schematic diagram of the structure within the circular dashed box. A first material layer 271, a second material layer 272, and a metal layer 273 are sequentially formed in the first gate trench 243A-1 and the second gate trench 251B-1; wherein, the first material layer 271 covers the bottom and sidewalls of the first gate trench 243A-1 and the second gate trench 251B-1, the second material layer 272 covers the surface of the first material layer 271, and the metal layer 273 covers the surface of the second material layer 272 and fills the first gate trench 243A-1 and the second gate trench 251B-1.

[0075] Here, the first material layer 271, the second material layer 272, and the metal layer 273 in the first gate trench 243A-1 constitute a metal gate. The first material layer 271, the second material layer 272, and the metal layer 273 in the second gate trench 251B-1 constitute a metal gate.

[0076] In an embodiment of the present disclosure, the gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer may be a single-layer or multi-layer structure, and the material may be, for example, an insulating material. In this example, the gate dielectric layer is a multi-layer structure, and the first dielectric layer 241B and the insulating layer 220A together serve as the gate dielectric layer of the metal gate structure. The gate conductive layer may be a single-layer or multi-layer structure, and the material may be, for example, a combination of metal electrode materials. The metal electrode materials may be, for example, one or more combinations of TiN, TiAl, Al, TaN, TaC, W, etc. In this example, the first material layer 271, the second material layer 272, and the metal layer 273 in the second gate trench 251B-1 constitute the gate conductive layer in the metal gate structure.

[0077] Here, the step of replacing the polysilicon gate structure with the metal gate structure is the step of replacing the polysilicon gate in the polysilicon gate structure with a metal gate, which specifically includes replacing the polysilicon layer 243B with the first material layer 271, the second material layer 272, and the metal layer 273.

[0078] In some embodiments, doped regions may be formed in the substrate 210 by ion implantation and / or thermal diffusion, and the doped regions are used as, for example, well regions and source / drain regions of transistors. Thus, the metal gate structure and the source / drain together form a transistor, and the transistor can be used to form a peripheral circuit. It should be understood that the details of manufacturing the transistor may vary according to the type of the transistor and will not be elaborated herein.

[0079] In the embodiments of the present disclosure, forming a metal gate in the polysilicon layer in electrical contact with the resistance layer includes: forming at least two metal gates on the resistance layer; wherein, the groove is located between any two of the metal gates.

[0080] In the embodiments of the present disclosure, the number of metal gates on the resistance layer may be two, which are respectively located at both ends of the resistance layer and are in direct contact with the resistance layer. Here, the metal gate serves as an electrode of the resistance structure and is used to realize the electrical connection between the resistance structure and the conductive contact structure. It can be understood that the embodiments of the present disclosure have no limitation on the number and distribution of the metal gates on the resistance layer.

[0081] It should be noted that when the number of metal gates on the resistance layer is more than two, resistors with different resistance values can be formed between every two metal gates to meet the different resistance value requirements of the storage device.

[0082] In the embodiments of the present disclosure, the method further includes: forming a conductive contact structure on the metal gate.

[0083] In the embodiments of the present disclosure, while replacing the polysilicon gate structure with a metal gate structure, a metal gate in electrical contact with the resistance layer is formed in the polysilicon layer.

[0084] Combined Figure 2G and Figure 2H As shown, an isolation layer 281 is formed. The isolation layer 281 covers the resistance structure in the isolation region and the metal gate in the resistance structure, and the metal gate structure in the active region. Here, the isolation layer 281 and the ILD layer 261 together constitute an interlayer isolation layer. A conductive contact structure 282 is formed in the isolation layer 281, and the conductive contact structure 282 is respectively formed on the metal gate in the resistance structure, the metal gate in the metal gate structure, and the source / drain.

[0085] In the embodiments of the present disclosure, the material of the conductive contact structure 282 includes metal materials such as Al and W. The conductive contact structure 282 is a columnar body with a trapezoidal cross section. In other embodiments, the conductive contact structure 282 may be of other shapes, and its cross section may be, for example but not limited to, circular, elliptical, triangular, etc.

[0086] In the embodiments of the present disclosure, the conductive contact structure 282 on the resistor structure and the metal gate structure is in direct contact with the metal layer 273 in the metal gate. In this example, the materials of the conductive contact structure 282 and the metal layer 273 can both be metal materials, so that a metal contact is formed between the conductive contact structure 282 and the metal layer 273.

[0087] In the embodiments of the present disclosure, while forming the metal gate structure in the active region, electrodes of the resistor structure are formed in the isolation region. The present disclosure utilizes the formation process of the metal gate structure in the active region to form the electrodes of the resistor structure in the isolation region. In other words, the electrodes of the resistor structure of the present disclosure can be formed by using existing process steps without adding new process steps. Thus, the process time and process cost are greatly reduced.

[0088] Moreover, the material of the resistor structure in the embodiments of the present disclosure is a metal compound (not a semiconductor material), so it can be in direct contact with the metal gate without considering the problem of excessive contact resistance generated during metal-semiconductor contact.

[0089] In the embodiments of the present disclosure, a semiconductor device is further provided. The semiconductor device includes:

[0090] A substrate, the substrate includes an isolation region, and the isolation region has at least one groove;

[0091] A resistor layer, located in the isolation region, and the resistor layer covers the groove;

[0092] At least two metal gates, electrically contacting the resistor layer;

[0093] Wherein, the grooves are all located between any two metal gates.

[0094] The resistor layer of the present disclosure is located in the isolation region, and since the resistor layer covers the groove, the resistor layer is a three-dimensional resistor structure. In other words, the present disclosure reduces the occupied area of the resistor layer in the three-dimensional resistor structure via the groove. Thus, the occupied area of the resistor structure in the semiconductor device can be reduced while ensuring that the effective area of the semiconductor device remains unchanged. On the other hand, by reducing the occupied area of the resistor structure in the semiconductor device, the integration degree of the storage device can be improved.

[0095] The present disclosure can control the resistance value of the resistor structure of the present disclosure by controlling the size (which can be the area) and thickness of the resistor layer in the resistor structure. Then, by controlling the number and size of the grooves, the adjustment of the occupied area of the resistor structure can be realized while ensuring that the effective area of the semiconductor device remains unchanged, so as to form resistor structures that meet different resistance value requirements.

[0096] In some embodiments, the semiconductor device further includes: a conductive contact structure, located on the metal gate.

[0097] In the embodiments of the present disclosure, the number of metal gates on the resistance layer can be two, which are respectively located at both ends of the resistance layer and are in direct contact with the resistance layer. Here, the metal gates serve as electrodes of the resistance layer to realize the electrical connection between the resistance layer and the conductive contact structure. It can be understood that the embodiments of the present disclosure have no limitation on the number and distribution of the metal gates on the resistance layer.

[0098] It should be noted that when the number of metal gates on the resistance layer is more than two, resistances with different resistance values can be formed between two metal gates to meet the different resistance value requirements of the storage device.

[0099] In some embodiments, the material of the resistance layer includes metal compounds.

[0100] The material of the resistance layer in the embodiments of the present disclosure is a metal compound (non-semiconductor material), so it can be in direct contact with the metal gate without considering the problem of excessive contact resistance generated when there is a metal-semiconductor contact.

[0101] In some embodiments, the substrate further includes an active region, and the semiconductor device further includes: a metal gate structure located in the active region.

[0102] The embodiments of the present disclosure further provide a storage device, which includes a storage cell array and a peripheral circuit. Among them, the peripheral circuit includes: the semiconductor device described in the above embodiments.

[0103] In some embodiments, the storage device includes a 3D NAND type storage device.

[0104] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the storage device provided by the embodiments of the present disclosure. Among them, the storage device 300 includes a storage cell array 310 and a peripheral circuit 320. Among them, the peripheral circuit 320 includes a semiconductor device 321. Specifically, the storage device can be a 3D NAND type storage device.

[0105] The embodiments of the present disclosure further provide a storage system, which includes a controller and a storage device. The controller is coupled to the storage device and is used to control the storage device to store data. The storage device includes the semiconductor device described in the above embodiments.

[0106] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the storage system provided by the embodiments of the present disclosure. The storage system 400 includes a controller 410 and a storage device 420. The controller 410 is coupled to the storage device 420 and is used to control the storage device 420 to store data. The storage device 420 includes a semiconductor device 421.

[0107] It should be noted that the descriptions of the above semiconductor devices, memory devices and memory systems are similar to the description of the manufacturing method of the above semiconductor devices, and have beneficial effects similar to those of the embodiments of the manufacturing method of semiconductor devices. For the technical details not disclosed in the embodiments of the semiconductor devices, memory devices and memory systems of the present disclosure, please refer to the description of the embodiments of the manufacturing method of semiconductor devices of the present disclosure for understanding.

[0108] The embodiments of the present disclosure provide a memory device, a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: providing a substrate structure, the substrate structure including a substrate and an insulating layer covering the substrate, the substrate including isolation regions; forming a first mask layer on the substrate structure, etching the insulating layer through the first mask layer to form at least one groove in the isolation regions; forming a resistance structure covering at least the groove in the isolation regions; the resistance structure including a resistance layer and a polysilicon layer; and forming a metal gate in the polysilicon layer in electrical contact with the resistance layer. In the present disclosure, the formed resistance structure includes a resistance layer and a polysilicon layer, a metal gate is used as an electrode of the resistance structure, and the metal gate is in direct contact with the resistance layer.

[0109] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0110] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made under the inventive concept of the present disclosure by using the content of the specification and drawings of the present disclosure, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: Providing a substrate structure, the substrate structure including a substrate and an insulating layer covering the substrate, the substrate including isolation regions; Forming a first mask layer on the substrate structure, and etching the insulating layer through the first mask layer to form at least one groove in the isolation regions; Forming a resistance structure in the isolation regions, the resistance structure covering at least the groove; the resistance structure including a resistance layer and a polysilicon layer; Forming a metal gate in the polysilicon layer that is in electrical contact with the resistance layer.

2. The method according to claim 1, wherein The forming a metal gate in the polysilicon layer that is in electrical contact with the resistance layer includes: Forming at least two metal gates on the resistance layer; Wherein, the grooves are all located between any two of the metal gates.

3. The method according to claim 1 or 2, characterized in that The method further includes: Forming a conductive contact structure on the metal gate.

4. The method according to claim 1, wherein The substrate further includes active regions; while forming a polysilicon gate structure in the active regions, forming a resistance structure covering at least the groove in the isolation regions.

5. The method according to claim 4, wherein The method further includes: While forming a first isolation structure on the top and sidewalls of the polysilicon gate structure, forming a second isolation structure on the top and sidewalls of the resistance structure.

6. The method according to claim 5, wherein The forming a metal gate in the polysilicon layer that is in electrical contact with the resistance layer includes: Etching the second isolation structure and the polysilicon layer to form a first gate trench in the polysilicon layer; Depositing a metal electrode material in the first gate trench to form a metal gate in the polysilicon layer that is in electrical contact with the resistance layer.

7. The method according to claim 6, wherein The forming a metal gate in the polysilicon layer that is in electrical contact with the resistance layer includes: While replacing the polysilicon gate structure with a metal gate structure, forming a metal gate in the polysilicon layer that is in electrical contact with the resistance layer.

8. The method according to any one of claims 1 to 7, wherein The material of the resistance layer includes a metal compound.

9. A semiconductor device, characterized in that, The semiconductor device includes: A substrate, the substrate including isolation regions, the isolation regions having at least one groove; A resistance layer, located in the isolation regions, and the resistance layer covering the groove; At least two metal gates, in electrical contact with the resistance layer; Wherein, the groove is located between any two of the metal gates.

10. The semiconductor device according to claim 9, characterized in that, It further includes: A conductive contact structure, located on the metal gate.

11. The semiconductor device according to claim 9, wherein The material of the resistance layer includes a metal compound.

12. A storage device, characterized in that, The storage device includes a storage cell array and a peripheral circuit, wherein, the peripheral circuit includes: the semiconductor device according to any one of claims 9 to 11.

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