Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device includes: a conductive pillar; the first insulating layer comprises a surrounding part located on the side wall of the conductive column; the conductive layer and the isolation layer are both located on the periphery of the surrounding part and are arranged in the extending direction of the conductive column, and a spacing distance exists between the first end face, close to the isolation layer, of the conductive column and the surface, close to the isolation layer, of the conductive layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In the iterative development process of semiconductor devices, the improvement of integration may lead to a reduction in device performance. It is desired to optimize the semiconductor device structure to balance integration and device performance. Summary of the Invention

[0003] This application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes: a conductive pillar; a first insulating layer including a surrounding portion on the sidewall of the conductive pillar; and a conductive layer and an isolation layer, both located on the outer periphery of the surrounding portion, wherein the conductive layer and the isolation layer are arranged along the extension direction of the conductive pillar, and there is a spacing distance between the first end face of the conductive pillar close to the isolation layer and the surface of the conductive layer close to the isolation layer.

[0005] In an exemplary embodiment, the semiconductor device further includes: a connection structure located at the first end face of the conductive pillar.

[0006] In an exemplary embodiment, the connection structure is in contact with the isolation layer.

[0007] In an exemplary embodiment, the semiconductor device further includes: a second insulating layer located on the side of the isolation layer away from the conductive layer, and the connection structure penetrates the second insulating layer.

[0008] In an exemplary embodiment, the second insulating layer is in contact with the first end face of the conductive pillar.

[0009] In an exemplary embodiment, the first insulating layer further includes a first extension portion located at the first end face, wherein the second insulating layer is in contact with the first extension portion.

[0010] In an exemplary embodiment, in a plane perpendicular to the extension direction of the conductive pillar, the size of the connection structure is less than or equal to the size of the surrounding portion.

[0011] In an exemplary embodiment, the connection structure and the conductive pillar are coaxially or offset-axis arranged.

[0012] In an exemplary embodiment, in a plane perpendicular to the extension direction of the conductive pillar, a plurality of conductive pillars and a plurality of surrounding portions are arranged in an array; the first insulating layer further includes a second extension portion located at the end of the surrounding portion away from the isolation layer and connecting adjacent surrounding portions.

[0013] In an exemplary embodiment, the semiconductor device further includes: a transistor located on a side of the connection structure away from the conductive pillar; wherein, one of the source or drain of the transistor is connected to the connection structure.

[0014] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory for controlling the memory to store data.

[0015] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: forming a conductive pillar and forming a surrounding portion covering the sidewall of the conductive pillar; forming a conductive layer in a partial space on the outer periphery of the surrounding portion, wherein there is a spacing distance between the surface of the conductive layer close to the first end face of the conductive pillar and the first end face; and forming an isolation layer on a side of the conductive layer close to the first end face.

[0016] In an exemplary embodiment, the method for manufacturing the semiconductor device further includes: forming a connection structure on the first end face.

[0017] In an exemplary embodiment, forming the conductive pillar includes: forming a sacrificial layer; forming an opening penetrating the sacrificial layer and forming a conductive pillar in the opening; and removing the sacrificial layer.

[0018] In an exemplary embodiment, during the process of forming the surrounding portion, an initial first extension portion covering the first end face of the conductive pillar is formed by a thin film deposition process.

[0019] In an exemplary embodiment, in a plane perpendicular to the extending direction of the conductive pillar, a plurality of conductive pillars are arranged in an array; wherein, during the process of forming the surrounding portion and the initial first extension portion, a second extension portion is formed by a thin film deposition process at an end of the surrounding portion away from the initial first extension portion, and the second extension portion connects adjacent surrounding portions.

[0020] In an exemplary embodiment, forming the conductive layer in a partial space on the outer periphery of the surrounding portion includes: forming an initial conductive layer on the outer periphery of the surrounding portion; and removing a part of the initial conductive layer close to the first end face to form the conductive layer.

[0021] In an exemplary embodiment, forming the isolation layer on a side of the conductive layer close to the first end face includes: forming an initial isolation layer in the space formed after removing a part of the initial conductive layer and on a side of the initial first extension portion away from the conductive pillar; removing a part of the initial isolation layer located on a side of the initial first extension portion away from the conductive pillar to the initial first extension portion by a chemical mechanical polishing process to form the isolation layer.

[0022] In an exemplary embodiment, the method for manufacturing the semiconductor device further includes: removing the initial first extension by a mechano-chemical polishing process.

[0023] In an exemplary embodiment, the method for the semiconductor device further includes: forming a second insulating layer on a surface of the isolation layer away from the conductive layer and the initial first extension; wherein, forming the connection structure on the first end face includes: forming a connection structure that penetrates through the second insulating layer and the initial first extension to the first end face.

[0024] In an exemplary embodiment, after forming the connection structure on the first end face, the method for manufacturing the semiconductor device further includes: forming a transistor on a side of the connection structure away from the conductive pillar, wherein one of the source or drain of the transistor is connected to the connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings. Among them:

[0026] Figure 1 is a cross-sectional schematic view of a semiconductor device provided by an embodiment of the present application;

[0027] Figure 2A is a cross-sectional schematic view of a semiconductor device provided by another embodiment of the present application;

[0028] Figure 2B is a cross-sectional schematic view of a semiconductor device provided by another embodiment of the present application including a transistor;

[0029] Figure 3 is a cross-sectional schematic view of a semiconductor device provided by yet another embodiment of the present application;

[0030] Figure 4 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0031] Figure 5 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0032] Figures 6A to 6H is a cross-sectional schematic view of a semiconductor device during manufacturing provided by an embodiment of the present application; and

[0033] Figure 7A and Figure 7B is a cross-sectional schematic view of a semiconductor device during manufacturing provided by another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another feature and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teachings of the present application, the first insulating layer discussed in the present application may also be referred to as the second insulating layer, and vice versa.

[0036] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation and not as terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" in this specification are open-ended rather than closed-ended expressions, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just an individual element in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which the present application pertains. It should also be understood that unless there is a clear statement in the present application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. In addition, unless explicitly defined or in conflict with the context, the specific steps included in the methods described in the present application do not have to be limited to the recited order and may be executed in any order or executed in parallel.

[0040] In addition, in the present application, when using "connected" or "coupled", it may indicate direct contact or indirect contact between corresponding components, unless there are clear other limitations or can be deduced from the context.

[0041] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0042] Figure 1 It is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application. It should be noted that hereinafter, the x-direction, y-direction, and z-direction in each drawing show the spatial relationship of each component in the semiconductor device. For example, the z-direction is the extension direction of the conductive pillar, and the x-direction and y-direction are two directions that intersect (e.g., perpendicular) with each other on a plane intersecting (e.g., perpendicular) to this extension direction. The same concept will be adopted throughout the present application to describe the spatial relationship of each component in the semiconductor device.

[0043] As Figure 1 shown, the semiconductor device 100 includes a conductive pillar 111, a surrounding portion 1121, a conductive layer 113, and a connection structure 115. In the semiconductor device 100, the surrounding portion 1121 is located on the sidewall of the conductive pillar 111, and the conductive layer 113 is located on the outer periphery of the surrounding portion 1121. The first end face 1111 of the conductive pillar 111 and the surface 1131 of the conductive layer 113 are substantially flush (e.g., the error is less than ±10%). The connection structure 115 is located on the first end face 1111 of the conductive pillar 111. In a plane perpendicular to the z-direction, the size d1 of the connection structure 115 is smaller than the size d2 of the surrounding portion 1121 to prevent the conductive pillar 111 from contacting the conductive layer 113 and thus causing a short circuit. However, this will result in a smaller lateral size of the connection structure 115, restricting the current transmission effect between the conductive pillar 111 and the connection structure 115. In addition, the manufacturing process requirements for the connection structure 115 are relatively high, and it is necessary to accurately align the connection structure 115 and the conductive pillar 111 to avoid contact between the two.

[0044] In view of this, other embodiments of the present application provide a semiconductor device to optimize the semiconductor device 100 in the above embodiment. Figure 2A It is a cross-sectional schematic diagram of a semiconductor device provided by another embodiment of the present application. Figure 2B It is a cross-sectional schematic diagram of a semiconductor device provided by another embodiment of the present application and including a transistor. As Figure 2A shown, the semiconductor device 200 includes a conductive pillar 211, a first insulating layer 212, a conductive layer 213, and an isolation layer 214.

[0045] The conductive pillar 211 can extend along the z direction. For example, the shape of the conductive pillar 211 in a plane perpendicular to the z direction can include a circle, a square, a hexagon, an octagon, or other irregular polygons. In one implementation, the conductive pillar 211 can be generally a cylindrical structure with a taper. For example, the radial dimension of the conductive pillar 211 decreases along the negative z direction. In the semiconductor device 200, the conductive pillar 211 can serve as one electrode (hereinafter referred to as the first electrode) in a capacitor. The material of the conductive pillar 211 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polysilicon (poly-Si), amorphous silicon (α-Si), or any other suitable conductive material.

[0046] The first insulating layer 212 includes a surrounding portion 2121 located on the sidewall of the conductive pillar 211. For example, the surrounding portion 2121 can be generally a tubular structure and sleeved outside the conductive pillar 211. For example, the inner side of the surrounding portion 2121 is in contact with the outer side of the conductive pillar 211. The material of the surrounding portion 2121 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y )), high-k dielectric materials, or any other suitable insulating materials. High-k dielectric materials can include, but are not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), hafnium oxide (HfO2), etc. For example, the material of the surrounding portion 2121 is a high-k dielectric material. In the semiconductor device 200, the surrounding portion 2121 can serve as the insulating dielectric in a capacitor.

[0047] The conductive layer 213 and the isolation layer 214 are both located on the outer periphery of the surrounding portion 2121. The conductive layer 213 and the isolation layer 214 are arranged along the z direction, and there is a spacing distance d3 between the first end face 2111 of the conductive column 211 close to the isolation layer 214 and the surface 2131 of the conductive layer 213 close to the isolation layer 214. In other words, both the conductive layer 213 and the isolation layer 214 extend horizontally in the x direction and the y direction. The isolation layer 214 is located on the surface 2131 of the conductive layer 213 in the z direction. For example, the size of the conductive layer 213 in the z direction can be larger than the size of the isolation layer 214 in the z direction. For example, the first end face 2111 of the conductive column 211, the end face of the surrounding portion 2121 far from the conductive layer 213, and the surface of the isolation layer 214 far from the conductive layer 213 are substantially flush (for example, the error is less than ±10%). In the semiconductor device 200, the conductive layer 213 can serve as another electrode (hereinafter referred to as the second electrode) in the capacitor. The material of the conductive layer 213 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polysilicon (poly-Si), amorphous silicon (α-Si), or any other suitable conductive material. The material of the isolation layer 214 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material.

[0048] In this embodiment, by providing the conductive layer 213 and the isolation layer 214 arranged along the z direction on the outer periphery of the surrounding portion 2121, and having a spacing distance d3 between the first end face 2111 of the conductive column 211 and the surface 2131 of the conductive layer 213, a height difference can be formed between the first end face 2111 of the conductive column 211 and the surface 2131 of the conductive layer 213 in the z direction, and the isolation layer 214 can electrically isolate the conductive column 211 and the conductive layer 213 in the z direction. When the conductive column 211 and the conductive layer 213 serve as the two electrodes of the capacitor respectively, compared with the previous embodiment, the isolation layer 214 can reduce the risk of short circuit between the lead-out structure (for example, the connection structure 215) of the conductive column 211 and the conductive layer 213. On the other hand, the isolation layer 214 helps to reduce the process difficulty of preparing the lead-out structure (for example, the connection structure 215) of the conductive column 211, improve the process window for preparing the lead-out structure (for example, the connection structure 215), and allow the lead-out structure (for example, the connection structure 215) to have a larger lateral dimension, thereby improving the current transmission effect between the conductive column 211 and the lead-out structure (for example, the connection structure 215).

[0049] In some embodiments, the semiconductor device 200 may further include a connection structure 215. The connection structure 215 is located on the first end face 2111 of the conductive pillar 211. In other words, the connection structure 215 may be in contact with the first end face 2111 of the conductive pillar 211. For example, the connection structure 215 may generally be in a columnar structure. The connection structure 215 can be used to lead out the conductive pillar 211 in the z direction and connect it to the channel in the transistor. The transistor will be described in detail below. The material of the connection structure 215 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polysilicon (poly-Si), amorphous silicon (α-Si), or any other suitable conductive material.

[0050] In some embodiments, the connection structure 215 may also be in contact with the isolation layer 214. For example, a part of the connection structure 215 is in contact with the conductive pillar 211 and the surrounding portion 2121, and another part is in contact with the isolation layer 214. In this embodiment, it is possible to allow the connection structure 215 to have a larger lateral dimension (for example, the dimension d1 in the plane perpendicular to the z direction), thereby further improving the current transmission effect between the connection structure 215 and the conductive pillar 211, and also increasing the overlay deviation between the connection structure 215 and the conductive pillar 211, reducing the process difficulty of fabricating the connection structure 215.

[0051] In some embodiments, the connection structure 215 and the conductive pillar 211 may be coaxially or offset axially arranged. When the connection structure 215 and the conductive pillar 211 are coaxially arranged, it is possible to allow the connection structure 215 to have a larger lateral dimension (for example, the dimension d1 in the plane perpendicular to the z direction), thereby improving the current transmission effect between the connection structure 215 and the conductive pillar 211. When the connection structure 215 and the conductive pillar 211 are offset axially arranged, it is possible to increase the overlay deviation between the connection structure 215 and the conductive pillar 211, reducing the process difficulty of fabricating the connection structure 215.

[0052] In some embodiments, in the plane perpendicular to the z direction, the dimension d1 (for example, the diameter d1) of the connection structure 215 is less than or equal to the dimension d2 (for example, the diameter d2) of the surrounding portion 2121, thereby effectively improving the feasibility of expanding the lateral dimension of the connection structure 215, and contributing to improving the current transmission effect between the connection structure 215 and the conductive pillar 211.

[0053] In some embodiments, the semiconductor device 200 may further include a second insulating layer 216. The second insulating layer 216 is located on the side (e.g., surface) of the isolation layer 214 away from the conductive layer 213. For example, the second insulating layer 216 may extend laterally in the x and y directions. Among them, the connection structure 215 may penetrate the second insulating layer 216. In the semiconductor device 200, the second insulating layer 216 may contact the first end face 2111 of the conductive pillar 211. The material of the second insulating layer 216 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. When the materials of the second insulating layer 216 and the isolation layer 214 are the same, there is no obvious interface between the two.

[0054] In some embodiments, the number of the conductive pillars 211 and the surrounding portions 2121 may be multiple, and the multiple conductive pillars 211 and the surrounding portions 2121 may be arranged in an array in a plane perpendicular to the z direction. For example, the multiple conductive pillars 211 and the surrounding portions 2121 may be arranged at intervals in the x and y directions, and the conductive layer 213 and the isolation layer 214 may be located on the outer periphery of each of the multiple surrounding portions 2121. In the semiconductor device 200, the conductive layer 213 may serve as a common second electrode for each of the multiple capacitors. In other words, the second electrodes of each of the multiple capacitors may be connected to each other through the conductive layer 213.

[0055] In some embodiments, the first insulating layer 212 may further include a second extension portion 2122. The second extension portion 2122 may be located at the end of the surrounding portion 2121 away from the isolation layer 214 and connect adjacent surrounding portions 2121. For example, the second extension portion 2122 and the surrounding portion 2121 may be formed by a single thin film deposition process. Thus, the second extension portion 2122 and the surrounding portion 2121 may be an integral structure, with the same material and no obvious interface between them. It should be noted that in the semiconductor device 200, when the first insulating layer 212 does not include the second extension portion 2122, the respective surrounding portions 2121 are arranged at intervals from each other.

[0056] The following combines Figure 2B to make an exemplary description of the transistor in the semiconductor device 200. In some embodiments, as Figure 2B shown, the semiconductor device 200 may further include a channel structure 217, gate structures 218-1, 218-2, gate dielectric layers 219-1, 219-2, bit line structures 220, and insulating structures 221. The above structures may all be located on the side of the connection structures 215-1, 215-2 away from the conductive pillars 211 (refer to Figure 2A ).

[0057] In some embodiments, the channel structure 217 may include a first side portion 2171, a second side portion 2172, and a connecting portion 2173. The first side portion 2171 and the second side portion 2172 are arranged in the x direction, and the connecting portion 2173 is connected to the first ends of the first side portion 2171 and the second side portion 2172 in the z direction. For example, when viewed from the y direction, the first side portion 2171, the second side portion 2172, and the connecting portion 2173 may be generally in an inverted U shape. The first side portion 2171, the second side portion 2172, and the connecting portion 2173 (i.e., the channel structure 217) may be formed by the same thin film deposition process. Thus, the channel structure 217 may be an integral structure. The material of the channel structure 217 may include one or more of semiconductor materials such as polysilicon (poly-Si), amorphous silicon (α-Si), metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)). When the material of the channel structure 217 is a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), the channel leakage current can be significantly reduced, the data retention characteristics can be improved, and a better sense margin can also be achieved.

[0058] In some embodiments, the channel structure 217 may further include third extension portions 2174-1 and 2174-2. The third extension portions 2174-1 and 2174-2 are respectively connected to the second ends of the first side portion 2171 and the second side portion 2172 in the z direction and extend in a direction away from the first side portion 2171 and the second side portion 2172. Among them, the third extension portion 2174-1 is in contact with the connection structure 215-1, and the third extension portion 2174-2 is in contact with another connection structure 215-2. The third extension portions 2174-1 and 2174-2 are beneficial to increasing the contact area between the channel structure 217 and the connection structures 215-1 and 215-2 and improving the electrical connection performance (e.g., increasing the current transmission efficiency).

[0059] In some embodiments, a plurality of channel structures 217 may be arranged at intervals in the x direction and the y direction. For example, the connecting portions 2173 of the plurality of channel structures 217 arranged in the x direction are not connected to each other.

[0060] In some embodiments, the gate dielectric layers 219-1 and 219-2 are respectively located on the surfaces of the first side portion 2171 and the second side portion 2172 facing away from each other. For example, the gate dielectric layers 219-1 and 219-2 may also cover the surfaces of the third extension portions 2174-1 and 2174-2. The materials of the gate dielectric layers 219-1 and 219-2 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) one or more of high-k dielectric materials or any other suitable insulating materials. For example, the materials of the gate dielectric layers 219-1 and 219-2 may include high-k dielectric materials such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), etc.

[0061] In some embodiments, the gate structures 218-1 and 218-2 may be respectively located on the surfaces of the gate dielectric layers 219-1 and 219-2 and extend in the y direction (e.g., continuously extend). For example, the gate structure 218-1 may be located on the surface of the gate dielectric layer 219-1 of a column of channel structures 217 arranged in the y direction, and the gate structure 218-2 may be located on the surface of another gate dielectric layer 219-2 of the above-mentioned column of channel structures 217. In some examples, the gate structure 218-1 (or the gate structure 218-2) may include an adhesion layer 2181 and a metal layer 2182 that are bonded to each other. The adhesion layer 2181 is in contact with the gate dielectric layer 219-1 and extends to the end face of the metal layer 2182 close to the connection structure 215-1. For example, viewed from the y direction, the adhesion layer 2181 may be generally L-shaped. Part of the adhesion layer 2181 is located between the metal layer 2182 and the gate dielectric layer 219-1, which helps to improve the bonding performance between the metal layer 2182 and the gate dielectric layer 219-1. The material of the adhesion layer 2181 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable materials. The material of the metal layer 2182 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), or any other suitable metal materials. In other examples, the gate structure 218-1 (or the gate structure 218-2) may not have a composite layer structure but be composed of a single conductive material, and the present application does not make specific limitations thereon.

[0062] According to the above description, for example, the first side portion 2171, the gate dielectric layer 219-1, and the portion of the gate structure 218-1 corresponding to the first side portion 2171 can form a transistor T. In the transistor T, the first side portion 2171 can serve as a channel, the portion of the gate structure 218-1 corresponding to the first side portion 2171 can serve as a gate, and the first end and the second end of the first side portion 2171 can respectively serve as one of the source and the drain. The gate structure 218-1 extending in the y direction can connect the respective gates of a column of transistors T arranged in the y direction to each other. Combining Figure 2A , the transistor T can be located on the side of the connection structure 215-1 away from the conductive pillar 211, and one of the source or the drain of the transistor T is connected to the connection structure 215-1. For example, one of the source or the drain of the transistor T is connected to the first electrode in the capacitor described above through the connection structure 215-1 to form a storage unit. For example, the storage unit may include a DRAM storage unit.

[0063] In some embodiments, the insulating structure 221 may be located in the space surrounded by the first side portion 2171, the second side portion 2172, and the connecting portion 2173. The material of the insulating structure 221 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. In some other embodiments, a shielding structure (not shown) may be provided in the space surrounded by the first side portion 2171, the second side portion 2172, and the connecting portion 2173. For example, by applying a voltage (e.g., a negative voltage or a ground voltage) to the shielding structure, the coupling effect between adjacent transistors T can be improved, which also helps to reduce the off-state current I off and the subthreshold voltage swing of the transistor T, and adjust the threshold voltage V t of the transistor T, so as to comprehensively optimize the electrical performance of the transistor T.

[0064] In some embodiments, continuing to refer to Figure 2B , the bit line structure 220 may extend in the x direction (e.g., continuously extend) and be connected (e.g., in contact) to the connecting portion 2173 in the channel structure 217. The bit line structure 220 may be connected (e.g., in contact) to each of the connecting portions 2173 in a row of channel structures 217 arranged in the x direction. In other words, one of the source or drain of a row of transistors T arranged in the x direction is connected (e.g., in contact) to the same bit line structure 220. The material of the bit line structure 220 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material.

[0065] Figure 3 is a cross-sectional schematic diagram of a semiconductor device provided by another embodiment of the present application. For the purpose of concise description, the same components as those in the previous embodiment will not be described again in this embodiment.

[0066] As shown in Figure 3As shown, the semiconductor device 300 includes a conductive pillar 311, a first insulating layer 312, a conductive layer 313, and an isolation layer 314. Among them, the first insulating layer 312 includes a surrounding portion 3121 located on the sidewall of the conductive pillar 311. The conductive layer 313 and the isolation layer 314 are both located on the outer periphery of the surrounding portion 3121 and are arranged in the z direction. There is a spacing distance d3 between the first end face 3111 of the conductive pillar 311 close to the isolation layer 314 and the surface 3131 of the conductive layer 313 close to the isolation layer 314. Optionally, the semiconductor device 300 may further include a connection structure 315 located on the first end face 3111 of the conductive pillar 311. The connection structure 315 can penetrate the second insulating layer 316.

[0067] In some embodiments, the first insulating layer 312 may further include a first extension portion 3123 located on the first end face 3111. For example, the first extension portion 3123 covers a part of the first end face 3111. For example, the first extension portion 3123 and the surrounding portion 3121 can be formed by a single thin film deposition process. Thus, the first extension portion 3123 and the surrounding portion 3121 can be an integral structure, with the same material and no obvious interface between them. In the semiconductor device 300, the second insulating layer 316 can be in contact with the first extension portion 3123.

[0068] In this embodiment, through the isolation layer 314, the risk of short - circuit between the lead - out structure (e.g., the connection structure 315) of the conductive pillar 311 and the conductive layer 313 can be reduced, the process difficulty of preparing the lead - out structure (e.g., the connection structure 315) can be reduced, the process window for preparing the lead - out structure (e.g., the connection structure 315) can be increased, and the lead - out structure (e.g., the connection structure 315) can be allowed to have a larger lateral dimension, thereby improving the current transmission effect between the conductive pillar 311 and the lead - out structure (e.g., the connection structure 315). In addition, the first insulating layer 312 has the first extension portion 3123, which can further reduce the process difficulty of preparing the lead - out structure (e.g., the connection structure 315), improve the connection reliability between the conductive pillar 311 and its lead - out structure (e.g., the connection structure 315), and improve the yield of the semiconductor device 300.

[0069] The embodiment of the present application also provides a memory system. Figure 4 It is a block diagram of a system with a memory system provided by the embodiment of the present application.

[0070] As Figure 4As shown, the system 400 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (which has a memory system 410 located therein). As Figure 4 shown, the system 400 can include a host 420 and a memory system 410. The memory system 410 can have one or more memories 411 and a controller 412. Among them, the memory 411 can include semiconductor devices as described in the above embodiments (for example, Figure 2A and Figure 2B the semiconductor device 200 shown or Figure 3 the semiconductor device 300 shown). The host 420 can be a processor of the electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 420 can be configured to send or receive data to and from the memory 411.

[0071] In some embodiments, the controller 412 can be coupled to the memory 411 and the host 420, and is configured to control the memory 411. For example, the controller 412 can be configured to control the memory 411 to perform operations such as reading, erasing, and programming. The controller 412 can also manage the data stored in the memory 411 and communicate with the host 420. For example, the controller 412 can communicate with an external device (such as the host 420) according to a specific communication protocol.

[0072] The embodiment of the present application also provides a manufacturing method of a semiconductor device. Figure 5 is a schematic flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present application. As Figure 5 shown, the manufacturing method 500 of the semiconductor device (hereinafter simply referred to as the manufacturing method 500) can include the following steps.

[0073] S510, forming a conductive pillar and forming a surrounding portion covering the sidewall of the conductive pillar.

[0074] S520, forming a conductive layer in a partial space on the outer periphery of the surrounding portion, wherein there is a spacing distance between the surface of the conductive layer close to the first end face of the conductive pillar and the first end face.

[0075] S530, forming an isolation layer on a side of the conductive layer close to the first end face.

[0076] According to the manufacturing method of the semiconductor device provided by the embodiments of the present application, by forming a conductive layer in a partial space on the outer periphery of the surrounding portion, and making there be a spacing distance between the surface of the conductive layer close to the first end face of the conductive column and the first end face, and forming an isolation layer on the side of the conductive layer close to the first end face, it helps to reduce the process difficulty of preparing the lead-out structure of the conductive column, improve the process window for preparing the lead-out structure, and allow the lead-out structure to have a larger lateral dimension, thereby improving the current transmission effect between the conductive column and the lead-out structure.

[0077] Figures 6A to 6H is a cross-sectional schematic diagram of the semiconductor device provided by the embodiments of the present application during the manufacturing process. For example, Figures 6A to 6H can be used to form Figure 2A and Figure 2B the semiconductor device 200 shown. The following will be described by way of example with respect to Figures 6A to 6H the above steps S510 to S530.

[0078] S510

[0079] Figures 6A to 6C shows the intermediate structures 600a to 600c during the formation of the conductive column 611. Figure 6D shows the intermediate structure 600d after the formation of the surrounding portion 6121. Among them, Figure 6A shows the intermediate structure 600a including the substrate 630, the sacrificial layer 631, and the opening 632. Figure 6B shows the intermediate structure 600b after forming the conductive column 611 in the opening 632. Figure 6C shows the intermediate structure 600c after removing the sacrificial layer 631.

[0080] In some embodiments, such as Figure 6AAs shown, a sacrificial layer 631 can be formed on one side of a substrate 630 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The sacrificial layer 631 can extend laterally in the x direction and the y direction. For example, the substrate 630 can serve as a carrier and be removed in subsequent processes. The substrate 630 can include a semiconductor substrate. For example, the substrate 630 can include a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc. Also, for example, the substrate 630 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate, etc. The material of the sacrificial layer 631 can include silicon dioxide (SiO2). Optionally, a material layer 633 can be formed between the sacrificial layer 631 and the substrate 630.

[0081] Further, an opening 632 penetrating the sacrificial layer 631 can be formed by an etching process (e.g., dry etching and / or wet etching). For example, a plurality of openings 632 can be formed in an array arrangement in the x direction and the y direction using the same mask. Then, as Figure 6B shown, a conductive material can be filled in the opening 632 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form a conductive pillar 611. Optionally, during the formation of the conductive pillar 611, the conductive material can cover the surface of the sacrificial layer 631 away from the substrate 630 (not shown). In this case, a chemical mechanical polishing (CMP) process can be used for planarization to expose the sacrificial layer 631. Subsequently, the sacrificial layer 631 can be removed by an etching process (e.g., wet etching), as Figure 6C shown. For example, after the above process, a plurality of conductive pillars 611 can be arranged in an array on a plane perpendicular to the z direction.

[0082] In some embodiments, as Figure 6DAs shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a first insulating layer 612 on the sidewalls and top of the conductive pillar 611 and on the surface of, for example, the material layer 633. Among them, the part of the first insulating layer 612 covering the sidewall of the conductive pillar 611 can be the surrounding part 6121. The part of the first insulating layer 612 covering the first end face 6111 of the conductive pillar 611 can be the initial first extension part 6123'. The part of the first insulating layer 612 covering, for example, the material layer 633 can be the second extension part 6122. In other words, the second extension part 6122 can be formed at the end of the surrounding part 6121 far from the initial first extension part 6123'. When a plurality of conductive pillars 611 are arranged in an array on a plane perpendicular to the z direction, the second extension part 6122 can connect adjacent surrounding parts 6121. It should be noted that after the first insulating layer 612 is formed, an etching process (for example, dry etching and / or wet etching) can be used to remove the second extension part 6122, and the present application does not limit this.

[0083] S520

[0084] Figure 6E The intermediate structure 600e after the formation of the conductive layer 613 is shown.

[0085] In some embodiments, continuing to refer to Figure 6D , a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form an initial conductive layer 613' on the outer periphery of the surrounding part 6121 and on the surface of the initial first extension part 6123' far from the substrate 630. Subsequently, an etching process (for example, wet etching) can be used to remove a part of the initial conductive layer 613' close to the first end face 6111 of the conductive pillar 611 to form the conductive layer 613, as Figure 6E shown. For example, during the process of removing part of the initial conductive layer 613', the etching process parameters (for example, etching rate and / or etching time) can be controlled so that there is a spacing distance d3 between the surface 6131 of the conductive layer 613 close to the first end face 6111 of the conductive pillar 611 and the first end face 6111. As another option, the thin film deposition process parameters can be controlled so that the conductive layer 613 is formed in a part of the space on the outer periphery of the surrounding part 6121, and the surface 6131 of the conductive layer 613 has a spacing distance d3 from the first end face 6111.

[0086] S530

[0087] Figure 6F The intermediate structure 600f after the formation of the initial isolation layer 614' is shown. Figure 6G The intermediate structure 600g after the formation of the isolation layer 614 is shown.

[0088] In some embodiments, such as Figure 6E and Figure 6F shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form an initial isolation layer 614' in the space formed after removing a part of the initial conductive layer 613' (refer to Figure 6D ) and on the side (e.g., surface) of the initial first extension 6123' away from the conductive pillar 611. Subsequently, a CMP process can be used to remove a part of the initial isolation layer 614' located on the side (e.g., surface) of the initial first extension 6123' away from the conductive pillar 611 and the initial first extension 6123' until the first end face 6111 of the conductive pillar 611, thereby forming the isolation layer 614, as Figure 6G shown. After the above process treatment, the first end face 6111 of the conductive pillar 611, the end face of the surrounding portion 6121 away from the conductive layer 613, and the surface of the isolation layer 614 away from the conductive layer 613 are substantially flush (e.g., the error is less than ±10%).

[0089] In some embodiments, the manufacturing method 500 may further include the step of forming a connection structure on the first end face 6111. Figure 6H shows the semiconductor device 600 after forming the connection structure 615. Exemplarily, first, a second insulating layer 616 can be formed on the surface of the isolation layer 614 away from the conductive layer 613 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. For example, the second insulating layer 616 can extend laterally in the x direction and the y direction and cover the first end face 6111 of the conductive pillar 611, the end face of the surrounding portion 6121 away from the conductive layer 613, and the surface of the isolation layer 614 away from the conductive layer 613. Then, as Figure 6H shown, an etching (e.g., dry etching and / or wet etching) process can be used to form a connection hole (corresponding to the outer contour of the connection structure 615) penetrating through the second insulating layer 616 to the first end face 6111. The connection hole can expose the first end face 6111 of the conductive pillar 611. Optionally, the connection hole can also expose the surrounding portion 6121 and the isolation layer 614. Then, a conductive material can be filled in the connection hole by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof to form the connection structure 615.

[0090] In some embodiments, after forming the connection structure 615, the manufacturing method 500 may further include the step of forming a transistor. Referring to Figure 2B , any known process in the art can be used to form a transistor T on the side of the connection structure 215-1 away from the conductive pillar 611 (refer to Figure 6H ). One of the source or drain of the transistor T is connected to the connection structure 215-1.

[0091] In the above embodiment, by forming a conductive layer 613 in a partial space on the outer periphery of the surrounding portion 6121, and making there be a spacing distance d3 between the surface 6131 of the conductive layer 613 close to the first end face 6111 of the conductive column 611 and the first end face 6111, and forming an isolation layer 614 on the side of the conductive layer 613 close to the first end face 6111, it helps to reduce the process difficulty of fabricating the lead-out structure (e.g., the connection structure 615) of the conductive column 611, improve the process window for fabricating the lead-out structure (e.g., the connection structure 615), and allow the lead-out structure (e.g., the connection structure 615) to have a larger lateral dimension, thereby improving the current transmission effect between the conductive column 611 and the lead-out structure (e.g., the connection structure 615).

[0092] Figure 7A and Figure 7B FIG. is a cross-sectional schematic view of a semiconductor device provided in another embodiment of the present application during manufacturing. Among them, steps S510 and S520 can be executed by using the same process method as in the previous embodiment. For the purpose of concise description, they will not be elaborated in this embodiment. For example, Figure 7A and Figure 7B can be used to form Figure 3 the semiconductor device 300 shown. The following combines Figure 7A and Figure 7B to give an exemplary illustration of the above step S530.

[0093] S530

[0094] Figure 7A FIG. shows the intermediate structure 700a after forming the isolation layer 714.

[0095] In some embodiments, as Figure 6F and Figure 7A shown, during the process of removing a part of the initial isolation layer 614' to form the isolation layer 714, CMP can be used to remove a part of the initial isolation layer 614' located on the side of the initial first extension portion 7123' away from the conductive column 711 to the initial first extension portion 7123' to form the isolation layer 714. After the above process treatment, the surface of the initial first extension portion 7123' and the isolation layer 714 away from the conductive layer 713 are substantially flush (e.g., the error is less than ±10%). In this embodiment, the initial first extension portion 7123' can be used as a stop layer for the CMP process, thereby facilitating the reduction of the control difficulty of the CMP process. For example, when the material of the initial first extension portion 7123' is a high-k material and the material of the initial isolation layer 614' is silicon oxide (SiO2), the initial first extension portion 7123' can be used as a stop layer for removing a part of the initial isolation layer 614'.

[0096] In some embodiments, the manufacturing method 500 may further include the step of forming a connection structure. Figure 7B A semiconductor device 700 after forming the connection structure 715 is shown. Exemplarily, first, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a second insulating layer 716 on the surface of the isolation layer 714 away from the conductive layer 713. For example, the second insulating layer 716 may extend laterally in the x and y directions and cover the initial first extension portion 7123' and the surface of the isolation layer 714 away from the conductive layer 713. Then, as Figure 7B shown, an etching process (e.g., dry etching and / or wet etching) may be used to form a connection hole (corresponding to the outer contour of the connection structure 715) that penetrates through the second insulating layer 716 and the initial first extension portion 7123' to the first end face 7111. The connection hole may expose the first end face 7111 of the conductive pillar 711. Optionally, the connection hole may also expose the surrounding portion 7121 and the isolation layer 714. During the formation of the connection hole, a part of the initial first extension portion 7123' is removed and thus transformed into the first extension portion 7123, as Figure 7B shown. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the connection hole with a conductive material to form the connection structure 715. In this embodiment, since the first end face 7111 of the conductive pillar 711 has the initial first extension portion 7123', the initial first extension portion 7123' can also serve as an etching stop layer for the connection hole. During the etching of the connection hole, the connection hole first stops at the initial first extension portion 7123' and then is further etched to expose the first end face 7111 of the conductive pillar 711, which is beneficial for reducing the control difficulty of etching the connection hole and can also cope with the over-etching of the conductive pillar 711.

[0097] The above description is only for the embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A conductive column; A first insulating layer, including a surrounding portion located on the side wall of the conductive column; And A conductive layer and an isolation layer, both located on the outer periphery of the surrounding portion, wherein the conductive layer and the isolation layer are arranged along the extending direction of the conductive column, and there is a spacing distance between the first end face of the conductive column close to the isolation layer and the surface of the conductive layer close to the isolation layer.

2. The semiconductor device according to claim 1, wherein, Further comprising: A connection structure, located on the first end face of the conductive column.

3. The semiconductor device according to claim 2, wherein, The connection structure is in contact with the isolation layer.

4. The semiconductor device according to claim 2, wherein Further comprising: A second insulating layer, located on the side of the isolation layer away from the conductive layer, and the connection structure penetrates through the second insulating layer.

5. The semiconductor device according to claim 4, wherein, The second insulating layer is in contact with the first end face of the conductive column.

6. The semiconductor device according to claim 4, wherein, The first insulating layer further includes a first extension portion located on the first end face, wherein the second insulating layer is in contact with the first extension portion.

7. The semiconductor device according to claim 2, wherein, In a plane perpendicular to the extending direction of the conductive column, the size of the connection structure is less than or equal to the size of the surrounding portion.

8. The semiconductor device according to claim 2, wherein, The connection structure and the conductive column are coaxially or eccentrically arranged.

9. The semiconductor device according to any one of claims 1 to 6, wherein, In a plane perpendicular to the extending direction of the conductive column, a plurality of the conductive columns and a plurality of the surrounding portions are arranged in an array; The first insulating layer further includes a second extension portion, and the second extension portion is located at an end of the surrounding portion away from the isolation layer and connects adjacent surrounding portions.

10. The semiconductor device according to claim 2, wherein, Further comprising: A transistor, located on the side of the connection structure away from the conductive column; Wherein, one of the source or drain of the transistor is connected to the connection structure.

11. A memory system, characterized in that, Comprising: A memory, including the semiconductor device according to any one of claims 1 to 10; And A controller, coupled to the memory, for controlling the memory to store data.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a conductive column and forming a surrounding portion covering the side wall of the conductive column; Forming a conductive layer in a partial space on the outer periphery of the surrounding portion, wherein there is a spacing distance between the surface of the conductive layer close to the first end face of the conductive column and the first end face; and Forming an isolation layer on the side of the conductive layer close to the first end face.

13. The manufacturing method according to claim 12, wherein, Further comprising: Forming a connection structure on the first end face.

14. The manufacturing method according to claim 12, wherein, Forming a conductive column includes: Forming a sacrificial layer; Forming an opening penetrating through the sacrificial layer and forming the conductive column in the opening; and Removing the sacrificial layer.

15. The manufacturing method according to claim 13, wherein, During the process of forming the surrounding portion, an initial first extension portion covering the first end face of the conductive column is formed by a thin film deposition process.

16. The manufacturing method according to claim 15, wherein, In a plane perpendicular to the extending direction of the conductive column, a plurality of the conductive columns are arranged in an array; Wherein, during the process of forming the surrounding portion and the initial first extension portion, a second extension portion is formed at an end of the surrounding portion away from the initial first extension portion by the thin film deposition process, and the second extension portion connects adjacent surrounding portions.

17. The manufacturing method according to claim 15, wherein Forming a conductive layer in a partial space on the outer periphery of the surrounding portion includes: Forming an initial conductive layer on the outer periphery of the surrounding portion; and Removing a part of the initial conductive layer close to the first end face to form the conductive layer.

18. The manufacturing method according to claim 17, wherein Forming an isolation layer on the side of the conductive layer close to the first end face includes: An initial isolation layer is formed in a space formed after removing a part of the initial conductive layer and on a side of the initial first extension away from the conductive pillar; A part of the initial isolation layer located on a side of the initial first extension away from the conductive pillar is removed to the initial first extension by a mechano-chemical polishing process to form the isolation layer.

19. The manufacturing method according to claim 18, wherein, The method further includes: Removing the initial first extension by the mechano-chemical polishing process.

20. The manufacturing method according to claim 18, wherein The method further includes: Forming a second insulating layer on a surface of the isolation layer away from the conductive layer and the initial first extension; Wherein, forming a connection structure on the first end face includes: Forming the connection structure penetrating through the second insulating layer and the initial first extension to the first end face.

21. The manufacturing method according to claim 13, wherein, After forming the connection structure on the first end face, the method further includes: Forming a transistor on a side of the connection structure away from the conductive pillar, wherein one of the source or drain of the transistor is connected to the connection structure.

Images