Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first stacked structure, a second stacked structure, a first vertical connector and a second vertical connector. The first stacked structure comprises a first stacked wafer and a first bonding layer, and the first stacked wafer comprises a plurality of first dielectric bonding interfaces. The second stacked structure includes a second stacked wafer and a second bonding layer. The second stacked wafer includes a plurality of second dielectric bonding interfaces. The first bonding layer is bonded and electrically connected to the second bonding layer such that there is a hybrid bonding interface between the first stacked structure and the second stacked structure. The first vertical connectors pass through the plurality of first dielectric bonding interfaces and are electrically connected to the first bonding layer. The second vertical connectors pass through the plurality of second dielectric bonding interfaces and are electrically connected to the second bonding layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] At present, many direct bonding technologies have been applied to semiconductor wafer stacking structures. However, these direct bonding technologies have limitations in bonding ability, routing design, or manufacturing cost, which further causes a bottleneck in the number of stacked layers and cannot be broken through. Therefore, how to meet the growing demand for the number of stacked layers is actually a challenge. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, which can effectively increase the number of stacked layers.

[0004] A semiconductor device of the present invention includes a first stacking structure, a second stacking structure, a first vertical connecting member, and a second vertical connecting member. The first stacking structure includes a first stacked wafer and a first bonding layer. The first stacked wafer includes a plurality of first dielectric bonding interfaces. The second stacking structure includes a second stacked wafer and a second bonding layer. The second stacked wafer includes a plurality of second dielectric bonding interfaces. The first bonding layer is bonded and electrically connected to the second bonding layer, so that there is a hybrid bonding interface between the first stacking structure and the second stacking structure. The first vertical connecting member penetrates through a plurality of first dielectric bonding interfaces and is electrically connected to the first bonding layer. The second vertical connecting member penetrates through a plurality of second dielectric bonding interfaces and is electrically connected to the second bonding layer.

[0005] In an embodiment of the present invention, the above-mentioned first stacking structure includes a plurality of first device wafers, and one of the plurality of first dielectric bonding interfaces is located between two adjacent ones of the plurality of first device wafers. The second stacking structure includes a plurality of second device wafers, and one of the plurality of second dielectric bonding interfaces is located between two adjacent ones of the plurality of second device wafers.

[0006] In an embodiment of the present invention, the number of the plurality of first device wafers is greater than or equal to three, and the number of the plurality of second device wafers is greater than or equal to three.

[0007] In an embodiment of the present invention, each of the above-mentioned first dielectric bonding interfaces is composed of a first dielectric material, each of the second dielectric bonding interfaces is composed of a second dielectric material, and the hybrid bonding interface is composed of a third dielectric material and a conductive material.

[0008] In an embodiment of the present invention, the tapered profile directions of the above-mentioned first vertical connecting member and the second vertical connecting member are the same.

[0009] In an embodiment of the present invention, the above-mentioned first vertical connector tapers away from the hybrid bonding interface, and the second vertical connector tapers towards the hybrid bonding interface.

[0010] In an embodiment of the present invention, the above-mentioned first stacked structure includes a series-connected layer, and two sides of the first vertical connector are directly in contact with the series-connected layer and the first bonding layer respectively.

[0011] In an embodiment of the present invention, at least two of the above-mentioned first vertical connectors are arranged adjacent to each other on the series-connected layer, and at least two second vertical connectors are correspondingly arranged on at least two first vertical connectors.

[0012] In an embodiment of the present invention, the above-mentioned semiconductor device further includes an external terminal arranged on the second vertical connector. The first vertical connector, the second vertical connector and the external terminal are stacked in sequence and electrically connected to each other.

[0013] In an embodiment of the present invention, the pads of the first bonding layer are in direct contact with the pads of the second bonding layer, and the dielectric layers of the first bonding layer are in direct contact with the dielectric layers of the second bonding layer.

[0014] In an embodiment of the present invention, the above-mentioned first stacked structure further includes a plurality of first signal lines. The second stacked structure further includes a plurality of second signal lines. The plurality of first signal lines are electrically connected to the first vertical connectors, and the plurality of second signal lines are electrically connected to the second vertical connectors.

[0015] A manufacturing method of a semiconductor device according to the present invention at least includes the following steps. Form a first stacked structure, which includes forming a first stacked wafer through a plurality of first direct bonding manufacturing processes, so that the first stacked wafer includes a plurality of first dielectric bonding interfaces; and forming a first bonding layer on the first stacked wafer. Form a second stacked structure, which includes forming a second stacked wafer through a plurality of second direct bonding manufacturing processes, so that the second stacked wafer includes a plurality of second dielectric bonding interfaces; and forming a second bonding layer on the second stacked wafer. Bond and electrically connect the first bonding layer and the second bonding layer through a third direct bonding manufacturing process, so that a hybrid bonding interface is formed between the first bonding layer and the second bonding layer. Form a second vertical connector to penetrate through a plurality of second dielectric bonding interfaces and electrically connect to the second bonding layer. The first vertical connector and the second vertical connector are electrically connected through the first bonding layer and the second bonding layer.

[0016] In an embodiment of the present invention, the above-mentioned plurality of first direct bonding manufacturing processes and the plurality of second direct bonding manufacturing processes are oxide bonding manufacturing processes, and the third direct bonding manufacturing process is a hybrid bonding manufacturing process.

[0017] In an embodiment of the present invention, the steps of each of the above-mentioned first direct bonding manufacturing processes and each of the second direct bonding manufacturing processes include bonding two component wafers such that the top dielectric layer of one of the two component wafers is in direct contact with the bottom dielectric layer of the other of the two component wafers.

[0018] In an embodiment of the present invention, between adjacent ones of the above-mentioned multiple first bonding manufacturing processes and between adjacent ones of the multiple second bonding manufacturing processes, a thinning manufacturing process is performed.

[0019] In an embodiment of the present invention, after bonding the first bonding layer and the second bonding layer through the above-mentioned third direct bonding manufacturing process, a second vertical connection member is formed.

[0020] In an embodiment of the present invention, the number of the above-mentioned multiple first direct bonding manufacturing processes is greater than or equal to two, and the number of the multiple second direct bonding manufacturing processes is greater than or equal to two.

[0021] In an embodiment of the present invention, neither the above-mentioned multiple first direct bonding manufacturing processes nor the multiple second direct bonding manufacturing processes include metal-to-metal bonding.

[0022] In an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor device further includes forming external terminals on the second vertical connection member.

[0023] In an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor device further includes: forming a plurality of first signal lines on the first stacked structure; and forming a plurality of second signal lines on the second stacked structure.

[0024] Based on the above, the present invention connects multiple stacked wafers through a hybrid bonding interface, thereby providing the required bonding strength for the semiconductor device, and respectively performing stacking within the multiple stacked wafers through a dielectric bonding interface, and then conducting through the vertical connection members for each layer to simplify the wiring density within the semiconductor device. In this way, a balance can be achieved among the bonding ability, wiring design, and manufacturing cost, and the stacking layer number can be effectively increased.

[0025] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given, and detailed descriptions are provided in conjunction with the accompanying drawings as follows. Description of the Drawings

[0026] Figures 1A to 1L is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0028] Symbol Description

[0029] 100, 200: Semiconductor device

[0030] 110, 120: Stacked wafers

[0031] 111, 112, 113, 114, 121, 122, 123, 124: Component wafers

[0032] 111a, 112a, 113a, 114a, 121a, 122a, 123a, 124a: Substrates

[0033] 111b, 112b, 112c, 113b, 113c, 114b, 114c, 116b, 121b, 121c, 122b, 122c, 123b, 123c, 124b, 124c, 126b, 130b: Dielectric layers

[0034] 111c: Tandem layer

[0035] 112r, 121r, 122r: Backs

[0036] 115, 125: Vertical connectors

[0037] 116, 126: Bonding layers

[0038] 116a, 126a: Pads

[0039] 130: External layer

[0040] 130a: Circuitry

[0041] 131: External terminals

[0042] 132: Protective layer

[0043] 241, 242: Signal lines

[0044] S1, S2: Dielectric bonding interfaces

[0045] S3: Hybrid bonding interface

[0046] T1, T2, T3, T4: Top surfaces Detailed implementation

[0047] In the following detailed description, for purposes of illustration and not limitation, exemplary embodiments are set forth that disclose specific details in order to provide a thorough understanding of the various principles of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention may be practiced in other embodiments that depart from the specific details disclosed herein. Additionally, descriptions of well-known devices, methods, and materials may be omitted so as not to obscure the description of the various principles of the present invention.

[0048] Exemplary embodiments of the present invention will be described fully hereinafter with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the sizes and thicknesses of regions, portions, and layers may not be drawn to actual scale for clarity. The same or similar reference numerals denote the same or similar elements, and a detailed description thereof will not be repeated in the following paragraphs.

[0049] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0051] Figures 1A to 1L is a cross-sectional schematic view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0052] Please refer to Figures 1A to 1D , in this embodiment, the manufacturing process of the stacked wafer 110 may at least include the following steps. First, as Figure 1A shown, a device wafer 111 and a device wafer 112 are provided, and the device wafer 111 and the device wafer 112 are bonded by a direct bonding manufacturing process to form a dielectric bonding interface S1. The device wafer 111 may include a substrate 111a and a dielectric layer 111b disposed thereon, the device wafer 112 may include a substrate 112a and a dielectric layer 112b disposed thereon, and the dielectric layer 111b and the dielectric layer 112b are in direct contact.

[0053] In some embodiments, the aforementioned direct bonding manufacturing process is, for example, an oxide-oxide bonding (which may also be referred to as fusion bonding) manufacturing process. Therefore, the direct bonding manufacturing process may not include metal-to-metal bonding, but the present invention is not limited thereto.

[0054] In this embodiment, the component wafer 111 further includes a serial connection layer 111c disposed on the substrate 111a and covered by the dielectric layer 111b to serve as subsequent internal connection lines. On the other hand, the substrate 112a of the component wafer 112 has a plurality of grooves, and the dielectric layer 112b can fill the aforementioned grooves and further extend onto the surface of the substrate 112a to engage with the dielectric layer 111b. Here, the serial connection layer 111c can be a redistribution layer (RDL) or the like.

[0055] Please refer to Figure 1B , after forming the dielectric bonding interface S1, a thinning manufacturing process is performed to remove a part of the back 112r of the component wafer 112 (such as the back of the substrate 112a), and the thinning manufacturing process can continuously thin in the direction of the component wafer 111 until the dielectric layer 112b is exposed. Here, the thinning manufacturing process is, for example, a chemical-mechanical polishing (CMP) manufacturing process or the like.

[0056] Please refer to Figure 1C , after performing the thinning manufacturing process, a dielectric layer 112c is formed on the substrate 112a for another direct bonding manufacturing process. Then, the component wafer 113 is provided, and the component wafer 113 and the component wafer 112 are bonded through a direct bonding manufacturing process similar to Figure 1A to form another dielectric bonding interface S1, where the component wafer 113 includes a substrate 113a and a dielectric layer 113b disposed thereon, and the dielectric layer 113b is in direct contact with the dielectric layer 112c. Here, the substrate 113a of the component wafer 113 has a plurality of grooves, and the dielectric layer 113b can fill the aforementioned grooves and further extend onto the surface of the substrate 113a to engage with the dielectric layer 112c.

[0057] Please refer to Figure 1D , repeat Figures 1B to 1C steps. In short, a thinning manufacturing process can be performed to remove a part of the back (not shown) of the component wafer 113. Then, a dielectric layer 113c is formed on the substrate 113a. Then, the component wafer 114 is provided, and the component wafer 114 and the component wafer 113 are bonded through a direct bonding manufacturing process similar to Figure 1A to form another dielectric bonding interface S1, where the component wafer 114 includes a substrate 114a and a dielectric layer 114b disposed thereon, and the dielectric layer 114b is in direct contact with the dielectric layer 113c. After bonding the component wafer 114, the thinning manufacturing process (not shown) is performed again and a dielectric layer 114c is formed on the substrate 114a. Through the above steps, the manufacturing of the stacked wafer 110 is substantially completed.

[0058] Furthermore, after the foregoing steps, the component wafer 112 may include a substrate 112a and dielectric layers 112b and 112c that are interconnected and surround the substrate 112a. The component wafer 113 may include a substrate 113a and dielectric layers 113b and 113c that are interconnected and surround the substrate 113a. And the component wafer 114 may include a substrate 114a and dielectric layers 114b and 114c that are interconnected and surround the substrate 114a.

[0059] It should be noted that although Figures 1A to 1D illustrates the direct bonding and stacking patterns of four component wafers (component wafers 111, 112, 113, and 114), the present invention does not limit the direct bonding manufacturing process and the stacking quantity of the first component wafer. Depending on the actual design requirements, the above stacking steps may be repeated multiple times to a predetermined stacking layer number. For example, the predetermined stacking layer number may be greater than or equal to three. Therefore, the number of component wafers of the stacked wafer 110 may be greater than or equal to three, and the number of direct bonding manufacturing processes may be greater than or equal to two.

[0060] Please refer to Figure 1E , after stacking the predetermined stacking layer number (such as Figure 1D the four layers in ), a vertical connector 115 (which may be referred to as the first vertical connector) that penetrates the dielectric bonding interface S1 may be formed. For example, in this embodiment, the vertical connector 115 may sequentially penetrate the dielectric layer 114c, the dielectric layer 114b, the dielectric layer 113c, the dielectric layer 113b, the dielectric layer 112c, the dielectric layer 112b, and the dielectric layer 111b from top to bottom and land on the series connection layer 111c. Therefore, the vertical connector 115 may be referred to as a through dielectric via (TDV), but the present invention is not limited thereto.

[0061] Next, a bonding layer 116 is formed on the stacked wafer 110, where the stacked wafer 110 and the bonding layer 116 may be regarded as a stacked structure. Furthermore, the bonding layer 116 includes a plurality of pads 116a and a dielectric layer 116b, where the dielectric layer 116b may surround the pads 116a, and the top surface T1 of the pads 116a and the top surface T2 of the dielectric layer 116b may be substantially coplanar.

[0062] In this embodiment, the vertical connector 115 is located between the series connection layer 111c and the bonding layer 116. For example, two sides of the vertical connector 115 are directly in contact with the series connection layer 111c and the bonding layer 116 respectively, but the present invention is not limited thereto.

[0063] It should be noted that the foregoing stacked structure and the components included therein may be referred to as "first". For example, the stacked structure may be referred to as the first stacked structure, the stacked wafer 110 may be referred to as the first stacked wafer, the component wafers 111, 112, 113, 114 may be referred to as a plurality of first component wafers, the direct bonding manufacturing process used may be referred to as the first direct bonding manufacturing process, the dielectric bonding interface S1 may be referred to as the first dielectric bonding interface, and the bonding layer 116 may be referred to as the first bonding layer.

[0064] In addition, the dielectric layers on both sides of the dielectric bonding interface S1 may be regarded as the top dielectric layer and the bottom dielectric layer of the corresponding component wafers. For example, in Figure 1A , the dielectric layer 111b and the dielectric layer 112b may be regarded as the top dielectric layer of the component wafer 111 and the bottom dielectric layer of the component wafer 112 respectively. Therefore, the top dielectric layer of the component wafer 111 is in direct contact with the bottom dielectric layer of the component wafer 112.

[0065] Please refer to Figures 1F to 1H , in this embodiment, the manufacturing process of the stacked wafer 120 may at least include the following steps. First, as Figure 1F shown, provide the component wafer 121 and the component wafer 122, and bond the component wafer 121 and the component wafer 122 through a direct bonding manufacturing process to form a dielectric bonding interface S2. The component wafer 121 may include a substrate 121a and a dielectric layer 121b disposed thereon, the component wafer 122 may include a substrate 122a and a dielectric layer 122b disposed thereon, and the dielectric layer 121b is in direct contact with the dielectric layer 122b.

[0066] In some embodiments, the foregoing direct bonding manufacturing process is, for example, an oxide bonding (also referred to as fusion bonding) manufacturing process. Therefore, the direct bonding manufacturing process may not include metal-to-metal bonding, but the present invention is not limited thereto.

[0067] In this embodiment, the substrates 121a, 122a of the component wafers 121, 122 respectively further have a plurality of grooves, and the dielectric layers 121b, 122b may respectively fill the foregoing grooves and further extend to the surfaces of the substrates 121a, 122a. Further, since there may be no series connection layer in the stacked wafer 120 (as Figure 1H shown), the component wafer 121 may be different from the component wafer 111, but the present invention is not limited thereto.

[0068] Please refer to Figure 1G, after forming the dielectric bonding interface S2, a thinning process is performed to remove a part of the back 122r of the component wafer 122 (such as the back of the substrate 122a), where the thinning process can continuously thin in the direction of the component wafer 121 until the dielectric layer 122b is exposed. Here, the thinning process is, for example, a chemical mechanical polishing process or the like.

[0069] Please refer to Figure 1H , after performing the thinning process, a dielectric layer 122c is formed on the substrate 122a. Then, a component wafer 123 is provided, and the component wafer 123 and the component wafer 122 are bonded by a direct bonding process similar to Figure 1F the one described to form another dielectric bonding interface S2, where the component wafer 123 includes a substrate 123a and a dielectric layer 123b disposed thereon, and the dielectric layer 123b is in direct contact with the dielectric layer 122c.

[0070] Repeat the foregoing steps. In short, a thinning process can be performed to remove a part of the back (not shown) of the component wafer 123. Then, a dielectric layer 123c is formed on the substrate 123a. Then, a component wafer 124 is provided, and the component wafer 124 and the component wafer 123 are bonded by a direct bonding process similar to Figure 1F the one described to form yet another dielectric bonding interface S2, where the component wafer 124 includes a substrate 124a and a dielectric layer 124b disposed thereon, and the dielectric layer 124b is in direct contact with the dielectric layer 123c. Subsequently, a thinning process (not shown) is performed and a dielectric layer 124c is formed on the substrate 124a, and the fabrication of the stacked wafer 120 is substantially completed via the above steps.

[0071] Furthermore, after the foregoing steps, the component wafer 122 can include a substrate 122a and dielectric layers 122b and 122c that are interconnected and surround the substrate 122a, the component wafer 123 can include a substrate 123a and dielectric layers 123b and 123c that are interconnected and surround the substrate 123a, and the component wafer 124 can include a substrate 124a and dielectric layers 124b and 124c that are interconnected and surround the substrate 124a.

[0072] Similar to the stacked wafer 110, depending on the actual design requirements, the above stacking steps can be repeated multiple times to a predetermined number of stacking layers. For example, the predetermined number of stacking layers can be greater than or equal to three. Therefore, the number of component wafers of the stacked wafer 120 can be greater than or equal to three, and the number of direct bonding processes can be greater than or equal to two. In addition, the number of component wafers in the stacked wafer 110 can be the same as or different from the number of component wafers in the stacked wafer 120.

[0073] Please refer to Figure 1I, after stacking a predetermined number of stacking layers (such as Figure 1H four layers), a bonding layer 126 is formed on the stacked wafers 120, and the stacked wafers 120 and the bonding layer 126 can be regarded as another stacked structure. Further, the bonding layer 126 includes a plurality of pads 126a and a dielectric layer 126b, wherein the dielectric layer 126b surrounds the pads 126a, and the top surface T3 of the pads 126a and the top surface T4 of the dielectric layer 126b can be substantially coplanar.

[0074] It should be noted that the foregoing stacked structure and the components included therein can be referred to as "second". For example, the stacked structure can be called the second stacked structure, the stacked wafers 120 can be called the second stacked wafers, the device wafers 121, 122, 123, 124 can be called a plurality of second device wafers, the direct bonding manufacturing process used can be called the second direct bonding manufacturing process, the dielectric bonding interface S2 can be called the second dielectric bonding interface, and the bonding layer 126 can be called the second bonding layer.

[0075] In addition, the dielectric layers on both sides of the dielectric bonding interface S2 can be regarded as the top dielectric layer and the bottom dielectric layer of the corresponding device wafers. For example, in Figure 1F , the dielectric layer 121b and the dielectric layer 122b can be regarded as the top dielectric layer of the device wafer 121 and the bottom dielectric layer of the device wafer 122 respectively. Therefore, the top dielectric layer of the device wafer 121 is in direct contact with the bottom dielectric layer of the device wafer 122.

[0076] In some embodiments, the type of any one of the device wafers 111, 112, 113, 114, 121, 122, 123, 124 includes DRAM wafers, logic wafers, IPDs, IPD wafers or the like, but the present invention is not limited thereto. The device wafers 111, 112, 113, 114, 121, 122, 123, 124 can adopt any suitable type according to the actual design requirements, and can be the same or different.

[0077] Please refer to Figure 1J , the bonding layer 116 and the bonding layer 126 are bonded and electrically connected through a direct bonding manufacturing process, so that a hybrid bonding interface S3 is formed between the bonding layer 116 and the bonding layer 126.

[0078] In some embodiments, the foregoing direct bonding fabrication process is, for example, a hybrid bonding fabrication process. That is, the hybrid bonding interface and the foregoing dielectric bonding interface can be formed using different fabrication process technologies. Therefore, the dielectric bonding interface formed in the hybrid bonding fabrication process is not the dielectric bonding interface described in the stacked wafers 110 and 120 herein. Moreover, the metal-to-metal and dielectric-to-dielectric bonding interfaces in the hybrid bonding interface (such as the pads 116a of the bonding layer 116 being in direct contact with the pads 126a of the bonding layer 126, and the dielectric layer 116b of the bonding layer 116 being in direct contact with the dielectric layer 126b of the bonding layer 126) are formed simultaneously, rather than being formed by separate bonding.

[0079] For example, the dielectric bonding interfaces S1 and S2 are each composed of a dielectric material, and the hybrid bonding interface S3 is composed of a dielectric material and a conductive material. The dielectric materials in the dielectric bonding interfaces S1 and S2 and the hybrid bonding interface S3 can be the same or different, and the present invention does not impose any limitations.

[0080] Please refer to Figure 1K , after forming the hybrid bonding interface S3, a thinning fabrication process is performed to remove a part of the back 121r of the component wafer 121 (such as the back of the substrate 121a). The thinning fabrication process can continuously thin in the direction of the hybrid bonding interface S3 until the dielectric layer 121b is exposed. Here, the thinning fabrication process is, for example, a chemical mechanical polishing fabrication process or the like.

[0081] Please refer to Figure 1L , after performing the thinning fabrication process, a dielectric layer 121c is formed on the substrate 121a. Then, a vertical connector 125 (which can be referred to as the second vertical connector) penetrating the dielectric bonding interface S2 is formed. Through the above steps, the fabrication of the semiconductor device 100 is substantially completed. Accordingly, in this embodiment, the multiple stacked wafers 110 and 120 are connected through the hybrid bonding interface S3, providing the required bonding strength for the semiconductor device 100. Moreover, the stacked structures are formed within the multiple stacked wafers 110 and 120 through the dielectric bonding interfaces S1 and S2 respectively, and then the vertical connectors 115 and 125 are used to conduct each layer, so as to simplify the wiring density within the semiconductor device. In this way, a balance can be achieved among the bonding ability, wiring design, and manufacturing cost, effectively increasing the number of stacked layers.

[0082] For example, when the number of stacked layers is greater than five, the current bonding technology that stacks in sequence from bottom to top consumes a large amount of wafers. And if all use the hybrid bonding fabrication process, the range that requires wire pulling is too large. However, through the design of this embodiment, the number of stacked layers can be greater than or equal to six (a stack of wafers with three or more layers is bonded to another stack of wafers with three or more layers), having a product competitive advantage.

[0083] In this embodiment, the vertical connector 125 can sequentially penetrate through the dielectric layer 121c, the dielectric layer 121b, the dielectric layer 122b, the dielectric layer 122c, the dielectric layer 123b, the dielectric layer 123c, the dielectric layer 124b, and the dielectric layer 124c from top to bottom and land on the pad 126a. Therefore, the vertical connector 125 can also be referred to as a through-dielectric via (TDV).

[0084] Furthermore, the vertical connector 115 and the vertical connector 125 are electrically connected through the bonding layer 116 and the bonding layer 126, and the orthographic projections of the vertical connector 115, the vertical connector 125, the bonding layer 116, and the bonding layer 126 on the device wafer 111 overlap each other to form a vertical conduction path, connecting the top wafer to the bottom wafer in the semiconductor device 100 in series.

[0085] In addition, since in this embodiment the vertical connector 125 is formed after the bonding layer 116 and the bonding layer 126 are bonded (which can be regarded as via-last), the tapered profile directions of the vertical connector 115 and the vertical connector 125 can be the same. For example, the vertical connector 115 tapers in a direction away from the hybrid bonding interface S3, and the vertical connector 125 tapers in a direction towards the hybrid bonding interface S3. In this way, better operability can be achieved, but the present invention is not limited thereto. In an embodiment not shown, the vertical connector can be formed in the stacked wafers Figure 1I in such a step, and in this way, the tapered profile directions of the two vertical connectors will be opposite.

[0086] In this embodiment, after the vertical connector 125 is formed, an external connection layer 130 (including a line 130a and a dielectric layer 130b), an external connection terminal 131, and a protective layer 132 can be further sequentially formed, as Figure 1L shown, where the external connection layer 130 is optional. In an embodiment not shown, the external connection layer 130 can also be omitted, such that the external connection terminal 131 is directly disposed on the vertical connector 125. Here, the vertical connector 115, the vertical connector 125, and the external connection terminal 131 are sequentially stacked and electrically connected to each other. On the other hand, the protective layer 132 can have an opening to expose the external connection terminal 131.

[0087] This embodiment can also include at least two vertical connectors 115 and two vertical connectors 125. The two vertical connectors 115 are arranged adjacent to each other on the series connection layer 111c, and the two vertical connectors 125 are correspondingly disposed on the two vertical connectors 115. Therefore, the vertically stacked vertical connectors 115 and vertical connectors 125 on one side can be electrically connected to the vertically stacked vertical connectors 115 and vertical connectors 125 on the other side through the series connection layer 111c to form a U-shaped conductive loop, but the present invention is not limited thereto.

[0088] In some embodiments, the material of any one of the substrates 111a, 112a, 113a, 114a, 121a, 122a, 123a, 124a includes silicon or other suitable substrate materials, and the material of any one of the dielectric layers 111b, 112b, 112c, 113b, 113c, 114b, 114c, 116b, 121b, 121c, 122b, 122c, 123b, 123c, 124b, 124c, 126b, 130b and the protective layer 132 includes silicon oxide or other suitable dielectric materials, while the materials of the series connection layer 111c and the line 130a include copper or other suitable conductive materials. In addition, any one of the dielectric layers 111b, 112b, 112c, 113b, 113c, 114b, 114c, 116b, 121b, 121c, 122b, 122c, 123b, 123c, 124b, 124c, 126b, 130b, the series connection layer 111c, the line 130a, the external terminal 131 and the protective layer 132 can be formed by chemical vapor deposition, atomic layer deposition or other suitable deposition methods. Here, those layers with the same reference can be formed using the same or similar materials and the same or similar manufacturing processes, and the present invention is not limited thereto.

[0089] It must be noted here that the following embodiments follow the component numbers and some content of the above embodiments, where the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0090] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention. Please refer to Figure 2 , compared with Figure 1L the semiconductor device 100, in this embodiment, the semiconductor device 200 further forms a plurality of signal lines 241 in the foregoing first stacked structure, and further forms a plurality of signal lines 242 in the foregoing second stacked structure, wherein the signal lines 241 are electrically connected to the vertical connectors 115, and the signal lines 242 are electrically connected to the vertical connectors 125. For example, the plurality of signal lines 241 in this embodiment can be in direct contact with the vertical connectors 115, and the plurality of signal lines 242 can be in direct contact with the vertical connectors 125. In this way, each layer only needs to arrange signal lines connected to the same vertical connector in the layer (without arranging vertical lines), so the complex wire routing design in multiple layers can be omitted. However, the present invention is not limited thereto, and other suitable electrical connection methods can also be used in the semiconductor device.

[0091] In summary, the present invention connects multiple stacked wafers through a hybrid bonding interface to provide the required bonding strength for the semiconductor device, and performs stacking within the multiple stacked wafers through a dielectric bonding interface respectively, and then conducts each layer through vertical connectors to simplify the wiring density within the semiconductor device. In this way, a balance can be achieved among the bonding ability, wiring design, and manufacturing cost, and the number of stacked layers can be effectively increased.

[0092] Although the present invention is disclosed in connection with the above embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first stacked structure, including a first stacked wafer and a first bonding layer, wherein the first stacked wafer includes a plurality of first dielectric bonding interfaces; A second stacked structure, including a second stacked wafer and a second bonding layer, wherein the second stacked wafer includes a plurality of second dielectric bonding interfaces, and the first bonding layer is bonded and electrically connected to the second bonding layer, such that there is a hybrid bonding interface between the first stacked structure and the second stacked structure; A first vertical connector, passing through the plurality of first dielectric bonding interfaces and electrically connected to the first bonding layer; And A second vertical connector, passing through the plurality of second dielectric bonding interfaces and electrically connected to the second bonding layer.

2. The semiconductor device according to claim 1, wherein: The first stacked structure includes a plurality of first device wafers, and one of the plurality of first dielectric bonding interfaces is located between two adjacent ones of the plurality of first device wafers; And The second stacked structure includes a plurality of second device wafers, and one of the plurality of second dielectric bonding interfaces is located between two adjacent ones of the plurality of second device wafers.

3. The semiconductor device according to claim 2, wherein the number of the plurality of first device wafers is greater than or equal to three, and the number of the plurality of second device wafers is greater than or equal to three.

4. The semiconductor device according to claim 1, wherein each of the first dielectric bonding interfaces is composed of a first dielectric material, each of the second dielectric bonding interfaces is composed of a second dielectric material, and the hybrid bonding interface is composed of a third dielectric material and a conductive material.

5. The semiconductor device according to claim 1, wherein the tapered profile directions of the first vertical connector and the second vertical connector are the same.

6. The semiconductor device according to claim 5, wherein the first vertical connector tapers in a direction away from the hybrid bonding interface, and the second vertical connector tapers in a direction toward the hybrid bonding interface.

7. The semiconductor device according to claim 1, wherein the first stacked structure includes a string layer, and two sides of the first vertical connector are directly in contact with the string layer and the first bonding layer respectively.

8. The semiconductor device according to claim 7, wherein at least two of the first vertical connectors are arranged adjacent to each other on the string layer, and at least two of the second vertical connectors are correspondingly arranged on the at least two first vertical connectors.

9. The semiconductor device according to claim 1, further comprising an external terminal, arranged on the second vertical connector, wherein the first vertical connector, the second vertical connector and the external terminal are stacked in sequence and electrically connected to each other.

10. The semiconductor device according to claim 1, wherein the pads of the first bonding layer are in direct contact with the pads of the second bonding layer, and the dielectric layers of the first bonding layer are in direct contact with the dielectric layers of the second bonding layer.

11. The semiconductor device according to claim 1, wherein the first stacked structure further includes a plurality of first signal lines, the second stacked structure further includes a plurality of second signal lines, the plurality of first signal lines are electrically connected to the first vertical connector, and the plurality of second signal lines are electrically connected to the second vertical connector.

12. A method of manufacturing a semiconductor device, comprising: forming a first stacked structure, including: forming a first stacked wafer through a plurality of first direct bonding processes such that a plurality of first dielectric bonding interfaces are included in the first stacked wafer; and forming a first bonding layer on the first stacked wafer; forming a first vertical connector penetrating through the plurality of first dielectric bonding interfaces; forming a second stacked structure, including: forming a second stacked wafer through a plurality of second direct bonding processes such that a plurality of second dielectric bonding interfaces are included in the second stacked wafer; and forming a second bonding layer on the second stacked wafer; bonding and electrically connecting the first bonding layer and the second bonding layer through a third direct bonding process such that a hybrid bonding interface is formed between the first bonding layer and the second bonding layer; and forming a second vertical connector penetrating through the plurality of second dielectric bonding interfaces and electrically connected to the second bonding layer, wherein the first vertical connector and the second vertical connector are electrically connected through the first bonding layer and the second bonding layer.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the plurality of first direct bonding processes and the plurality of second direct bonding processes are oxide bonding processes, and the third direct bonding process is a hybrid bonding process.

14. The method of manufacturing a semiconductor device according to claim 12, wherein each step of the plurality of first direct bonding processes and each step of the plurality of second direct bonding processes includes bonding two element wafers such that the top dielectric layer of one of the two element wafers directly contacts the bottom dielectric layer of the other of the two element wafers.

15. The method of manufacturing a semiconductor device according to claim 12, wherein a thinning process is performed between adjacent ones of the plurality of first bonding processes and between adjacent ones of the plurality of second bonding processes.

16. The method of manufacturing a semiconductor device according to claim 12, wherein the second vertical connector is formed after bonding the first bonding layer and the second bonding layer through the third direct bonding process.

17. The method of manufacturing a semiconductor device according to claim 12, wherein the number of the plurality of first direct bonding processes is greater than or equal to two, and the number of the plurality of second direct bonding processes is greater than or equal to two.

18. The method of manufacturing a semiconductor device according to claim 12, wherein neither the plurality of first direct bonding processes nor the plurality of second direct bonding processes includes metal-to-metal bonding.

19. The method of manufacturing a semiconductor device according to claim 12, further comprising forming external terminals on the second vertical connector.

20. The manufacturing method of the semiconductor device according to claim 12 further includes: forming a plurality of first signal lines on the first stacked structure; and forming a plurality of second signal lines on the second stacked structure.

Images