Power switch MOS tube driving power supply protection circuit

Abstract

The invention discloses a power switch MOS tube driving power supply protection circuit, and the circuit comprises a driving amplitude detection module which is used for sampling and monitoring the voltage swing of power switch MOS tube driving power supply in real time; the driving amplitude limiting module is configured to be used for limiting the voltage swing which is externally provided for driving and supplying power to the power switch MOS tube, so that the voltage swing does not exceed a preset threshold value; and the driving amplitude response module is used for receiving and processing the control signal of the driving amplitude detection module and outputting a feedback signal with loading capacity to the inside and the outside simultaneously. When the swing of the power supply voltage externally provided for the power switch MOS tube drive is unstable, the drive amplitude detection module is used for sampling and detecting the power supply voltage in real time, and then the drive amplitude response module is used for processing signals and feeding back whether the power supply information meets the protection action triggering requirement or not to the outside. And meanwhile, reasonable voltage limiting protection measures are implemented through the driving amplitude limiting module, so that the safe operation of the power switch MOS tube is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to a power switch MOS transistor drive power supply protection circuit. Background Art

[0002] In current system designs or application solutions for motor drives, power switch MOS transistors are widely used as key electrical switching nodes. The supply voltage parameters provided externally to the drive stage circuit of the power switch MOS transistor play a decisive role in its electrical characteristic indicators, and thus affect the performance of the entire system or solution.

[0003] If the externally provided supply voltage is insufficient, the electrical characteristic indicators of the power switch MOS transistor cannot be fully exerted, and it is easy to cause adverse consequences such as serious device heating and reduced system efficiency.

[0004] If the externally provided supply voltage is too large, it is easy to cause a reduction in the gate oxide lifetime of the power switch MOS transistor, or even a breakdown and damage situation.

[0005] Therefore, it is necessary to perform real-time detection on the power supply situation of the power switch MOS transistor drive and take relevant protection measures to ensure the safe operation of the power switch MOS transistor and maintain the long-term working state of the motor drive system or application solution. Summary of the Invention

[0006] In order to solve the above technical problems, the present invention provides a power switch MOS transistor drive power supply protection circuit, including: A drive amplitude detection module configured to sample and monitor in real time the voltage swing of the power supply for driving the power switch MOS transistor; A drive amplitude limiting module configured to limit the voltage swing of the power supply provided externally to drive the power switch MOS transistor so that it does not exceed a preset threshold value; and A drive amplitude response module configured to receive and process the control signal of the drive amplitude detection module, and output a feedback signal with load-carrying capacity both internally and externally.

[0007] Further, a port VA is provided between the drive amplitude detection module and the drive amplitude limiting module; a port VB is provided between the drive amplitude limiting module and the drive amplitude response module; the input end of the drive amplitude response module is connected to the port VA; the output end of the drive amplitude detection module is connected to the port VB.

[0008] Further, the drive amplitude detection module includes a self-biased and supply voltage swing sampling and conversion circuit and a hysteresis response circuit.

[0009] Further, the self - bias and supply voltage swing sampling and conversion circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor N1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3, where: The source of the first PMOS transistor P1 and the upper end of the fourth resistor R4 are both connected to the port VDD; The lower end of the fourth resistor R4 is connected to the source of the second PMOS transistor P2; The gate of the first PMOS transistor P1, the drain of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the upper end of the first resistor R1; The lower end of the first resistor R1 and the upper end of the second resistor R2 are both connected to the gate of the first NMOS transistor N1; The drain of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are both connected to the port VA; The source of the first NMOS transistor N1 is connected to the source of the third PMOS transistor P3.

[0010] Further, the hysteresis response circuit includes a second NMOS transistor N2, where: The lower end of the second resistor R2 is connected to the drain of the second NMOS transistor N2; The gate of the third PMOS transistor P3, the drain of the third PMOS transistor P3, the lower end of the third resistor R3, and the source of the second NMOS transistor N2 are all connected to the port VSS; The gate of the second NMOS transistor N2 is connected to the port VB.

[0011] Further, the drive amplitude limiting module includes a positive amplitude limiting circuit and a negative amplitude limiting circuit.

[0012] Further, the positive amplitude limiting circuit includes a fifth resistor R5, a sixth resistor R6, a third NMOS transistor N3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6, where: The gate of the fourth PMOS transistor P4 is connected to the port VA; The drain of the fourth PMOS transistor P4 and the drain of the third NMOS transistor N3 are both connected to the upper end of the fifth resistor R5; The gate of the third NMOS transistor N3 and the upper end of the sixth resistor R6 are both connected to the lower end of the fifth resistor R5; The source of the third NMOS transistor N3 is connected to the source of the fifth PMOS transistor P5; The gate of the fifth PMOS transistor P5, the drain of the fifth PMOS transistor P5, and the lower end of the sixth resistor R6 are all connected to the source of the sixth PMOS transistor P6; The gate of the sixth PMOS transistor P6 is connected to the port VB.

[0013] Further, the negative amplitude limiting circuit includes a first diode D1, where: The positive electrode of the first diode D1 and the source of the fourth PMOS transistor P4 are both connected to the port VDD; The negative electrode of the first diode D1 and the drain of the sixth PMOS transistor P6 are both connected to the port VSS.

[0014] Further, the drive amplitude response module includes a seventh PMOS transistor P7, a seventh resistor R7, a first Schmitt inverter I1, and a second inverter I2, where: The gate of the seventh PMOS transistor P7 is connected to the port VA; The source of the seventh PMOS transistor P7, the positive power supply terminal of the first Schmitt inverter I1, and the positive power supply terminal of the second inverter I2 are all connected to the port VDD; The drain of the seventh PMOS transistor P7 and the upper end of the seventh resistor R7 are both connected to the input terminal of the first Schmitt inverter I1; The lower end of the seventh resistor R7, the negative power supply terminal of the first Schmitt inverter I1, and the negative power supply terminal of the second inverter I2 are all connected to the port VSS; The output terminal of the first Schmitt inverter I1 and the input terminal of the second inverter I2 are both connected to the port VB; The output terminal of the second inverter I2 is connected to the port VN.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: By providing a power switch MOS transistor drive power supply protection circuit, when the supply voltage swing provided externally for driving the power switch MOS transistor is unstable, the drive amplitude detection module is used to sample and detect the supply voltage in real time, and then relevant signal processing is performed through the drive amplitude response module and the supply information is fed back to the outside to determine whether it meets the requirements for triggering the protection action. At the same time, reasonable voltage limit protection measures are implemented through the drive amplitude limiting module, ensuring the safe operation of the power switch MOS transistor. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 It is a schematic application diagram disclosed in the embodiments of the present invention; Figure 2 It is a schematic block diagram disclosed in the embodiments of the present invention; Figure 3 It is a schematic circuit diagram disclosed in the embodiments of the present invention.

[0018] In the figure: 10, driving amplitude detection module; 20, driving amplitude limiting module; 30, driving amplitude response module. Specific embodiments

[0019] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0020] The present invention aims to provide a power switch MOS transistor drive power supply protection circuit, which performs real-time detection on the power supply situation of the power switch MOS transistor drive and takes relevant protection measures to ensure the safe operation of the power switch MOS transistor.

[0021] Please refer to Figure 2 , the power switch MOS transistor drive power supply protection circuit provided by the present invention mainly includes a driving amplitude detection module 10, a driving amplitude limiting module 20, and a driving amplitude response module 30.

[0022] The driving amplitude detection module 10, the driving amplitude limiting module 20, and the driving amplitude response module 30 are all connected to the port VDD and the port VSS. A port VA is provided between the driving amplitude detection module and the driving amplitude limiting module; a port VB is provided between the driving amplitude limiting module and the driving amplitude response module; the input end of the driving amplitude response module is connected to the port VA; the output end of the driving amplitude detection module is connected to the port VB; the output end of the driving amplitude response module is connected with a port VN.

[0023] The port VSS is the negative port of the power supply VP; the port VDD is the positive port of the power supply VP; the port VN is used to feedback to the outside whether the power supply information of the external power supply VP meets the requirements for triggering the protection action. The ports VA and VB are the communication ports between the three modules of the drive amplitude detection module 10, the drive amplitude limiting module 20, and the drive amplitude response module 30 respectively.

[0024] First, the drive amplitude detection module 10 in this embodiment will be described.

[0025] The drive amplitude detection module 10 is configured to sample and monitor in real time the voltage swing of the power supply for driving the power switch MOS transistor, sample and judge whether the current power supply situation is reasonable, and simultaneously convert the control signals required by the subsequent modules synchronously.

[0026] Please refer to Figure 3 , the drive amplitude detection module 10 includes a self - bias and supply voltage swing sampling and conversion circuit and a hysteresis response circuit, where: The self - bias and voltage swing sampling and conversion circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor N1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3.

[0027] In a further aspect of this embodiment, the source of the first PMOS transistor P1 and the upper end of the fourth resistor R4 are both connected to the port VDD; the lower end of the fourth resistor R4 is connected to the source of the second PMOS transistor P2; the gate of the first PMOS transistor P1, the drain of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the upper end of the first resistor R1; the lower end of the first resistor R1 and the upper end of the second resistor R2 are both connected to the gate of the first NMOS transistor N1; the drain of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are both connected to the port VA; the source of the first NMOS transistor N1 is connected to the source of the third PMOS transistor P3.

[0028] The hysteresis response circuit includes a second NMOS transistor N2.

[0029] In a further aspect of this embodiment, the lower end of the second resistor R2 is connected to the drain of the second NMOS transistor N2; the gate of the third PMOS transistor P3, the drain of the third PMOS transistor P3, the lower end of the third resistor R3, and the source of the second NMOS transistor N2 are all connected to the port VSS; the gate of the second NMOS transistor N2 is connected to the port VB.

[0030] Then, the drive amplitude limiting module 20 in this embodiment will be described.

[0031] The driving amplitude limiting module 20 is configured to limit the upper and lower limits of the voltage swing externally supplied to the power switch MOS transistor drive power supply, so that it does not exceed a preset threshold value.

[0032] Please refer to Figure 3 , the driving amplitude limiting module 20 includes a positive amplitude limiting circuit and a negative amplitude limiting circuit, where: The positive amplitude limiting circuit includes a fifth resistor R5, a sixth resistor R6, a third NMOS transistor N3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6.

[0033] In a further embodiment of the present invention, the gate of the fourth PMOS transistor P4 is connected to the port VA; the drain of the fourth PMOS transistor P4 and the drain of the third NMOS transistor N3 are both connected to the upper end of the fifth resistor R5; the gate of the third NMOS transistor N3 and the upper end of the sixth resistor R6 are both connected to the lower end of the fifth resistor R5; the source of the third NMOS transistor N3 is connected to the source of the fifth PMOS transistor P5; the gate of the fifth PMOS transistor P5, the drain of the fifth PMOS transistor P5, and the lower end of the sixth resistor R6 are all connected to the source of the sixth PMOS transistor P6; the gate of the sixth PMOS transistor P6 is connected to the port VB.

[0034] The negative amplitude limiting circuit includes a first diode D1.

[0035] In a further embodiment of the present invention, the positive electrode of the first diode D1 and the source of the fourth PMOS transistor P4 are both connected to the port VDD; the negative electrode of the first diode D1 and the drain of the sixth PMOS transistor P6 are both connected to the port VSS.

[0036] Finally, the driving amplitude response module 30 in this embodiment will be described.

[0037] The driving amplitude response module 30 is configured to receive and process the control signal from the driving amplitude detection module 10, and output a feedback signal with load-carrying capacity both internally and externally.

[0038] Please refer to Figure 3 , the driving amplitude response module 30 includes a seventh PMOS transistor P7, a seventh resistor R7, a first Schmitt inverter I1, and a second inverter I2, where: The gate of the seventh PMOS transistor P7 is connected to port VA; the source of the seventh PMOS transistor P7, the positive power supply terminal of the first Schmitt inverter I1, and the positive power supply terminal of the second inverter I2 are all connected to port VDD; the drain of the seventh PMOS transistor P7 and the upper end of the seventh resistor R7 are both connected to the input terminal of the first Schmitt inverter I1; the lower end of the seventh resistor R7, the negative power supply terminal of the first Schmitt inverter I1, and the negative power supply terminal of the second inverter I2 are all connected to port VSS; the output terminal of the first Schmitt inverter I1 and the input terminal of the second inverter I2 are both connected to port VB; the output terminal of the second inverter I2 is connected to port VN.

[0039] Those skilled in the art further explain that while the power supply voltage provided externally is implemented for driving the power switch MOS transistor, it is also implemented for the power switch MOS transistor drive power supply protection circuit. In the drive amplitude detection module 10, the self-biased and power supply voltage swing sampling conversion circuit composed of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first NMOS transistor N1, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 can start to operate. The first PMOS transistor P1 forming a diode circuit form provides a working bias voltage for the second PMOS transistor P2 and the fourth resistor R4, and forms a series circuit relationship with the first resistor R1, the second resistor R2, and the third resistor R3 to perform real-time voltage division sampling on the above-mentioned power supply voltage. When the divided voltage value of the power supply voltage on the second resistor R2 and the third resistor R3 exceeds the lower threshold voltage defined by the series-connected MOS circuit composed of the first NMOS transistor N1 and the third PMOS transistor P3, the first NMOS transistor N1 is turned on and pulls down the voltage amplitude of port VA to a low voltage level. At this time, it can be considered that the power supply voltage amplitude reaches or exceeds the preset lower threshold voltage value, and the subsequent module circuit is allowed to start working; otherwise, the first NMOS transistor N1 will be in the off state, and the voltage amplitude of port VA will be pulled up to a high voltage level by the second PMOS transistor P2, so that the subsequent module circuit will be in a low-power off state.

[0040] The driving amplitude response module 30 can obtain the voltage signal indicating whether this module is allowed to work from port VA. If it is allowed, that is, the voltage amplitude of port VA is at a low voltage level value, then the seventh PMOS transistor P7 in this module will be in an on and pull-up working state, and the voltage across the seventh resistor R7 will no longer be zero. Also, the voltage signal is inverted, amplified, and waveform-shaped by the first Schmitt inverter I1, and then transmitted to port VB and a reliable low voltage level value is output. On the one hand, it can enable the driving amplitude limiting module 20 to start running, and in the self-biased and supply voltage swing sampling conversion circuit of the driving amplitude detection module 10, by turning off the second NMOS transistor N2, the voltage division effect of the supply voltage across the second resistor R2 and the third resistor R3 is strengthened, forming a hysteresis response, ensuring that the driving amplitude detection module 10 has a certain anti-interference ability; on the other hand, the voltage at port VB is inverted and amplified by the second inverter I2, and finally a high voltage level signal with load-carrying capacity is formed at port VN, that is, it indicates to the outside that the above-mentioned externally provided supply voltage signal is normal and does not meet the requirements for triggering the protection action. At this time, the AND logic I0 for driving the power switch MOS transistor is allowed to transmit signals normally, and the input signal VI forms the required in-phase control effect on the gate voltage VG of the power switch MOS transistor M0.

[0041] The driving amplitude limiting module 20 obtains the voltage signals indicating whether this module is allowed to work from port VA and port VB. If it is allowed, that is, the voltage amplitudes of both port VA and port VB are at low voltage level values at the same time, then the fourth PMOS transistor P4 and the sixth PMOS transistor P6 are turned on, allowing a current path from port VDD to port VSS to be formed, and the fifth resistor R5, the sixth resistor R6, the third NMOS transistor N3, and the fifth PMOS transistor P5 constitute a positive amplitude limiting circuit. When the amplitude of the externally provided supply voltage attempts to exceed the upper threshold voltage set by this circuit, the current path from port VDD to port VSS is automatically turned on and a clamping mechanism is formed through the positive amplitude limiting circuit. Through the forced discharge effect of this current path, it is ensured that the amplitude of the externally provided supply voltage can only be maintained at the preset upper threshold voltage amplitude level at most. And the first diode D1 constitutes a negative amplitude limiting circuit, and through the clamping action of the diode itself, it is also ensured that the lower limit of the supply voltage amplitude will not be too negative, that is, a negative amplitude limiting effect is formed.

[0042] Please refer to Figure 1 , when the voltage swing of the power supply VP provided externally to drive the power switch MOS transistor (such as the AND logic I0) is unstable, either large or small, positive or negative, the power switch MOS transistor driving power supply protection circuit will detect and limit the amplitude of the supply voltage, and feedback to the outside whether the supply information meets the requirements for triggering the protection action, ensuring the safe operation of the power switch MOS transistor in real time.

[0043] When the supply voltage externally provided for driving the power switch MOS transistor fails to reach the preset lower threshold, that is, when the swing voltage is too low, the circuit port VN will output a low-level signal. Through the AND logic I0 of the power switch MOS transistor drive, the gate voltage VG of the power switch MOS transistor M0 is set to a low-level voltage, that is, the power switch MOS transistor M0 is forced to turn off and is independent of the input signal VI.

[0044] When the supply voltage externally provided for driving the power switch MOS transistor attempts to exceed the preset upper threshold, that is, when the swing voltage is too large, on the one hand, the drive amplitude limiting function is enabled inside the circuit to ensure that the supply voltage value only maintains at the preset upper threshold voltage amplitude level at most. On the other hand, the circuit port VN will output a high-level signal, so as not to affect the normal signal transmission of the AND logic I0 of the power switch MOS transistor drive, and the input signal VI still forms a normal in-phase control function for the gate voltage VG of the power switch MOS transistor M0.

[0045] Through the cooperation among the drive amplitude detection module 10, the drive amplitude limiting module 20, and the drive amplitude response module 30, when there are unstable situations of the supply voltage swing externally provided for driving the power switch MOS transistor, such as being too large or too small, positive or negative, the present invention realizes the detection and amplitude limitation of the supply voltage, and feeds back to the outside whether the supply information meets the requirements for triggering the protection action, thus ensuring the safe operation of the power switch MOS transistor.

[0046] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A power switch MOS transistor drive power supply protection circuit, characterized in that, Comprising: A drive amplitude detection module configured to perform real-time sampling and monitor the voltage swing of the power switch MOS transistor drive power supply; A drive amplitude limiting module configured to limit the voltage swing of the power switch MOS transistor drive power supply provided externally so that it does not exceed a preset threshold value; And A drive amplitude response module configured to receive and process the control signal of the drive amplitude detection module and output a feedback signal with load-carrying capacity both internally and externally.

2. The power switch MOS transistor driving power supply protection circuit according to claim 1, wherein A port VA is provided between the drive amplitude detection module and the drive amplitude limiting module; a port VB is provided between the drive amplitude limiting module and the drive amplitude response module; the input end of the drive amplitude response module is connected to the port VA; the output end of the drive amplitude detection module is connected to the port VB; the output end of the drive amplitude response module is connected with a port VN.

3. The power switch MOS transistor driving power supply protection circuit according to claim 2, characterized in that The drive amplitude detection module includes a self-biased and power supply voltage swing sampling and conversion circuit and a hysteresis response circuit.

4. The power switch MOS transistor driving power supply protection circuit according to claim 3, wherein The self-biased and power supply voltage swing sampling and conversion circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor N1, a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3, where: The source of the first PMOS transistor P1 and the upper end of the fourth resistor R4 are both connected to the port VDD; The lower end of the fourth resistor R4 is connected to the source of the second PMOS transistor P2; The gate of the first PMOS transistor P1, the drain of the first PMOS transistor P1, and the gate of the second PMOS transistor P2 are all connected to the upper end of the first resistor R1; The lower end of the first resistor R1 and the upper end of the second resistor R2 are both connected to the gate of the first NMOS transistor N1; The drain of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are both connected to the port VA; The source of the first NMOS transistor N1 is connected to the source of the third PMOS transistor P3.

5. The power switch MOS transistor driving power supply protection circuit according to claim 4, wherein The hysteresis response circuit includes a second NMOS transistor N2, where: The lower end of the second resistor R2 is connected to the drain of the second NMOS transistor N2; The gate of the third PMOS transistor P3, the drain of the third PMOS transistor P3, the lower end of the third resistor R3, and the source of the second NMOS transistor N2 are all connected to the port VSS; The gate of the second NMOS transistor N2 is connected to the port VB.

6. The power switch MOS transistor driving power supply protection circuit according to claim 2, wherein The drive amplitude limiting module includes a positive amplitude limiting circuit and a negative amplitude limiting circuit.

7. The power switch MOS transistor driving power supply protection circuit according to claim 6, characterized in that, The positive amplitude limiting circuit includes a fifth resistor R5, a sixth resistor R6, a third NMOS transistor N3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6, where: The gate of the fourth PMOS transistor P4 is connected to the port VA; The drain of the fourth PMOS transistor P4 and the drain of the third NMOS transistor N3 are both connected to the upper end of the fifth resistor R5; The gate of the third NMOS transistor N3 and the upper end of the sixth resistor R6 are both connected to the lower end of the fifth resistor R5; The source of the third NMOS transistor N3 is connected to the source of the fifth PMOS transistor P5; The gate of the fifth PMOS transistor P5, the drain of the fifth PMOS transistor P5, and the lower end of the sixth resistor R6 are all connected to the source of the sixth PMOS transistor P6; The gate of the sixth PMOS transistor P6 is connected to the port VB.

8. The power switch MOS transistor driving power supply protection circuit according to claim 7, characterized in that, The negative amplitude limiting circuit includes a first diode D1, where: The positive electrode of the first diode D1 and the source of the fourth PMOS transistor P4 are both connected to the port VDD; The negative electrode of the first diode D1 and the drain of the sixth PMOS transistor P6 are both connected to the port VSS.

9. The power switch MOS transistor driving power supply protection circuit according to claim 2, wherein The drive amplitude response module includes a seventh PMOS transistor P7, a seventh resistor R7, a first Schmitt inverter I1, and a second inverter I2, where: The gate of the seventh PMOS transistor P7 is connected to the port VA; The source of the seventh PMOS transistor P7, the positive power supply terminal of the first Schmitt inverter I1, and the positive power supply terminal of the second inverter I2 are all connected to the port VDD; The drain of the seventh PMOS transistor P7 and the upper end of the seventh resistor R7 are both connected to the input terminal of the first Schmitt inverter I1; The lower end of the seventh resistor R7, the negative power supply terminal of the first Schmitt inverter I1, and the negative power supply terminal of the second inverter I2 are all connected to the port VSS; The output terminal of the first Schmitt inverter I1 and the input terminal of the second inverter I2 are both connected to the port VB; The output terminal of the second inverter I2 is connected to the port VN.

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