Line longitudinal differential protection method and system with dual CPU protection logic equivalence

Abstract

The present invention relates to the field of power system control technology, and provides a method and system for line longitudinal differential protection with dual-CPU protection logic equivalence. The method comprises: configuring longitudinal differential protection devices on both sides of the line, and both adopting a dual-CPU protection architecture of a master CPU and a slave CPU; using a ping-pong synchronization algorithm to calculate the synchronization error on both sides; the master CPU and the slave CPU of the host have a fixed sampling rhythm; the master CPU of the slave adjusts the sampling time of the CPU according to the synchronization error on both sides; each slave CPU performs a sampling synchronization pulse legitimacy check to achieve sampling synchronization of the four CPUs of the master and slave machines on both sides of the line; each master CPU obtains the synchronous sampling data of the master CPU and the slave CPU on the opposite side through an optical longitudinal module, and establishes a line longitudinal differential protection function with the master CPU and the slave CPU being logically equivalent. The present invention can effectively avoid abnormal protection action behavior caused by sampling deviation.

Description

Technical Field

[0001] The present invention relates to the technical field of power system control, and in particular to a line longitudinal differential protection method and system with dual-CPU protection logic equivalence. Background Art

[0002] Line longitudinal differential protection devices generally adopt a single CPU or dual CPU architecture. When a single CPU architecture is used, a dual AD sampling mode is generally used to improve the reliability of the protection action. However, since the dual ADs are located on the same board, a single board abnormality may cause the protection to refuse to operate or malfunction, resulting in poor reliability. Therefore, a single CPU architecture is generally not usable on lines with high reliability requirements. When a dual CPU architecture is used, since the devices on both sides need to synchronize sampling to perform differential protection operations, the main CPU on one side will generally follow the main CPU on the opposite side for sampling adjustments, while the slave CPU generally samples independently. Therefore, the master and slave CPUs of the devices on both sides sample asynchronously. Based on the above sampling method, the optical fiber channel of the line longitudinal differential protection device generally only transmits the analog sampling data of the main CPU. Since the devices on both sides can only obtain the analog sampling data of the opposite side, the master and slave CPUs of the devices on both sides are sampled asynchronously. The main CPU on the side synchronizes data, so the longitudinal differential protection device can generally only adopt the "protection" + "start" mode, that is, the main CPU is used to determine the protection logic, and the slave CPU can only be used to determine the protection start. When the slave CPU meets the start conditions and opens the output relay power supply, and the main CPU meets the protection action logic, the protection device can trip at the output. Although the above logic is improved in reliability compared with the single CPU architecture, it lowers the control threshold of the slave CPU and cannot realize the "protection" + "protection" logical architecture, that is, the protection output cannot be opened according to the master and slave CPUs meeting the differential protection action threshold. When the main CPU sampling abnormality occurs and is accompanied by out-of-zone disturbances, the device has a greater risk of false operation and reliability is difficult to guarantee. In addition, among the various protection functions of the longitudinal differential protection device, other single-ended backup protections except the longitudinal differential protection function have the conditions for dual-CPU protection logic equivalence because they can obtain the sampling data of the master and slave CPUs, and can adopt a "protection" + "protection" architecture. However, since the main protection longitudinal differential protection can only use the "protection" + "start" architecture, in order to reduce the complexity of the device design, the longitudinal current differential protection device generally uses the "protection" + "start" architecture as a whole, which further reduces the reliability of the device. Summary of the Invention

[0003] The object of the present invention is to solve at least one technical problem in the background technology and to provide a line longitudinal differential protection method and system with dual CPU protection logic equivalence.

[0004] To achieve the above object, the present invention provides a line longitudinal differential protection method with dual CPU protection logic equivalence, comprising:

[0005] Longitudinal differential protection devices are configured on both sides of the line, and both adopt a dual-CPU protection architecture with a master CPU and a slave CPU. The master CPU and the slave CPU obtain local sampled data through their respective sampling modules, and the master CPU obtains sampled data from the master CPU and slave CPU on the opposite side through the optical longitudinal module.

[0006] The longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication characteristic word information through the optical fiber channel, and use the ping-pong synchronization algorithm to synchronize the synchronization error between the two sides. Calculation of

[0007] The host's main CPU and slave CPU sampling beats are fixed, and the main CPU samples the samples at intervals through the sampling synchronization bus based on its own sampling beat. Send sampling synchronization pulse to the master's slave CPU;

[0008] The slave's main CPU calculates the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave;

[0009] Each slave CPU performs a sampling synchronization pulse validity check. If the sampling synchronization pulse is detected to be illegal, it enters the sampling synchronization pulse exception processing process. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving sampling synchronization of the four CPUs of the master and slave machines on both sides of the line.

[0010] Each slave CPU sends the synchronous sampling data to each master CPU through a high-speed data bus. The data is then sent to the optical longitudinal module by the master CPU for packaging. The switching value and communication feature word are then packaged into a complete frame of data and sent to the optical longitudinal module of the opposite longitudinal differential protection device through the optical fiber channel.

[0011] Each master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent.

[0012] According to one aspect of the present invention, the master CPU and the slave CPU both adopt a sampling architecture that combines a CPU processor, an FPGA processing chip, and an A / D sampling chip;

[0013] The CPU processor is used to complete the protection logic processing. The CPU processor of each main CPU uses the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time, and regularly sends synchronization pulses to correct the sampling beat of the FPGA processing chip;

[0014] The FPGA processing chip adjusts its own sampling beat according to the synchronization pulse sent regularly by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling beat;

[0015] The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip;

[0016] A sampling synchronization pulse bus is provided between the master CPU and the slave CPU. The synchronization pulse sent by the master CPU to the FPGA processing chip is sent to the slave CPU via the synchronization pulse bus to correct the sampling beat of the slave CPU.

[0017] According to one aspect of the present invention, a method for determining the master and slave devices on both sides of the line is as follows:

[0018] After powering up, the longitudinal differential protection devices on both sides of the line each generate a random code A and B, and send them to the other side in each frame of data transmission. After receiving the random code from the opposite side device, the longitudinal differential protection devices on both sides compare the values ​​of A and B and determine the master and slave devices based on the relative size of the values.

[0019] If it is found that the two random codes A and B are the same, a random code is generated again for a second comparison; when the reception channel of the longitudinal differential protection device on one side is interrupted, the previous master and slave determination status is maintained. After the channel is restored, the master and slave are determined again by re-comparing the sizes of the two random codes.

[0020] According to one aspect of the present invention, the time interval , where n is the number of sampling points per cycle; T s is the sampling interval; It is the reliability coefficient of the host sampling synchronization pulse sending interval.

[0021] According to one aspect of the present invention, the time interval , where n is the number of sampling points per cycle; T s is the sampling interval; It is the reliability coefficient of the interval of sending the sampling synchronization pulse of the slave.

[0022] According to one aspect of the present invention, the master and the slave further include: Perform time t synchronization;

[0023] ;

[0024] in, The minimum threshold for starting synchronization error adjustment for the master and slave; The maximum value of the single-cycle sampling beat adjustment amplitude; f is the frequency corresponding to the single cycle, and f=50HZ under the power frequency condition.

[0025] According to one aspect of the present invention, each slave CPU performs a sampling synchronization pulse legitimacy check. When the sampling synchronization pulse is detected to be illegal, the sampling synchronization pulse exception handling process is entered. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU, and the sampling synchronization between the master CPU and the slave CPU is completed as follows:

[0026] The CPU sets the sampling synchronization pulse legitimacy check threshold based on the upper limit of the accumulated deviation of each sampling synchronization pulse adjustment amount, sampling synchronization pulse sending execution deviation, CPU crystal oscillator deviation, and FPGA processing chip crystal oscillator deviation. ; When the FPGA processing chip detects the sampling synchronization pulse deviation is not greater than When the sampling synchronization pulse interval is determined to be within the legal range, the slave CPU adjusts the sampling beat according to the sampling synchronization pulse to achieve synchronization between the master CPU and the slave CPU; when the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse exception processing flow is entered.

[0027] According to one aspect of the present invention, the sampling synchronization pulse abnormality processing process includes:

[0028] When the FPGA processing chip detects that the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse interval is determined to be beyond the legal range, the sampling beat will no longer be adjusted according to the sampling synchronization pulse, and the FPGA processing chip will use its own beat to keep time; during the timekeeping process, if the FPGA processing chip detects the sampling synchronization pulse deviation for N1 consecutive times and it is not greater than , then the sampling synchronization pulse is restored to adjust the sampling beat. During the recovery process, the longitudinal differential protection device briefly blocks the longitudinal differential protection to avoid malfunction of the differential protection caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery. If the sampling synchronization pulse deviation still does not meet the conditions for recovery after the punctual time, the sampling synchronization pulse abnormal flag is directly set to block the longitudinal differential protection.

[0029] When the FPGA detects that the sampling synchronization pulse deviation is greater than 3 times in a row When the sync pulse abnormal flag is set directly, the longitudinal differential protection is locked. If the FPGA processing chip detects the sampling sync pulse deviation for N2 consecutive times, it is not greater than , then the sampling synchronization pulse is used to adjust the sampling beat. During the recovery process, the longitudinal differential protection device temporarily locks the longitudinal differential protection to avoid the differential protection malfunction caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery. The longitudinal differential protection will be opened after the sampling synchronization pulse is stable.

[0030] According to one aspect of the present invention, after the four CPUs of the host and slave machines on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side are sent to the master CPU through a high-speed data bus. The master CPU sends the communication feature word, master CPU sampling data, slave CPU sampling data, switch quantity information, channel number, and application layer check code to the FPGA processing chip for data encapsulation in accordance with the optical vertical data agreed format; wherein the communication feature word includes the master-slave random code, sampling point number, and the most recently received sampling point number; the master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value; the slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

[0031] According to one aspect of the present invention, each master CPU obtains synchronous sampling data of the opposite master CPU and slave CPU through an optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and the slave CPU are logically equivalent, including:

[0032] The master CPU on each side of the line selects synchronous sampling data from the opposite master CPU to construct the master CPU differential protection action equation, and the slave CPU on each side of the line selects synchronous sampling data from the opposite slave CPU to construct the slave CPU differential protection action equation;

[0033] The master and slave machines both perform protection logic discrimination through the differential protection action equations of the master CPU and slave CPU that they have completed. When both the master CPU and the slave CPU meet the differential protection action logic, the differential protection action exits. If only one CPU meets the differential protection action conditions, the master or slave machine only sends a message.

[0034] To achieve the above object, the present invention further provides a line longitudinal differential protection system with dual CPU protection logic equivalence, comprising:

[0035] The master CPU and slave CPU configuration modules are configured, and longitudinal differential protection devices are configured on both sides of the line. The longitudinal differential protection devices on both sides adopt a dual-CPU protection architecture of the master CPU and the slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains sampling data from the master CPU and slave CPU on the opposite side through the optical longitudinal module;

[0036] Master-slave synchronization error calculation module, the longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication feature word information through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error on both sides. Calculation of

[0037] The host CPU sampling module has a fixed sampling rhythm for the host CPU and the slave CPU. The master CPU samples the data at a fixed time interval through the sampling synchronization bus based on its own sampling rhythm. Send sampling synchronization pulse to the master's slave CPU;

[0038] The slave CPU sampling module, the slave's main CPU according to the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave;

[0039] The master-slave sampling synchronization module verifies the validity of the sampling synchronization pulses of each slave CPU. If the sampling synchronization pulse is detected to be illegal, the abnormal processing flow of the sampling synchronization pulse is entered. Otherwise, the sampling rhythm is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving the sampling synchronization of the four CPUs of the master and slave machines on both sides of the line.

[0040] Synchronous sampling data processing module: each slave CPU sends the synchronous sampling data to each master CPU through a high-speed data bus. The master CPU then sends the data to the optical longitudinal module for encapsulation. The switching value and communication feature word are packaged into a complete frame of data and sent to the optical longitudinal module of the opposite longitudinal differential protection device through the optical fiber channel.

[0041] In the line longitudinal differential protection module, each master CPU and slave CPU obtains the synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent.

[0042] To achieve the above-mentioned purpose, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the line longitudinal differential protection method with dual-CPU protection logic equivalence as described above is implemented.

[0043] To achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the line longitudinal differential protection method with dual CPU protection logic equivalence as described above is implemented.

[0044] According to the solution of the present invention, the present invention solves the problem that the existing line protection device can only use the main CPU sampling data to perform differential protection logic operations through synchronous adjustment of the dual CPUs of the longitudinal differential protection devices on both sides of the line and verification of the legitimacy of the sampled synchronous pulses. It provides a practical method for building a safe, reliable and logically equivalent master and slave dual-CPU line longitudinal differential protection, and upgrades the existing "protection" + "start" architecture design to a "protection" + "protection" logic architecture, which can greatly improve the reliability of the line longitudinal differential protection device.

[0045] In the present invention, the device has a reliable sampling synchronization pulse legitimacy verification mechanism and complete exception handling and alarm measures, which can ensure the safety of using sampling synchronization pulses to adjust the sampling beat while effectively improving the reliability and stability of the device operation.

[0046] In the present invention, the device adopts a sampling architecture of "CPU processor" + "FPGA processing chip" + "A / D sampling chip", puts the sampling link in front, and completes the sampling by FPGA, while the CPU is only used to correct the FPGA sampling rhythm, which can effectively reduce the CPU load and improve the operating efficiency of the device.

[0047] In the present invention, the master and slave dual CPU sampling synchronization can greatly improve the consistency of dual CPU sampling of the line longitudinal differential protection device, and effectively avoid abnormal protection action behavior caused by sampling deviation.

[0048] The present invention is based on synchronous regulation of current and voltage by master and slave dual CPUs on both sides of the line, has a simple principle, is easy to implement, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A flow chart schematically illustrates a line longitudinal differential protection method with dual CPU protection logic equivalence according to an embodiment of the present invention;

[0050] Figure 2 The diagram schematically shows a master and slave architecture diagram according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are only intended to enable those skilled in the art to better understand and implement the present invention, rather than to imply any limitation on the scope of the present invention.

[0052] As used herein, the term "including" and variations thereof are to be interpreted as open-ended terms meaning "including, but not limited to." The term "based on" is to be interpreted as "based, at least in part, on." The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment."

[0053] Figure 1 A flow chart schematically illustrates a line longitudinal differential protection method with dual CPU protection logic equivalence according to an embodiment of the present invention; Figure 2 Schematically shows a master and slave architecture diagram according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, in this embodiment, the line longitudinal differential protection method with dual CPU protection logic equivalence includes:

[0054] Longitudinal differential protection devices are configured on both sides of the line, and both adopt a dual-CPU protection architecture with a master CPU and a slave CPU. The master CPU and the slave CPU obtain local sampled data through their respective sampling modules, and the master CPU obtains sampled data from the master CPU and slave CPU on the opposite side through the optical longitudinal module.

[0055] The longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication characteristic word information through the optical fiber channel, and use the ping-pong synchronization algorithm to synchronize the synchronization error between the two sides. Calculation of

[0056] The host's main CPU and slave CPU sampling beats are fixed, and the main CPU samples the samples at intervals through the sampling synchronization bus based on its own sampling beat. Send sampling synchronization pulse to the master's slave CPU;

[0057] The slave's main CPU calculates the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave;

[0058] Each slave CPU performs a sampling synchronization pulse validity check. If the sampling synchronization pulse is detected to be illegal, it enters the sampling synchronization pulse exception processing process. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving sampling synchronization of the four CPUs of the master and slave machines on both sides of the line.

[0059] Each slave CPU sends the synchronous sampling data to each master CPU via a high-speed data bus. The data is then sent to the optical longitudinal module by the master CPU for packaging (the optical longitudinal module sends and receives the sampled data, and then the data is packaged by the FPGA processing chip). The switching value and communication feature word are packaged into a complete frame of data and sent to the optical longitudinal module of the opposite longitudinal differential protection device via the optical fiber channel.

[0060] Each master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent.

[0061] In this embodiment, the main (longitudinal differential protection function) and backup (distance, zero-sequence, etc. backup) protection functions of the longitudinal differential protection device are designed according to the dual-CPU action logic, realizing the "protection" + "protection" logic architecture of the line longitudinal differential protection device and improving the reliability of the protection device.

[0062] Furthermore, according to one embodiment of the present invention, both the master CPU and the slave CPU adopt a sampling architecture that combines a CPU processor, an FPGA processing chip, and an A / D sampling chip;

[0063] The CPU processor is used to complete the protection logic processing. The CPU processor of each main CPU uses the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time, and regularly sends synchronization pulses to correct the sampling beat of the FPGA processing chip;

[0064] The FPGA processing chip adjusts its own sampling beat according to the synchronization pulse sent regularly by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling beat;

[0065] The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip;

[0066] A sampling synchronization pulse bus is provided between the master CPU and the slave CPU. The synchronization pulse sent by the master CPU to the FPGA processing chip is sent to the slave CPU via the synchronization pulse bus to correct the sampling beat of the slave CPU.

[0067] The above sampling architecture puts the sampling link in front, and the sampling is completed by the FPGA processing chip, while the CPU is only used to correct the FPGA sampling rhythm, which can effectively reduce the CPU load and improve the operating efficiency of the device.

[0068] Furthermore, in this embodiment, the optical longitudinal data is encapsulated and unpacked through the FPGA processing chip of the main CPU, and information is transmitted through the optical longitudinal interface of the optical longitudinal module to achieve reliable interaction of information between the longitudinal differential protection devices on both sides.

[0069] Furthermore, according to an embodiment of the present invention, a method for determining the master and slave devices on both sides of the line is as follows:

[0070] After powering up, the longitudinal differential protection devices on both sides of the line each generate a random code A and B, and send them to the other side in each frame of data transmission. After receiving the random code from the opposite side device, the longitudinal differential protection devices on both sides compare the values ​​of A and B, and determine the master and slave devices based on the relationship between the values ​​of A and B (for example, the device with the larger value is the master, and the device with the smaller value is the slave).

[0071] If it is found that the two random codes A and B are the same, a random code is generated again for a second comparison; when the reception channel of the longitudinal differential protection device on one side is interrupted, the previous master and slave determination status is maintained. After the channel is restored, the master and slave are determined again by re-comparing the sizes of the two random codes.

[0072] Furthermore, according to one embodiment of the present invention, the above time interval , where n is the number of sampling points per cycle; T s is the sampling interval; It is the reliability coefficient of the host sampling synchronization pulse sending interval.

[0073] In this embodiment, since the host sampling beat is fixed, it is only necessary to ensure that the slave CPU and the master CPU have the same sampling beat, so The value of can be appropriately relaxed. The value can be 5 to 50, which is n*T at the power frequency of 50HZ. S =0.02s, The value is generally 0.1~1s.

[0074] Furthermore, according to one embodiment of the present invention, the above time interval , where n is the number of sampling points per cycle; T s is the sampling interval; It is the reliability coefficient of the interval of sending the sampling synchronization pulse of the slave.

[0075] In this embodiment, the master CPU and slave CPU of the slave need to be synchronized according to the error between the two sides of the line. Adjust the sampling to improve the sampling beat adjustment accuracy and at the same time consider reducing the impact of the sampling beat adjustment process on the protection algorithm. The value of should not be too large. The value ranges from 1 to 5. At a power frequency of 50HZ, it is n*T S =0.02s, The value is generally 0.02~0.1s.

[0076] Furthermore, according to one embodiment of the present invention, in order to achieve smooth adjustment of the synchronization process, the synchronization error on the slave side The adjustment range adopts a step-by-step approach, and the master and slave are based on the synchronization error on both sides. Perform time t synchronization;

[0077] ;

[0078] in, The minimum threshold for the master and slave to start synchronization error adjustment, generally no more than 50μs; The maximum value of the single-cycle sampling beat adjustment amplitude is generally 10 to 15 μs; f is the frequency corresponding to the single cycle, and f=50HZ under the power frequency condition.

[0079] Furthermore, according to an embodiment of the present invention, each slave CPU performs a sampling synchronization pulse validity check. When the sampling synchronization pulse is detected to be illegal, the sampling synchronization pulse exception handling process is entered. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU. The sampling synchronization between the master CPU and the slave CPU is completed as follows:

[0080] The CPU sets the sampling synchronization pulse legitimacy check threshold based on the upper limit of the accumulated deviation of each sampling synchronization pulse adjustment amount, sampling synchronization pulse sending execution deviation, CPU crystal oscillator deviation, and FPGA processing chip crystal oscillator deviation. , The general value is 200 to 300 μs; when the FPGA processing chip detects the sampling synchronization pulse deviation is not greater than When the sampling synchronization pulse interval is determined to be within the legal range, the slave CPU adjusts the sampling beat according to the sampling synchronization pulse to achieve synchronization between the master CPU and the slave CPU; when the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse is abnormal, the process of handling the abnormality of the sampling synchronization pulse is entered. This solution can ensure the reliability of the device using the sampling synchronization pulse to adjust the sampling beat.

[0081] Furthermore, according to an embodiment of the present invention, the sampling synchronization pulse abnormality processing process includes:

[0082] When the FPGA processing chip detects that the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse interval is determined to be beyond the legal range, the sampling beat will no longer be adjusted according to the sampling synchronization pulse, and the FPGA processing chip will use its own beat to keep time; during the timekeeping process, if the FPGA processing chip detects the sampling synchronization pulse deviation is not greater than N1 times (N1 value is generally not greater than 5) , then the sampling synchronization pulse is restored to adjust the sampling beat. During the recovery process, the longitudinal differential protection device briefly blocks the longitudinal differential protection to avoid malfunction of the differential protection caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery. If the sampling synchronization pulse deviation still does not meet the conditions for recovery after the punctual time, the sampling synchronization pulse abnormal flag is directly set to block the longitudinal differential protection.

[0083] When the FPGA detects that the sampling synchronization pulse deviation is greater than 3 times in a row When the sync pulse abnormal flag is set directly, the longitudinal differential protection is locked. If the FPGA processing chip detects the sampling sync pulse deviation for N2 consecutive times (N2 value is generally not greater than 10), the sync pulse abnormal flag is set directly, the longitudinal differential protection is locked, and the FPGA processing chip detects the sampling sync pulse deviation for N2 consecutive times (N2 value is generally not greater than 10) , then the sampling synchronization pulse is used to adjust the sampling beat. During the recovery process, the longitudinal differential protection device temporarily locks the longitudinal differential protection to avoid the differential protection malfunction caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery. The longitudinal differential protection will be opened after the sampling synchronization pulse is stable.

[0084] Furthermore, according to one embodiment of the present invention, after the four CPUs of the host and slave machines on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side are sent to the master CPU through the high-speed data bus, and the master CPU sends the communication feature word, master CPU sampling data, slave CPU sampling data, switch quantity information, channel number, and application layer check code in accordance with the optical vertical data agreed format to the FPGA processing chip for data encapsulation; wherein, the communication feature word includes the master-slave random code, sampling point number, the most recently received sampling point number, etc.; the master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value; the slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

[0085] Furthermore, according to an embodiment of the present invention, each master CPU obtains synchronous sampling data of the opposite master CPU and slave CPU through an optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and the slave CPU are logically equivalent, including:

[0086] After the master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, it synchronizes the sampling data to the slave CPU through the sampling synchronization bus;

[0087] The master CPU on each side of the line selects synchronous sampling data from the opposite master CPU to construct the master CPU differential protection action equation, and the slave CPU on each side of the line selects synchronous sampling data from the opposite slave CPU to construct the slave CPU differential protection action equation;

[0088] Both the master and slave units determine the protection logic based on the differential protection action equations of their respective master and slave CPUs. When both the master and slave CPUs satisfy the differential protection action logic, the differential protection trip output is activated. If only one CPU meets the differential protection action conditions, the master or slave unit merely sends a message without illuminating the trip action indicator or activating the protection trip output. Backup protection follows the differential protection action logic, activating the output when both CPUs satisfy the action logic. This allows the line differential protection device to achieve dual-CPU protection logic parity, effectively improving the reliability of protection action.

[0089] According to the above-mentioned scheme of the present invention, the present invention solves the problem that the existing line protection device can only use the main CPU sampling data to perform differential protection logic operations by synchronously adjusting the dual CPUs of the longitudinal differential protection devices on both sides of the line and checking the legitimacy of the sampled synchronization pulses. It provides a practical method for constructing safe, reliable, and logically equivalent master and slave dual-CPU line longitudinal differential protection, and upgrades the existing "protection" + "start" architecture design to a "protection" + "protection" logic architecture, which can greatly improve the reliability of the line longitudinal differential protection device.

[0090] In the present invention, the device has a reliable sampling synchronization pulse legitimacy verification mechanism and complete exception handling and alarm measures, which can ensure the safety of using sampling synchronization pulses to adjust the sampling beat while effectively improving the reliability and stability of the device operation.

[0091] In the present invention, the device adopts a sampling architecture of "CPU processor" + "FPGA processing chip" + "A / D sampling chip", puts the sampling link in front, and completes the sampling by FPGA, while the CPU is only used to correct the FPGA sampling rhythm, which can effectively reduce the CPU load and improve the operating efficiency of the device.

[0092] In the present invention, the master and slave dual CPU sampling synchronization can greatly improve the consistency of dual CPU sampling of the line longitudinal differential protection device, and effectively avoid abnormal protection action behavior caused by sampling deviation.

[0093] The present invention is based on synchronous regulation of current and voltage by master and slave dual CPUs on both sides of the line, has a simple principle, is easy to implement, and has broad application prospects.

[0094] Furthermore, to achieve the above-mentioned object, the present invention also provides a line longitudinal differential protection system with dual CPU protection logic equivalence, comprising:

[0095] The master CPU and slave CPU configuration modules are configured, and longitudinal differential protection devices are configured on both sides of the line. The longitudinal differential protection devices on both sides adopt a dual-CPU protection architecture of the master CPU and the slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains sampling data from the master CPU and slave CPU on the opposite side through the optical longitudinal module;

[0096] Master-slave synchronization error calculation module, the longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication feature word information through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error on both sides. Calculation of

[0097] The host CPU sampling module has a fixed sampling rhythm for the host CPU and the slave CPU. The master CPU samples the data at a fixed time interval through the sampling synchronization bus based on its own sampling rhythm. Send sampling synchronization pulse to the master's slave CPU;

[0098] The slave CPU sampling module, the slave's main CPU according to the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave;

[0099] The master-slave sampling synchronization module verifies the validity of the sampling synchronization pulses of each slave CPU. If the sampling synchronization pulse is detected to be illegal, the abnormal processing flow of the sampling synchronization pulse is entered. Otherwise, the sampling rhythm is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving the sampling synchronization of the four CPUs of the master and slave machines on both sides of the line.

[0100] Synchronous sampling data processing module: each slave CPU sends the synchronous sampling data to each master CPU through a high-speed data bus, and then sends it to the optical longitudinal module through the master CPU for optical longitudinal data encapsulation. The switching value and communication feature word are packaged into a complete frame of data and sent to the optical longitudinal module of the opposite side longitudinal differential protection device through the optical fiber channel;

[0101] In the line longitudinal differential protection module, each master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and establishes a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent.

[0102] The line longitudinal differential protection system with dual CPU protection logic equivalence according to the present invention can implement the line longitudinal differential protection method with dual CPU protection logic equivalence. The specific process steps are as described above and will not be repeated here.

[0103] Furthermore, to achieve the above-mentioned purpose, the present invention also provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the line longitudinal differential protection method with dual-CPU protection logic equivalence as described above is implemented.

[0104] Furthermore, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the line longitudinal differential protection method with dual CPU protection logic equivalence as described above is implemented.

[0105] Those skilled in the art will appreciate that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0106] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and equipment can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0107] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0108] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

[0109] In addition, each functional module in the embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0110] If the functions are implemented as software modules and sold or used as standalone products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the energy-saving signal transmission / reception method according to various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, ROM, RAM, a magnetic disk, or an optical disk.

[0111] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0112] It should be understood that the size of the serial numbers of each step in the content of the invention and the implementation methods of the present invention does not absolutely mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present invention.

Claims

1. A line longitudinal differential protection method with dual CPU protection logic equivalence is characterized by: include: Longitudinal differential protection devices are configured on both sides of the line, and both adopt a dual-CPU protection architecture with a master CPU and a slave CPU. The master CPU and the slave CPU obtain local sampled data through their respective sampling modules, and the master CPU obtains sampled data from the master CPU and slave CPU on the opposite side through the optical longitudinal module. The longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication characteristic word information through the optical fiber channel, and use the ping-pong synchronization algorithm to synchronize the synchronization error between the two sides. Calculation of The host's main CPU and slave CPU sampling beats are fixed, and the main CPU samples the samples at intervals through the sampling synchronization bus based on its own sampling beat. Send sampling synchronization pulse to the master's slave CPU; The slave's main CPU calculates the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave; Each slave CPU performs a sampling synchronization pulse validity check. If the sampling synchronization pulse is detected to be illegal, it enters the sampling synchronization pulse exception processing process. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving sampling synchronization of the four CPUs of the master and slave machines on both sides of the line. Each slave CPU sends the synchronous sampling data to each master CPU through a high-speed data bus. The data is then sent to the optical longitudinal module by the master CPU for packaging. The switching value and communication feature word are then packaged into a complete frame of data and sent to the optical longitudinal module of the opposite longitudinal differential protection device through the optical fiber channel. Each master CPU obtains synchronous sampling data from the opposite master CPU and slave CPU through the optical longitudinal module, establishing a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent. The master and slave devices on both sides of the line are determined as follows: After powering up, the longitudinal differential protection devices on both sides of the line each generate a random code A and B, and send them to the other side in each frame of data transmission. After receiving the random code from the opposite side device, the longitudinal differential protection devices on both sides compare the values ​​of A and B and determine the master and slave devices based on the relative size of the values. If the two random codes A and B are found to be the same, another random code is generated for a second comparison; When the receiving channel of the longitudinal differential protection device on one side is interrupted, the previous master and slave determination status is maintained. After the channel is restored, the master and slave are determined again by re-comparing the size of the random codes of the two. Each master CPU obtains synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and constructs a line longitudinal differential protection function in which the master CPU and the slave CPU are logically equivalent, including: the master CPU on each side of the line selects the synchronous sampling data of the opposite master CPU to construct the master CPU differential protection action equation, and the slave CPU on each side of the line selects the synchronous sampling data of the opposite slave CPU to construct the slave CPU differential protection action equation; The master and slave machines both perform protection logic discrimination through the differential protection action equations of the master CPU and slave CPU that they have completed. When both the master CPU and the slave CPU meet the differential protection action logic, the differential protection action exits. If only one CPU meets the differential protection action conditions, the master or slave machine only sends a message.

2. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 1 is characterized in that: The master CPU and the slave CPU both adopt a sampling architecture that combines a CPU processor, an FPGA processing chip, and an A / D sampling chip; The CPU processor is used to complete the protection logic processing. The CPU processor of each main CPU uses the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time, and regularly sends synchronization pulses to correct the sampling beat of the FPGA processing chip; The FPGA processing chip adjusts its own sampling beat according to the synchronization pulse sent regularly by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling beat; The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip; A sampling synchronization pulse bus is provided between the master CPU and the slave CPU. The synchronization pulse sent by the master CPU to the FPGA processing chip is sent to the slave CPU via the synchronization pulse bus to correct the sampling beat of the slave CPU.

3. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 1 is characterized in that: The time interval , where n is the number of sampling points per cycle; is the sampling interval; It is the reliability coefficient of the host sampling synchronization pulse sending interval.

4. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 1 is characterized in that: The time interval , where n is the number of sampling points per cycle; is the sampling interval; It is the reliability coefficient of the interval of sending the sampling synchronization pulse of the slave.

5. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 1 is characterized in that: Also includes: The master and slave are based on the synchronization error on both sides Perform time t synchronization; ； in, The minimum threshold for starting synchronization error adjustment for the master and slave; is the maximum value of the single-cycle sampling beat adjustment amplitude; f is the frequency corresponding to the single cycle, and f=50HZ under the working frequency condition.

6. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 2, characterized in that: Each slave CPU performs a sampling synchronization pulse validity check. When the sampling synchronization pulse is detected to be illegal, the sampling synchronization pulse exception processing flow is entered. Otherwise, the sampling beat is adjusted according to the sampling synchronization pulse of the master CPU. The sampling synchronization between the master CPU and the slave CPU is completed as follows: The CPU sets the sampling synchronization pulse legitimacy check threshold based on the upper limit of the accumulated deviation of each sampling synchronization pulse adjustment amount, sampling synchronization pulse sending execution deviation, CPU crystal oscillator deviation, and FPGA processing chip crystal oscillator deviation. ; When the FPGA processing chip detects the sampling synchronization pulse deviation is not greater than When the sampling synchronization pulse interval is determined to be within the legal range, the slave CPU adjusts the sampling beat according to the sampling synchronization pulse to achieve synchronization between the master CPU and the slave CPU; when the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse exception processing flow is entered.

7. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 6, characterized in that: The sampling synchronization pulse abnormality processing process includes: When the FPGA processing chip detects that the sampling synchronization pulse deviation is greater than When the sampling synchronization pulse interval is determined to be beyond the legal range, the sampling beat will no longer be adjusted according to the sampling synchronization pulse, and the FPGA processing chip will use its own beat to keep time; during the timekeeping process, if the FPGA processing chip detects the sampling synchronization pulse deviation for N1 consecutive times and it is not greater than , then the sampling synchronization pulse is restored to adjust the sampling beat. During the restoration process, the longitudinal differential protection device is temporarily locked for the longitudinal differential protection. If the sampling synchronization pulse deviation still does not meet the conditions for restoration after the punctual time, the sampling synchronization pulse abnormal flag is directly set to lock the longitudinal differential protection. When the FPGA detects that the sampling synchronization pulse deviation is greater than 3 times in a row When the sync pulse abnormal flag is set directly, the longitudinal differential protection is locked. If the FPGA processing chip detects the sampling sync pulse deviation for N2 consecutive times, it is not greater than , then the sampling rhythm is adjusted by using the sampling synchronization pulse. During the recovery process, the longitudinal differential protection device temporarily blocks the longitudinal differential protection and opens the longitudinal differential protection after the sampling synchronization pulse stabilizes.

8. The line longitudinal differential protection method with dual CPU protection logic equivalence according to claim 2, characterized in that: After the four CPUs of the host and slave machines on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side are sent to the master CPU through the high-speed data bus. The master CPU sends the communication feature word, master CPU sampling data, slave CPU sampling data, switch quantity information, channel number, and application layer check code to the FPGA processing chip for data encapsulation in accordance with the optical longitudinal data agreed format; among them, the communication feature word includes the master-slave random code, sampling point number, and the most recently received sampling point number; the master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value; the slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

9. The line longitudinal differential protection system with dual CPU protection logic is characterized by: include: The master CPU and slave CPU configuration modules are configured, and longitudinal differential protection devices are configured on both sides of the line. The longitudinal differential protection devices on both sides adopt a dual-CPU protection architecture of the master CPU and the slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains sampling data from the master CPU and slave CPU on the opposite side through the optical longitudinal module; Master-slave synchronization error calculation module, the longitudinal differential protection device on one side of the line is the master, and the longitudinal differential protection device on the other side is the slave. The master and the slave exchange analog quantity, switch quantity, and communication feature word information through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error on both sides. Calculation of The host CPU sampling module has a fixed sampling rhythm for the host CPU and the slave CPU. The master CPU samples the data at a fixed time interval through the sampling synchronization bus based on its own sampling rhythm. Send sampling synchronization pulse to the master's slave CPU; The slave CPU sampling module, the slave's main CPU according to the synchronization error between the two sides Adjust the CPU sampling time regularly to track the host sampling beat and sample at intervals through the sampling synchronization bus Send sampling synchronization pulse to the slave CPU of the slave; The master-slave sampling synchronization module verifies the validity of the sampling synchronization pulses of each slave CPU. If the sampling synchronization pulse is detected to be illegal, the abnormal processing flow of the sampling synchronization pulse is entered. Otherwise, the sampling rhythm is adjusted according to the sampling synchronization pulse of the master CPU to complete the sampling synchronization of the master CPU and the slave CPU, thus achieving the sampling synchronization of the four CPUs of the master and slave machines on both sides of the line. Synchronous sampling data processing module: each slave CPU sends the synchronous sampling data to each master CPU through a high-speed data bus. The master CPU then sends the data to the optical longitudinal module for encapsulation. The switching value and communication feature word are packaged into a complete frame of data and sent to the optical longitudinal module of the opposite longitudinal differential protection device through the optical fiber channel. Line longitudinal differential protection module: Each master CPU obtains synchronous sampling data from the opposite master CPU and slave CPU through the optical longitudinal module, establishing a line longitudinal differential protection function in which the master CPU and slave CPU are logically equivalent. The master and slave devices on both sides of the line are determined as follows: After powering up, the longitudinal differential protection devices on both sides of the line each generate a random code A and B, and send them to the other side in each frame of data transmission. After receiving the random code from the opposite side device, the longitudinal differential protection devices on both sides compare the values ​​of A and B and determine the master and slave devices based on the relative size of the values. If the two random codes A and B are found to be the same, another random code is generated for a second comparison; When the receiving channel of the longitudinal differential protection device on one side is interrupted, the previous master and slave determination status is maintained. After the channel is restored, the master and slave are determined again by re-comparing the size of the random codes of the two. Each master CPU obtains synchronous sampling data of the opposite master CPU and slave CPU through the optical longitudinal module, and constructs a line longitudinal differential protection function in which the master CPU and the slave CPU are logically equivalent, including: the master CPU on each side of the line selects the synchronous sampling data of the opposite master CPU to construct the master CPU differential protection action equation, and the slave CPU on each side of the line selects the synchronous sampling data of the opposite slave CPU to construct the slave CPU differential protection action equation; The master and slave machines both perform protection logic discrimination through the differential protection action equations of the master CPU and slave CPU that they have completed. When both the master CPU and the slave CPU meet the differential protection action logic, the differential protection action exits. If only one CPU meets the differential protection action conditions, the master or slave machine only sends a message.

10. An electronic device, characterized in that The invention comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the line longitudinal differential protection method with dual-CPU protection logic equivalence as described in any one of claims 1 to 8 is implemented.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the line longitudinal differential protection method with dual-CPU protection logic equivalence according to any one of claims 1 to 8 is implemented.

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