ESD / EOS protection circuit for dynamic leakage suppression

Abstract

The invention discloses an ESD / EOS protection circuit for dynamic electric leakage suppression, which is connected between a voltage source and electronic equipment and comprises a reference circuit, a high-voltage leakage circuit and an electric leakage elimination circuit, the reference circuit is used for starting the high-voltage bleeder circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamping the voltage at the set voltage; the high-voltage bleeder circuit is used for quickly discharging current when the ESD / EOS is attacked; the electric leakage elimination circuit is used for reducing dynamic electric leakage of the ESD / EOS protection circuit when the protected electronic equipment is normally powered on and works; according to the protection circuit, a large amount of current can be discharged in a relatively short time, so that the protected circuit is more difficult to be broken down and damaged by high voltage; according to the embodiment of the invention, the leakage current of the protection circuit is reduced by adopting the special circuit, the dynamic power consumption is greatly reduced, and the normal work of the protection circuit is not influenced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supplies, and particularly relates to an ESD / EOS protection circuit for dynamic leakage suppression. Background Art

[0002] In the current era when various electronic components have entered thousands of households, electrostatic discharge / electrical overstress (ESD / EOS) and voltage transients, as a major killer of electronic components, can cause semiconductor devices (diodes, transistors, etc.) in electronic circuits to burn out or break down, affecting the normal functions of the circuits. There are many scenarios where ESD / EOS and transient voltages can be generated, ranging from natural lightning strikes to simple circuit switches, and even after a person moves, there may be tens of thousands of volts of high voltage on the body. Therefore, the direct or indirect economic losses caused by it every year are extremely huge. Therefore, taking protective measures against ESD / EOS and voltage transients and building an ESD / EOS protection circuit between electronic components and voltage sources has high practical value.

[0003] Existing ESD / EOS protection circuits usually work in the way of diode breakdown, that is, multiple Zener diodes are connected in series to limit the clamping voltage, so that the voltage received by the protected circuit is not greater than its breakdown voltage. And a metal-oxide-semiconductor (MOS) transistor is used as a switch to turn on the discharge circuit when the external ESD / EOS voltage is greater than the clamping voltage, playing the role of ESD / EOS protection.

[0004] There are defects in the protection method of this kind of ESD / EOS protection circuit. Since when the protected circuit is working normally, during the power-on process of the normal working voltage or when the working voltage fluctuates dynamically, this voltage change (dv / dt) will charge the source-drain capacitance on the MOS transistor, generating a source-drain current, and the MOS transistor is in a slightly conducting state, and a certain current will flow through the circuit, which is called dynamic leakage. If no additional dynamic leakage reduction circuit is added, a large dynamic leakage current will be generated in the circuit, increasing the dynamic power consumption. Summary of the Invention

[0005] Object of the Invention: The object of the present invention is to provide an ESD / EOS protection circuit that uses a metal-oxide-semiconductor field-effect transistor (MOSFET) to set the clamping voltage. When ESD / EOS strikes, it can clamp the voltage at a certain fixed voltage value, and an additional leakage elimination circuit is adopted to eliminate dynamic leakage.

[0006] Technical Solution: A dynamic leakage suppression ESD / EOS protection circuit of the present invention is connected between a voltage source and an electronic device. The ESD / EOS protection circuit is jointly composed of a reference circuit and a leakage elimination circuit connected in parallel at an external voltage input end, and a high-voltage discharge circuit connected in series between the reference circuit and the protected circuit, forming a three-stage linkage protection system;

[0007] The reference circuit is used to turn on the high-voltage discharge circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamp the voltage at the set voltage; the reference circuit is composed of a PLDMOS transistor PM0, a resistor R0, and n-1 Zener diodes D2~Dn.

[0008] The high-voltage discharge circuit is used to quickly discharge current when ESD / EOS strikes; the high-voltage discharge circuit is composed of a Zener diode D0, a resistor R1, and an NLDMOS transistor NM0.

[0009] The leakage elimination circuit is used to reduce the dynamic leakage of the ESD / EOS protection circuit when the protected electronic device is normally powered on and working; the leakage elimination circuit is composed of a charging capacitor C0, a Zener diode D1, a resistor R2, and an NLDMOS transistor NM1.

[0010] Further, in the reference circuit, the connection method of the n-1 Zener diodes D2~Dn is: the n-1 Zener diodes D2~Dn are connected in reverse series, that is, the positive electrode is connected to the low potential, the negative electrode is connected to the high potential and is connected across the voltage source and the ground.

[0011] Further, the G terminal of PM0 is connected to one end of the gate resistor R0, the other end of R0 and the S terminal of PM0 are connected to the positive electrode of the voltage source, and the D terminal is connected to the cathode of D0 in the high-voltage discharge circuit, the upper end of R1, the G terminal of NM0, and the D terminal of the leakage elimination circuit; R1 is in parallel with D0, the anode of D0, the lower end of R1, and the S terminal of NM0 are all connected to the negative electrode of the voltage source, and the D terminal of NM0 is connected to the positive electrode of the voltage source.

[0012] Further, in the leakage elimination circuit, the anode of C0 is connected to the positive electrode of the voltage source, and the cathode is connected to the anode of D1, R2, and the G terminal of NM1; the cathode of D0, the lower end of R2, and the S terminal of NM1 are all connected to the negative electrode of the voltage source.

[0013] Further, the n-1 Zener diodes D2~Dn are responsible for clamping, and clamp the external high ESD / EOS voltage to a specified value when it is high. PM0 is used as a driving transistor to generate the turn-on voltage of NM0 on R1, and NM0 is used as a discharge transistor to release the ESD / EOS current.

[0014] Further, C0 is charged when the external normal operating voltage is applied, and generates the turn-on voltage of NM1 on R2. NM1 is used to reduce the dynamic leakage current in the ESD / EOS protection circuit.

[0015] Beneficial effects: Compared with the prior art, the present invention has the following remarkable advantages:

[0016] 1. The protection circuit of the present invention can discharge a large amount of current in a relatively short time during an external ESD / EOS event, making it more difficult for the protected circuit to be damaged by high voltage breakdown.

[0017] 2. The embodiment of the present invention uses a dedicated circuit to reduce the leakage current of the protection circuit, which can significantly reduce the dynamic power consumption when the circuit is powered on under non-ESD / EOS events, and is especially suitable for low-power or battery-powered scenarios.

[0018] 3. The embodiment of the present invention can improve the stability of the circuit under voltage transients or surge impulses.

[0019] 4. The embodiment of the present invention is compatible with ordinary CMOS processes, does not introduce additional layers, and can save manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic block diagram of the ESD / EOS protection circuit according to the embodiment of the present invention.

[0021] Figure 2 It is a circuit diagram of the ESD / EOS protection circuit according to the embodiment of the present invention.

[0022] Figure 3 It is a circuit diagram of Example 1 of the ESD / EOS protection circuit according to the embodiment of the present invention.

[0023] Figure 4 It is a comparison diagram of the leakage current magnitudes between Example 1 of the ESD / EOS protection circuit according to the embodiment of the present invention and the original ESD / EOS protection circuit without a leakage elimination circuit.

[0024] Figure 5 It is a schematic diagram of the externally applied normal operating voltage when testing the leakage of Example 1 of the ESD / EOS protection circuit according to the embodiment of the present invention and the original ESD / EOS protection circuit without a leakage elimination circuit.

[0025] Figure 6 It is a schematic diagram of the clamping effect of Example 1 of the ESD / EOS protection circuit according to the embodiment of the present invention under an external ESD voltage. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Embodiments of the present invention disclose a novel ESD / EOS protection circuit, which can clamp the voltage at the protected circuit to the normal operating voltage when the protected circuit is subjected to a high ESD / EOS voltage impact, ensuring that the protected circuit is not affected by external ESD / EOS and maintaining normal operation. It should be noted that in the embodiments of the present invention, the protected circuit generally includes, but is not limited to, MOS, capacitors, inductors, resistors, etc. It should be pointed out that in the embodiments of the present invention, high voltage and low voltage are relative concepts. For example, if the protected circuit is a circuit that can operate normally at a voltage below 50V, then a voltage with a peak voltage exceeding 50V is a high ESD / EOS voltage, and the ESD / EOS protection circuit needs to play a clamping role to clamp the voltage to 50V. It should be pointed out that only the distinction criteria for high voltage and low voltage are pointed out here. According to the actual situation, the protected circuit can also be a circuit that operates at other voltages, and the corresponding clamping voltage can also change accordingly.

[0027] Based on the types and application scenarios of the protected circuits described above, the following embodiments of the invention are proposed.

[0028] As Figure 1 and Figure 2 shown, the ESD / EOS protection circuit of the embodiments of the present invention should be composed of a reference circuit, a high-voltage discharge circuit, and a leakage elimination circuit. The ESD / EOS protection circuit of the embodiments of the present invention should be connected between the voltage source and the electronic device, and its components include:

[0029] The reference circuit is used to turn on the high-voltage discharge circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamp the voltage at the set voltage.

[0030] The high-voltage discharge circuit is used to quickly discharge the current when ESD / EOS strikes.

[0031] The leakage elimination circuit is used to reduce the dynamic leakage of the ESD / EOS protection circuit when the protected electronic device is powered on and operates normally.

[0032] The circuit should specifically include:

[0033] The reference circuit is composed of a PLDMOS (referred to as PM0), a resistor R0, and Zener diodes D2 to Dn.

[0034] The high-voltage discharge circuit is composed of a Zener diode D0, a resistor R1, and an NLDMOS (referred to as NM0).

[0035] The leakage elimination circuit is composed of a charging capacitor C0, a Zener diode D1, a resistor R2, and an NLDMOS (referred to as NM1).

[0036] The connection mode of the n - 1 Zener diodes D2 to Dn in the reference circuit is as follows: The n - 1 Zener diodes D2 to Dn are connected in reverse series, that is, the positive electrodes are connected to the low potential, the negative electrodes are connected to the high potential and are connected across the voltage source and the ground. One end of the gate resistor R0 is connected to the G - terminal of PM0, the other end of R0 and the S - terminal of PM0 are connected to the positive electrode of the voltage source, and the D - terminal is connected to the cathode of D0 in the high - voltage discharge circuit, the upper end of R1, the G - terminal of NM0 and the D - terminal of the leakage elimination circuit; R1 is in parallel with D0, the anode of D0, the lower end of R1 and the S - terminal of NM0 are all connected to the negative electrode of the voltage source, and the D - terminal of NM0 is connected to the positive electrode of the voltage source; In the leakage elimination circuit, the anode of C0 is connected to the positive electrode of the voltage source, and the cathode is connected to the anode of D1, R2 and the G - terminal of NM1; The cathode of D0, the lower end of R2 and the S - terminal of NM1 are all connected to the negative electrode of the voltage source.

[0037] As an implementation, the reference circuit is composed of a PLDMOS (referred to as PM0). One end of R0 is connected to the G - terminal of PM0, the other end of R0 and the S - terminal of PM0 are connected to the positive electrode of the voltage source, and the D - terminal is connected to the cathode of D0.

[0038] As an implementation, PM0 acts as a breakdown tube to generate the turn - on voltage of NM0 on R1, and NM0 acts as a discharge tube to release the ESD / EOS current.

[0039] As an implementation, C0 is charged when the normal operating voltage is applied externally, generates the turn - on voltage of NM1 on R2, and NM1 is used to reduce the dynamic leakage current in the ESD / EOS protection circuit.

[0040] The working principle of the embodiment of the present invention is as follows: When the surge voltage is greater than the specified clamping voltage, multiple series-connected Zener diodes are simultaneously broken down to generate a reference voltage. At the same time, since a current flows through the gate resistor R0, the gate voltage increases, causing a driving current to be generated at PM0. This current flows through the resistor R1, raising the voltage across R1, thereby enabling the gate voltage of the high-voltage discharge transistor NM0 to reach its threshold voltage, turning on M0, discharging a large amount of current, and clamping the entire circuit at a certain voltage. In actual use, when an external voltage source provides a normal operating voltage to power on the protected circuit normally, or when there is a voltage fluctuation in the applied voltage, due to the existence of the source-drain capacitance of the MOS transistor, a source-drain current is generated. When this current flows through R1, it will cause NM0 to be in a slightly conducting state, and there will still be a small current in the circuit, resulting in leakage of the protection circuit, which is called dynamic leakage. In the embodiment of the present invention, when powering on, since the capacitance value of C0 in the leakage elimination circuit is much larger than the parasitic capacitance of the PLDMOS, the current flowing through the leakage elimination circuit is much larger than the current flowing through the PLDMOS. At this time, the current flowing through the leakage elimination circuit flows through the gate resistor R2 of NM1, raising the voltage across R2, thereby enabling the gate voltage of the leakage elimination transistor NM1 to reach its threshold voltage, turning on M0. Due to the small on-resistance of NM0, the voltage across the gate resistor of NM0 is not sufficient to turn on the discharge transistor NM0, and the dynamic leakage of the circuit is greatly eliminated at this time. When an external ESD / EOS occurs, the external voltage frequency is small, C0 will not be charged, the leakage elimination circuit does not work, and it does not affect the normal operation of the ESD / EOS protection circuit.

[0041] It should be noted that the clamping voltage value in the embodiment of the present invention should be less than the source-drain breakdown voltage value of the LDMOS transistor PM0. Therefore, the type of LDMOS transistor can be selected according to the required clamping voltage value.

[0042] In the embodiment of the present invention, the values of the capacitance and resistance can be modified according to requirements. At the same time, the source-drain breakdown voltage values of the NLDMOS and NLDMOS are not limited and can be determined according to actual application requirements. Optionally, for the specific circuit connection relationship of the device that needs to be protected against ESD / EOS, it can also be flexibly set according to actual application requirements.

[0043] It is worth noting that in order to reduce the dynamic leakage current, a dedicated dynamic leakage elimination circuit is added in the embodiment of the present invention. This will be illustrated by specific examples below.

[0044] Example 1:

[0045] It should be noted that as Figure 3As shown, the ESD / EOS protection circuit shown in this example is an embodiment of the invention with a clamping voltage of 32.5V, which is exactly the same as the above-mentioned embodiment of the invention except for the source-drain breakdown voltage value of PM0. The original ESD / EOS protection circuit for comparison only lacks a dedicated dynamic leakage elimination circuit compared with the above-mentioned ESD / EOS protection circuit.

[0046] The dynamic leakage test results of the ESD / EOS protection circuit described in Example 1 of the embodiment of the present invention are as Figure 4 shown. Figure 4 For the comparison of the dynamic leakage magnitudes of the two circuits under the same Trise.

[0047] It can be seen that after adding a dedicated leakage elimination circuit, when the external temperature is 300K, the peak value of Ileak of the ESD / EOS protection circuit can be reduced to 15.8% of the original. Thus, it can be seen that adding a leakage elimination circuit significantly reduces the dynamic leakage of the circuit, reduces the dynamic power consumption of the circuit, and improves the transparency of the ESD / EOS protection circuit.

[0048] It should be emphasized that the dynamic leakage of the ESD / EOS protection circuit shown in this Example 1 is very small, and the clamping effect is excellent, which can provide high transparency and high reliability ESD / EOS protection for the protected working circuit.

[0049] It should be emphasized that the circuit of the embodiment of the present invention is not limited to a clamping voltage of 32.5V. For Example 1, the clamping voltage can be modified by modifying the number of series-connected forward and reverse diodes. For example, when it is necessary to limit the clamping voltage to 56V, 9 reverse-biased 6V Zener diodes need to be connected in series. At this time, the clamping voltage value is approximately the sum of the threshold voltage of PM0 and the total breakdown voltage of the Zener diodes.

[0050] In addition, for the selection of the capacitor and NLDMOS of the leakage elimination circuit in the ESD / EOS protection circuit of the embodiments of the present invention. The capacitor should act as an open circuit when an external ESD / EOS voltage is applied and conduct the leakage elimination circuit when a normal operating voltage is applied. That is, the capacitor should block when a slowly changing ESD / EOS voltage arrives and conduct when a rapidly changing operating voltage arrives. Therefore, a relatively large capacitance value needs to be selected for the capacitor. However, considering the manufacturing process limitations of large capacitors, in integrated circuits, MIM capacitors, MOM capacitors or MOS capacitors can be used, but the maximum capacitance value should not exceed 1 nF. For the NLDMOS used in the leakage elimination circuit, considering that it needs to quickly discharge a certain amount of current and comprehensively considering the process complexity, the same NLDMOS as the dynamic leakage discharge transistor can be selected. However, since the discharge current is much smaller than that of the transistor, the width of the transistor should be appropriately reduced to save area. It should be emphasized that in other applications of this invention patent, NLDMOS\PLDMOS can be replaced with other types of MOS transistors or switching devices according to the specific implementation form, and it is still regarded as a derivative of this invention.

[0051] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these examples without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A dynamic leakage suppression ESD / EOS protection circuit, connected between a voltage source and an electronic device, characterized in that, The ESD / EOS protection circuit is composed of a reference circuit and a leakage elimination circuit connected in parallel to the external voltage input terminal, and a high-voltage discharge circuit connected in series between the reference circuit and the circuit to be protected, forming a three-stage linkage protection system; The reference circuit is used to turn on the high-voltage discharge circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamp the voltage at a set voltage; the reference circuit is composed of a PLDMOS transistor PM0, a resistor R0, and n - 1 Zener diodes D2~Dn; The high-voltage discharge circuit is used to quickly discharge the current when ESD / EOS strikes; the high-voltage discharge circuit is composed of a Zener diode D0, a resistor R1, and an NLDMOS transistor NM0; The leakage elimination circuit is used to reduce the dynamic leakage of the ESD / EOS protection circuit when the protected electronic device is powered on and working normally; the leakage elimination circuit is composed of a charging capacitor C0, a Zener diode D1, a resistor R2, and an NLDMOS transistor NM1.

2. The ESD / EOS protection circuit for dynamic leakage suppression according to claim 1, wherein In the reference circuit, the connection method of the n - 1 Zener diodes D2~Dn is: the n - 1 Zener diodes D2~Dn are connected in reverse series, that is, the positive electrode is connected to the low potential, the negative electrode is connected to the high potential and is connected across the voltage source and the ground.

3. The ESD / EOS protection circuit for dynamic leakage suppression according to claim 1, characterized in that, The G terminal of the PM0 is connected to one end of the gate resistor R0, the other end of the R0 and the S terminal of the PM0 are connected to the positive electrode of the voltage source, and the D terminal is connected to the cathode of D0 in the high-voltage discharge circuit, the upper end of R1, the G terminal of NM0, and the D terminal of the leakage elimination circuit; R1 is connected in parallel with D0, the anode of D0, the lower end of R1, and the S terminal of NM0 are all connected to the negative electrode of the voltage source, and the D terminal of NM0 is connected to the positive electrode of the voltage source.

4. The ESD / EOS protection circuit for dynamic leakage suppression according to claim 1, wherein In the leakage elimination circuit, the anode of C0 is connected to the positive electrode of the voltage source, and the cathode is connected to the anode of D1, R2, and the G terminal of NM1; the cathode of D0, the lower end of R2, and the S terminal of NM1 are all connected to the negative electrode of the voltage source.

5. The ESD / EOS protection circuit for dynamic leakage suppression according to claim 1, wherein The n - 1 Zener diodes D2~Dn are responsible for clamping, clamping the external high ESD / EOS voltage to a specified value, PM0 acts as a driving transistor, generating the turn-on voltage of NM0 on R1, and NM0 acts as a discharge transistor to release the ESD / EOS current.

6. The ESD / EOS protection circuit for dynamic leakage suppression according to claim 1, characterized in that The C0 is charged when the normal operating voltage is applied externally, generating the turn-on voltage of NM1 on R2, and NM1 is used to reduce the dynamic leakage current in the ESD / EOS protection circuit.

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