Bleeding circuit, domain controller and vehicle

Abstract

The invention provides a bleeder circuit, a domain controller and a vehicle. The bleeder circuit provided by the embodiment of the invention is applied to the domain controller, the SoC in the domain controller is powered by a plurality of SoC power supplies, the bleeder circuit comprises a control unit and a plurality of charge bleeder units, and each charge bleeder unit is connected with one SoC power supply. When the SoC power supply is abnormal, the control unit can control each charge discharge unit to synchronously conduct the discharge path under the triggering of a control signal provided by the MCU, thereby synchronously and quickly discharging the residual charge of each SoC power supply. According to the embodiment of the invention, the stability and reliability of the domain controller can be improved, and faults of the domain controller such as starting abnormity and repeated restarting after abnormal power-on can be effectively avoided.

Description

Technical Field

[0001] The present disclosure relates to intelligent driving technology, and in particular, to a discharge circuit, a domain controller, and a vehicle. Background Art

[0002] With the wide application of autonomous driving technology, the domain controller deployed in a vehicle needs to complete many tasks such as perception, positioning, decision-making, planning, and control functions. Therefore, in a domain controller, one or more system-on-chip (SoC) and MCU with different computing powers usually need to be integrated to meet the requirements of high-performance computing and data processing in vehicle intelligence.

[0003] However, since the SoC in the domain controller usually has clear power-on timing requirements, after abnormal power-on, the domain controller is prone to failures such as power-on failure, abnormal startup, startup failure, and repeated restart due to problems such as charge residue in the SoC power supply, which affects the normal operation of functions such as autonomous driving and the safe driving of the vehicle. Summary of the Invention

[0004] In view of this, the present disclosure provides a discharge circuit, a domain controller, and a vehicle.

[0005] According to a first aspect of the present disclosure, a discharge circuit is provided, which is applied to a domain controller. The domain controller includes a microcontroller (MCU) and a system-on-chip (SoC). The SoC is powered by multiple SoC power supplies. The discharge circuit includes a control unit and multiple charge discharge units. Each charge discharge unit is connected to one of the SoC power supplies, and the control unit is connected to each charge discharge unit and the MCU;

[0006] The control unit is configured to generate a high-level trigger signal in response to a low-level control signal and send it to each charge discharge unit. The low-level control signal is output from the MCU to the control unit when the MCU detects that the state of the SoC power supply is abnormal;

[0007] Each charge discharge unit is configured to conduct its own discharge path in response to the high-level trigger signal to discharge the residual charge of the SoC power supply to which it is connected.

[0008] In some embodiments of the first aspect of the present disclosure, the control unit is further configured to generate a low-level trigger signal in response to a high-level control signal. The high-level control signal is output from the MCU to the control unit when the MCU detects that the state of the SoC power supply is normal. When the trigger signal is low, each charge discharge unit does not act.

[0009] In some embodiments of the first aspect of the present disclosure, the control unit includes a first NMOS transistor, a voltage-dividing resistor, a pull-down resistor, and a current-limiting resistor. The gate of the first NMOS transistor is connected to the control signal output terminal of the MCU through the voltage-dividing resistor and grounded through the pull-down resistor at the same time. The source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor serves as the output terminal of the trigger signal and is connected to the first power supply through the current-limiting resistor. The first power supply is used to provide the working voltage for the control unit.

[0010] In some embodiments of the first aspect of the present disclosure, a fixed resistor is connected in parallel between the drain and the source of the first NMOS transistor; and / or, a diode is connected in parallel between the drain and the source of the first NMOS transistor; and / or, a filter capacitor is connected in parallel between the drain and the source of the first NMOS transistor.

[0011] In some embodiments of the first aspect of the present disclosure, each charge discharge unit includes: a second NMOS transistor, a voltage-dividing resistor, a pull-down resistor, and a current-limiting resistor. The gate of the second NMOS transistor is connected to the trigger signal output terminal of the control unit through the voltage-dividing resistor and grounded through the pull-down resistor. The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to one of the SoC power supplies through the current-limiting resistor.

[0012] In some embodiments of the first aspect of the present disclosure, the multiple SoC power supplies include a first SoC power supply and a second SoC power supply for power supply. The voltage of the first SoC power supply is lower than that of the second SoC power supply. The discharge circuit includes a first charge discharge unit and a second charge discharge unit; the first charge discharge unit is connected to the first SoC power supply and is configured to conduct its own discharge path in response to the high-level trigger signal to discharge the residual charge of the first SoC power supply; the second charge discharge unit is connected to the second SoC power supply and is configured to conduct its own discharge path in response to the high-level trigger signal to discharge the residual charge of the second SoC power supply.

[0013] According to the second aspect of the present disclosure, a domain controller is provided. The domain controller includes: a microcontroller MCU, a system-on-chip SoC, and the above-mentioned discharge circuit. The SoC is powered by multiple SoC power supplies. The control terminal of the control unit in the discharge circuit is connected to the MCU, the output terminal of the control unit is connected to the control terminals of each charge discharge unit, and one end of each charge discharge unit is connected to one of the SoC power supplies and the other end is grounded.

[0014] In some embodiments of the second aspect of the present disclosure, the MCU is configured to detect the status of the SoC power supply. When the SoC power supply is absent, it determines that the SoC power supply status is abnormal and outputs the control signal with a low level to the discharge circuit. When it detects that the SoC is normally powered, it determines that the SoC power supply status is normal and outputs the control signal with a high level to the discharge circuit.

[0015] In some embodiments of the second aspect of the present disclosure, the absence of the SoC power supply includes one or more of the following: under-voltage of the SoC power supply, interruption of the SoC power supply, zero voltage of the SoC power supply, and power-off of the SoC power supply.

[0016] According to the third aspect of the present disclosure, a vehicle is provided, including the above-mentioned domain controller.

[0017] It can be seen from the above technical solutions that in the embodiments of the present disclosure, when the SoC power supply is abnormal (for example, abnormal power-on of the SoC, interruption of the SoC power supply, under-voltage of the SoC power supply, etc.), the residual charge of the SoC power supply can be quickly discharged through the discharge circuit to ensure that the domain controller can be normally started during the next power-on. At the same time, by adding a discharge circuit in the domain controller, it can ensure the stable and reliable operation of the domain controller during rapid power-on and power-off, and avoid faults such as abnormal startup and repeated restart after abnormal power-on. In addition, the embodiments of the present disclosure realize the safe discharge of the SoC power supply in the domain controller through hardware-level control, with higher reliability, and are applicable to high-reliability scenarios such as autonomous driving. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of the domain controller and the discharge circuit provided by the embodiments of the present disclosure;

[0020] Figure 2 It is a schematic circuit diagram of the control unit in the discharge circuit provided by the embodiments of the present disclosure;

[0021] Figure 3 It is a schematic circuit diagram of the second charge discharge unit in the discharge circuit provided by the embodiments of the present disclosure;

[0022] Figure 4 It is a schematic circuit diagram of the first charge discharge unit in the discharge circuit provided by the embodiments of the present disclosure;

[0023] Figure 5 Schematic diagram of the residual charge discharge process of the SoC power supply in the domain controller provided by the embodiments of the present disclosure. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0025] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. The singular forms of "a", "the" and "said" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0026] Depending on the context, words such as "if" and "when" used herein may be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determining" or "when detected (stated condition or event)" or "in response to detecting (stated condition or event)".

[0027] As described above, the SoC in the domain controller usually has clear power-on timing requirements, and charge residues are likely to occur in the SoC power supply under abnormal power-on conditions. Specifically, in the domain controller, abnormal power-on of the SoC refers to the phenomenon that the SoC fails to complete the normal power-on process due to problems such as power supply, timing, hardware or software during the startup process, resulting in the absence of the SoC power supply and the SoC being unable to enter the expected working state. Such abnormalities may cause system startup failures, functional disorders or even hardware damage to the domain controller.

[0028] In the domain controller, when the SoC has abnormal power-on, charge residue phenomena are likely to occur in the SoC power supply circuit, mainly in the following aspects:

[0029] 1) If the power management integrated circuit (PMIC) of the domain controller fails to completely cut off the power path during abnormal power-off (such as voltage drop or forced shutdown), some power rails may still form leakage current paths through internal or external circuits, resulting in slow discharge of the capacitor or even partial charge residue.

[0030] 2) The normal power-on / power-off of the SoC usually needs to follow strict timing control. If abnormal power-off disrupts the timing, the PMIC may not be able to correctly turn off some power domains, resulting in incomplete discharge of the capacitors.

[0031] 3) The power supply circuit of the SoC power usually includes large-capacity energy storage capacitors (such as decoupling capacitors and energy storage capacitors). These capacitors may not be able to discharge quickly through the load during abnormal power-off, and the charge will stay for a long time.

[0032] 4) Some protection circuits (such as reverse diodes, etc.) in the power supply circuit of the SoC power may cut off the low-impedance discharge path under abnormal conditions, resulting in the capacitors can only discharge through the high-impedance parasitic path, prolonging the charge retention time.

[0033] 5) During abnormal power-on events, the protection circuit in the SoC or domain controller may actively cut off the power supply, and the capacitor charge will be "latched" in the isolated power network.

[0034] 6) If the software fails to send a power-off command in time when the SoC is powered off abnormally, the internal power domain may be in a "suspended" state (such as some modules are still powered on), resulting in the external power supply needs to continuously supply power to the internal circuit, delaying the capacitor discharge and causing charge retention.

[0035] There is charge retention in the SoC power supply, which may interfere with the subsequent power-on process, continue to cause abnormal power-on, and then cause the domain controller to have faults such as power-on failure, startup anomaly, startup failure, and repeated restart. For example, the residual charge causes the power rail to have a voltage before power-on, that is, the initial voltage offset, resulting in the PMIC misjudging the power supply state (such as misjudging as powered on), causing the SoC power supply to fail to power on; or for another example, the residual voltage causes some modules in the SoC to start in advance, disrupting the power sequence (such as the I / O power supply is turned on earlier than the core power supply), resulting in a timing conflict and causing the SoC power-on timing to be disordered; or for another example, the SoC detecting a non-zero voltage will trigger an internal protection mechanism (such as latch-up effect), preventing normal initialization and resulting in power-on failure.

[0036] As can be seen from the above, in the actual system, charge retention and abnormal power-on may form a positive feedback loop, that is, the first abnormal power-on causes charge retention, the residual charge interferes with the next power-on resulting in secondary abnormal power-on, and the secondary anomaly further exacerbates the charge retention, and so on in a cycle until it causes the domain controller to frequently have faults such as power-on failure, startup anomaly, startup failure, and repeated restart.

[0037] In practical applications, if the vehicle is suddenly powered off, resulting in charge retention, the residual charge will cause the timing of the PMIC in the domain controller to be chaotic during the next startup, triggering secondary abnormal power-on, and the system of the domain controller may enter this endless loop.

[0038] In view of this, the embodiments of the present disclosure provide the following discharge circuit, domain controller, and vehicle. By arranging a discharge circuit between the MCU of the domain controller and each SoC power supply for powering the SoC, the residual charge of the SoC power supply is quickly discharged, thereby effectively reducing the problem of charge residue of the SoC power supply and improving the reliability and safety of the domain controller.

[0039] In the embodiments of the present disclosure, the residual charge of the SoC power supply may include, but is not limited to, the residual charge on the power rail associated with the SoC power supply.

[0040] Figure 1 The schematic structural diagram of the discharge circuit 130 provided by the embodiments of the present disclosure and the domain controller 100 including the discharge circuit 130 is shown.

[0041] See Figure 1 , in addition to including the discharge circuit 130, the domain controller 100 to which the discharge circuit 130 provided by the embodiments of the present disclosure is applied may further include a microcontroller (MCU) 110 and an SoC 120. The SoC 120 is powered by multiple SoC power supplies, and the multiple SoC power supplies may be converted from an external power supply (such as a vehicle power supply, an auxiliary power supply, etc.).

[0042] See Figure 1 , the discharge circuit 130 provided by the embodiments of the present disclosure may include a control unit 131 and multiple charge discharge units 132. Each charge discharge unit 132 is connected to one SoC power supply, and the control unit 131 is connected to each charge discharge unit 132 and the MCU 110. Among them, the control unit 131 is configured to generate a high-level trigger signal in response to a low-level control signal and send it to each charge discharge unit 132. The low-level control signal is output from the MCU 110 to the control unit 131 when the SoC power supply state is detected to be abnormal; each charge discharge unit 132 is configured to turn on its own discharge path in response to the high-level trigger signal to discharge the residual charge of the SoC power supply connected thereto.

[0043] Further, the control unit 131 is further configured to generate a low-level trigger signal in response to a high-level control signal. The high-level control signal is output from the MCU 110 to the control unit 131 when the SoC power supply state is detected to be normal. When the trigger signal is low, each charge discharge unit 132 does not act.

[0044] Thus, the discharge circuit 130 provided by the embodiments of the present disclosure can synchronously and quickly discharge the residual charge of each SoC power supply under the control of the MCU 110 when the SoC power supply is abnormal, so as to ensure that the domain controller 100 can be normally started the next time it is powered on, improve the reliability and stability of the domain controller 100, and avoid the occurrence of faults such as power-on failure, abnormal startup, and repeated restart after abnormal power-on.

[0045] The abnormal state of the SoC power supply may include, but is not limited to, one or more of the following: SoC power supply undervoltage, SoC power supply undervoltage, SoC power supply interruption, SoC power supply voltage being zero, no output of the SoC power supply, SoC power supply power-off, etc. The abnormal state of the SoC power supply may include, but is not limited to: the SoC power supply can supply power normally.

[0046] In specific applications, regarding "abnormal state of the SoC power supply" and "abnormal state of the SoC power supply", it can be flexibly set or predefined in advance according to the requirements of the actual application scenario. In this regard, the embodiments of the present disclosure do not make any limitations.

[0047] In specific applications, the state of the SoC power supply can be detected in real time by the MCU 110.

[0048] In some embodiments, the control unit 131 may include a first NMOS transistor, a voltage-dividing resistor, a pull-down resistor, and a current-limiting resistor. The gate of the first NMOS transistor is connected to the control signal output terminal of the MCU 110 through the voltage-dividing resistor and is grounded through the pull-down resistor at the same time. The source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor serves as the output terminal of the trigger signal and is connected to the first power supply through the current-limiting resistor. The first power supply is used to provide the working voltage for the control unit 131.

[0049] Furthermore, the control unit 131 may further include a fixed resistor, a diode, and / or a filtering capacitor. That is, a fixed resistor is connected in parallel between the drain and the source of the first NMOS transistor; and / or, a diode is connected in parallel between the drain and the source of the first NMOS transistor; and / or, a filtering capacitor is connected in parallel between the drain and the source of the first NMOS transistor.

[0050] Figure 2 An exemplary circuit structure diagram of the control unit 131 is shown. Among them, VIN_PWR_BAD_N_M is the control signal given by the MCU 110 to the discharge circuit 130; VIN represents the power supply of the control unit 131 (that is, the discharge circuit 130); M1 is the first NMOS transistor, which serves as a switch to control each charge discharge unit 132; POFF_EN_M represents the trigger signal output by the control unit 131, and the POFF_EN_M signal is taken from the drain of M1 and pulled up to VIN through R13.

[0051] See Figure 2 , the voltage-dividing resistor R11 is connected in series between the control signal output terminal of the MCU 110 and the gate of M1.

[0052] See Figure 2 , the pull-down resistor R12 is connected in parallel between the gate and the source of M1 and the source of M1 is grounded, so as to ensure that the gate of M1 is at a low level when there is no signal, and M1 is default off, avoiding mis-triggering caused by a floating gate.

[0053] See Figure 2 , the current-limiting resistor R13 is connected in series between the drain of M1 and the power supply VIN, and can also be used as a pull-up resistor to pull up the POFF_EN_M signal to VIN. It can be used to ensure that POFF_EN_M is reliably pulled up when M1 is turned off, and at the same time has a current-limiting effect to prevent the current output by the control unit 131 from being too high and causing damage to circuit components.

[0054] See Figure 2 , the fixed resistor R14 is connected in parallel between the drain and source of the first NMOS transistor. When M1 is turned off, the drain may be in a high-impedance state (floating), resulting in an uncertain potential, which may cause circuit malfunction or noise interference. Connecting the resistor R14 in parallel between the drain and source of M1 can pull the drain of M1 to the source potential (i.e., ground), ensuring that the drain of M1 is at a definite low level, thereby avoiding circuit malfunction and reducing noise interference.

[0055] See Figure 2 , the diode D1 is connected in parallel between the drain and source of the first NMOS transistor. In some examples, D1 is an 11V Zener diode, which is used to protect the gate of M1 from damage by voltage spikes. When the voltage of VIN_PWR_BAD_N_M exceeds the Zener voltage of D1 (e.g., 11V), D1 breaks down and conducts, clamping the gate voltage of M1 at its Zener voltage (i.e., 11V), which can effectively prevent the gate of M1 from being damaged by overvoltage. In addition, D1 also has the function of preventing incorrect input polarity.

[0056] See Figure 2 , the filter capacitor C1 is a filter capacitor connected in parallel between the drain and source of the first NMOS transistor. Connecting the filter capacitor C1 in parallel between the drain (Drain) and source (Source) of M1 can reduce high-frequency noise, voltage fluctuations and electromagnetic interference. When M1 is turned on or off quickly as a switch, the voltage between the drain and source of M1 will jump violently, generating high-frequency harmonic noise. The high-frequency noise can be absorbed through the low-pass filtering characteristic of the parallel capacitor C1, thereby reducing the interference of the rapid on or off of M1 to the surrounding circuits.

[0057] Figure 2 In the example of

[0058] In some examples, M1 can be, but is not limited to, an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET) (simply referred to as NMOS transistor in this article), R11 can be a fixed resistor with a resistance value of 1KΩ to 2KΩ, R12 can be a fixed resistor with a resistance value of 10KΩ to 20KΩ, R13 can be, but is not limited to, a fixed resistor with a resistance value of 10KΩ to 33KΩ, R14 can be, but is not limited to, a fixed resistor with a resistance value of 10KΩ to 33KΩ, R15 can be, but is not limited to, a fixed resistor with a resistance value of 0KΩ to 1KΩ, D1 can be, but is not limited to, a Zener diode with a Zener voltage of 11V, and C1 can be, but is not limited to, a capacitor of 100nF / 50V.

[0059] When the SoC power supply is in an abnormal state, VIN_PWR_BAD_N_M output by the MCU 110 is at a low level. The gate voltage of M1 is pulled down to a low level by R12, M1 is turned off, and POFF_EN_M is pulled up to VIN through R13 and is at a high level. At this time, the discharge paths in each charge discharge unit 132 are turned on by the high-level POFF_EN_M, and each charge discharge unit 132 performs the charge discharge of the corresponding SoC power supply.

[0060] When the SoC power supply is in a normal state, that is, when the SoC power supply is normally powered and there is no need for discharge, VIN_PWR_BAD_N_M output by the MCU 110 is at a high level. The gate voltage of M1 is pulled up by VIN_PWR_BAD_N_M. When the gate voltage of M1 exceeds the threshold voltage, M1 conducts. After M1 conducts, the drain of M1 is pulled down to the ground, and VIN forms a low-impedance path to the ground through R13, R14, and M1, and POFF_EN_M is at a low level. At this time, the discharge paths in each charge discharge unit 132 remain closed and do not perform any actions.

[0061] As described above, the control unit 131 in the discharge circuit 130 can output a high-level POFF_EN_M to start each charge discharge unit 132 to release the residual charge of the SoC power supply when the control signal VIN_PWR_BAD_N_M provided by the MCU 110 is valid (i.e., at a low level).

[0062] In some embodiments, each charge discharge unit 132 can include: a second NMOS transistor, a voltage-dividing resistor, a pull-down resistor, and a current-limiting resistor. The gate of the second NMOS transistor is connected to the trigger signal output terminal of the control unit 131 through the voltage-dividing resistor and is grounded through the pull-down resistor. The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to a SoC power supply through the current-limiting resistor.

[0063] In some examples, multiple SoC power supplies include a first SoC power supply and a second SoC power supply, and the voltage of the first SoC power supply is lower than that of the second SoC power supply. At this time, the discharge circuit 130 may include a first charge discharge unit 132 and a second charge discharge unit 132. The first charge discharge unit 132 is connected to the first SoC power supply to conduct its own discharge path in response to a high-level trigger signal to discharge the residual charge of the first SoC power supply. The second charge discharge unit 132 is connected to the second SoC power supply to conduct its own discharge path in response to a high-level trigger signal to discharge the residual charge of the second SoC power supply.

[0064] Figure 3 An exemplary circuit structure diagram of the second charge discharge unit 132 is shown. Refer to Figure 3 , the second charge discharge unit 132 may include: an NMOS transistor M2 (i.e., an example of the second NMOS transistor), and resistors R21, R22, R23, and R24. The gate of M2 is connected to the trigger signal output terminal of the control unit 131 after being serially connected with the resistor R21 to access the POFF_EN_M signal, where POFF_EN_M represents the trigger signal output by the control unit 131. A resistor R22 is connected in parallel between the gate and the source of M2. The source of M2 is grounded. The drain of M2 is serially connected with resistors R24 and R23 and connected to X_VIN_HV, where X_VIN_HV represents the second SoC power supply.

[0065] R23 and R24 are used as current-limiting resistors to limit the current to protect M2.

[0066] M2 serves as a switch and is controlled by POFF_EN_M. When POFF_EN_M is at a high level, the voltage between the gate and the source of M2 is higher than its threshold voltage, so M2 conducts. After M2 conducts, the discharge path of the first SoC power supply OM_VIN_HV "R23 → R24 → M2 drain → M2 source → ground" conducts, and the residual charge in the first SoC power supply is released to the ground through this discharge path. When POFF_EN_M is at a low level, the voltage between the gate and the source of M2 is lower than its threshold voltage, so M2 is cut off, and the above discharge path of the first SoC power supply OM_VIN_HV is disconnected, and no charge discharge is performed.

[0067] R22 is used as a pull-down resistor to ensure that M2 is default off and avoid mis-triggering caused by a floating gate.

[0068] R21 is used as a voltage-dividing resistor for reserved voltage regulation.

[0069] Exemplarily, R21 can be a fixed resistor with a resistance value ranging from 0 Ω to 1 KΩ, R22 can be a fixed resistor with a resistance value ranging from 370 to 400 kΩ, R23 can be a fixed resistor with a resistance value ranging from 50 to 70 Ω, and R24 can be a fixed resistor with a resistance value ranging from 100 to 130 Ω. In specific applications, the resistance values of each resistor can be flexibly adjusted as needed.

[0070] Figure 4 The exemplary circuit structure diagram of the first charge discharge unit 132 is shown. Refer to Figure 4 , the first charge discharge unit 132 can include: an NMOS transistor M3 (i.e., an example of the second NMOS transistor) and resistors R31, R32, R33, and R34. The gate of M3 is connected to the trigger signal output terminal of the control unit 131 in series with the resistor R31 to access the trigger signal POFF_EN_M, where POFF_EN_M represents the trigger signal output by the control unit 131. A resistor R22 is connected in parallel between the gate and the source of M3. The source of M3 is grounded, and the drain of M3 is connected to X_VIN_MV in series with resistors R24 and R23, where X_VIN_MV represents the first SoC power supply.

[0071] R33 and R34 act as current limiting resistors to limit the current to protect M3.

[0072] M3 acts as a switch and is controlled by POFF_EN_M. When POFF_EN_M is at a high level, the voltage between the gate and the source of M3 is higher than its threshold voltage, so M3 conducts. After M3 conducts, the discharge path of the second SoC power supply OM_VIN_MV "R33 → R34 → drain of M3 → source of M3 → ground" conducts, and the residual charge in the second SoC power supply is released to the ground through this discharge path. When POFF_EN_M is at a low level, the voltage between the gate and the source of M3 is lower than its threshold voltage, so M3 is cut off, and the discharge path of the second SoC power supply OM_VIN_MV is disconnected, and no charge discharge is performed.

[0073] R32 acts as a pull-down resistor to ensure that M3 is default off and avoid mis-triggering caused by a floating gate.

[0074] R21 acts as a voltage dividing resistor and can be used for reserved voltage regulation.

[0075] Exemplarily, R31 can be a fixed resistor with a resistance value ranging from 0 Ω to 1 KΩ, R32 can be a fixed resistor with a resistance value ranging from 370 to 400 kΩ, R33 can be a fixed resistor with a resistance value ranging from 50 to 70 Ω, and R34 can be a fixed resistor with a resistance value ranging from 100 to 130 Ω. In specific applications, the resistance values of each resistor can be flexibly adjusted as needed.

[0076] As described above, the discharge circuit 130 passes through Figure 2 the control unit 131 shown in Figure 4 andFigure 5 The multi-channel charge discharge unit 132 shown realizes the fast and safe discharge of multiple SoC power supplies. When an abnormal SoC power supply is detected, the MCU 110 outputs a low-level control signal VIN_PWR_BAD_N_M, turning off the NMOS transistor M1 in the control unit 131, pulling up the trigger signal POFF_EN_M output by the control unit 131, triggering the conduction of each discharge path, and releasing the residual charge of each SoC power supply to the ground through a current-limiting resistor. This structure of the discharge circuit 130 takes into account reliability, safety, and efficiency, and is suitable for high-requirement scenarios such as vehicles and industrial equipment.

[0077] As described above, the discharge circuit 130 provided by the embodiments of the present disclosure can be implemented by a hardware-level circuit. Therefore, the safe discharge of the SoC power supply in the domain controller 100 can be achieved through hardware-level control, with higher reliability, and is suitable for high-reliability scenarios such as autonomous driving.

[0078] Figure 1 At the same time, a schematic structural diagram of the domain controller 100 provided by the embodiments of the present disclosure is shown. Refer to Figure 1 , the domain controller 100 may include: an SoC 120, an MCU 110, and the above-mentioned discharge circuit 130. The SoC 120 is powered by multiple SoC power supplies.

[0079] The MCU 110 is mainly responsible for, but not limited to, power-on and power-off management, real-time control (e.g., CAN / LIN communication, I / O signal processing), safety monitoring (e.g., fault diagnosis), low-power mode management, etc.

[0080] The SoC 120 is mainly responsible for, but not limited to, high-performance computing such as autonomous driving perception, decision-making, and intelligent cockpit rendering, data fusion of multiple sensors such as cameras and radars, and running complex operating systems.

[0081] In some examples, the SoC 120 can be powered by dual power supplies, which can meet the requirements of multi-module differentiated power supply, dynamic power consumption optimization, redundant safety, etc. Specifically, the dual power supplies of the SoC 120 can include the aforementioned first SoC power supply and second SoC power supply. The first SoC power supply is the core power supply X_VIN_MV of the SoC 120, with a voltage of approximately 0.8V to 1.2V, used to power the core components of the SoC120 (e.g., CPU, GPU, memory controller, etc.). The second SoC power supply is the peripheral power supply X_VIN_HV of the SoC 120, with a voltage of approximately 1.8V to 3.3V, which can be used to drive I / O interfaces, high-speed communication modules (such as PCIe, Ethernet PHY), or power peripherals such as audio components.

[0082] The startup of SoC 120 requires a strict power-on sequence: the core voltage X_VIN_MV of SoC 120 is powered on before the peripheral power supply X_VIN_HV of SoC 120 to ensure that the core logic is stable before starting the peripherals.

[0083] Furthermore, referring to Figure 1 , the domain controller 100 may further include: a power management module (PMIC), which can be used for but not limited to voltage conversion, multi-power domain isolation, dynamic voltage adjustment, etc.

[0084] Specifically, the power management module is connected to one or more external power supplies and can be used to convert the voltage of the external power supplies to provide operating voltages for the MCU 110, SoC 120, and the discharge circuit 130. These external power supplies are the system power supplies of the domain controller 100.

[0085] The system power supplies of the domain controller 100 may include two or more. Referring to the example of Figure 1 , taking a vehicle as an example, the system power supplies of the domain controller 100 may include: a vehicle-mounted power supply and an auxiliary power supply. The vehicle-mounted power supply can be but not limited to 12V, 24V, 48V, etc., and the auxiliary power supply can be but not limited to a 5V USB interface power supply, a backup power supply, etc.

[0086] The aforementioned SoC power supply can be provided to SoC 120 after the PMIC converts the system power supply of the domain controller 100. Taking the dual-power supply design described above as an example, the PMIC can convert the 12V vehicle-mounted power supply and output a first SoC power supply of 0.75V to power the core components of SoC 120, and the PMIC can convert the 5V auxiliary power supply and output a second SoC power supply of approximately 3.3V to power the peripheral components of SoC 120.

[0087] In some examples, the domain controller 100 can adopt a dual-PMIC redundant design. When the main PMIC fails, the slave PMIC takes over the power supply to improve the reliability and safety of the domain controller 100.

[0088] Exemplarily, the discharge circuit 130 can be connected to each SoC power supply network, the power rail on the SoC power supply side, or the power rail used to provide the system power supply side of the domain controller 100.

[0089] Further, in the domain controller 100 of the embodiments of the present disclosure, the MCU 110 can be used to detect the status of the SoC power supply. When it detects the absence of the SoC power supply, it determines that the SoC power supply status is abnormal and outputs a control signal with a low level to the discharge circuit 130. When it detects that the SoC 120 is normally powered, it determines that the SoC power supply status is normal and outputs the control signal with a high level to the discharge circuit 130. Thus, the MCU 110 can detect the SoC power supply status in real time to control the discharge circuit 130, so as to discharge the residual charge of the SoC power supply in a timely and rapid manner when needed.

[0090] Here, the absence of the SoC power supply may include, but is not limited to, one or more of the following: SoC power supply undervoltage, SoC power supply interruption, SoC power supply voltage being zero, and SoC power supply power-off.

[0091] Specifically, the MCU 110 monitors the SoC power supply in real time. The SoC power supply is connected to the pins of the analog-to-digital converter (ADC) of the SoC 120. The MCU 110 can sample the voltage value of each SoC power supply in real time through the ADC or rely on a comparator / threshold circuit to judge the existence of each SoC power supply. When the MCU 110 monitors the absence of the second SoC power supply X_VIN_HV and / or the first SoC power supply, the MCU 110 pulls down the control signal to turn on each discharge path in the discharge circuit 130 and discharge the residual charge of each SoC power supply. When the MCU 110 monitors that the second SoC power supply X_VIN_HV and the first SoC power supply X_VIN_MV are normally powered, the MCU 110 pulls up the control signal to turn off the discharge path of the discharge circuit 130 and does not perform charge discharge.

[0092] Figure 5 The figure shows a schematic diagram of the discharge process of the domain controller 100 provided by the embodiments of the present disclosure. Refer to Figure 5 , the residual charge discharge process of the SoC power supply in the domain controller 100 may include the following steps:

[0093] Step 501, the MCU 110 detects whether the SoC power supply status is normal;

[0094] For example, when it detects the absence (power loss) of X_VIN_HV and X_VIN_MV, the MCU 110 determines that the SoC power supply status is abnormal. When it detects that X_VIN_HV and X_VIN_MV are normally powered (Power Rail Active) (for example, the voltage is stable at the set value), the MCU 110 determines that the SoC power supply status is normal. X_VIN_HV represents the second SoC power supply, and X_VIN_MV represents the first SoC power supply.

[0095] Step 502, if the SoC power supply status is normal, the MCU 110 outputs a high-level control signal VIN_PWR_BAD_N_M to the control unit 131 of the discharging circuit 130;

[0096] Step 503, the high-level control signal VIN_PWR_BAD_N_M turns on the NMOS transistor (i.e., the first NMOS transistor mentioned above) in the control unit 131, and the control unit 131 outputs a low-level trigger signal POFF_EN_M to each charge discharging unit 132;

[0097] Step 504, each charge discharging unit 132 does not perform an action, its MOS transistor remains off, and the discharging path remains off.

[0098] Step 505, if the SoC power supply status is abnormal, the MCU 110 outputs a low-level control signal VIN_PWR_BAD_N_M to the control unit 131 of the discharging circuit 130;

[0099] Step 506, under the action of the low-level control signal VIN_PWR_BAD_N_M, the NMOS transistor of the control unit 131 turns off, and the control unit 131 outputs a high-level trigger signal POFF_EN_M to each charge discharging unit 132;

[0100] Step 507, the high-level trigger signal POFF_EN_M turns on the NMOS transistors in each charge discharging unit 132, the discharging path is turned on, and the residual charges of the SoC power supply connected to each charge discharging unit 132 are released to the ground through the discharging path.

[0101] The embodiments of the present disclosure can be applied to various scenarios where the SoC is abnormal and the domain controller fails due to residual charges in the SoC power supply. Exemplarily, in the following various scenarios, the domain controller of the embodiments of the present disclosure can automatically and quickly discharge the residual charges of the SoC power supply through the discharging circuit, ensuring that the domain controller can start normally the next time it is powered on:

[0102] 1) When the vehicle's battery or generator quickly loses power, due to the existence of internal energy storage components, the internal circuit of the domain controller will slowly shut down. If a power-on signal is received again before the internal circuit is completely shut down, it will cause the SoC power supply timing to be chaotic and unable to start. The embodiments of the present disclosure can effectively avoid this situation by adding a discharging circuit in the domain controller to quickly discharge the residual charges of the SoC power supply in time.

[0103] 2) During the debugging or operation of the vehicle or domain controller, if power is suddenly cut off and then quickly restored, since the power-off process is incomplete and power is quickly restored, it often causes the SoC to malfunction and the domain controller cannot start. In the embodiments of the present disclosure, by adding a discharge circuit in the domain controller to quickly discharge the residual charge of the SoC power supply in a timely manner, this situation can be effectively avoided.

[0104] 3) During the debugging of the domain controller, in the case of sudden power failure and then quick power supply, due to the incomplete power-off process, when power is restored again, the SoC often malfunctions and the domain controller cannot start. In the embodiments of the present disclosure, by adding a discharge circuit in the domain controller to quickly discharge the residual charge of the SoC power supply in a timely manner, this situation can be effectively avoided.

[0105] 4) During the operation of the vehicle, if the vehicle power supply unit is powered off and then powered on again, due to the incomplete power-off process, when power is restored again, the SoC often malfunctions and the domain controller cannot start. In the embodiments of the present disclosure, by adding a discharge circuit in the domain controller to quickly discharge the residual charge of the SoC power supply in a timely manner, this situation can be effectively avoided.

[0106] The domain controller 100 provided by the embodiments of the present disclosure can be of any type. For example, the domain controller 100 can be implemented as but not limited to the following types: power domain controller, chassis domain controller, body domain controller, intelligent cockpit domain controller, autonomous driving domain controller. For another example, the domain controller can also be implemented as the following types: L2-level domain controller, L3-level domain controller, L4-level domain controller.

[0107] The embodiments of the present disclosure can be applied to the control of various devices such as multiple wheeled mobile robots, wheeled mobile robots, mobile robots, vehicles, aircraft, ships, intelligent rail rapid transit systems (ART, Autonomous rail Rapid Transit), etc. The vehicle can be but not limited to passenger cars, commercial vehicles (such as trucks, buses, freight trucks, etc.), special-purpose vehicles (such as ambulances, fire trucks, engineering vehicles, rescue vehicles, etc.), agricultural and industrial vehicles (such as harvesters, forklifts, etc.), transportation and logistics vehicles (such as container trucks, refrigerated trucks, etc.), new energy vehicles (such as electric vehicles, hybrid vehicles), special carriers (such as garbage trucks, sprinkler trucks, etc.). In other words, the "vehicle" and the like involved in the embodiments of the present disclosure can be replaced with any of the foregoing devices.

[0108] The embodiments of the present disclosure also provide a vehicle, which may include the aforementioned domain controller 100. The vehicle can be implemented as but not limited to the foregoing various devices such as multiple wheeled mobile robots, wheeled mobile robots, mobile robots, vehicles, aircraft, ships, intelligent rail rapid transit systems (ART, Autonomous rail Rapid Transit).

[0109] The vehicle provided by the embodiments of the present disclosure can be applied to scenarios such as ports, highways, logistics, mines, farms, closed parks, and urban transportation, and can be applicable to many aspects such as logistics distribution, unmanned transportation, last-mile delivery, ride-hailing, automated agricultural operations, and automated sanitation. Of course, the embodiments of the present disclosure can also be applied to any other scenarios involving domain controllers. The present disclosure does not limit the application scenarios and applicable fields of the embodiments of the present disclosure.

[0110] The above has introduced the technical solutions provided by the present disclosure in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

[0111] The above are only the preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A discharge circuit, characterized in that, Applied to a domain controller, the domain controller includes a microcontroller unit (MCU) and a system-on-chip (SoC). The SoC is powered by multiple SoC power supplies. The discharge circuit includes a control unit and multiple charge discharge units. Each charge discharge unit is connected to one of the SoC power supplies, and the control unit is connected to each charge discharge unit and the MCU; The control unit is configured to generate a high-level trigger signal in response to a low-level control signal and send it to each charge discharge unit. The low-level control signal is output from the MCU to the control unit when the MCU detects an abnormal state of the SoC power supply; Each charge discharge unit is configured to turn on its own discharge path in response to the high-level trigger signal to discharge the residual charge of the SoC power supply it is connected to.

2. The discharge circuit according to claim 1, wherein, The control unit is further configured to generate a low-level trigger signal in response to a high-level control signal. The high-level control signal is output from the MCU to the control unit when the MCU detects a normal state of the SoC power supply. When the trigger signal is at a low level, each charge discharge unit does not operate.

3. The bleed circuit according to claim 1 or 2, characterized in that, The control unit includes a first NMOS transistor, a voltage dividing resistor, a pull-down resistor, and a current limiting resistor. The gate of the first NMOS transistor is connected to the control signal output terminal of the MCU through the voltage dividing resistor and grounded through the pull-down resistor. The source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor serves as the output terminal of the trigger signal and is connected to a first power supply through the current limiting resistor. The first power supply is used to provide a working voltage for the control unit.

4. The discharge circuit according to claim 3, wherein, A fixed resistor is connected in parallel between the drain and source of the first NMOS transistor; and / or, A diode is connected in parallel between the drain and source of the first NMOS transistor; and / or, A filter capacitor is connected in parallel between the drain and source of the first NMOS transistor.

5. The discharge circuit according to claim 1, wherein, Each charge discharge unit includes: a second NMOS transistor, a voltage dividing resistor, a pull-down resistor, and a current limiting resistor. The gate of the second NMOS transistor is connected to the trigger signal output terminal of the control unit through the voltage dividing resistor and grounded through the pull-down resistor. The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to one of the SoC power supplies through the current limiting resistor.

6. The discharge circuit according to claim 1 or 5, wherein, The multiple SoC power supplies include a first SoC power supply and a second SoC power supply. The voltage of the first SoC power supply is lower than that of the second SoC power supply. The discharge circuit includes a first charge discharge unit and a second charge discharge unit; The first charge discharge unit is connected to the first SoC power supply and is configured to turn on its own discharge path in response to the high-level trigger signal to discharge the residual charge of the first SoC power supply; The second charge discharge unit is connected to the second SoC power supply and is configured to turn on its own discharge path in response to the trigger signal at a high level to discharge the residual charge of the second SoC power supply.

7. A domain controller, characterized in that, The domain controller includes: a microcontroller MCU, a system-on-chip SoC, and the discharge circuit according to any one of claims 1 to 6. The SoC is powered by a plurality of SoC power supplies. The control terminal of the control unit in the discharge circuit is connected to the MCU, and the output terminal of the control unit is connected to the control terminals of the respective charge discharge units. One end of each charge discharge unit is connected to one of the SoC power supplies and the other end is grounded.

8. The domain controller according to claim 7, wherein The MCU is configured to detect the status of the SoC power supply, determine that the status of the SoC power supply is abnormal and output the control signal at a low level to the discharge circuit when the absence of the SoC power supply is detected, and determine that the status of the SoC power supply is normal and output the control signal at a high level to the discharge circuit when the normal power supply of the SoC is detected.

9. The domain controller according to claim 8, characterized in that, The absence of the SoC power supply includes one or more of the following: undervoltage of the SoC power supply, interruption of the SoC power supply, zero voltage of the SoC power supply, and power-off of the SoC power supply.

10. A vehicle, characterized in that, It includes the domain controller according to any one of claims 7 to 9.

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