A fault ride-through method and system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management

Abstract

The present invention discloses a fault ride-through method and system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management. The method comprises the following steps: S1. obtaining a data point; S2. obtaining a dual-sequence current reference value; S3. adjusting the operating mode for junction temperature management; and calculating the maximum value of the current output current. I max , and according to I max and I lim1 、 I lim2 and I lim3 The operating mode is adjusted according to the size relationship; S4. Dual-sequence current control; the system includes: a data point acquisition module, a current reference value generation module, a junction temperature management module, and a dual-sequence current control module.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a fault ride-through method and system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management. Background Art

[0002] Compared to grid-connected inverters based on Si IGBTs, grid-connected inverters based on SiC MOSFETs offer significant improvements in efficiency, power density, and power quality. However, SiC MOSFETs' high cost per ampere, limited current ratings, and unresolved long-term reliability issues have limited their widespread adoption in high-power power conversion applications.

[0003] To address this issue, a new concept, the hybrid switching frequency parallel inverter system (HSFPIS), has recently been proposed. As shown in Figure 1, the HSFPIS consists of a parallel hybrid system consisting of a high-power Si IGBT main unit (MU) and a low-power SiC MOSFET auxiliary unit (SU). The MU processes the majority of the load power at a low switching frequency, achieving the advantages of high current and low cost. The SU, on the other hand, processes a small portion of the load power at a high switching frequency and compensates for the low-frequency ripple generated by the MU, significantly improving the power quality of the grid-connected current. By properly configuring the MUs and SUs, the HSFPIS can deliver nearly the same efficiency and power quality as a full SiC MOSFET inverter while significantly reducing component costs.

[0004] Previous work has focused on the design and optimization of the HSFPIS itself under rated operating conditions, including hardware circuit design, power distribution ratio and switching frequency optimization, and precise ripple compensation strategies. However, research has yet to address the reliable operation of the HSFPIS under grid fault conditions and its role in supporting reliable grid power supply. The increased control freedom of the main and auxiliary converter units within the HSFPIS allows for improved system overload capacity to cope with various complex fault conditions. However, the thermal characteristics of the MU and SU differ significantly. Without an appropriate control strategy, heat dissipation will be excessively concentrated in the SU, hindering the full utilization of the HSFPIS's overload capacity and potentially damaging it. Summary of the Invention

[0005] In view of this, the present invention provides a fault ride-through method and system for a Si / SiC hybrid parallel inverter system with active junction temperature management, which is used to at least solve the problem of how to reliably operate the HSFPIS and support reliable power supply to the grid under grid fault conditions.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A fault ride-through method for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management comprises the following steps:

[0008] S1. Obtain data points; record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ;

[0009] S2. Get the double-sequence current reference value; get the data point The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ;

[0010] S3. Adjust the operating mode to manage junction temperature; calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively:

[0011] Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified;

[0012] Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete the AC-DC conversion;

[0013] Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it;

[0014] Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following;

[0015] S4. Double sequence current control; dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

[0016] Preferably, in S1, and Calculate grid voltage The specific contents include:

[0017] ;

[0018] in, for dq Grid voltage in coordinate system The positive sequence complex vector of for dq Grid voltage in coordinate system The negative sequence complex vector of for dq Grid connection point voltage in the coordinate system The positive sequence complex vector of for dq Grid connection point voltage in the coordinate system The negative sequence complex vector of for dq Grid connection point current in the coordinate system The positive sequence complex vector of for dq Grid connection point current in the coordinate system The negative sequence complex vector of ,in, is a complex vector, indicating or , and They are of d Axis and q The component on the axis, is the imaginary unit, is the fundamental angular frequency, is the line inductance.

[0019] Preferably, the specific content of S2 includes:

[0020] Based on the optimal current reference value lookup table, data points are obtained by interpolation The corresponding optimal current reference value that needs to be injected into the system;

[0021] The specific content of the optimal current reference value lookup table is:

[0022] Assume that the positive and negative sequence components of the current that the converter needs to inject into the grid are and After the corresponding current is injected, the PCC voltage amplitude, current amplitude and active power fluctuation value are expressed as:

[0023] ;

[0024] ;

[0025] ;

[0026] Where, 、 and They are exist The components on the three phases, 、 and They are exist The components on the three phases, is the active power fluctuation value, and the other parameters in the formula are intermediate variables. The calculation methods are:

[0027] ;

[0028] ;

[0029] ;

[0030] Where, and The grid connection point voltage of d Axis and q Axis positive sequence component, and The grid connection point voltage of d Axis and q axis negative sequence component; and Current reference values of d Axis and q Axis positive sequence component, and Current reference values of d Axis and q The axis negative sequence component, where the current reference value is such that the current The current value that meets the fault ride-through requirements;

[0031] By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation values into the constraints of the optimal fault ride-through at several data points and solving the target, a lookup table of optimal current reference values is obtained.

[0032] For data points not covered by the optimal current reference value lookup table, the current reference value is determined using an interpolation method.

[0033] Preferably, calculate the maximum output current of the system under the optimal current reference value The specific contents include:

[0034] ;

[0035] Where, and The current output current is d Axis and q Axis component.

[0036] Preferably, the optimal fault traversal in S4 is expressed as:

[0037] ;

[0038] in, The system outputs active power. is the active power fluctuation value; 、 is the output voltage and current amplitude, is the rated voltage, is the power reference value.

[0039] A fault ride-through system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management, comprising:

[0040] The data point acquisition module is used to record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ;

[0041] Current reference value generation module for obtaining data points The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ;

[0042] Junction temperature management module, used to calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively:

[0043] Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified;

[0044] Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete AC-DC conversion;

[0045] Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it;

[0046] Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following;

[0047] Dual sequence current control module, used in dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

[0048] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a fault ride-through method and system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management, which has the following beneficial effects:

[0049] The present invention provides a fault ride-through method with active junction temperature management for HSFPIS. The method comprises device-level active junction temperature control and system-level optimal support control. Device-level control maximizes the overload capacity of the HSFPIS by adjusting parameters such as switching frequency, power distribution ratio, and DC side voltage. System-level control fully utilizes the overload capacity of the HSFPIS by rationally allocating positive and negative sequence currents, achieving comprehensive optimization of ride-through objectives such as grid connection point voltage support, output current amplitude limitation, power fluctuation suppression, and power output maximization, thereby effectively improving the fault overcurrent capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1The basic topology of the Si / SiC HSFPIS provided in the embodiment of the present invention;

[0052] Figure 2 A flow chart of a fault ride-through method for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management provided by the present invention;

[0053] Figure 3 HSFPIS output current under overload conditions provided by the embodiment of the present invention MU current SU current And the junction temperature waveforms of MU and SU;

[0054] Figure 4 A block diagram of the principle of a fault ride-through method for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management provided by the present invention;

[0055] Figure 5 Four operating modes of the active junction temperature management strategy provided by an embodiment of the present invention;

[0056] Figure 6 The optimal current reference value lookup table provided by the embodiment of the present invention; wherein (a) according to 、 and , search , (b) according to 、 and , search , (c) according to 、 and , search (d) according to 、 and , search ;

[0057] Figure 7 Schematic diagram of various fault types provided by the embodiment of the present invention; (a) single-phase grounding fault of phase A; (b) short circuit between phases A and B; (c) two-phase grounding of phases A and B;

[0058] Figure 8 These are the simulation results under various typical faults provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0060] The present invention provides a fault ride-through method for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management, such as Figure 2 As shown, the following steps are included:

[0061] S1. Obtain data points; record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ;

[0062] S2. Get the double-sequence current reference value; get the data point The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ;

[0063] S3. Adjust the operating mode to manage junction temperature; calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively:

[0064] Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified;

[0065] Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete the AC-DC conversion;

[0066] Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it;

[0067] Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following;

[0068] S4. Double sequence current control; dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

[0069] HSFPIS is composed of a high-power Si IGBT main unit (MU) and a low-power SiC MOSFET auxiliary unit (SU) in parallel, as shown in Figure 1. The system specifications are as follows: Output current Rated value is 80A, DC side voltage U dc The rated voltage is 1200V; the power distribution ratio between MU and SU is 4:1, that is, MU handles 80% of the load current and SU handles 20% of the rated current; the power devices used by MU and SU are Infineon IKQ75N120CH7 (1200V, 82A) and Wolfspeed C2M0080120D (1200V, 36A), respectively, with switching frequencies of 20 kHz and 100 kHz, respectively;C dc is the DC link capacitance, L 1 is the MU filter inductor, L 2 is the SU filter inductor. In order to illustrate the basic principle of HSFPIS and the problem of junction temperature imbalance between MU / SU, Figure 3 From top to bottom, the HSFPIS output current under overload conditions is shown MU current SU current And the junction temperature waveforms of MU and SU.

[0070] (1) Basic principles of HSFPIS: Figure 3 As can be seen from the current waveforms in the HSFPIS, the MU handles the majority of the load power, while the SU compensates for the harmonics generated by the MU to improve power quality. On the one hand, to reduce switching losses, the high-power MU operates at a low switching frequency. On the other hand, while the SU requires high switching frequency to ensure compensation accuracy, it only handles a small portion of the power, so increasing the switching frequency does not significantly reduce overall efficiency. Therefore, by combining the MU and SU, the HSFPIS combines the high power and low cost of Si inverters with the excellent switching characteristics of SiC inverters.

[0071] (2) Junction temperature imbalance between MU / SU: In order to cope with various complex grid conditions that may occur during grid-connected operation, HSFPIS needs to have a certain overload capacity. Figure 3 The junction temperature distribution curve in Figure 2 shows that under a 1.5 pu overload condition, the SU junction temperature approaches its threshold of 150°C. Under higher overload conditions, the SU junction temperature exceeds the limit, while the MU junction temperature remains below the threshold. This indicates that the junction temperature imbalance restricts the optimal performance of the HSFPIS overload capability.

[0072] In order to give full play to the overload capacity of HSFPIS and achieve optimal fault ride-through, this paper proposes a HSFPIS fault ride-through strategy based on multi-level collaboration of "device + system", such as Figure 4 As shown, U g1 is the grid side voltage of the isolation transformer, V MU is the MU control pulse signal, V SU is the pulse signal for SU control. The proposed strategy consists of two main parts:

[0073] 1) Active device-level junction temperature management: Dynamically adjusts the power device operating mode based on the output current reference, thereby maximizing the system overload capability while avoiding junction temperature exceeding the limit;

[0074] 2) System-level optimal support strategy: Fully utilize the system overload capacity to achieve comprehensive optimization of goals such as grid connection point voltage support, output current amplitude limitation, and power fluctuation suppression during grid faults.

[0075] HSFPIS needs to withstand high overcurrent during fault ride-through, and the junction temperature of internal power devices increases significantly, facing the risk of failure. To this end, the present invention proposes a new active junction temperature management strategy based on the load current amplitude to fully utilize the advantageous characteristics of each device in the hybrid structure. The main motivation of the proposed strategy is to keep the junction temperature of the main and auxiliary units in HSFPIS below the threshold (set to 150°C in this embodiment) to ensure the safe operation of the device, while maximizing the overall overcurrent capability of the system. The new active junction temperature management strategy consists of four operating modes with different DC link voltages, switching frequencies and power distribution ratios, such as Figure 5 As shown, in this embodiment, each mode is specifically set as follows:

[0076] (1) Mode 1: Maintain rated parameters. When the load current amplitude is When the temperature is within the specified range, even without changing any parameters, HSFPIS can ensure that the junction temperature of the internal MU and SU is lower than 150°C.

[0077] (2) Mode 2: Reduce the DC link voltage. In typical scenarios such as photovoltaic power generation and wind power generation, the converter system usually has a DC voltage control link. The switching loss of the power device is positively correlated with the DC bus voltage. Reducing the DC voltage can significantly reduce the temperature of the power device. In this embodiment, when the load current amplitude is When the voltage of the DC bus is within the range, the DC bus voltage is adjusted from 1200 V to 800 V.

[0078] (3) Mode 3: Adjust the switching frequency and power distribution ratio. Due to the limitation of DC voltage utilization, the DC voltage of the inverter cannot be too low. When the load current amplitude is When the power device reliability is no longer guaranteed by simply reducing the DC bus voltage, the switching frequencies of MU and SU are reduced to 10 kHz and 50 kHz respectively to reduce switching losses at the expense of a certain power quality. K Increased to 5.66:1 to avoid excessive heat loss concentration in SU. When the junction temperature of MU and SU reaches 150℃ at the same time, it indicates that This is the maximum overcurrent that the HSFPIS can withstand.

[0079] (4) Mode 4: Current limiting. When the load current is greater than When the flow of electricity is too high, current limiting measures must be taken.

[0080] Determined through simulation 、 and The values are: 120 A (1.50 pu), 145 A (1.81 pu) and 185 A (2.31 pu).

[0081] In order to further implement the above technical solution, S1 and Calculate grid voltage The specific contents include:

[0082] ;

[0083] in, for dq Grid voltage in coordinate system The positive sequence complex vector of for dq Grid voltage in coordinate system The negative sequence complex vector of for dq Grid connection point voltage in the coordinate system The positive sequence complex vector of for dq Grid connection point voltage in the coordinate system The negative sequence complex vector of for dq Grid connection point current in the coordinate system The positive sequence complex vector of for dq Grid connection point current in the coordinate system The negative sequence complex vector of ,in, is a complex vector, indicating or , and They are of d Axis and q The component on the axis, is the imaginary unit, is the fundamental angular frequency, is the line inductance.

[0084] It should be noted that:

[0085] Assume that the power grid fails t = 0. Before and after the fault ride-through strategy is enabled, the grid voltage u g It can be considered as unchanged. Therefore, t =0-time to obtain the grid voltage and then determine the fault type.

[0086] In order to further implement the above technical solutions, the specific contents of S2 include:

[0087] Based on the optimal current reference value lookup table, data points are obtained by interpolation The corresponding optimal current reference value that needs to be injected into the system;

[0088] The specific content of the optimal current reference value lookup table is:

[0089] Assume that the positive and negative sequence components of the current that the converter needs to inject into the grid are and After the corresponding current is injected, the PCC voltage amplitude, current amplitude and active power fluctuation value are expressed as:

[0090] ;

[0091] ;

[0092] ;

[0093] Where, 、 and They are exist The components on the three phases, and They are exist The components on the three phases, is the active power fluctuation value, and the other parameters in the formula are intermediate variables. The calculation methods are:

[0094] ;

[0095] ;

[0096] ;

[0097] Where, and The grid connection point voltage of d Axis and q Axis positive sequence component, and The grid connection point voltage of d Axis and q axis negative sequence component; and Current reference values of d Axis and q Axis positive sequence component, and Current reference values of d Axis and q The axis negative sequence component, where the current reference value is such that the current The current value that meets the fault ride-through requirements;

[0098] By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation values into the constraints of the optimal fault ride-through at several data points and solving the target, a lookup table of optimal current reference values is obtained.

[0099] For data points not covered by the optimal current reference value lookup table, the current reference value is determined using an interpolation method.

[0100] It should be noted that:

[0101] By solving the above PCC voltage amplitude, current amplitude and active power fluctuation value expressions for optimal fault ride-through at several data points, the following can be obtained: Figure 6 The optimal current reference value lookup table is shown. Figure 6 It shows that for a given set of grid voltage positive and negative sequence component amplitudes and phase angle difference , we can uniquely determine a set of current reference values that satisfy formula (1) 、 、 and For data points not covered by the data lookup table, the current reference value can be determined using interpolation methods.

[0102] based on Figure 5 The optimal current reference value lookup table shown is used to calculate the data points using high-dimensional interpolation methods (such as linear interpolation, nearest neighbor interpolation, etc.). Corresponding current reference value 、 、 and .

[0103] In order to further implement the above technical solution, calculate the maximum output current of the system under the optimal current reference value The specific contents include:

[0104] ;

[0105] Where, and The current output current is d Axis and q Axis component.

[0106] In order to further implement the above technical solution, the optimal fault traversal in S4 is expressed as:

[0107] ;

[0108] in, The system outputs active power. is the active power fluctuation value; is the output voltage and current amplitude, is the rated voltage, is the power reference value.

[0109] It should be noted that:

[0110] The optimal ride-through model addresses the question of how to rationally utilize the overcurrent capacity of the HSFPIS to achieve optimal fault ride-through. To minimize the impact of grid faults on loads, grid-connected converters are generally expected to provide grid-connection point voltage support, power fluctuation suppression, and current peak limiting under fault conditions, while also ensuring maximum active power transmission. Therefore, the control objective of the fault ride-through strategy proposed in this embodiment can be expressed in the aforementioned model.

[0111] A fault ride-through system for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management, comprising:

[0112] The data point acquisition module is used to record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ;

[0113] Current reference value generation module for obtaining data points The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ;

[0114] Junction temperature management module, used to calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively:

[0115] Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified;

[0116] Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete AC-DC conversion;

[0117] Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it;

[0118] Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following;

[0119] Dual sequence current control module, used in dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

[0120] The present invention will be further described below through simulation experiments:

[0121] like Figure 7 As shown in the figure, at a certain point in the system, (a) a single-phase grounding fault of phase A, (b) a short circuit between phases A and B, and (c) a two-phase grounding fault of phases A and B occur in sequence. and are the phase voltages of A, B, and C at the fault point, respectively. and They are the phase currents of A, B and C at the fault point respectively. is the ground impedance. Using the method of the present invention, the fault type is calculated based on the voltage and current signals measured at the PCC point ( ) and the optimal current reference value required for fault ride-through ( and ), as shown in Table 1, where is the maximum phase voltage amplitude, is the minimum phase voltage amplitude. In addition, Table 1 also gives the theoretical values of active power and PCC voltage range after applying the fault ride-through strategy. Figure 8 shown.

[0122] Table 1 Optimal current reference values, operating modes, and theoretical ride-through effects under different fault conditions

[0123] ;

[0124] (1) Scenario 1: Single-phase grounding fault.

[0125] exist t = 0 s, a phase A single-phase grounding fault occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for 0.5 s. At , the voltages of phases A and B drop asymmetrically, with the minimum phase voltage of phase A dropping to 0.69 pu. Through sampling and calculation, we get The amplitude of the positive-sequence component, the amplitude of the negative-sequence component and the phase angle difference between the positive-sequence component and the negative-sequence component are 251.182 V, 61.9919 V and 0.627128 rad / s respectively.

[0126] Through table lookup and interpolation, the optimal current reference values required for fault ride-through are obtained, as shown in Table 1. Furthermore, the maximum system output current calculated at these current reference values is 126.5701 A. Therefore, the system operating mode is adjusted to Mode 2, which specifies a DC bus voltage of 800 V, a power split ratio of 4:1 between the MU and SU, and switching frequencies of 20 kHz and 100 kHz for the MU and SU, respectively.

[0127] After implementing the fault ride-through strategy, the PCC minimum phase voltage rose to 0.87 pu, exceeding the national standard threshold of 0.85 pu. Meanwhile, the maximum phase voltage and maximum phase current reached 1.10 pu and 1.58 pu, respectively. The errors between the sampled and measured values of the maximum phase voltage, minimum phase voltage, and maximum phase current were 1.9%, 2.1%, and 0.07%, respectively.

[0128] (2) Scenario 2: Phase-to-phase short circuit fault.

[0129] exist t = 0.5 s, a short circuit fault of phases A and B occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for 0.5 s. At , the voltages of phases B and C drop asymmetrically, with the minimum phase voltage of phase B dropping to 0.71 pu. Through sampling and calculation, we get The amplitude of the positive-sequence component, the amplitude of the negative-sequence component and the phase angle difference between the positive-sequence component and the negative-sequence component are 267 V, 47.5251 V and -1.2901 rad / s respectively.

[0130] Through table lookup and interpolation, the optimal current reference values required for fault ride-through are obtained, as shown in Table 1. Furthermore, the maximum system output current calculated at these current reference values is 114.3585 A. Therefore, the system operating mode is adjusted to Mode 1, which specifies a DC bus voltage of 1200 V, a power split ratio of 4:1 between the MU and SU, and switching frequencies of 20 kHz and 100 kHz for the MU and SU, respectively.

[0131] After implementing the fault ride-through strategy, the PCC's minimum phase voltage rose to 0.92 pu, exceeding the national standard threshold of 0.85 pu. Meanwhile, the maximum phase voltage and current reached 1.09 pu and 1.43 pu, respectively. The errors between the sampled and measured values of the maximum phase voltage, minimum phase voltage, and maximum phase current were 0.8%, 2.8%, and 0.3%, respectively.

[0132] (3) Scenario 3: Two-phase grounding fault.

[0133] exist t =1.0 s, a two-phase ground fault of phases A and B occurs at a certain point on the grid side of the isolation transformer in the system, and the fault lasts for 0.5 s. At , the three-phase voltage asymmetric drop is observed, among which the minimum phase voltage B phase drops to 0.42 pu. Through sampling and calculation, we get The amplitude of the positive-sequence component, the amplitude of the negative-sequence component and the phase angle difference between the positive-sequence component and the negative-sequence component are 190.696 V, 62.8239 V and -1.60899 rad / s, respectively.

[0134] Through table lookup and interpolation, the optimal current reference values required for fault ride-through are obtained, as shown in Table 1. Furthermore, the maximum system output current under these current reference values is calculated to be 180.9725 A. Therefore, the system operating mode is adjusted to Mode 3, which specifies a DC bus voltage of 800 V, a power distribution ratio of 5.66:1 between the MU and SU, and switching frequencies of 10 kHz and 50 kHz for the MU and SU, respectively.

[0135] After implementing the fault ride-through strategy, the PCC minimum phase voltage rose to 0.87 pu, exceeding the national standard threshold of 0.85 pu. Meanwhile, the maximum phase voltage and maximum phase current reached 1.10 pu and 2.28 pu, respectively. The errors between the sampled and measured values of the maximum phase voltage, minimum phase voltage, and maximum phase current were 1.8%, 2.1%, and 0.5%, respectively.

[0136] In addition, the output power and device junction temperature throughout the fault process were observed. Under the three fault scenarios, the average output power was 37.65 kW, 37.72 kW, and 37.85 kW, respectively, demonstrating that the proposed fault ride-through strategy maximizes active power transfer during the fault. Throughout the fault process, the maximum junction temperature of the Si IGBT in the MU was 127°C, and the maximum junction temperature of the SiC MOSFET in the SU was 144.363°C, both within the power device's safe operating threshold of 150°C.

[0137] In power systems with a high proportion of renewable energy, grid-connected converters need to have a certain overload capacity to cope with complex working conditions and provide grid support. To improve overload capacity, traditional converters rely on the selection of power devices with larger ratings, which significantly increases system costs. To this end, the present invention provides a fault ride-through strategy with active junction temperature management for the newly proposed HSFPIS. The proposed strategy consists of device-level active junction temperature control and system-level optimal support control. Among them, device-level control is used to give full play to the advantages of the HSFPIS topology and maximize the overload capacity; system-level control makes full use of the HSFPIS overload capacity to achieve comprehensive optimization of the ride-through target. The main conclusions are as follows:

[0138] (1) By rationally combining Si-based MUs and SiC-based MUs, the HSFPIS’s overcurrent capability is fully exploited, avoiding over-reliance on redundant designs. During a grid fault, a support current of up to 2.3 pu can be injected into the grid, a 153% improvement over the 1.5 pu overcurrent capability of conventional converters.

[0139] (2) Through multi-level coordinated control at the device and system levels, maximum active power transmission during grid faults is achieved. Taking into account constraints such as grid connection point voltage support, power fluctuation suppression, and current peak limiting, a grid-connected system fault ride-through strategy for maximizing power output is proposed. By rationally allocating positive and negative sequence currents, the proposed strategy significantly improves the maximum active power output capability of the grid-connected system during grid faults, thereby minimizing active power shortages and avoiding large-scale load shedding.

[0140] Furthermore, the proposed fault ride-through strategy was verified under typical fault scenarios, including single-phase ground fault, interphase short-circuit fault, and two-phase ground fault. The results show that throughout the fault process, the system output power barely derates, and the junction temperature of the power devices remains within the safe operating range.

[0141] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A fault ride-through method for a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management, characterized in that: The following steps are involved: S1. Obtain data points; record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ; S2. Obtain the double-sequence current reference value; Get data points The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ; S3. Adjust the operating mode to manage junction temperature; calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively: Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified; Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete the AC-DC conversion; Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it; Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following; S4. Double sequence current control; dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

2. The fault ride-through method of a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management according to claim 1, characterized in that: According to S1 and Calculate grid voltage The specific contents include: ； in, for dq Grid voltage in coordinate system The positive sequence complex vector of for dq Grid voltage in coordinate system The negative sequence complex vector of for dq Grid connection point voltage in the coordinate system The positive sequence complex vector of for dq Grid connection point voltage in the coordinate system The negative sequence complex vector of for dq Grid connection point current in the coordinate system The positive sequence complex vector of for dq Grid connection point current in the coordinate system The negative sequence complex vector of ,in, is a complex vector, indicating or , and They are of d Axis and q The component on the axis, is the imaginary unit, is the fundamental angular frequency, is the line inductance.

3. The fault ride-through method of a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management according to claim 1, characterized in that: The specific contents of S2 include: Based on the optimal current reference value lookup table, data points are obtained by interpolation The corresponding optimal current reference value that needs to be injected into the system; The specific content of the optimal current reference value lookup table is: Assume that the positive and negative sequence components of the current that the converter needs to inject into the grid are and After the corresponding current is injected, the PCC voltage amplitude, current amplitude and active power fluctuation value are expressed as: ； ； ； Where, and They are exist The components on the three phases, and They are exist The components on the three phases, is the active power fluctuation value, and the other parameters in the formula are intermediate variables. The calculation methods are: ； ； ； Where, and The grid connection point voltage of d Axis and q Axis positive sequence component, and The grid connection point voltage of d Axis and q axis negative sequence component; and Current reference values of d Axis and q Axis positive sequence component, and Current reference values of d Axis and q The axis negative sequence component, where the current reference value is such that the current The current value that meets the fault ride-through requirements; By substituting the PCC voltage amplitude, current amplitude, and active power fluctuation values into the constraints of the optimal fault ride-through at several data points and solving the target, a lookup table of optimal current reference values is obtained. For data points not covered by the optimal current reference value lookup table, the current reference value is determined using an interpolation method.

4. The fault ride-through method of a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management according to claim 1, characterized in that: Calculate the maximum output current of the system under the optimal current reference value The specific contents include: ； Where, and The current output current is d Axis and q Axis component.

5. The fault ride-through method of a Si / SiC mixed-frequency parallel inverter system capable of active junction temperature management according to claim 1, characterized in that: The optimal fault crossing in S4 is expressed as: ； in, The system outputs active power. is the active power fluctuation value; is the output voltage and current amplitude, is the rated voltage, is the power reference value.

6. A fault ride-through system for a Si / SiC hybrid parallel inverter system capable of active junction temperature management, based on a fault ride-through method for a Si / SiC hybrid parallel inverter system capable of active junction temperature management according to any one of claims 1 to 5, characterized in that: include: Data point acquisition module, used to record the time when the power grid fault occurs as t =0, sampling t =0-grid point voltage and current ,according to and Calculate grid voltage ,get The positive sequence component amplitude , negative sequence component amplitude and the phase angle difference between the positive and negative sequence components , which constitutes the data points ; Current reference value generation module for obtaining data points The corresponding optimal current reference value that needs to be injected into the system, based on the current optimal current reference value to achieve fault ride-through, update the current output current , where the optimal current reference values include: d Axis positive sequence reference current 、 q Axis positive sequence reference current 、 d Axis negative sequence reference current and q Axis positive sequence reference current ; Junction temperature management module, used to calculate the maximum value of the current output current , and according to and 、 and The size relationship is used to adjust the operating mode, where 、 and The load current values corresponding to when the Si or SiC junction temperature reaches the maximum junction temperature in mode 1, mode 2, and mode 3 are respectively: Mode 1: Maintain rated parameters; when exist When within the range, maintain the DC link voltage , switching frequency and power distribution ratio K No changes, no parameters are modified; Mode 2: Keep the parameter values in Mode 1 and only reduce the DC link voltage ;when exist When within the range, reduce Until the minimum DC voltage required to complete the AC-DC conversion; Mode 3: Keep the parameter values in Mode 2 and adjust the switching frequency and power distribution ratio K ;when exist When the switching frequency is within the range, the switching frequency is reduced until the switching frequency required to meet the minimum output power quality is met, thereby improving the power distribution ratio. K Until the maximum current that SU can withstand flows through it; Mode 4: Keep the parameter values in Mode 3 and limit the current; when When the current limiting measures are taken, Adjust to the following; Dual sequence current control module, used in dq The output current is controlled in the coordinate system so that the output current tracks the optimal current reference value and achieves optimal fault ride-through. The specific content of the optimal fault ride-through is: under the constraints of grid connection point voltage support, power fluctuation suppression and current peak limit, the goal is to maximize the active power transmission.

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