Offset correction circuit and data driving device including same

Abstract

The invention relates to an offset correction circuit and a data driving device including the same. A detuning correction circuit according to one embodiment of the present invention deliberately applies, as an input to an amplifier of a reception circuit, a fixed voltage and a variable voltage having a prescribed voltage difference between a plurality of voltages adjacent to each other with the fixed voltage as a reference. As the bias circuit receives an average value obtained by using a bias process of the bias circuit as feedback to correct the offset, the offset may be further accurately corrected.

Description

Technical Field

[0001] The present invention relates to an offset calibration circuit and a data driving device including the same. More specifically, the present invention relates to an offset calibration circuit that applies a plurality of voltages with a voltage difference to an amplifier and corrects the offset through biasing, and a data driving device including the same. Background Art

[0002] With the development of the information society, there is an increasing demand for various types of display devices for displaying images. According to such requirements, in addition to liquid crystal display devices (LCDs), various types of display devices such as organic light emitting display devices (OLEDs) are being applied.

[0003] Such a display device includes: a source driver integrated circuit (IC) for supplying data voltages to data lines of a display panel; a gate driver integrated circuit for sequentially supplying gate pulses (or scan pulses) to gate lines (or scan lines) of the display panel; and a timing controller for controlling the source driver integrated circuit and the gate driver integrated circuit.

[0004] The source driver integrated circuit receives external signals from a timing controller or the like through a receiving circuit and transmits the signals to an internal circuit. When the internal circuit directly receives signals from the outside, since the magnitude of the signals is not sufficient to restore data, the receiving circuit needs to amplify the signals through an internal amplifier (Receiver Amplifier) and transmit them to the internal circuit. However, in actual operation, since there is an offset in the amplifier of the receiving circuit, and this offset of the amplifier causes distortion of the signals transmitted to the internal circuit, errors may occur in the restored data. Summary of the Invention

[0005] Technical Problem

[0006] In order to improve the prior art, the present invention provides an offset calibration circuit that applies a plurality of voltages with a voltage difference to an amplifier of a receiving circuit of a source driver integrated circuit and corrects the offset through biasing, and a data driving device including the same.

[0007] An object of an embodiment of the present invention is to provide an offset calibration circuit that applies a fixed voltage and a variable voltage to an amplifier instead of an external signal and corrects the offset through biasing, and a data driving device including the same.

[0008] Another object of the embodiments of the present invention is to provide an offset correction circuit that corrects an offset based on an average value obtained by biasing according to a plurality of variable voltages, and a data driving device including the same.

[0009] The object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those of ordinary skill in the technical field to which the present invention belongs through the following description.

[0010] Technical solution

[0011] An offset correction circuit according to an embodiment of the present invention includes: a standard signal generation circuit configured to generate a fixed voltage and a plurality of variable voltages having a plurality of voltage differences from the fixed voltage; a bias circuit connected to a plurality of amplifiers to sequentially increase the current flowing to a connection node; and a plurality of registers configured to store a plurality of binary code values of the bias circuit. The plurality of amplifiers include: a first amplifier that receives a differentially input external signal and differentially outputs it to the next amplifier; and a second amplifier that receives a differentially output signal of one of the plurality of amplifiers with differentially input and outputs it to an internal circuit. The offset correction circuit blocks the external signal differentially input to the first amplifier, and inputs the fixed voltage and one of the plurality of variable voltages to the first amplifier. The first binary code value of the bias circuit is stored in one of the plurality of registers, and the offset of the plurality of amplifiers is corrected based on the average value of the first binary code values respectively related to the plurality of variable voltages stored in the plurality of registers.

[0012] A data driving device according to an embodiment of the present invention includes: a receiving circuit that receives an external signal and transmits it to an internal circuit, and includes a plurality of amplifiers; and an offset correction circuit that corrects the offset of the plurality of amplifiers of the receiving circuit. The plurality of amplifiers include: a first amplifier that receives a differentially input external signal and differentially outputs it to the next amplifier; and a second amplifier that receives a differentially output signal of one of the plurality of amplifiers with differentially input and outputs it to an internal circuit. The offset correction circuit includes a standard signal generation circuit, a bias circuit, and a plurality of registers. The fixed voltage and the plurality of variable voltages having a plurality of voltage differences from the fixed voltage are generated by the standard signal generation circuit. The external signal differentially input to the first amplifier is blocked by the offset correction circuit, and the fixed voltage and one of the plurality of variable voltages are input to the first amplifier. The bias circuit is alternately connected to the differentially input node of the second amplifier to sequentially increase the flowing current, and the first binary code value of the bias circuit that causes the output of the second amplifier to change from a low level to a high level is stored in one of the plurality of registers. The offset of the plurality of amplifiers is corrected based on the average value of the first binary code values respectively related to the plurality of variable voltages stored in the plurality of registers.

[0013] Details of other embodiments are included in the detailed description and the drawings.

[0014] Technical effects

[0015] According to an embodiment of the present invention, the offset correction circuit intentionally applies a fixed voltage and a variable voltage with a specified voltage difference between a plurality of voltages adjacent to the fixed voltage as the input of the amplifier of the receiving circuit. As the bias circuit receives the average value obtained through the biasing process of the bias circuit as feedback to correct the offset, the offset can be corrected more precisely.

[0016] According to an embodiment of the present invention, as an added circuit, the offset correction circuit does not need to change the circuit structure related to the amplifier of the receiving circuit. Therefore, in addition to the offset correction effect, if the receiving circuit of the source driver circuit applies the offset correction circuit, better stability can be achieved at the circuit change level.

[0017] According to an embodiment of the present invention, the offset correction circuit performs two offset correction steps through two bias circuits on the receiving circuit including three or more amplifiers. Therefore, a wider adjustable offset range can be further ensured.

[0018] The effects of the present invention are not limited to the above-mentioned effects. Those of ordinary skill in the technical field to which the present invention pertains can clearly understand other effects not mentioned through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By referring to the accompanying drawings and describing the exemplary embodiments of the present disclosure in detail, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art. In the drawings:

[0020] Figure 1 is a structural diagram of a display device according to an embodiment of the present invention.

[0021] Figure 2 is a circuit diagram showing the receiving circuit of the source driver circuit of the present invention.

[0022] Figure 3 is a circuit diagram of a source driver circuit according to an embodiment of the present invention.

[0023] Figure 4 is a circuit diagram of a switch circuit included in the offset correction circuit according to an embodiment of the present invention.

[0024] Figure 5 is a circuit diagram of a standard signal generation circuit included in the offset correction circuit according to an embodiment of the present invention.

[0025] Figure 6 is a circuit diagram of a bias circuit included in the offset correction circuit according to an embodiment of the present invention.

[0026] Figure 7 Flowchart showing the offset correction method according to an embodiment of the present invention.

[0027] Figure 8 and Figure 9 Chart for explaining the offset correction result according to an embodiment of the present invention.

[0028] Figure 10 Circuit diagram of a source driver circuit according to another embodiment of the present invention.

[0029] Figure 11 Circuit diagram of a source driver circuit according to another embodiment of the present invention.

[0030] Figure 12 Timing diagram of the offset correction enable signal according to another embodiment of the present invention.

[0031] Description of reference numerals

[0032] 11, 12, 13, 15, 16: Receiving amplifier

[0033] 20: Switching circuit

[0034] 30: Standard signal generation circuit

[0035] 40, 42: Multiplexer circuit

[0036] 50, 52: Bias circuit

[0037] 70: Register

[0038] 80: Arithmetic circuit

[0039] 90: Internal circuit

[0040] 92: Recovery circuit

[0041] 94: Logic circuit

[0042] 100: Display device

[0043] 110: Image processing device

[0044] 120: Data driver device

[0045] 130: Gate driver device

[0046] 140: Data processing device

[0047] 150: Display panel

[0048] 152: Active area

[0049] 154: Peripheral part Detailed description of the embodiments

[0050] The advantages, features and implementation methods of the present invention can be made clear with reference to the embodiments described in detail in the accompanying Figure 1 drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in different ways. These embodiments are only used to make the disclosure of the present invention complete so that those of ordinary skill in the technical field to which the present invention pertains can fully understand the scope of the present invention. The present invention should be defined based on the scope of the invention claimed.

[0051] In the drawings used to illustrate the embodiments of the present invention, the shapes, sizes, ratios, angles, quantities, etc. disclosed are only examples, and the present invention is not limited to what is illustrated. Throughout the entire content of the specification, the same reference numerals represent the same structural elements. Also, during the process of describing the present invention, when it is determined that a detailed description of related well-known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In this specification, unless "only" is used, the terms "including", "having", "implementing", etc. mentioned mean that other parts can also be included. When a structural element is represented in the singular, it includes the plural case unless specifically defined otherwise.

[0052] During the process of explaining structural elements, even if not explicitly recorded separately, it should be interpreted as including the meaning of an error range.

[0053] When describing the positional relationship, for example, when using terms such as "above", "upper part", "lower part", "around" to describe the positional relationship between two parts, unless "directly" is used, there may be more than one other part between the two parts.

[0054] When describing the time relationship, for example, when using terms such as "subsequently", "then", "next", "before" to describe the sequence relationship in terms of time, unless "immediately" or "directly" is used, it may also include discontinuous cases.

[0055] In this specification, the "unit" used refers to a unit that processes at least one function or operation. For example, it can represent a software or hardware structural element. The functions provided by the "unit" can be dispersed and executed by multiple structural elements, or can be combined with other additional structural elements. In this specification, the "unit" is implemented by a single circuit or multiple circuits, or can be implemented by a single device or multiple devices.

[0056] In this specification, the features of multiple embodiments can be partially combined or combined or integrally combined or combined, and various linkages and drives can be achieved at the technical level. They can be independently implemented with respect to each embodiment, or can be implemented together according to the relevant relationships.

[0057] In this specification, the switching device applied to the source driving circuit may be a transistor of an n-type or p-type metal oxide semiconductor field effect transistor (MOSFET). The technical idea of the present invention is not limited to the types of transistors illustrated in the following embodiments. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. Inside the transistor, the carriers flow starting from the source. The drain is an electrode through which the carriers flow out of the transistor. That is, in a metal oxide semiconductor field effect transistor, the flow of carriers is from the source to the drain. In the case of an n-type metal oxide semiconductor field effect transistor (NMOS), since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type metal oxide semiconductor field effect transistor, since electrons flow from the source to the drain side, the current flows from the drain to the source side. In the case of a p-type metal oxide semiconductor field effect transistor (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type metal oxide semiconductor field effect transistor, since holes flow from the source to the source side, the current flows from the source to the drain side. It should be noted that the source and drain of a metal oxide semiconductor field effect transistor are not fixed. For example, the source and drain of a metal oxide semiconductor field effect transistor can change according to the applied voltage. In this specification, the source and drain of the transistor may be referred to as the first electrode and the second electrode, and the technical idea of the present invention is not limited to the source and drain of the transistor.

[0058] Hereinafter, the offset correction circuit and the data driving device including the same according to embodiments of the present invention will be described with reference to the drawings.

[0059] A display device according to an embodiment of the present invention includes: a display panel formed with a plurality of data lines and a plurality of gate lines; a plurality of source driving circuits for driving the plurality of data lines; a gate driving circuit for sequentially driving the plurality of gate lines; and a timing controller for controlling the source driving circuit and the gate driving circuit.

[0060] The timing controller provides digital image data to the source driving circuit, and accurately inputs a source driving signal corresponding to the digital image data to the display panel by controlling the source driving circuit and the gate driving circuit.

[0061] The timing controller can transmit an input signal including lock failure data to the source driver circuit according to each predetermined interval. Among them, the predetermined interval can be set as a partial interval in the vertical blanking interval between frames. In one embodiment, the timing controller can transmit an input signal including lock failure data on a per-frame basis.

[0062] During the display interval, the timing controller transmits an input signal including digital video data and control data together with a clock signal to the source driver circuit through a data transmission line, and can transmit an input signal including lock failure data to the source driver circuit in a partial interval in the vertical blanking interval.

[0063] The source driver circuit recovers the clock signal, digital video data, and control data based on the input signal provided by the timing controller during the display interval, arranges the recovered digital video data, converts the arranged digital video data into an analog source drive signal, and supplies the source drive signal to the data lines of the display panel. One source driver circuit can be composed of one integrated circuit (SD-IC), and the number of source driver circuits can be determined considering the size and resolution of the display panel.

[0064] Figure 1 It is a structural diagram of a display device according to an embodiment of the present invention. Refer to Figure 1 , the display device 100 may include a plurality of panel driving devices (or panel driving circuits) 110, 120, 130, 140 and a display panel 150.

[0065] A plurality of data lines DL and a plurality of gate lines GL are provided on the display panel 150, and a plurality of pixels may be provided. The pixel P may be composed of a plurality of sub-pixels (SP, Sub-Pixel).

[0066] Among them, the sub-pixels may be red (R, red), green (G, green), blue (B, blue), white (W, white), etc. One pixel bundle is composed of RGB sub-pixels SP, or composed of RGBG sub-pixels SP, or may be composed of RGBW sub-pixels SP, etc. Hereinafter, for the sake of convenience of description, an example in which one pixel is composed of RGB sub-pixels will be described.

[0067] The panel driving devices (or panel driving circuits) 110, 120, 130, 140 refer to devices for generating signals required for the display panel 150 to display an image, and may include at least one of an image processing device (or image processing circuit) 110, a data driving device (or data driving circuit) 120, a gate driving device (or gate driving circuit) 130, and a data processing device (or data processing circuit) 140.

[0068] The gate driving device (or gate driving circuit) 130 may supply a gate driving signal of an on-voltage or an off-voltage to the gate line GL. If the gate driving signal of the on-voltage is supplied to the sub-pixel SP, the sub-pixel SP may be connected to the data line DL. Moreover, if the gate driving signal of the off-voltage is supplied to the sub-pixel SP, the connection of the sub-pixel SP to the data line DL may be released. The gate driving device 130 may be referred to as a gate driver.

[0069] The data driving device (or data driving circuit) 120 may supply a data voltage Vp to the sub-pixel SP through the data line DL. The data voltage Vp supplied to the data line DL may be supplied to the sub-pixel SP according to the gate driving signal. The data driving device 120 may be referred to as a source driver.

[0070] The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit is of a tape automated bonding (TAB) type or a chip on glass (COG) type, and is connected to a bonding pad of the display panel 150, or may be directly formed on the display panel 150. According to an embodiment, it may also be integrated in the display panel 150.

[0071] Moreover, the data driving device 120 may be of a chip on film (COF) type. If the data driving device 120 is of a chip on glass type, the integrated circuit constituting the data driving device 120 may be formed in an outer peripheral portion 154 of an effective area 152 where the sub-pixel SP is provided. In order to maximize the effective area 152 of the display panel 150, the area of the outer peripheral portion 154 may be narrowed, and the chip size of the integrated circuit constituting the data driving device 120 may be reduced.

[0072] The data processing device (or data processing circuit) 140 may supply control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS for starting to execute scanning to the gate driving device 130. Moreover, the data processing device 140 may output image data IMG to the data driving device 120. And the data processing device 140 may send a data control signal DCS to control the data driving device 120 to supply the data voltage Vp to each sub-pixel SP. The data processing device 140 may be referred to as a timing controller.

[0073] The image processing device 110 may generate image data IMG and send it to the data processing device 140. The image processing device 110 may be referred to as a host.

[0074] The data processing device 140 may include at least one data processing circuit in the form of an integrated circuit and may include at least one data driving circuit in the form of an integrated circuit. A high-speed communication interface is formed between the data processing circuit and the data driving circuit, and the data processing circuit may send a data control signal DCS and / or image data IMG to the data driving circuit through such a high-speed communication interface. In the embodiments described below, from the perspective of the image data IMG transceiver device, the device that sends the image data is called the display processing device, and the device that receives the image data is called the display driving device.

[0075] For example, referring to Figure 1 , the image processing device 110 transmits the image data IMG to the data processing device 140. The image processing device 110 may be called the display processing device, and the data processing device 140 may be called the display driving device.

[0076] Also, the data processing device 140 transmits the image data IMG to the data driving device 120. The data processing device 140 may be called the display processing device, and the data driving device 120 may be called the display driving device.

[0077] Figure 2 The circuit diagram of the receiving circuit of the source driving circuit of the present invention is shown.

[0078] For example, the amplifier of the receiving circuit inside the source driving circuit may receive a differential input signal with a low swing width from an external device or circuit such as a timing controller through INP and INN which are differential input terminals (or differential input nodes), and amplify the signal size through the internal circuit included in the source driving circuit to transmit the signal.

[0079] When the internal circuit directly receives an external signal, since the signal size is not sufficient to recover the data, the receiving circuit may amplify the signal through an internal amplifier (Receiver Amplifier) and transmit it to the internal circuit. During the actual working process, since there is an offset in the amplifier of the receiving circuit, and this offset of the amplifier causes the signal transmitted to the internal circuit to be distorted, it may lead to errors in the recovered data. For example, if the offset of the amplifier is greater than the size (i.e., swing) of the input signal, it is transmitted to the internal circuit through the amplifier, so it may lead to errors in the recovered data.

[0080] The reason for the occurrence of the offset is, for example, in the semiconductor processing step, when the layout of the semiconductor is not symmetric, as mismatches occur, even for the same circuit, an offset may occur. As described above, in the case of an offset occurring in the process, each semiconductor may have different values of offset, so there is a problem that the same value cannot be uniformly applied for correction.

[0081] Figure 3Circuit diagram of a source driver circuit according to an embodiment of the present invention Figure 4 Circuit diagram of a switch circuit included in an offset correction circuit according to an embodiment of the present invention Figure 5 Circuit diagram of a standard signal generation circuit included in an offset correction circuit according to an embodiment of the present invention Figure 6 Circuit diagram of a bias circuit included in an offset correction circuit according to an embodiment of the present invention

[0082] A source driver circuit according to an embodiment of the present invention may include a receiving circuit, an internal circuit 90, and an offset correction circuit

[0083] The receiving circuit may include a first amplifier 11 and a second amplifier 12. The receiving circuit receives an external signal through the differential input terminals INP1 and INN1 of the first amplifier 11 and differentially outputs it to the second amplifier 12. The second amplifier 12 may receive the differential output signal of the first amplifier 11 and output an output signal to transmit an amplified signal to the internal circuit 90. Among them, the output signal of the second amplifier 12 is an analog signal, which means a signal that improves the noise and signal size of the input data to suit the protocol. The signal received from the external transmitter may have a small signal size or be mixed with noise signals. In order to smoothly recover the received signal and amplify the signal to the extent required by the internal circuit 90, an amplifier with two or more stages may be required

[0084] Among them, it should be noted that the terms "first amplifier" and "second amplifier" are only named according to the setting order of the amplifiers in the Figure 3 circuit diagram shown. Terms such as "first" or "second" do not limit the technical idea of the present invention. For example, according to an embodiment of the present invention, among multiple amplifiers connected in a cascade manner that receive differential inputs and differentially output them to the differential input terminals of the next amplifier, the amplifier set at the forefront may be named the "first amplifier", or the amplifier set at the end may be named the "second amplifier". The meaning referred to by such terms should be explained together based on the specific description

[0085] The internal circuit 90 includes a recovery circuit 92 and a logic circuit 94, and can be a circuit disposed inside a source driver circuit including such circuits. In one embodiment, the recovery circuit 92 can be a clock data recovery circuit (CDR), but is not limited thereto. When the recovery circuit 92 is a clock data recovery circuit, serial data embedded with standard clock information can be received from an external device or circuit, and the recovery circuit 92 can extract the standard clock information by separating the data and the standard clock signal. Then, by sampling the received data using the extracted standard clock information, the data can be accurately reconstructed. The logic circuit 94 can process the digital image data recovered by the recovery circuit 92.

[0086] The offset correction circuit according to an embodiment of the present invention may include a switch circuit (IN_SW) 20, a reference signal generation circuit (REF_GEN) 30, a multiplexer circuit (MUX) 40, a bias circuit (OS BIAS) 50, a plurality of registers 70, and an arithmetic circuit 80.

[0087] The switch circuit 20 can supply a signal generated from the reference signal generation circuit 30 to the differential input terminals (or differential input nodes) of the first amplifier 11 of the receiving circuit that receives an external signal, instead of the external signal. Referring to Figure 4 , the offset correction circuit can control the switch circuit 20 using an offset correction enable signal EN_OC and an inverted signal EN_OCB of the offset correction enable signal.

[0088] When the offset correction circuit starts to operate, the offset correction enable signal EN_OC becomes a high level. Accordingly, the inverted signal EN_OCB of the offset correction enable signal can become a low level. The switching device controlled by the inverted signal EN_OCB of the offset correction enable signal is turned off, and the connection between the differential input terminals INP1 and INN1 of the first amplifier 11 and the input external signal INP and INN terminals can be disconnected. Also, the switching device controlled by the offset correction enable signal EN_OC is turned on, and the differential input terminals INP1 and INN1 of the first amplifier 11 can be connected to the REF_P and REF_N nodes that supply the signal generated from the reference signal generation circuit 30.

[0089] Therefore, when starting to perform the offset correction according to an embodiment of the present invention, the external signal input to the first amplifier 11 can be blocked by the operation of the switch circuit 20, and the signal generated from the reference signal generation circuit 30 of the offset correction circuit can be supplied instead.

[0090] In an embodiment of the present invention, the reference signal generation circuit 30 can be Figure 5The circuit shown can generate a fixed voltage and variable voltages having a plurality of voltage differences from the fixed voltage. For example, a standard signal generation circuit outputs a fixed voltage Vs to the REF_P node, generates variable voltages having the same voltage as the fixed voltage Vs and having a specified voltage difference from the fixed voltage, which are Vs + 20 mV and Vs + 40 mV in the increasing direction and Vs - 20 mV and Vs - 40 mV in the decreasing direction, and outputs these variable voltages to the REF_N node. The variable voltages generated in this way include the voltage value of the fixed voltage, and the voltage difference between adjacent voltage values can all be equal to 20 mV. The voltage difference between adjacent voltage values is the same value and can be set to be suitable for offset correction and is not limited to a specific value.

[0091] In one embodiment, the standard signal generation circuit 30 may include a P-type transistor, a standard signal generation amplifier (Ref_gen Amp) 19, a plurality of resistors connected in series, and a plurality of switches. A power supply voltage VDD is applied to the second electrode of the transistor, the gate electrode is connected to the output of the standard signal generation amplifier 19, and the first electrode may be connected to the positive (+) terminal of the standard signal generation amplifier 19. A standard voltage VREF may be supplied to the negative (-) terminal of the standard signal generation amplifier 19.

[0092] In one embodiment, five resistors are connected in series to the first electrode of the transistor, and the last resistor may be connected to the ground GND. Switching devices controlled by binary code values are connected to each node between the resistors, and variable voltages can be output to the REF_N node corresponding to the fixed voltage output to the REF_P node. The binary code value for controlling the switching devices may be 3 bits, for example, S<2:0>. When the switching device is turned on by the S<000> control signal, the minimum variable voltage is output, and when the switching device is turned on by the S<100> control signal, the maximum variable voltage can be output.

[0093] As Figure 5 shown, in one embodiment, although the standard signal generation circuit 30 generates five variable voltages, the technical idea of the present invention is not limited thereto. The number of variable voltages that can be generated may also be seven, nine, or more, and can be adjusted according to the user's settings.

[0094] Moreover, according to an embodiment of the present invention, the fixed voltage output from the standard signal generation circuit 30 may be input to the INP1 node of the differential input terminals of the first amplifier 11, and the variable voltage may be input to the INN1 node of the differential input terminals of the first amplifier 11, but it is not limited thereto. Offset correction may also be performed by applying a fixed voltage to the INN1 node and applying a variable voltage to the INP1 node.

[0095] The current flowing to the connected (or electrically connected) differential input terminals is sequentially increased by alternately connecting a bias circuit 50 to the differential input terminals of the second amplifier 12. Refer to Figure 6 As the two switching devices PNS and PNSB are turned on and off, the bias circuit 50 of an embodiment of the present invention can be electrically connected to the differential input nodes INP2 and INN2 of the second amplifier 12. The switching device PNS and the switching device PNSB operate separately from each other, enabling the bias circuit 50 to be alternately connected to the differential input terminals of the second amplifier 12.

[0096] In an embodiment of the present invention, the bias circuit 50 refers to the circuit corresponding to the Figure 6 dotted line box, and the current flowing to the node connected to the second amplifier 12 can be sequentially increased by switching devices controlled by binary code values.

[0097] In one embodiment, the bias circuit 50 may include a plurality of transistors and a plurality of switching devices. The plurality of transistors may be connected in parallel by connecting their gate electrodes to the gate electrode of a transistor at one node and applying the bias voltage V of the amplifier BIAS . The first electrodes of the plurality of transistors can be connected to one node through switching devices (such as D<0>) controlled by binary code values, and the node connected to the first electrodes of the transistors can be electrically connected to the differential input terminals of the second amplifier 12 through the switching device PNS or the switching device PNSB.

[0098] In one embodiment, in order to increase the current flowing to the differential input node electrically connected to the bias circuit 50, the bias circuit 50 may perform the following operations. Among the switching devices connected to the plurality of transistors, if the switching device controlled by D<0> is turned on, a preset loc current can flow additionally. If the switching device controlled by D<1> is turned on, a current twice the preset loc (2*Ioc) can flow additionally. Similarly, if the switching devices controlled by D<2>, D<3>, and D<4> are turned on respectively, currents four times (4*Ioc), eight times (8*Ioc), and sixteen times (16*Ioc) the preset loc can flow additionally.

[0099] As Figure 6 shown, in one embodiment, although the bias circuit 50 includes five transistors and five switching devices and sequentially increases the current through the 5-bit binary code value of D<4:0>, the technical idea of the present invention is not limited thereto. When it is necessary to control more fine currents to precisely perform offset correction, the number of transistors and switching devices can also be further increased, and the number of such transistors and switching devices can be adjusted according to the user's settings.

[0100] The multiplexer circuit 40 is controlled by an offset correction enable signal EN_OC, and can output a binary code value D_IN<4:0> for the bias circuit 50 or an offset correction related feedback value D_FINAL to the bias circuit 50. In the case of starting offset correction, if the offset correction enable signal EN_OC is at the active level, the multiplexer circuit 40 outputs the binary code value D_IN<4:0> and transmits it to the bias circuit 50. In the period when offset correction is not performed, if the offset correction enable signal EN_OC is at the inactive level, the multiplexer circuit 40 can output the feedback value D_FINAL to the bias circuit 50 to correct the offset of the amplifier of the receiving circuit.

[0101] In the state before offset correction, the multiplexer circuit 40 can output the feedback value D_FINAL to the bias circuit 50 before starting offset correction. In one embodiment, the initial setting value of the feedback value D_FINAL can be set to PNSB = ON, PNS = OFF, D<00000>. After performing offset correction, the feedback value D_FINAL changes to a value reflecting the offset correction, and the binary code value used to determine the operation of the switching device of the bias circuit 50 can be determined through the feedback value D_FINAL to correct the offset of the amplifier of the receiving circuit.

[0102] When the bias circuit 50 is connected and working, the plurality of registers 70 can store the binary code value of the bias circuit 50 at the time point when the output level of the second amplifier 12 changes. In one embodiment, as the binary code value of the bias circuit 50 increases in sequence (i.e., the current flowing to the differential input node of the second amplifier 12 increases through the bias circuit 50 in sequence), the output level of the second amplifier 12 can change from a low level to a high level. For example, in D<01110>, when the output level of the second amplifier 12 changes from low to high, one of the plurality of registers 70 can store 01110 as the binary code value.

[0103] The plurality of registers 70 can respectively store the binary code values of the bias circuit 50 generated by the standard signal generation circuit 30 to respectively correspond to a plurality of variable voltages having a plurality of voltage differences with respect to a fixed voltage. Referring again to Figure 3 , as an example, the first register Register#1 in the plurality of registers 70 can store the binary code value D<4:0> of the bias circuit 50 as a result of performing offset correction based on the fixed voltage Vs and the variable voltage Vs - 40mV generated by the standard signal generation circuit 30. In this case, the binary code value of the standard signal generation circuit 30 that outputs the variable voltage Vs - 40mV is S<000>, and the signal having the binary code value S<000> is used as a control signal for determining the register, such as Figure 3As shown, the binary code value D<4:0> of the bias circuit 50 can be stored in the first register Register#1.

[0104] As Figure 3 shown, in one embodiment, corresponding to the structure of the standard signal generation circuit 30 generating 5 variable voltages, although there are 5 multiple registers 70, the technical idea of the present invention is not limited thereto. The number of variable voltages that can be generated can be adjusted according to user settings. Similarly, the number of registers 70 that can be used can also be adjusted according to user settings.

[0105] The arithmetic circuit 80 can perform arithmetic operations based on the binary code values D<4:0> of the bias circuit 50 respectively stored in the multiple registers 70 to calculate the average value. And the arithmetic circuit 80 can output the calculated average value and provide it as a feedback value D_FINAL to the inputs of the multiple multiplexer circuits 40. As described above, in the state before offset correction, before starting offset correction, the feedback value D_FINAL output by the arithmetic circuit 80 can be the initial setting value. In one embodiment, the initial setting value of the feedback value D_FINAL can be set to PNSB = ON, PNS = OFF, D<00000>. After performing offset correction, the feedback value D_FINAL can be changed to a value reflecting the offset correction.

[0106] Figure 7 It is a flowchart showing the offset correction method of an embodiment of the present invention.

[0107] The offset correction method 600 of an embodiment of the present invention is as follows.

[0108] In step S610, the external voltage (or external signal) supplied to the differential input terminals INP1 and INN1 of the first amplifier 11 can be blocked. The external voltage applied from the outside is supplied to the INP and INN nodes, and the connection path between the INP and INN nodes and the differential input terminals of the first amplifier 11 can be blocked by the switch circuit 20 of the offset correction circuit. Referring again to Figure 3 and Figure 4 , at the same time, the switch circuit 20 connects the standard signal output nodes REF_P and REF_N of the standard signal generation circuit 30 to the differential input terminals of the first amplifier 11, and an internal voltage of the source driver circuit having a first voltage difference can be applied to the INP1 and INN1 nodes. For example, if the fixed voltage is Vs and the variable voltage is Vs - 40 mV, then the first voltage difference is 40 mV.

[0109] In step S620, as one of the differential input terminals of the second amplifier 12, after connecting the bias circuit 50 to the INP2 node, the binary code value for controlling the internal switching device can be sequentially increased through the operation of the bias circuit 50. This can be a bias determination process for the INN2 node. In this case, referring to Figure 6 , the switching device PNS is in the on state and the switching device PNSB is in the off state. The binary code value D<4:0> of the bias circuit 50 at the time point when the output level of the second amplifier 12 changes (for example, at the time point when it changes from a low level to a high level while maintaining the low level) can be stored in one of the multiple registers 70. For example, if the fixed voltage is Vs and the variable voltage is Vs - 40 mV, the binary code value of the standard signal generation circuit 30 that outputs the variable voltage Vs - 40 mV is S<000>, and the signal with the binary code value S<000> is used as a control signal for determining the register. As shown in Figure 3 , the binary code value D<4:0> of the bias circuit 50 can be stored in the first register Register#1.

[0110] In step S630, as one of the differential input terminals of the second amplifier 12, after connecting the bias circuit 50 to the INN2 node, the binary code value for controlling the internal switching device can be sequentially increased through the operation of the bias circuit 50. This can be a bias determination process for the INP2 node. In this case, referring to Figure 6 , the switching device PNS is in the on state and the switching device PNSB is in the off state. The binary code value D<4:0> of the bias circuit 50 at the time point when the output level of the second amplifier 12 changes (for example, at the time point when it changes from a low level to a high level while maintaining the low level) can be stored in one of the multiple registers 70. For example, if the fixed voltage is Vs and the variable voltage is Vs - 40 mV, the binary code value of the standard signal generation circuit 30 that outputs the variable voltage Vs - 40 mV is S<000>, and the signal with the binary code value S<000> is used as a control signal for determining the register. As shown in Figure 3 , the binary code value D<4:0> of the bias circuit 50 can be stored in the first register Register#1.

[0111] In steps S620 and S630, the binary code values of the bias circuit 50 can both be stored in the first register Register#1. Since the same register is used, in one embodiment, additional data bits can be used to distinguish the binary code value in step S620, which is the bias process for the INP2 node, from the binary code value in step S630, which is the bias process for the INN2 node. Alternatively, in one embodiment, when storing the binary code value of the INP2 node in the register by adding one bit of the most significant bit (MSB) to the binary code value D<4:0> stored in the first register Register#1, the binary code value D<5:0> with the most significant bit value of 1 can be stored. As an example, in each D<01101>, if the output level of the second amplifier 12 changes, the stored value of the register for the INP2 node is 001101, and the stored value of the memory for the INN2 node can be 101101.

[0112] In step S640, the internal voltage of the source driving circuit with a second voltage difference can be applied to the INP1 and INN1 nodes. For example, if the fixed voltage is Vs and the variable voltage is Vs - 20 mV, the second voltage difference is 20 mV. As described above, after changing the variable voltage applied to the differential input terminals of the first amplifier 11, steps S620 and S630 can be repeatedly executed again. The binary code value of the standard signal generation circuit 30 that outputs the variable voltage Vs - 20 mV is S<001>, and the signal with the binary code value S<001> is used as a control signal for determining the register, as Figure 3 shown, the binary code value D<4:0> of the bias circuit 50 can be stored in the second register Register#2.

[0113] Next, the internal voltage of the source driving circuit with a third voltage difference can be applied to the INP1 and INN1 nodes. For example, if the fixed voltage is Vs and the variable voltage is Vs, the third voltage difference is 0V. As described above, after changing the variable voltage applied to the differential input terminals of the first amplifier 11, steps S620 and S630 can be repeatedly executed again. The binary code value of the standard signal generation circuit 30 that outputs the variable voltage Vs is S<010>, and the signal with the binary code value S<010> is used as a control signal for determining the register, as Figure 3 shown, the binary code value D<4:0> of the bias circuit 50 can be stored in the third register Register#3.

[0114] In the same manner, the internal voltages of the source driver circuit having the fourth voltage difference and the fifth voltage difference can be applied to the INP1 and INN1 nodes. For example, if the fixed voltage is Vs and the variable voltage is Vs + 20 mV, the fourth voltage difference is -20 mV, and if the variable voltage is Vs + 40 mV, the fifth voltage difference is -40 mV. The following process is the same as that for the first voltage difference to the third voltage value, and thus, the related description will be omitted.

[0115] Hereinafter, the register storage operation of an exemplary embodiment will be described.

[0116] In a state where a fixed voltage and a variable voltage having a first voltage difference are applied to the differential input terminals of the first amplifier 11, as one of the differential input terminals of the second amplifier 12, the bias circuit 50 electrically connected to the INP2 node sequentially increases the binary code value by operation. In the case where the output level of the second amplifier 12 does not change, the binary code value D<011111> of one bit of the most significant bit can be stored in the first register Register#1. Then, the bias circuit 50 electrically connected to the INN2 node sequentially increases the binary code value by operation. In D<01111>, if the output level of the second amplifier 12 changes from low to high, the binary code value D<101111> of one bit of the most significant bit can be stored in the first register Register#1, and it can be stored by replacing the binary code value D<011111> where the output level of the currently stored INP2 node does not change.

[0117] In a state where a fixed voltage and a variable voltage having a second voltage difference are applied to the differential input terminals of the first amplifier 11, as one of the differential input terminals of the second amplifier 12, the bias circuit 50 electrically connected to the INP2 node sequentially increases the binary code value by operation. In the case where the output level of the second amplifier 12 does not change, the binary code value D<011111> of one bit of the most significant bit can be stored in the second register Register#2. Then, the bias circuit 50 electrically connected to the INN2 node sequentially increases the binary code value by operation. In D<01110>, if the output level of the second amplifier 12 changes from low to high, the binary code value D<101110> of one bit of the most significant bit can be stored in the second register Register#2, and it can be stored by replacing the binary code value D<011111> where the output level of the currently stored INP2 node does not change.

[0118] For fixed voltages and variable voltages with a third voltage difference to a fifth voltage difference, the register storage operation can also be performed in the same manner. According to the biasing result of connecting to the INP2 node, the output level of the second amplifier 12 does not change. Therefore, the binary code values D<011111> with one bit of the most significant bit added can be stored in the third register Register#3 to the fifth register Register#5 respectively. According to the biasing result of connecting to the INN2 node, the binary code values D<01101>, D<01100>, D<01011> whose output levels of the second amplifier 12 do not change, and the binary code values D<101101>, D<101100>, D<101011> with one bit of the most significant bit added can be stored in the third register Register#3 to the fifth register Register#5 respectively, and can be stored by replacing the current stored binary code values D<011111> with unchanged output levels of the INP2 node.

[0119] Finally, the first register Register#1 to the fifth register Register#5 can store the binary code values D<101111>, D<101110>, D<101101>, D<101100>, D<101011> respectively.

[0120] In step S650, the arithmetic circuit 80 calculates the average value based on the binary code values stored in the registers, and can provide the calculated average value as a feedback value D_FINAL to the multiplexer circuit 40. The input state of the biasing circuit 50 can be determined by the average value calculated in this way. For example, when the calculated average value is D<101111>, since the feedback value is determined in such a way that more current flows to the INN2 node in the state where the biasing circuit 50 is connected to the INN2 node (i.e., the switching device state of PNSB = ON, PNS = OFF), it can be known that the voltage of the INN2 node is higher than the voltage of the INP2 node due to offset. In one embodiment, the control level of the biasing circuit 50 for the binary code value can be adjusted according to the user's setting.

[0121] In step S660, contrary to step S610, the external power supply (or external signal) supplied to the differential input terminals INP1, INN1 of the first amplifier 11 can be connected again. The external power supply applied from the outside is supplied to the INP and INN nodes, and the connection path between the INP and INN nodes and the differential input terminals of the first amplifier 11 can be connected through the switching circuit 20 of the offset correction circuit. Referring again to Figure 4 and Figure 5, meanwhile, the switching circuit 20 can block the internal voltage of the source driver circuit applied to the INP1 and INN1 nodes by blocking the connection between the standard signal output nodes REF_P and REF_N of the standard signal generation circuit 30 and the differential input terminals of the first amplifier 11.

[0122] Also, in step S660, the feedback value D_FINAL is input to the bias circuit 50, and as the bias circuit 50 operates based on this, the offset of the amplifier in the receiving circuit can be corrected.

[0123] Figure 8 and Figure 9 is a graph for explaining the offset correction result of an embodiment of the present invention.

[0124] Referring to Figure 8 , in an ideal situation where there is no offset in the multiple amplifiers of the receiving circuit, if voltages as shown in the table are respectively input to the differential input terminals INP1 and INN1 of the first amplifier 11, then the values shown as OUT2 are output through the output of the second amplifier 12 and can be stored in each register. It should be noted that Figure 8 the numerical values are only example numerical values for easy understanding.

[0125] Referring to Figure 9 , in an actual situation where there is offset in the multiple amplifiers of the receiving circuit, if voltages as shown in the table are respectively input to the differential input terminals INP1 and INN1 of the first amplifier 11, then the values shown as OUT2 are output through the output of the second amplifier 12 and can be stored in each register. Even if the same voltage as Figure 8 is input, due to the offset of the amplifier being reflected, the output values will be different. As a reference, it should be noted that Figure 9 the numerical values are also example numerical values for easy understanding.

[0126] With the use of the offset correction circuit of an embodiment of the present invention, if the multiple amplifiers of the receiving circuit apply the offset correction method of an embodiment of the present invention, then Figure 9 the output result shown as Figure 8 can be changed to the output shown as Figure 9 due to the offset correction of the amplifier. In the example of

[0127] , the offset of the amplifier can be corrected based on the average value 20 of 5 registers.

[0128] Figure 10 is the circuit diagram of the source driver circuit according to another embodiment of the present invention, Figure 11 is the circuit diagram of the source driver circuit according to another embodiment of the present invention, Figure 12Timing diagram of the offset correction enable signal for another embodiment of the present invention.

[0129] The basic structure or operation is similar to Figure 3 the source driver circuit of

[0130] Referring to Figure 10 , the receiving circuit may include three amplifiers 11, 12, and 13 connected in a cascade manner to receive a differential input and differentially output it to the differential input terminals of the next amplifier. When the receiving circuit receives an external signal and transmits the signal to the internal circuit, a situation may occur where it is necessary to further increase the amplification factor of the amplifier. In this case, the desired amplification factor can be obtained by using more than three amplifiers. As described above, in the case of using a multi-terminal amplifier, the offset may be further increased. As a result, there may be a problem that it is difficult to correct the increased offset only by using the offset correction of one bias circuit 50. Therefore, the offset correction range can be increased by additionally adding a bias circuit 52.

[0131] The bias circuit of another embodiment of the present invention may include a first bias circuit 50 and a second bias circuit 52, and the multiplexer circuit may include a first multiplexer circuit 40 and a second multiplexer circuit 42.

[0132] The first bias circuit 50 is alternately connected to the differential input terminals INP3 and INN3 of the third amplifier 13, and sequentially increases the current flowing to the electrically connected differential input terminals. The binary code value COARSE<4:0> determined by the operation of the first bias circuit 50 is stored in a plurality of registers 70, and the average value can be calculated by the arithmetic circuit 80 and provided to the first multiplexer circuit 40 as the feedback value D_FINAL_COARSE.

[0133] The second bias circuit 52 is alternately connected to the differential input terminals INP2 and INN2 of the first amplifier 11 (or the differential input terminals of the second amplifier 12), and sequentially increases the current flowing to the electrically connected differential input terminals. The binary code value FINE<4:0> determined by the operation of the second bias circuit 52 is stored in a plurality of registers 70, and the average value can be calculated by the arithmetic circuit 80 and provided to the second multiplexer circuit 42 as the feedback value D_FINAL_FINE.

[0134] Multiple registers 70 can be shared during the offset correction process by the first bias circuit 50 and the offset correction process by the second bias circuit 52. The average value calculated by the operation of the first bias circuit 50 is stored as a feedback value D_FINAL_COARSE at the input of the first multiplexer circuit 40. Since it is in a state of being continuously input to the first bias circuit 50, the binary code value FINE<4:0> generated by the operation of the second bias circuit 52 can be stored in the multiple registers 70 instead of the feedback value.

[0135] The initially output feedback values D_FINAL_COARSE and D_FINAL_FINE of the arithmetic circuit 80 can be initial setting values. In one embodiment, the initial setting values of the feedback values D_FINAL_COARSE and D_FINAL_FINE can be set to PNSB = ON, PNS = OFF, D<00000>. After performing offset correction, the feedback values D_FINAL_COARSE and D_FINAL_FINE can be changed to values reflecting the offset correction.

[0136] Referring to Figure 12 , in another embodiment of the present invention, the operation of the offset correction circuit can be performed according to the opening and closing of the offset correction enable signal EN_OC. More specifically, offset correction can be performed by the operation of the first bias circuit 50 in the high level interval of the first offset correction enable signal EN_C_OC, and offset correction can be performed by the operation of the second bias circuit 52 in the high level interval of the second offset correction enable signal EN_F_OC. Therefore, after performing offset correction by the operation of the first bias circuit 50, the offset correction circuit of another embodiment of the present invention can perform offset correction by the operation of the second bias circuit 52.

[0137] On the other hand, referring to Figure 11 , the receiving circuit can include four or more n amplifiers 11, 12, 15, 16 connected in a cascade manner to receive a differential input and differentially output it to the differential input terminals of the next amplifier.

[0138] The bias circuit of another embodiment of the present invention can include a first bias circuit 50 and a second bias circuit 52, and the multiplexer circuit can include a first multiplexer circuit 40 and a second multiplexer circuit 42.

[0139] The first bias circuit 50 is alternately connected to the differential input terminals INPn and INNn of the nth amplifier 16, and sequentially increases the current flowing to the electrically connected differential input terminals. The binary code value COARSE<4:0> determined by the operation of the first bias circuit 50 is stored in the plurality of registers 70, and the average value can be calculated by the arithmetic circuit 80 and provided as the feedback value D_FINAL_COARSE to the first multiplexer circuit 40.

[0140] The second bias circuit 52 is alternately connected to the differential input terminals INP2 and INN2 of the first amplifier 11 (or the differential input terminals of the second amplifier 12), and sequentially increases the current flowing to the electrically connected differential input terminals. The binary code value FINE<4:0> determined by the operation of the second bias circuit 52 is stored in the plurality of registers 70, and the average value can be calculated by the arithmetic circuit 80 and provided as the feedback value D_FINAL_FINE to the second multiplexer circuit 42.

[0141] Same as Figure 10 the embodiment of, the plurality of registers 70 can be shared and used in the offset correction process by the first bias circuit 50 and the offset correction process by the second bias circuit 52. Also, the initial setting values of the feedback values D_FINAL_COARSE and D_FINAL_FINE initially output by the arithmetic circuit 80 can be set to PNSB = ON, PNS = OFF, D<00000>.

[0142] In Figure 10 and Figure 11 the embodiment of the present invention, in a plurality of amplifiers connected in a cascade manner, when the last amplifier performs offset correction through the first bias circuit 50 at the front end, since the magnification of the last amplifier is relatively high, therefore, the voltage fluctuation range related to the bias of the first bias circuit 50 can be set relatively high. When the first amplifier performs offset correction through the second bias circuit 52 at the back end, since the magnification of the first amplifier is relatively low, therefore, the voltage fluctuation range related to the bias of the second bias circuit 52 can be set relatively low.

[0143] It should be noted that the terms "first amplifier" and "second amplifier" are only named according to the setting order of the amplifiers in the Figure 10 or Figure 11 shown circuit diagram, and terms such as "first" or "second" do not limit the technical idea of the present invention. For example, according to an embodiment of the present invention, in a cascade-connected amplifier that receives a differential input and differentially outputs it to the differential input terminals of the next amplifier, such as Figure 10 or Figure 11Among the multiple amplifiers shown, the amplifier set at the forefront is named the "first amplifier", and the amplifier set at the end can also be named the "second amplifier". The meaning referred to by such terms should be explained together based on the specific description.

[0144] As described above, the offset correction circuit of an embodiment of the present invention intentionally applies a fixed voltage and a variable voltage with a specified voltage difference between multiple voltages adjacent to the fixed voltage as the input of the amplifier of the receiving circuit. As the bias circuit corrects the offset by receiving the average value obtained through the biasing process of the bias circuit, the offset can be corrected more precisely. Moreover, as the offset correction circuit performs two offset correction steps through two bias circuits on the receiving circuit including three or more amplifiers, a wider adjustable offset range can be further ensured.

[0145] On the other hand, the source driver circuit described above can be provided in the data driving device. In this case, the data driving device can include: a source driver circuit; and a display panel provided with a plurality of pixels that receive power from the source driver circuit to operate.

[0146] Such a source driver circuit can include: a receiving circuit that receives an external signal and transmits it to an internal circuit, including a plurality of amplifiers; and an offset correction circuit that corrects the offset of the plurality of amplifiers of the receiving circuit.

[0147] Among them, the plurality of amplifiers can include: a first amplifier 11 that receives a differentially input external signal and differentially outputs it to the next amplifier; and a second amplifier 12 that receives the differentially output signal of one of the plurality of amplifiers with differentially input and outputs it to the internal circuit.

[0148] In this case, the offset correction circuit can include a standard signal generation circuit 30, a bias circuit 50, and a plurality of registers 70.

[0149] Moreover, the offset correction circuit generates a fixed voltage and a plurality of variable voltages with a plurality of voltage differences from the fixed voltage through the standard signal generation circuit 30, and stores the first binary code value of the bias circuit 50 that causes the output of the second amplifier 12 to change from a low level to a high level in one of the plurality of registers.

[0150] And the offset correction circuit corrects the offset of the plurality of amplifiers based on the average value of the first binary code values respectively related to the plurality of variable voltages stored in the plurality of registers.

[0151] As described above, although the embodiments of the present invention have been further described in detail with reference to the accompanying drawings, the present invention is not limited to such embodiments, and various modifications can be made without departing from the technical idea of the present invention. In addition, the embodiments disclosed in the present invention are only for illustration and do not limit the technical idea of the present invention. The scope of the technical idea of the present invention is not limited to such embodiments. Therefore, the embodiments described above are only examples in all aspects and should not be construed as having a limiting meaning. The protection scope of the present invention should be interpreted based on the scope of the invention claimed, and all technical ideas within the equivalent scope thereof belong to the scope of the invention claimed.

[0152] Cross - reference to related applications

[0153] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0002749, filed on January 8, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An offset correction circuit, the offset correction circuit comprising: A standard signal generation circuit for generating a fixed voltage and a plurality of variable voltages having a plurality of voltage differences with respect to the fixed voltage; A bias circuit connected to a plurality of amplifiers, sequentially increasing the current flowing to a connection node; And A plurality of registers for storing a plurality of binary code values of the bias circuit, Wherein, the plurality of amplifiers include: A first amplifier that receives a differentially input external signal and differentially outputs it to the next amplifier; and A second amplifier that receives a differentially output signal of one of the plurality of amplifiers with differentially input and outputs it to an internal circuit, Wherein, the offset correction circuit blocks the external signal differentially input to the first amplifier and inputs the fixed voltage and one of the plurality of variable voltages to the first amplifier, Stores a first binary code value of the bias circuit in one of the plurality of registers, and Corrects the offset of the plurality of amplifiers based on an average value of the first binary code values respectively related to the plurality of variable voltages stored in the plurality of registers.

2. The offset correction circuit according to claim 1, wherein, The voltage values of the plurality of variable voltages include the voltage value of the fixed voltage, and The voltage differences between adjacent voltage values of the plurality of variable voltages are all the same.

3. The offset correction circuit according to claim 1, wherein, The standard signal generation circuit controls the opening and closing of an internal switch circuit based on a second binary code value to generate the plurality of variable voltages, and Selects a register for storing the first binary code value of the bias circuit based on the second binary code value.

4. The offset correction circuit according to claim 1, wherein, The bias circuit receives an average value of the first binary code values and supplies an output corresponding to the average value of the first binary code values to the second amplifier to correct the offset of the plurality of amplifiers.

5. The offset correction circuit according to claim 1, wherein, The plurality of amplifiers are three or more, The bias circuit includes a first bias circuit and a second bias circuit, The first bias circuit is connected to a differentially input node of the second amplifier, and the second bias circuit is connected to a differentially output node of the first amplifier, thereby correcting the offset of the plurality of amplifiers.

6. The offset correction circuit according to claim 5, wherein, After correcting the offset of the plurality of amplifiers through the first bias circuit, the offset of the plurality of amplifiers is additionally corrected through the second bias circuit.

7. The offset correction circuit according to claim 1, wherein, The bias circuit is alternately connected to a differentially input node of the second amplifier to sequentially increase the flowing current.

8. A data driving device, the data driving device comprising: A receiving circuit that receives an external signal and transmits it to an internal circuit, including a plurality of amplifiers; And An offset correction circuit that corrects the offset of a plurality of amplifiers of the receiving circuit, Wherein, the plurality of amplifiers include: A first amplifier that receives a differentially input external signal and differentially outputs it to the next amplifier; and A second amplifier that receives the differential output signal of one of the plurality of amplifiers with differential inputs and outputs it to an internal circuit. Wherein, the offset correction circuit includes a standard signal generation circuit, a bias circuit, and a plurality of registers. Wherein, a fixed voltage and a plurality of variable voltages having a plurality of voltage differences from the fixed voltage are generated by the standard signal generation circuit. The offset correction circuit blocks the external signal input differentially to the first amplifier and inputs the fixed voltage and one of the plurality of variable voltages to the first amplifier. Store the first binary code value of the bias circuit in one of the plurality of registers, and Correct the offset of the plurality of amplifiers based on the average value of the first binary code values respectively related to the plurality of variable voltages stored in the plurality of registers.

9. The data driving device according to claim 8, wherein The voltage values of the plurality of variable voltages include the voltage value of the fixed voltage, and The voltage differences between adjacent voltage values of the plurality of variable voltages are all the same.

10. The data driving device according to claim 8, wherein The standard signal generation circuit controls the opening and closing of an internal switch circuit based on a second binary code value to generate the plurality of variable voltages, and Selects a register for storing the first binary code value of the bias circuit based on the second binary code value.

11. The data driving device according to claim 8, wherein, The offset correction circuit inputs the average value of the first binary code values to the bias circuit and supplies an output corresponding to the average value of the first binary code values to the second amplifier to correct the offset of the plurality of amplifiers.

12. The data driving device according to claim 8, wherein The plurality of amplifiers are three or more. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is connected to the differential input node of the second amplifier, and the second bias circuit is connected to the differential output node of the first amplifier, thereby correcting the offset of the plurality of amplifiers.

13. The data driving device according to claim 12, wherein, After the offset correction circuit corrects the offset of the plurality of amplifiers through the first bias circuit, it additionally corrects the offset of the plurality of amplifiers through the second bias circuit.

14. The data driving device according to claim 8, wherein, The bias circuit is alternately connected to the differential input node of the second amplifier to sequentially increase the flowing current.

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