Reference clock signal transceiver and terminal equipment
The control signal is received through the terminal matching circuit, the reference clock signal transceiver is configured as a receiver or transmitter, and it works in AC or DC coupled modes, which solves the problem of insufficient flexibility in the prior art and realizes flexible mode switching and adaptability enhancement.
Patent Information
- Application Number
- CN202410020679.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-05
- Publication Date
- 2025-07-08
AI Technical Summary
Existing reference clock signal transceivers are less flexible and can usually only be configured in input mode or output mode, or can only be configured in AC-coupled mode or DC-coupled mode.
A reference clock signal transceiver is provided that receives the first and second control signals through a terminal matching circuit, is configured as a reference clock signal receiver or transmitter based on the level of the control signal, and is operable in an AC-coupled mode or a DC-coupled mode.
The flexible configuration of the reference clock signal transceiver is realized, and the ability to switch in different modes is enhanced, which enhances its adaptability and functional diversity.
Smart Images
Figure CN120281331A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technologies, and in particular, to a reference clock signal transceiver and a terminal device. Background Art
[0002] A high-speed serial serializer / deserializer (Serdes) is an interface resource inside a Field Programmable Gate Array (FPGA), which realizes data interaction with an off-chip system. The Serdes receives an external reference clock signal through a reference clock signal transceiver, and generates a high-speed clock signal through a configurable frequency synthesizer; the Serdes can also adopt an internal Clock Data Recovery (CDR) module to recover a clock signal from the received data, and provide it to an external device as a reference clock through the reference clock signal transceiver.
[0003] The flexibility of the reference clock signal transceiver in the prior art is relatively low. Summary of the Invention
[0004] The technical problem solved by the present invention is that the flexibility of the existing reference clock signal transceiver is relatively low.
[0005] To solve the above technical problem, the present invention provides a reference clock signal transceiver, including: a termination matching circuit, a receiver, and a transmitter, where: the termination matching circuit is adapted to receive a first control signal and a second control signal; configure to form a reference clock signal receiver with the receiver or form a reference clock signal transmitter with the transmitter based on the level of the first control signal; and, when it is determined to form a reference clock signal receiver with the receiver, configure the received reference clock signal to be in an AC coupling mode or a DC coupling mode based on the level of the second control signal.
[0006] Optionally, when the first control signal is at a first level and the second control signal is at a first level, the termination matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in an AC coupling mode; when the first control signal is at a first level and the second control signal is at a second level, the termination matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in a DC coupling mode; when the first control signal is at a second level and the second control signal is at a second level, the termination matching circuit forms a reference clock signal transmitter with the transmitter to transmit the reference clock signal.
[0007] Optionally, the terminal matching circuit includes: a first resistor, a second resistor, a DC bias voltage source, a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, where: the first switch unit, its first end is coupled to the first reference clock signal port and the first output end of the terminal matching circuit, and its second end is coupled to the first end of the first resistor; the first resistor, its second end is coupled to the first end of the second resistor, the first end of the third switch unit, and the first end of the fourth switch unit; the second resistor, its second end is coupled to the first end of the second switch unit; the second switch unit, its second end is coupled to the second reference clock signal port; the third switch unit, its second end inputs a power supply voltage; the fourth switch unit, its second end is coupled to the first end of the DC bias voltage source; the second end of the DC bias voltage source is grounded.
[0008] Optionally, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all MOS transistors, and the size of the third switch unit is larger than that of the first switch unit, the second switch unit, and the fourth switch unit.
[0009] Optionally, the receiver includes: a differential amplification unit and an operational amplifier, where: the differential amplification unit, its first input end is coupled to the first output end of the terminal matching circuit, its second input end is coupled to the second output end of the terminal matching circuit, its first output end is coupled to the first input end of the operational amplifier, and its second output end is coupled to the second input end of the operational amplifier; the operational amplifier, its first output end and second output end differentially output a logic low level and a logic high level.
[0010] Optionally, the differential amplification unit includes: a third resistor, a fourth resistor, a first NMOS transistor, and a second NMOS transistor, where: the third resistor, its first end inputs a power supply voltage, and its second end is coupled to the drain of the first NMOS transistor; the fourth resistor, its first end inputs the power supply voltage, and its second end is coupled to the drain of the second NMOS transistor; the first NMOS transistor, its gate is coupled to the first input end of the differential amplification unit, and its source is grounded; the second NMOS transistor, its gate is coupled to the second input end of the differential amplification unit, and its source is grounded.
[0011] Optionally, the receiver further includes: a bias current source adapted to output a first bias current, where: the bias current source, its first end is coupled to the sources of the first NMOS transistor and the second NMOS transistor, and its second end is grounded.
[0012] Optionally, the transmitter includes: N differential current mode logic (CML) amplifiers, and any one of the differential CML amplifiers includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a fifth switching unit, where: the drain of the third NMOS transistor is coupled to the first output terminal of the terminal matching circuit, its gate receives a first differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; the drain of the fourth NMOS transistor is coupled to the second output terminal of the terminal matching circuit, its gate receives a second differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is coupled to the second terminal of the fifth switching unit, and its source is grounded; the first terminal of the fifth switching unit receives a second bias current, and its control terminal receives a third control signal.
[0013] The present invention also provides a terminal device, including any one of the reference clock signal transceivers provided above.
[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0015] The terminal matching circuit can receive a first control signal and a second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with the receiver, or form a reference clock signal transmitter with the transmitter. When the terminal matching circuit forms a reference clock signal receiver with the receiver, the received reference clock signal can be configured to be in an AC coupling mode or a DC coupling mode based on the second control signal. Thus, the reception, transmission, and reception mode of the reference clock signal transceiver can be flexibly configured. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic structural diagram of a reference clock signal transceiver in an embodiment of the present invention;
[0017] Figure 2 is a schematic structural diagram of a terminal matching circuit in an embodiment of the present invention;
[0018] Figure 3 is a schematic structural diagram of a receiver in an embodiment of the present invention;
[0019] Figure 4 is a schematic structural diagram of a transmitter in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0020] In the prior art, the flexibility of the reference clock signal transceiver is relatively low, and it can usually only be configured as an input mode or an output mode, or can only be configured as an AC coupling mode or a DC coupling mode.
[0021] In the embodiments of the present invention, the terminal matching circuit can receive a first control signal and a second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with the receiver, or form a reference clock signal transmitter with the transmitter. When the terminal matching circuit forms a reference clock signal receiver with the receiver, it can configure the received reference clock signal to be in an AC coupling mode or a DC coupling mode based on the second control signal. Thus, the reception, transmission, and reception mode of the reference clock signal transceiver can be flexibly configured.
[0022] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the accompanying drawings.
[0023] Referring to Figure 1 , a schematic structural diagram of a reference clock signal transceiver in the embodiments of the present invention is given.
[0024] In the embodiments of the present invention, the reference clock signal transceiver 10 may include a terminal matching circuit term, a receiver rx, and a transmitter tx. The reference clock signal transceiver 10 may include a first reference clock signal port REFCLKP and a second reference clock signal port REFCLKN.
[0025] In a specific implementation, the terminal matching circuit term may receive a first control signal en_tx output by an external control module. Based on the level of the first control signal en_tx, the terminal matching circuit term configures to form a reference clock signal receiver with the receiver rx to receive the reference clock signal; or configures to form a reference clock signal transmitter with the transmitter tx to transmit the reference clock signal recovered by the clock data recovery module.
[0026] Moreover, when the terminal matching circuit term forms a reference clock signal receiver with the receiver rx, the reference clock signal receiver may also be based on the received second control signal enb_dc. The reference clock signal receiver can configure the received reference clock signal to be in an AC (alternating current) coupling mode or a DC (direct current) coupling mode based on the level of the second control signal enb_dc.
[0027] Specifically, when the level of the first control signal en_tx is a first level, the terminal matching circuit term forms a reference clock signal receiver with the receiver rx; when the level of the first control signal en_tx is a second level, the terminal matching circuit term forms a reference clock signal transmitter with the receiver rx.
[0028] When the level of the second control signal enb_dc is the first level, the reference clock signal received by the reference clock signal receiver is in the alternating current (AC) coupling mode; when the level of the second control signal enb_dc is the second level, the reference clock signal received by the reference clock signal receiver is in the direct current (DC) coupling mode.
[0029] In a specific implementation, the first level is not equal to the second level. Specifically, the first level not being equal to the second level may mean that the voltage corresponding to the first level is not equal to the voltage corresponding to the second level.
[0030] In some embodiments, the first level is a low level and the second level is a high level. In other embodiments, the first level is a high level and the second level is a low level.
[0031] In an embodiment of the present invention, the reference clock signal may include two differential reference clock signals. When the terminal matching circuit term and the receiver rx form a reference clock signal receiver, the first reference clock signal port REFCLKP inputs the first differential reference clock signal CKP, and the second clock reference signal port REFCLKN inputs the second differential reference clock signal CKN.
[0032] The above-mentioned reference clock signal transceiver will be described in detail below.
[0033] Referring to Figure 2 a schematic structural diagram of a terminal matching circuit term in an embodiment of the present invention is given.
[0034] In an embodiment of the present invention, the terminal matching circuit term may include: a first resistor R1, a second resistor R2, a DC bias voltage source Vcm, a first switch unit S1, a second switch unit S2, a third switch unit S3, and a fourth switch unit S4, where:
[0035] The first end of the first switch unit S1 is coupled to the first reference clock signal port REFCLKP and the first output end VP of the terminal matching circuit term, and the second end of the first switch unit S1 is coupled to the first end of the first resistor R1;
[0036] The second end of the first resistor R1 may be coupled to the first end of the second resistor R2, the first end of the third switch unit S3, and the first end of the fourth switch unit S4;
[0037] The first end of the second resistor R2 is coupled to the second end of the first resistor R1, and the second end of the second resistor R2 is coupled to the first end of the second switch unit S2;
[0038] The second end of the second switch unit S2 is coupled to the second reference clock signal port REFCLKN and the second output end VN of the terminal matching circuit term;
[0039] The second terminal of the third switch unit S3 inputs the power supply voltage Vdd;
[0040] The second terminal of the fourth switch unit S4 is coupled to the first terminal of the DC bias voltage source Vcm;
[0041] The second terminal of the DC bias voltage source Vcm is grounded, and the DC bias voltage source Vcm can output a DC bias voltage.
[0042] In a specific implementation, the switching states of the first switch unit S1 and the second switch unit S2 can be controlled by the first control signal en_tx or the second control signal enb_dc. The switching states of the first switch unit S1 and the second switch unit S2 are the same. That is to say, the first switch unit S1 and the second switch unit S2 are turned on or off simultaneously.
[0043] Specifically, the control terminal of the first switch unit S1 and the control terminal of the second switch unit S2 can simultaneously input the first control signal en_tx, or simultaneously input the second control signal enb_dc. When the first control signal en_tx is at a high level, both the first switch unit S1 and the second switch unit S2 are turned on; when the first control signal en_tx is at a low level, both the first switch unit S1 and the second switch unit S2 are turned off. When the second control signal enb_dc is at a high level, both the first switch unit S1 and the second switch unit S2 are turned on; when the second control signal enb_dc is at a low level, both the first switch unit S1 and the second switch unit S2 are turned off.
[0044] The switching state of the third switch unit S3 can be controlled by the first control signal en_tx. When the first control signal en_tx is at a high level, the third switch unit S3 is turned on; when the first control signal en_tx is at a low level, the third switch unit S3 is turned off.
[0045] Specifically, the control terminal of the third switch unit S3 can input the first control signal en_tx. Thus, the switching state of the third switch unit S3 is controlled by the first control signal en_tx.
[0046] The switching state of the fourth switch unit S4 can be controlled by the second control signal enb_dc. When the second control signal enb_dc is at a high level, the fourth switch unit S4 is turned on; when the second control signal enb_dc is at a low level, the fourth switch unit S4 is turned off.
[0047] Specifically, the control terminal of the fourth switch unit S4 can input the second control signal enb_dc. Thus, the switching state of the fourth switch unit S4 is controlled by the second control signal enb_dc.
[0048] In some embodiments, the above-mentioned first switching unit S1, second switching unit S2, third switching unit S3, and fourth switching unit S4 can all be MOS transistors (such as PMOS transistors or NMOS transistors), or other devices, modules, or circuit units capable of implementing a switching function.
[0049] In the embodiments of the present invention, when the above-mentioned first switching unit S1, second switching unit S2, third switching unit S3, and fourth switching unit S4 are all MOS transistors, the sizes of the first switching unit S1, second switching unit S2, and fourth switching unit S4 can be the same or different.
[0050] Since the third switching unit S3 is connected to the power supply voltage Vdd, the third switching unit S3 can use a large-size MOS transistor, and the size of the MOS transistor used by the third switching unit S3 can be larger than the sizes of the first switching unit S1, second switching unit S2, and fourth switching unit S4. Using a large-size MOS transistor for the third switching unit S3 can reduce the conduction resistance voltage drop.
[0051] Combined with Figure 2 the terminal matching circuit term provided in, when the first control signal en_tx is at a low level, the terminal matching circuit term and the receiver rx form a reference clock signal receiver.
[0052] When the second control signal enb_dc is at a low level, the first resistor R1, second resistor R2, and the DC bias voltage source Vcm are not connected to the first output terminal VP and the second output terminal VN of the terminal matching circuit term. In this scenario, the DC coupling mode of the input reference clock signal is realized.
[0053] When the second control signal enb_dc is at a high level, the first switching unit S1, second switching unit S2, and fourth switching unit S4 are turned on, and the first resistor R1, second resistor R2, and the DC bias voltage source Vcm all participate in the operation. The DC bias voltage output by the DC bias voltage source Vcm is output to the first resistor R1 and the second resistor R2. After being divided by the first resistor R1 and the second resistor R2, they are respectively input to the first output terminal VP of the terminal matching circuit term and the second output terminal VN of the terminal matching circuit term. At this time, the input reference clock signal can be coupled to the first output terminal VP and the second output terminal VN of the terminal matching circuit term after passing through an off-chip capacitor. The input reference clock signal is in the AC coupling mode.
[0054] When the first control signal en_tx is at a high level, the first switch unit S1, the second switch unit S2, and the third switch unit S3 are turned on, and the fourth switch unit S4 is turned off. At this time, the terminal matching circuit term and the transmitter tx form a reference clock signal transmitter. The power supply voltage Vdd is output via the first resistor R1 and the second resistor R2 as the power supply for the transmitter tx. The first resistor R1 and the second resistor R2 can serve as pull-up resistors for the transmitter tx.
[0055] In a specific implementation, the resistance values of the first resistor R1 and the second resistor R2 can both be 50 ohms.
[0056] In the implementation of the present invention, the receiver rx can include a differential amplification unit and an operational amplifier, where:
[0057] The first input terminal of the differential amplification unit is coupled to the first output terminal of the terminal matching circuit term, the second input terminal of the differential amplification unit is coupled to the second output terminal of the terminal matching circuit term, the first output terminal of the differential amplification unit is coupled to the first input terminal of the operational amplifier, and the second output terminal of the differential amplification unit is coupled to the second input terminal of the operational amplifier.
[0058] The first output terminal and the second output terminal of the operational amplifier can be inverted with respect to each other, differentially outputting a logic low level and a logic high level. That is to say, when one output terminal of the operational amplifier outputs a logic low level, the other output terminal outputs a logic high level.
[0059] In a specific implementation, the above-mentioned logic low level can be logic level "0", and the above-mentioned logic high level can be logic level "1".
[0060] In a specific implementation, the first input terminal of the differential amplification unit inputs VP, and the second input terminal of the differential amplification unit inputs VN. Through the differential amplification unit, the differential logic levels on the first output terminal and the second output terminal of the terminal matching circuit term are converted to current mode (CML) logic levels; through a rail-to-rail operational amplifier, the CML logic levels are converted to CMOS logic levels.
[0061] Referring to Figure 3 shows a schematic structural diagram of a receiver rx in an embodiment of the present invention.
[0062] In a specific implementation, the differential amplification unit can include a third resistor R3, a fourth resistor R4, a first NMOS transistor M1, and a second NMOS transistor M2, where:
[0063] The first end of the third resistor R3 inputs the power supply voltage Vdd, and the second end of the third resistor R3 is coupled to the drain of the first NMOS transistor M1;
[0064] The first end of the fourth resistor R4 receives the power supply voltage Vdd, and the second end of the fourth resistor R4 is coupled to the drain of the second NMOS transistor M2;
[0065] The gate of the first NMOS transistor M1 is coupled to the first input terminal of the differential amplification unit (or serves as the first input terminal of the differential amplification unit), and the source of the first NMOS transistor M1 is grounded;
[0066] The gate of the second NMOS transistor M2 is coupled to the second input terminal of the differential amplification unit (or serves as the second input terminal of the differential amplification unit), and the source of the second NMOS transistor M2 is grounded.
[0067] VP is input to the gate of the first NMOS transistor M1, and VN is input to the gate of the second NMOS transistor M2. The drain of the first NMOS transistor M1 is coupled to the first input terminal of the operational amplifier OP and can serve as the first output terminal of the differential amplification unit; the drain of the second NMOS transistor M2 is coupled to the second input terminal of the operational amplifier OP and can serve as the second output terminal of the differential amplification unit.
[0068] In a specific implementation, the receiver rx may further include: a bias current source Ibias that outputs a first bias current, where:
[0069] The first end of the bias current source Ibias is coupled to the sources of the first NMOS transistor M1 and the second NMOS transistor M2, and the second end of the bias current source Ibias is grounded.
[0070] In some embodiments, the first bias current output by the bias current source Ibias may be a fixed value.
[0071] In the embodiments of the present invention, the transmitter tx may include N differential CML amplifiers 41. For any one of the differential CML amplifiers 41, its structure may be the same. Referring to Figure 4 a schematic structural diagram of a transmitter tx in the embodiments of the present invention is given.
[0072] In a specific implementation, for any one of the differential CML amplifiers, it may include: a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, and a fifth switch unit S5, where:
[0073] The first differential reference clock signal clkp may be input to the gate of the third NMOS transistor M3, the drain of the third NMOS transistor M3 may be coupled to the first output terminal VP of the terminal matching circuit term, and the source of the third NMOS transistor M3 is coupled to the drain of the fifth NMOS transistor M5;
[0074] The gate of the fourth NMOS transistor M4 can receive the second differential reference clock signal clkn. The drain of the fourth NMOS transistor M4 is coupled to the second output terminal VN of the terminal matching circuit term. The source of the fourth NMOS transistor M4 can be coupled to the drain of the fifth NMOS transistor M5.
[0075] The gate of the fifth NMOS transistor M5 can be coupled to the second terminal of the fifth switch unit S5, and the source of the fifth NMOS transistor M5 is grounded.
[0076] The first terminal of the fifth switch unit S5 receives the second bias current biasn, and the control terminal of the fifth switch unit S5 receives the third control signal.
[0077] In a specific implementation, the above-mentioned first differential reference clock signal clkp and second differential reference clock signal clkn are the reference clock signals recovered by the clock recovery circuit.
[0078] In a specific implementation, the differential CML amplifier 41 can reuse the first resistor R1, the second resistor R2, and the power supply voltage Vdd in the terminal matching circuit term.
[0079] In a specific implementation, the tail current of the transmitter tx is configurable. By configuring the tail current of the transmitter tx, the pulling-down current intensity of the first output terminal VP and the second output terminal VN of the terminal matching circuit term can be regulated, thereby changing the driving ability of the output stage.
[0080] For some specific output requirements, according to the logic level specifications, the level of the power supply voltage Vdd of the terminal matching circuit term and the number M of the turned-on differential CML amplifiers can be determined. Specifically, assuming that the load of the two output terminals of the transmitter tx is 100 ohms, for the logic high level, VOH = Vdd - Itx × M × 12.5Ω; for the logic low level, VOH = Vdd - Itx × M × 37.5Ω.
[0081] Specifically, by controlling the switching state of the fifth switch unit S5 through the third control signal, the number of turned-on differential CML amplifiers 41 can be controlled.
[0082] In summary, by using the reference clock signal transceiver provided in the above embodiment, the terminal matching circuit can receive the first control signal and the second control signal. Based on the level of the first control signal, the terminal matching circuit can form a reference clock signal receiver with the receiver, or form a reference clock signal transmitter with the transmitter. When the terminal matching circuit forms a reference clock signal receiver with the receiver, based on the second control signal, the received reference clock signal can be configured to be in the AC coupling mode or the DC coupling mode. Thus, the reception, transmission, and reception mode of the reference clock signal transceiver can be flexibly configured.
[0083] An embodiment of the present invention further provides a terminal device, including the reference clock signal transceiver provided in any of the above embodiments.
[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A reference clock signal transceiver, characterized in that, Comprising: A terminal matching circuit, a receiver, and a transmitter, wherein: The terminal matching circuit is adapted to receive a first control signal and a second control signal; configure to form a reference clock signal receiver with the receiver or a reference clock signal transmitter with the transmitter based on the level of the first control signal; and, when determining to form a reference clock signal receiver with the receiver, configure the received reference clock signal to be in an AC coupling mode or a DC coupling mode based on the level of the second control signal.
2. The reference clock signal transceiver according to claim 1, characterized in that When the first control signal is at a first level and the second control signal is at a first level, the terminal matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in an AC coupling mode; When the first control signal is at a first level and the second control signal is at a second level, the terminal matching circuit forms a reference clock signal receiver with the receiver, and the reference clock signal received by the reference clock signal receiver is in a DC coupling mode; When the first control signal is at a second level and the second control signal is at a second level, the terminal matching circuit forms a reference clock signal transmitter with the receiver and transmits the reference clock signal.
3. The reference clock signal transceiver according to claim 2, wherein The terminal matching circuit includes: a first resistor, a second resistor, a DC bias voltage source, a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, wherein: The first switch unit has its first end coupled to a first reference clock signal port and the first output end of the terminal matching circuit, and its second end coupled to the first end of the first resistor; The first resistor has its second end coupled to the first end of the second resistor, the first end of the third switch unit, and the first end of the fourth switch unit; The second resistor has its second end coupled to the first end of the second switch unit; The second switch unit has its second end coupled to a second reference clock signal port; The third switch unit has its second end input with a power supply voltage; The fourth switch unit has its second end coupled to the first end of the DC bias voltage source; The second end of the DC bias voltage source is grounded.
4. The reference clock signal transceiver according to claim 3, wherein, The first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are all MOS transistors, and the size of the third switch unit is larger than that of the first switch unit, the second switch unit, and the fourth switch unit.
5. The reference clock signal transceiver according to claim 2, wherein The receiver includes: a differential amplification unit and an operational amplifier, wherein: The differential amplification unit has its first input end coupled to the first output end of the terminal matching circuit, its second input end coupled to the second output end of the terminal matching circuit, its first output end coupled to the first input end of the operational amplifier, and its second output end coupled to the second input end of the operational amplifier; The operational amplifier has its first output end and second output end differentially outputting a logic low level and a logic high level.
6. The reference clock signal transceiver according to claim 5, wherein The differential amplification unit includes: a third resistor, a fourth resistor, a first NMOS transistor, and a second NMOS transistor, where: for the third resistor, its first end inputs a power supply voltage, and its second end is coupled to the drain of the first NMOS transistor; for the fourth resistor, its first end inputs the power supply voltage, and its second end is coupled to the drain of the second NMOS transistor; for the first NMOS transistor, its gate is coupled to the first input end of the differential amplification unit, and its source is grounded; for the second NMOS transistor, its gate is coupled to the second input end of the differential amplification unit, and its source is grounded.
7. The reference clock signal transceiver according to claim 6, wherein The receiver further includes: a bias current source adapted to output a first bias current, where: for the bias current source, its first end is coupled to the sources of the first NMOS transistor and the second NMOS transistor, and its second end is grounded.
8. The reference clock signal transceiver according to claim 2, wherein The transmitter includes: N differential current mode logic (CML) amplifiers, and any one of the differential CML amplifiers includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a fifth switching unit, where: for the third NMOS transistor, its drain is coupled to the first output end of the terminal matching circuit, its gate inputs a first differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; for the fourth NMOS transistor, its drain is coupled to the second output end of the terminal matching circuit, its gate inputs a second differential reference clock signal, and its source is coupled to the drain of the fifth NMOS transistor; for the fifth NMOS transistor, its gate is coupled to the second end of the fifth switching unit, and its source is grounded; for the fifth switching unit, its first end inputs a second bias current, and its control end inputs a third control signal.
9. A terminal device, characterized in that, It includes a reference clock signal transceiver according to any one of claims 1 to 8.