ASK 100% modulation communication system and method applied to passive NFC tag

Abstract

The invention discloses an ASK (Amplitude Shift Keying) 100% modulation communication system and method applied to a passive NFC (Near Field Communication) tag. According to the invention, a high-precision numerical control oscillator circuit is introduced to generate a recovery clock signal, a carrier clock signal is used for performing time sequence control in a signal receiving process of the NFC tag, and the recovery clock signal is switched for performing time sequence control in a signal sending process, so that the passive NFC tag has a stable clock source during a clock loss period of ASK 100% modulation, and the reliability of the passive NFC tag is improved. And normal work of the digital circuit can be ensured. Meanwhile, a digital clock calibration circuit is also introduced, so that on the premise of ensuring the calibration frequency, the device has relatively small area and power consumption, and is more suitable for the development trend and requirements of low power consumption and low cost of the passive NFC tag. According to the invention, the passive NFC tag adopts ASK 100% to carry out load modulation and PCD communication, the anti-interference capability of signals is greatly improved, the requirement for the minimum antenna coupling coefficient k can be optimized, the geometric alignment requirement of the antenna is optimized, and the long-distance communication capability of the tag is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an ASK 100% modulation communication system and method applied to passive NFC tags. Background Art

[0002] NFC is a contactless information transfer technology that has been widely applied in fields such as finance, identity recognition, and logistics warehousing management. With the rapid development of modern social and economic activities and technological progress, data exchange between readers and transponders faces huge challenges. They need to communicate at high speed, accurately, and securely in an environment full of electromagnetic noise. Electromagnetic interference in such an environment seriously threatens the accuracy and stability of data transmission. Once communication errors or data loss occur, it may not only lead to economic losses but also damage the brand reputation and customer loyalty of financial institutions. Therefore, in such scenarios, it is extremely necessary to improve the anti-interference performance of the chip and ensure accurate communication.

[0003] Conventional passive NFC transponders to readers belong to passive modulation, and the modulation process depends on the carrier signal. The passive NFC tag returns signals through load modulation. The load modulation circuit selects whether to connect a resistor according to 0 or 1 of the load modulation signal, thereby affecting the amplitude of the carrier on the antenna and transmitting information through the amplitude difference. During the process, in order to maintain the normal operation of the digital circuit inside the tag, a stable clock input must be ensured.

[0004] The non-ASK 100% load modulation of the tag has advantages such as simple implementation and good continuity. The disadvantages are that the ASK demodulation circuit at the receiving end is relatively complex, the signal anti-interference ability is limited, and it is easy to increase the demodulation difficulty of the reader due to the insignificant amplitude difference problem during long-distance transmission, resulting in communication failure. In ASK 100% modulation communication, the transponder cannot obtain a stable clock signal input, so it cannot maintain the normal operation of the digital circuit inside the tag and cannot keep the output of the response signal. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides an ASK 100% modulation communication system and method applied to passive NFC tags.

[0006] The first aspect of the present invention provides an ASK 100% modulation communication system applied to passive NFC tags, including:

[0007] A clock extraction circuit, which is used to extract a carrier clock from the carrier signal and use the carrier clock to maintain the working timing of the NFC tag during signal reception;

[0008] An ASK demodulation circuit, which is used to obtain the binary encoded signal from the reader transmitted by the radio frequency field;

[0009] A decoding module, which is used to decode the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0010] A response control module, which is used to generate a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module;

[0011] A numerically controlled oscillator circuit, which is used to generate a recovered clock signal, and use the recovered clock signal to maintain the working timing of the NFC tag during signal transmission;

[0012] A digital clock calibration circuit, which is used to calibrate the recovered clock signal;

[0013] An encoding module, which is used to encode the binary original code signal to generate a baseband signal;

[0014] A subcarrier modulation module, which is used to perform subcarrier modulation on the baseband signal to generate a subcarrier modulation signal;

[0015] A load modulation circuit, which is used to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulation signal to generate a response signal and send it to the reader.

[0016] Further, the numerically controlled oscillator circuit includes:

[0017] A current mirror circuit, which is used to adjust the charging and discharging current of the oscillator capacitor to control the voltage change speed of the oscillator capacitor, and further adjust the frequency of the recovered clock signal;

[0018] A comparator circuit, which is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal;

[0019] A frequency division-by-two circuit, which is used to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovered clock signal with a 50% duty cycle.

[0020] Further, the current mirror circuit includes a plurality of current mirror branches; each current mirror branch is composed of a PMOS transistor and an NMOS transistor; the base of the NMOS transistor is connected to the digital clock calibration circuit, and the on / off of the NMOS transistor in each current mirror branch is controlled by the control word with different control bits output by the digital clock calibration circuit to adjust the charging and discharging current of the oscillator capacitor.

[0021] Further, the digital clock calibration circuit includes:

[0022] A first counter for counting the number of cycles of a carrier signal;

[0023] A second counter for counting the number of cycles of a recovered clock signal output by the numerically controlled oscillator circuit;

[0024] A judgment module for judging the quantitative relationship between the number of cycles counted by the first counter and the second counter to generate a fast / slow judgment signal;

[0025] A calibration module for adjusting a control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to calibrate the recovered clock signal.

[0026] Further, the second counter has a counting upper limit; when the second counter reaches the counting upper limit, the current control word setting output to the numerically controlled oscillator circuit is saved, and it is judged that the calibration of the recovered clock signal is completed.

[0027] Further, the quantitative relationship judgment performed by the judgment module is: whether the number of cycles counted by the first counter is four times the number of cycles counted by the second counter; the target frequency of the recovered clock signal is a quarter-frequency of the carrier signal clock cycle;

[0028] When the number of cycles counted by the first counter is greater than four times the number of cycles counted by the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovered clock signal is lower than the target frequency;

[0029] When the number of cycles counted by the first counter is less than four times the number of cycles counted by the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency;

[0030] When the number of cycles counted by the first counter is equal to four times the number of cycles counted by the second counter and the second counter has not reached the upper limit value, the judgment module judges that the current counting time is not sufficient to distinguish the frequency fast / slow of the recovered clock signal, and does not output a fast / slow judgment signal, and the two counters continue to work.

[0031] Further, when the calibration module receives a slow judgment signal, the control word currently output to the numerically controlled oscillator circuit is set to 1;

[0032] When the calibration module receives a fast judgment signal, the control word currently output to the numerically controlled oscillator circuit is set to 0;

[0033] When the calibration module receives the calibration completion signal, it maintains the current control word set to 1, saves the current output to the control word setting of the numerically controlled oscillator circuit, determines that the recovery clock signal has completed calibration, ends the calibration process in advance, and subsequent control words will no longer be calibrated.

[0034] The second aspect of the present invention discloses an ASK 100% modulation communication method applied to a passive NFC tag, which is applied to an ASK 100% modulation communication system for passive NFC tags described in the first aspect, and includes a signal reception process and a signal transmission process;

[0035] Among them, the signal reception process specifically includes:

[0036] Use a clock extraction circuit to extract the carrier clock from the carrier signal, and use the carrier clock to maintain the working timing of the NFC tag during signal reception;

[0037] Use an ASK demodulation circuit to obtain the binary coded signal from the reader transmitted by the radio frequency field;

[0038] Use a decoding module to decode the binary coded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0039] Use a response control module to generate a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module;

[0040] The signal transmission process specifically includes:

[0041] Use a numerically controlled oscillator circuit to generate a recovery clock signal, and use the recovery clock signal to maintain the working timing of the NFC tag during signal transmission;

[0042] Use a digital clock calibration circuit to calibrate the recovery clock signal;

[0043] Use an encoding module to encode the binary original code signal to generate a baseband signal;

[0044] Use a subcarrier modulation module to perform subcarrier modulation on the baseband signal to generate a subcarrier modulation signal;

[0045] Use a load modulation circuit to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulation signal to generate a response signal and send it to the reader.

[0046] Further, the recovery clock signal is generated through the following steps:

[0047] Use a current mirror circuit to control the on and off of the NMOS transistors in each current mirror branch according to the control words of different control bits output by the digital clock calibration circuit, so as to adjust the charging and discharging current of the oscillator capacitor;

[0048] Use a comparator circuit to compare the voltage difference between the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal;

[0049] Use a frequency divider circuit to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovered clock signal with a 1 / 2 duty cycle.

[0050] Further, the recovered clock signal is calibrated through the following steps:

[0051] Use a first counter to count the number of cycles of the carrier signal;

[0052] Use a second counter to count the number of cycles of the recovered clock signal output by the numerically controlled oscillator circuit;

[0053] Use a judgment module to judge the quantitative relationship between the number of cycles counted by the first counter and the second counter to generate a fast / slow judgment signal;

[0054] Use a calibration module to adjust the control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to achieve calibration of the recovered clock signal.

[0055] The embodiments of the present invention have the following beneficial effects: By introducing a high-precision numerically controlled oscillator circuit to generate a recovered clock signal, the present invention uses a carrier clock signal for timing control in the signal receiving process of the NFC tag, and switches to the recovered clock signal for timing control in the signal sending process, realizing that the passive NFC tag has a stable clock source during the clock loss period of ASK100% modulation, and can ensure the normal operation of the digital circuit. At the same time, the present invention also introduces a digital clock calibration circuit, which has a relatively small area and power consumption on the premise of ensuring the calibration frequency, and is more suitable for the development trend and requirements of low power consumption and low cost of passive NFC tags. The present invention realizes the communication between the passive NFC tag and the PCD using ASK100% for load modulation, which can not only greatly improve the anti-interference ability of the signal, but also reduce the demodulation difficulty at the receiving end, simplify the structure of the ASK demodulation circuit, and in addition, can optimize the requirements for the minimum antenna coupling coefficient k required to maintain normal communication, optimize the geometric alignment requirements of the antenna, and improve the long-distance communication ability of the tag.

[0056] The additional aspects and advantages of the present invention will be given in the following description section, some of which will become obvious from the following description, or can be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0058] Figure 1 It is a comparison diagram of non-ASK100% load modulation and ASK100% modulation antenna waveforms.

[0059] Figure 2 It is a schematic diagram of an ASK100% modulation communication system applied to a passive NFC tag according to the present invention.

[0060] Figure 3 It is a schematic diagram of an ASK100% modulation communication process applied to a passive NFC tag.

[0061] Figure 4 It is a schematic diagram of the circuit structure of a numerically controlled oscillator according to the present invention.

[0062] Figure 5 It is a schematic diagram of the overall operation of the numerically controlled oscillator circuit and the digital clock calibration circuit according to the present invention.

[0063] Figure 6 It is a schematic diagram of the working effect of the digital calibration circuit according to the present invention.

[0064] Figure 7 It is a schematic diagram of the AMS simulation results of ASK100% modulation communication between the NFC tag and the reader according to the present invention.

[0065] Figure 8 It is a schematic diagram of the AMS simulation results of the response signal of the NFC tag according to the present invention. Specific embodiments

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] Comparison of antenna waveforms of non-ASK100% load modulation and ASK100% modulation Figure 1 As shown. Figure 1On the left side is the antenna waveform of non-ASK 100% load modulation. It can be seen from the antenna waveform that the carrier wave of non-100% load modulation always exists, so the signal continuity is good. However, the amplitude difference of its waveform is small and the bit error rate is higher. As a result, the ASK demodulation circuit at the receiving end is relatively complex, the signal anti-interference ability is limited, and it is easy to increase the demodulation difficulty of the reader due to the insignificant amplitude difference in long-distance transmission, resulting in communication failure. Figure 1 On the right side is the antenna waveform of ASK 100% modulation. It can be seen from the antenna waveform that the carrier signal of ASK 100% modulation is only output at high levels and completely disappears at low levels. The amplitude difference of its waveform is large, which can significantly enhance the anti-interference ability of communication. At the same time, it can optimize the communication distance to a certain extent, simplify the ASK demodulation circuit at the receiving end, and optimize the communication performance.

[0068] In actual operation, as a transponder, the load modulation process of the passive NFC tag depends on the carrier signal and belongs to passive modulation. After the antenna at the receiving end of the tag receives the electromagnetic wave transmitted by the reader, it will analyze the information data carried by the electromagnetic wave and then convert it into a binary signal for demodulation by the digital circuit. The information data carried by the electromagnetic wave may include operation instructions and operation data of the host computer, etc. The digital circuit inside the tag further returns a response signal to the reader according to the instruction content. Specifically, according to different instructions, the original response data content may be generated in different ways. For some instructions with fixed response content, the corresponding response data (such as ATQA) is directly generated inside the digital circuit and encoded and modulated. For some instructions, the received binary data needs to be calculated to obtain the original code to be responded; while for some, it needs to be obtained from the storage unit. For example, for a read instruction, the data is read from the storage unit EEPROM into the digital circuit, and the digital circuit encodes and modulates the read original code again. It can be seen that the digital circuit inside the tag plays a key role in the tag response process, and the clock source that controls the timing of the digital circuit is the carrier clock carried by the carrier signal.

[0069] However, during the ASK 100% modulation communication process, the carrier signal will be completely turned off at the low level of the modulation signal, which will cause the RF front end of the tag to be unable to continue parsing and unable to provide a stable and accurate clock signal to the clock extraction circuit for the digital circuit. Without being able to maintain the output of the clock signal, the digital circuit timing will stagnate at the state at the moment of clock loss. After waiting for a period of time, the reader will judge a communication error and end the communication with the transponder. Since the communication between the reader and the transponder is half-duplex, during the process of the transponder sending and the reader receiving, the reader will continuously receive the signal sent by the transponder and will not perform any actions during the process. Therefore, it is impossible to require the reader to restart the carrier clock when waiting for the modulation signal to pass the low-level moment, resulting in the occurrence of modulation communication interruption.

[0070] To solve this problem, as Figure 2 shown, the first embodiment of the present invention provides an ASK 100% modulation communication system applied to a passive NFC tag, including:

[0071] A clock extraction circuit for extracting a carrier clock from a carrier signal and using the carrier clock to maintain the working timing of the NFC tag during signal reception;

[0072] An ASK demodulation circuit for obtaining a binary encoded signal from a reader transmitted by a radio frequency field;

[0073] A decoding module for decoding the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0074] A response control module for generating a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module;

[0075] A numerically controlled oscillator circuit for generating a recovered clock signal and using the recovered clock signal to maintain the working timing of the NFC tag during signal transmission;

[0076] A digital clock calibration circuit for calibrating the recovered clock signal;

[0077] An encoding module for encoding the binary original code signal to generate a baseband signal;

[0078] A subcarrier modulation module for performing subcarrier modulation on the baseband signal to generate a subcarrier modulation signal;

[0079] A load modulation circuit for modulating the amplitude of the carrier signal by 100% according to the subcarrier modulation signal to generate a response signal and send it to the reader.

[0080] In the embodiment of the present invention, by introducing a high-precision recovered clock circuit based on a numerically controlled oscillator circuit, the problem of clock loss during ASK 100% modulation communication of a passive NFC tag is solved. The carrier clock signal is used for timing control during the signal reception process of the NFC tag, and the recovered clock signal is switched to for timing control during the signal transmission process, realizing that the passive NFC tag has a stable clock source during the clock loss period of ASK 100% modulation, which can ensure the normal operation of the digital circuit, and further realizing the ASK 100% modulation communication of the passive NFC tag.

[0081] The label circuit design of the embodiments of the present invention is compatible with the ISO / IEC 14443-A protocol. After enabling the ASK100% modulation configuration, the numerically controlled oscillator circuit and the digital clock calibration circuit start the calibration work. When the label finishes parsing the received signal and is ready to return a response signal to the reader, the switched recovery clock circuit instead of the carrier clock is used to maintain the operation of the digital timing circuit. The implementation effect of the present invention is as Figure 3 shown. Under normal operation, when the label receives an instruction, it will output corresponding information according to the instruction. The original code of the information output by the label through the demodulation module will first be passed to the encoding module, where Manchester encoding is completed. Then, a subcarrier modulation signal is loaded, and finally, the subcarrier modulation signal is output to the analog load modulation circuit. The load modulation circuit realizes amplitude modulation by connecting or disconnecting the resistor in the circuit according to the high or low level of the subcarrier modulation signal.

[0082] The following specifically describes the design of the numerically controlled oscillator circuit and the digital clock calibration circuit of the present invention.

[0083] As Figure 4 shown, the numerically controlled oscillator circuit of the present invention includes:

[0084] A current mirror circuit, which is used to adjust the charging and discharging current of the oscillator capacitor to control the voltage change speed of the oscillator capacitor, and further adjust the frequency of the recovery clock signal;

[0085] A comparator circuit, which is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal;

[0086] A divide-by-two circuit, which is used to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovery clock signal with a 50% duty cycle.

[0087] In the embodiments of the present invention, the numerically controlled oscillator circuit (DCO, Digital Control Oscillator) is used to provide a clock source, and is used to provide a stable and high-precision recovery clock signal for the digital circuit of the label when the ASK100% communication clock is lost. In the embodiments of the present invention, the recovery clock signal is adjusted by using a control word. Different control words FCW output by the digital clock calibration circuit are used to adjust the magnitude of the charging and discharging current, and further affect the charging and discharging speed of the capacitor to control the frequency change of the output clock.

[0088] As a specific embodiment, the current mirror circuit in the numerically controlled oscillator circuit includes a plurality of current mirror branches; each current mirror branch is composed of a PMOS transistor and an NMOS transistor; the base of the NMOS transistor is connected to the digital clock calibration circuit, and a control word with different control bits is output by the digital clock calibration circuit to control the on-off of the NMOS transistor in each current mirror branch, so as to adjust the charging and discharging current of the oscillator capacitor. The current mirror circuit in the embodiment of the present invention includes 12 branches, and further increasing the number of branches of the current mirror can improve the resolution of the output recovery clock signal frequency. The specific number of current mirror branches is not limited in the embodiment of the present invention. In the embodiment of the present invention, the base of the NMOS transistor in each current mirror branch is connected to the control terminal ENI of the digital clock calibration circuit <x>, by controlling the ENI <x>The high and low levels are used to control the conduction and closing of the NMOS switches in each current mirror branch, thereby controlling the charging current I of the capacitor at node A. osc , changing the speed at which the voltage of the positive plate of the capacitor reaches the preset value, that is, changing the time t, and then changing the frequency of the output square wave. The formula is as follows:

[0089]

[0090] In the formula, t represents time, Iref is the reference current, i represents the branch number, Vc(t) represents the voltage from the capacitor at node A to the signal ground, W1 / L1 represents the aspect ratio of the PMOS transistor corresponding to the reference current, W2 / L2 represents the aspect ratio of the PMOS transistor MP1 corresponding to current mirror branch 1, and the branch current of current mirror branch 1 is k times Iref, where k = (W2 / L2) / (W1 / L1). The aspect ratio of the PMOS transistor MP2 in current mirror branch 2 is twice that of MP1, and the branch current is 2k times Iref. The same applies to MP3 - MP12 subsequently, and the corresponding current mirror branch currents are twice that of the previous one. ENI<0> to ENI<11> take "1" (high level) or "0" (low level).

[0091] In the embodiment of the present invention, as the control word number increases, the current magnitude controlled by the corresponding current mirror branch increases exponentially, realizing higher-precision control of the capacitor charge and discharge current.

[0092] In the comparator circuit, the inputs of the positive and negative terminals of the comparator are the reference voltage Vref and the voltage (Vch) of the capacitor at node A respectively. Initially, Vch is 0, and the output of the comparator is the power supply voltage. Since the current mirror current charges the capacitor at node A, when Vch continuously rises until Vch is greater than the reference voltage Vref by a certain value, that is, reaching the precision of the comparator, the output voltage VOUT is ground. By transmitting signals through the loop, the NMOS switch OUT_B is controlled to conduct, and the branch discharges current. At this time, Vch drops to 0 again, and the output returns to the power supply voltage. During this process, a square wave with a corresponding frequency is formed by charging and discharging the capacitor.

[0093] Since the duty cycle of the square wave is not an ideal 50%, and the non-ideal duty cycle will affect the calibration accuracy of the digital calibration circuit. Therefore, the clock signal output by the comparator will also pass through a frequency division circuit. The circuit structure of the frequency division circuit is a D flip-flop, and the square wave signal is frequency-reduced by the D flip-flop to obtain a restored clock signal with an ideal 50% duty cycle.

[0094] As Figure 5 shown, the digital clock calibration circuit in the embodiment of the present invention includes:

[0095] A first counter, which is used to count the number of cycles of the carrier signal;

[0096] A second counter for counting the number of periods of the recovered clock signal output by the numerically controlled oscillator circuit;

[0097] A judgment module for judging the quantitative relationship between the number of periods counted by the first counter and the second counter to generate a fast / slow judgment signal;

[0098] A calibration module for adjusting the control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to achieve calibration of the recovered clock signal.

[0099] In the embodiment of the present invention, the digital clock calibration circuit calibrates the recovered clock signal using the binary search method, calibrating bit by bit from the high bit to the low bit. By comparing the relationship between the number of input clocks and the number of reference clocks within a certain time length, it is determined whether the clock frequency output by the numerically controlled oscillator corresponding to the current control word is fast or slow. Since the input clock and the reference clock are asynchronous clocks, the input clock needs to be synchronized into the reference clock for rising edge pulse acquisition. The number of rising edge pulses is used to replace the number of periods of the input clock passed, and the core counting work is completed in the reference clock domain.

[0100] In the embodiment of the present invention, the carrier clock is used as the reference clock, and the target frequency of the recovered clock signal is one-fourth of the carrier clock. Therefore, when the target frequency of the recovered clock signal is one-fourth of the carrier clock frequency, it is the ideal recovered clock signal frequency. In the embodiment of the present invention, counters are used to count the clock frequency, and the value of the corresponding second counter (counter2) should satisfy: counter1 = counter2 * 4 with respect to the first counter (counter1).

[0101] The quantitative relationship judgment performed by the judgment module is: whether the number of periods counted by the first counter is four times the number of periods counted by the second counter; the target frequency of the recovered clock signal is one-fourth of the carrier signal clock period;

[0102] When the number of periods counted by the first counter is greater than four times the number of periods counted by the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovered clock signal is lower than the target frequency.

[0103] When the number of periods counted by the first counter is less than four times the number of periods counted by the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency.

[0104] When the number of cycles counted by the first counter is equal to four times the number of cycles counted by the second counter, and the second counter has not reached its upper limit value, the judgment module determines that the current counting time is not sufficient to distinguish the frequency of the recovered clock signal, and does not output a fast / slow judgment signal. The two counters continue to work.

[0105] When the calibration module receives a slow judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 1.

[0106] When the calibration module receives a fast judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 0.

[0107] When the calibration module receives a calibration completion signal, it maintains the current control word set to 1, saves the control word setting currently output to the numerically controlled oscillator circuit, determines that the recovered clock signal has been calibrated, ends the calibration process in advance, and no longer calibrates subsequent control words.

[0108] The calibration process is as Figure 6 shown. At the start of calibration, the highest-bit control word is first calibrated. The input clock is synchronized within the reference clock domain to obtain a rising-edge pulse. After receiving the rising-edge pulse signal, the first counter and the second counter both start to enter the counting state. Whenever the count of the second counter increases, that is, when a rising-edge pulse is received, it indicates that another recovered clock signal input clk_dco has passed. At this time, the quantity relationship between the first counter and the second counter is judged. If the ideal quantity relationship between the reference clock frequency and the target clock frequency is satisfied, it means that the current elapsed counting time is not sufficient to identify the frequency difference between the input clock and the reference clock, and continue counting until it is judged that the quantity relationship is not satisfied. At this time, according to the magnitude of the quantity relationship, it is determined whether the current input clock, that is, the clock frequency of the recovered clock signal output by the DCO, is faster or slower than the target clock frequency. If it is too fast, the current control word is set to 0 and the calibration of the next control word is entered. If it is too slow, the current control word is kept set to 1 and the calibration of the next control word is entered. Repeat the above process until all control words are calibrated.

[0109] If the ideal quantity relationship is continuously satisfied for a long time and the second counter counts up to the maximum count value MAX, it means that the frequency difference between the input clock and the reference clock still cannot be distinguished within the set counting duration. The maximum count value MAX of the second counter is designed according to the required frequency accuracy. Therefore, in this case, it is considered that the DCO output frequency corresponding to the current control word is equal to the target required clock frequency, or the accuracy is within the set range. Keep the control word set to 1 and end the calibration process without calibrating other control words.

[0110] After calibration is completed, save the corresponding control word configuration and wait for the NFC tag to enter the message response process.

[0111] The DCO recovery clock circuit completes calibration before the tag sends the response message. During the calibration of the DCO recovery clock circuit, the carrier clock normally exists, so at this time the tag is in the normal receiving process. As Figure 2 shown, for a tag operating normally, after receiving an instruction, it will output corresponding information according to the instruction. The original code of the information output by the tag will first be passed to the encoding module, where Manchester encoding is completed. Then, a subcarrier signal is loaded, and finally the subcarrier signal is output to the analog load modulation circuit. The load modulation circuit selects to connect or disconnect the resistor in the circuit according to the 0 and 1 of the signal to achieve amplitude modulation.

[0112] In ASK100% modulation, the carrier circuit is selected or disconnected to achieve an antenna output waveform with a 100% amplitude difference between high and low signal levels. When the load modulation signal is at a low level, the carrier is turned off. At this time, the clock source of the DCO will take over the carrier clock to continue to maintain the normal operation of the digital circuit until the load modulation signal is at a high level and then the load modulation signal is normally output. This cycle is repeated to complete the transmission of a complete response message. Wait for the tag to complete the transmission of all response messages and enter the information reception process, then switch the clock source to the original carrier clock. When waiting for the next transmission, switch to the output clock of the DCO as the clock source to maintain the normal operation of the tag.

[0113] In the embodiment of the present invention, the clock frequency of the carrier signal applied is 13.56 MHz, the target frequency of the recovery clock signal is 3.39 MHz; the clock frequency of the subcarrier modulation signal is 848 kHz.

[0114] Figure 7 、 8 are the AMS simulation results of the communication between the tag chip with ASK100% modulation designed based on this solution and the reader. It can be seen that the antenna carrier has a carrier amplitude of 0 at the low signal level of the subcarrier modulation signal, achieving the transmission of ASK100% modulation. Below are the tag encoding signal and the reader shaping output. Except for the phase difference caused by propagation, the signal waveforms are exactly the same, that is, the encoding signal output after the reader demodulation and shaping is the same as the signal sent by the tag, and the reception is successful and the communication is correct.

[0115] The present invention provides a stable clock source for the tag during the loss of the ASK100% modulation clock by introducing a high-precision DCO clock recovery circuit, ensuring the normal operation of the digital circuit and enabling passive NFC to communicate with the reader using ASK100% for load modulation. The extreme amplitude difference not only helps improve the anti-interference ability of the NFC tag and optimize the situation where signal attenuation in long-distance communication causes the receiving end to fail to recognize, but also greatly reduces the demodulation difficulty at the receiving end and simplifies the design of the ASK demodulation circuit.

[0116] The second embodiment of the present invention discloses an ASK100% modulation communication method applied to a passive NFC tag, including a signal reception process and a signal transmission process;

[0117] Among them, the signal reception process specifically includes:

[0118] Use a clock extraction circuit to extract the carrier clock from the carrier signal, and use the carrier clock to maintain the working timing of the NFC tag during signal reception;

[0119] Use an ASK demodulation circuit to obtain the binary coded signal from the reader transmitted by the RF field;

[0120] Use a decoding module to decode the binary coded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0121] Use a response control module to generate a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module;

[0122] The signal transmission process specifically includes:

[0123] Use a numerically controlled oscillator circuit to generate a recovery clock signal, and use the recovery clock signal to maintain the working timing of the NFC tag during signal transmission;

[0124] Use a digital clock calibration circuit to calibrate the recovery clock signal;

[0125] Use an encoding module to encode the binary original code signal to generate a baseband signal;

[0126] Use a subcarrier modulation module to perform subcarrier modulation on the baseband signal to generate a subcarrier modulation signal;

[0127] Use a load modulation circuit to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulation signal to generate a response signal and send it to the reader.

[0128] Specifically, in some embodiments, the recovery clock signal is generated through the following steps:

[0129] The current mirror circuit is used to control the on / off of the NMOS transistors in each current mirror branch according to the control word of different control bits output by the digital clock calibration circuit, so as to adjust the charging and discharging current of the oscillator capacitor.

[0130] The comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal.

[0131] The frequency division circuit is used to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovered clock signal with a 1 / 2 duty cycle.

[0132] In some embodiments, the recovered clock signal is calibrated through the following steps:

[0133] The first counter is used to count the number of cycles of the carrier signal.

[0134] The second counter is used to count the number of cycles of the recovered clock signal output by the numerically controlled oscillator circuit.

[0135] The judgment module is used to judge the quantitative relationship between the number of cycles counted by the first counter and the second counter to generate a fast / slow judgment signal.

[0136] The calibration module is used to adjust the control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to realize the calibration of the recovered clock signal.

[0137] The content of the system in the first embodiment of the present invention is applicable to the method embodiment of the present invention. The functions specifically implemented by the method embodiment are the same as those of the above system embodiment, and the beneficial effects achieved are also the same as those of the above system.

[0138] It should be noted that the user information (including but not limited to user system information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties. The collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0139] Those skilled in the art can understand that the modules in the system in the embodiments of the present invention can be adaptively changed and set in one or more systems different from this embodiment. The modules or units or components in the embodiments of the present invention can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the corresponding claims, abstract and drawings) and all the processes or units of any method or system so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the corresponding claims, abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0140] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0141] In addition, each embodiment in this specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other. In particular, for embodiments such as devices and systems, since they are basically similar to the method embodiments, the relevant parts can refer to the partial description of the method embodiments. The device, system and other embodiments described above are only illustrative. The modules, units, etc. described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed to multiple places, such as the nodes of a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above embodiment solutions. Those skilled in the art can understand and implement without creative work.

[0142] It should be understood that each part of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following well-known technologies in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0143] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0144] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated in this embodiment. Thus, the features defined with terms such as "first", "second", etc. in the embodiments of the present invention may explicitly or implicitly indicate that at least one such feature is included in this embodiment. In the description of the present invention, the meaning of the word "plural" is at least two or more than two, such as two, three, four, etc., unless otherwise specifically defined in the embodiment.

[0145] In the embodiments of the present invention, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or may have different meanings, and their specific meanings need to be determined according to their explanations in the specific embodiment or further in combination with the context of the specific embodiment.

[0146] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. After considering the specification and practicing the present invention, those skilled in the art will readily think of other embodiments of the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.< / x> < / x>

Claims

1. An ASK 100% modulation communication system applied to passive NFC tags, characterized in that, Comprising: A clock extraction circuit for extracting a carrier clock from a carrier signal and using the carrier clock to maintain the working timing of the NFC tag when receiving a signal; An ASK demodulation circuit for obtaining a binary coded signal from the reader transmitted by the radio frequency field; A decoding module for decoding the binary coded signal transmitted by the ASK demodulation circuit to obtain instruction data; A response control module for generating a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module; A numerically controlled oscillator circuit for generating a recovered clock signal and using the recovered clock signal to maintain the working timing of the NFC tag when sending a signal; A digital clock calibration circuit for calibrating the recovered clock signal; An encoding module for encoding the binary original code signal to generate a baseband signal; A subcarrier modulation module for performing subcarrier modulation on the baseband signal to generate a subcarrier modulation signal; A load modulation circuit for modulating the amplitude of the carrier signal by 100% according to the subcarrier modulation signal to generate a response signal and send it to the reader.

2. The ASK 100% modulation communication system applied to the passive NFC tag according to claim 1, wherein, The numerically controlled oscillator circuit includes: A current mirror circuit for adjusting the charging and discharging current of the oscillator capacitor to control the voltage change speed of the oscillator capacitor, thereby adjusting the frequency of the recovered clock signal; A comparator circuit for comparing the difference between the voltage of the oscillator capacitor and a reference voltage and controlling the charging or discharging of the oscillator capacitor to form a square wave signal; A frequency division by two circuit for reducing the frequency of the square wave signal output by the comparator circuit to obtain a recovered clock signal with a duty cycle of 1 / 2.

3. The ASK 100% modulation communication system applied to a passive NFC tag according to claim 2, wherein The current mirror circuit includes a plurality of current mirror branches; each current mirror branch is composed of a PMOS transistor and an NMOS transistor; the base of the NMOS transistor is connected to the digital clock calibration circuit, and a control word with different control bits is output through the digital clock calibration circuit to control the on and off of the NMOS transistor in each current mirror branch, so as to adjust the charging and discharging current of the oscillator capacitor.

4. A 100% ASK modulation communication method applied to a passive NFC tag according to claim 1, characterized in that, The digital clock calibration circuit includes: A first counter for counting the number of periods of the carrier clock signal; a second counter for counting the number of periods of the recovered clock signal output by the numerically controlled oscillator circuit; A judgment module for judging the quantitative relationship between the number of periods counted by the first counter and the second counter to generate a fast / slow judgment signal; A calibration module for adjusting the control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to realize the calibration of the recovered clock signal.

5. The ASK 100% modulation communication system applied to a passive NFC tag according to claim 4, characterized in that, The second counter has a counting upper limit; when the second counter reaches the counting upper limit, the control word setting currently output to the numerically controlled oscillator circuit is saved, and it is judged that the recovered clock signal is calibrated.

6. The ASK 100% modulation communication system applied to a passive NFC tag according to claim 4, characterized in that, The quantitative relationship judgment performed by the judgment module is: whether the number of counted cycles of the first counter is four times that of the second counter; the target frequency of the recovered clock signal is the quarter frequency division of the carrier clock signal period. When the number of counted cycles of the first counter is greater than four times that of the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovered clock signal is lower than the target frequency. When the number of counted cycles of the first counter is less than four times that of the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency. When the number of counted cycles of the first counter is equal to four times that of the second counter and the second counter has not reached the upper limit value, the judgment module determines that the current counting time is not sufficient to distinguish the frequency speed of the recovered clock signal, does not output a fast or slow judgment signal, and the two counters continue to work.

7. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 6, characterized in that, When the calibration module receives the slow judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 1. When the calibration module receives the fast judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 0. When the calibration module receives the calibration completion signal, it maintains the current control word set to 1, saves the current control word setting output to the numerically controlled oscillator circuit, determines that the recovered clock signal is calibrated, ends the calibration process in advance, and the subsequent control words are no longer calibrated.

8. An ASK 100% modulation communication method applied to a passive NFC tag, which is applied to an ASK 100% modulation communication system for a passive NFC tag according to any one of claims 1-8, characterized in that, It includes a signal reception process and a signal transmission process. Among them, the signal reception process specifically includes: Using a clock extraction circuit to extract the carrier clock from the carrier signal, and using the carrier clock to maintain the working timing of the NFC tag during signal reception. Using an ASK demodulation circuit to obtain the binary coded signal transmitted from the reader in the radio frequency field. Using a decoding module to decode the binary coded signal transmitted by the ASK demodulation circuit to obtain command data. Using a response control module to generate a binary original code signal for responding to the reader according to the command data obtained by the decoding module. The signal transmission process specifically includes: Using a numerically controlled oscillator circuit to generate a recovered clock signal, and using the recovered clock signal to maintain the working timing of the NFC tag during signal transmission. Using a digital clock calibration circuit to calibrate the recovered clock signal. Using an encoding module to encode the binary original code signal to generate a baseband signal. Using a subcarrier modulation module to perform subcarrier modulation on the baseband signal to generate a subcarrier modulated signal. Using a load modulation circuit to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulated signal, and generate a response signal to be sent to the reader.

9. The ASK 100% modulation communication method applied to a passive NFC tag according to claim 8, wherein The recovered clock signal is generated through the following steps: Using a current mirror circuit to control the on / off of the NMOS transistors in each current mirror branch according to the control word with different control bits output by the digital clock calibration circuit, so as to adjust the charge and discharge current of the oscillator capacitor. Use a comparator circuit to compare the voltage difference between the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal; Use a frequency divider circuit to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovered clock signal with a 50% duty cycle.

10. A 100% ASK modulation communication method applied to a passive NFC tag according to claim 9, characterized in that, The recovered clock signal is calibrated through the following steps: Use a first counter to count the number of cycles of the carrier signal; Use a second counter to count the number of cycles of the recovered clock signal output by the numerically controlled oscillator circuit; Use a judgment module to judge the quantitative relationship between the number of cycles counted by the first counter and the second counter to generate a fast / slow judgment signal; Use a calibration module to adjust the control word output to the numerically controlled oscillator circuit according to the fast / slow judgment signal to achieve calibration of the recovered clock signal.

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