Hierarchical TCAM message analysis and field extraction system based on analysis graph optimization

Abstract

The invention discloses a hierarchical TCAM (Ternary Content Addressable Memory) message parsing and field extraction system based on parsing graph optimization, which relates to the technical field of communication, and comprises a software calculation configuration module used for carrying out graph topology optimization on a protocol parsing graph to generate a plurality of mutually independent parsing sub-graphs; and according to the key bit set corresponding to each analysis sub-graph, generating a hardware resource configuration table corresponding to each analysis sub-graph, and distributing the hardware resource configuration table to a key bit extraction unit, a mapping table matching unit, a flow classification module and a field extraction module on a hardware side, thereby configuring a logic structure of a target circuit according to hardware configuration information. And dynamic reconstruction of a protocol analysis function is realized. According to the method, the protocol analysis diagram is decomposed into the analysis sub-diagrams, the multi-level unit fusion architecture is adopted in the hardware level, streamlined protocol analysis is achieved, the TCAM storage requirement can be remarkably reduced in combination with the key bit matrix compression technology, and the time sequence and storage bottleneck during large-scale message header analysis is effectively solved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a hierarchical TCAM message parsing and field extraction system optimized based on a parsing graph. Background Art

[0002] With the rapid development of 5G communication, Internet of Things, and cloud computing technologies, network data traffic shows the dual characteristics of explosive growth and highly heterogeneous protocol types. The multi-modal fusion network is gradually becoming the trend of future network architectures. Multi-modal fusion networks (such as industrial Internet, computing power network) require underlying devices to have the capabilities of flexibly parsing new protocols, high-speed data processing, and programmability. In this context, programmable switches, as the core components of the network data plane, undertake important tasks of traffic parsing, forwarding, and processing.

[0003] Traditional network devices usually rely on fixed hardware logic for message parsing and field extraction. Although this method can provide high throughput, it lacks flexibility and is difficult to adapt to the introduction and change of new protocols.

[0004] The programmable data plane technology based on the P4 (Programming Protocol-independent Packet Processors) language has become the core direction to solve this challenge. Among them, the programmable parser, as the first-level processing unit of the switch, directly determines the overall processing capacity of the machine. However, the existing programmable parsers still face the following technical bottlenecks:

[0005] (1) The contradiction between the explosion of parsing path combinations and TCAM (Ternary Content Addressable Memory) resources. The current programmable parser uses TCAM to store protocol path rules. However, as the protocol complexity increases, such as tunnel nesting, custom headers, etc., the number of parsing graph paths grows exponentially. The existing programmable parsers achieve protocol compatibility through full-path storage, which will cause a waste of a considerable amount of TCAM resources and seriously restrict the large-scale deployment of multi-modal networks.

[0006] (2) In the scenario of parsing a 2048-bit ultra-long message header, the existing field extraction methods use a layer-by-layer parsing method, and the parsing depth deepens as the protocol complexity increases, resulting in pipeline stalls and increased storage resource overhead, affecting the overall parsing performance. In addition, most existing programmable parsers use a fixed field offset matching method, which is difficult to handle dynamically changing message formats, such as variable-length fields, protocol optional headers, etc., reducing the flexibility and adaptability of the system.

[0007] (3) In a high-speed network environment, the programmable parser needs to complete field extraction and protocol matching within a limited number of clock cycles. However, existing programmable parsers often require additional parallel parsing units to ensure high throughput, resulting in a sharp increase in hardware resource consumption, power consumption, and affecting the scalability of FPGAs or ASICs. In addition, updating the parsing rules requires additional computing resources, further exacerbating the contradiction between throughput and hardware utilization.

[0008] (4) When existing programmable parsers process complex packets with multiple protocols coexisting, they usually rely on serial parsing methods, that is, matching and extracting fields layer by layer according to the protocol hierarchy. This method is prone to increased parsing latency when facing high-concurrency traffic and is difficult to fully utilize the parallel computing power of the hardware. Although those skilled in the art have tried to introduce multi-stage pipelines or multiple parsing units, there are still parsing path dependency problems, resulting in limited parsing throughput capacity and difficulty in meeting the low-latency requirements in ultra-high-speed network environments. Summary of the Invention

[0009] In order to solve the above problems existing in the prior art, the present invention provides a hierarchical TCAM packet parsing and field extraction system based on parsing graph optimization. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0010] The present invention provides a hierarchical TCAM packet parsing and field extraction system based on parsing graph optimization, including:

[0011] A software calculation and configuration module, which is used to perform graph topology optimization on the protocol parsing graph to generate a plurality of independent parsing sub-graphs; according to the key bit set corresponding to each parsing sub-graph, generate a hardware resource configuration table corresponding to each parsing sub-graph, and distribute the hardware resource configuration table to a multi-level extraction and mapping module, a flow classification module, and a field extraction module;

[0012] A multi-level extraction and mapping module corresponding to a plurality of parsing sub-graphs respectively; the key bit extraction unit in each level of extraction and mapping module is used to obtain a byte data block containing the key bits of the parsing sub-graph according to the hardware resource configuration table, separate the key bits therefrom, and aggregate the key bits of all parsing sub-graphs by using a first programmable cross-switch, and output the formed key bit set to the mapping table matching unit in this level of extraction and mapping module;

[0013] The mapping table matching unit in each level of extraction and mapping module is used to use the key bit set as an index address to identify the protocol parsing paths corresponding to each parsing sub-graph based on the index address;

[0014] The flow classification module is used to integrate the protocol parsing paths corresponding to all parsing subgraphs, generate a complete protocol parsing path topology, use the set of key bits of all parsing subgraphs as a combined index to input into the TCAM action table, and determine the specific fields to be extracted from the current data packet from the external physical access port in combination with the complete protocol parsing path topology;

[0015] The field extraction module is used to locate the physical offset and length of the specific field from the current data packet according to the field extraction instruction, and route the specific field to the specified storage area of the PHV through the second programmable crossbar switch.

[0016] In an embodiment of the present invention, the software calculation configuration module includes a parsing graph optimization unit and a key bit selection unit;

[0017] The parsing graph optimization unit is used to perform graph topology optimization on the protocol parsing graph constructed based on the P4 code by using the multi-subgraph partitioning algorithm to generate multiple independent parsing subgraphs;

[0018] The key bit selection unit is used to locate the corresponding set of key bits according to the structural characteristics of each parsing subgraph, and generate a hardware resource configuration table corresponding to each parsing subgraph according to the physical positions of each key bit in the set of key bits and the semantic attributes of the nodes in the parsing subgraph corresponding to each key bit; distribute the hardware resource configuration table to the key bit extraction unit, the mapping table matching unit, the flow classification module, and the field extraction module through the software and hardware interface.

[0019] In an embodiment of the present invention, the parsing graph optimization unit is specifically used to perform graph topology optimization on the protocol parsing graph constructed based on the P4 code by using the multi-subgraph partitioning algorithm to obtain multiple independent parsing subgraphs, traverse all paths in each parsing subgraph, and generate a bit string encoding corresponding to each path according to a preset rule;

[0020] The key bit selection unit is specifically used to retain the original value of the core flag bit indicating the protocol layer inheritance relationship in the bit string encoding, replace the remaining non-key bits with the wildcard X to generate an original bit string; make the lengths of the original bit strings consistent by filling the wildcard X to form a first-level bit string matrix; sequentially remove the all-identical columns, fuzzy columns, and duplicate columns in the first-level bit string matrix to generate a compressed second-level bit string matrix; quantify the information contribution degree of each bit in the original bit string to path discrimination based on the information entropy evaluation algorithm; based on the greedy iterative strategy, remove the low-discrimination bit positions with an information contribution degree lower than the first preset threshold from the second-level bit string until the remaining bit positions can uniquely identify all paths or reach the theoretical minimum number of bits to obtain the set of key bits of the parsing subgraph.

[0021] In one embodiment of the present invention, the parsing graph optimization unit generates a plurality of independent parsing subgraphs according to the following steps:

[0022] Calculate the in-degree, out-degree and total degree of each vertex in the protocol parsing graph, and determine the maximum-degree vertex with the highest connection density in the protocol parsing graph;

[0023] Generate a topologically equivalent copy node for the maximum-degree vertex and assign edge attributes, and perform edge separation operations on the maximum-degree vertex and the copy node based on the semantic attributes, separating the in-edges and out-edges of the maximum-degree vertex and the copy node to obtain a plurality of parsing subgraphs;

[0024] Update the vertex degrees, vertex sets and edge sets in each parsing subgraph, and verify the segmentation status of the parsing subgraph through a connectivity detection algorithm; if there are no shared edges between the parsing subgraphs and the vertex scale of each parsing subgraph meets the second preset threshold, it is determined as an effective segmentation; otherwise, use a community detection algorithm to further segment the parsing subgraphs that are not effectively segmented.

[0025] In one embodiment of the present invention, the key bit extraction unit in each level extraction mapping module is specifically configured to obtain a byte data block containing the key bits in byte-level coarse-grained manner according to the physical positions of the key bits of the parsing subgraphs in the received hardware resource configuration table, and further separate the key bits from the byte data block in bit-level fine-grained manner, and aggregate the key bits of all parsing subgraphs by using a first programmable crossbar, and output the formed key bit set to the mapping table matching unit in this level extraction mapping module.

[0026] In one embodiment of the present invention, the key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit;

[0027] The byte address extraction subunit is used to strip the low 3-bit addresses of each key bit based on the shift register parameters provided by the hardware resource configuration table, generate a byte-aligned physical address, and extract the byte data block containing the key bits according to the physical address;

[0028] The bit address extraction subunit is used to perform bit-plane decomposition operations on the byte data block, grab the key bits specified by the mask from the byte data block through a combination logic of a bit mask and a shifter; aggregate the key bits of all parsing subgraphs by using a first programmable crossbar, and output the formed key bit set to the mapping table matching unit in this level extraction mapping module.

[0029] In one embodiment of the present invention, the key bit extraction unit further includes an arbiter;

[0030] The arbiter is used to sort and schedule conflicting key bits based on the TCAM rule priority field when the key bits of multiple parsing sub - graphs are located in the same byte data block.

[0031] In an embodiment of the present invention, the mapping table matching unit in each - level extraction and mapping module includes a heterogeneous TCAM storage block, and paths in the parsing sub - graph corresponding to this - level extraction and mapping module are stored in the heterogeneous TCAM storage block;

[0032] The mapping table matching unit is specifically configured to use the set of key bits as an index address and input it into the heterogeneous TCAM storage block for matching to obtain the protocol parsing path corresponding to the parsing sub - graph.

[0033] In an embodiment of the present invention, the flow classification module includes a matching unit and a TCAM unit;

[0034] The matching unit is used to aggregate the protocol parsing paths corresponding to each parsing sub - graph according to the preset weights of the protocol levels to generate a complete protocol parsing path topology; input the combined index into the heterogeneous TCAM storage block, match it with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and obtain the information related to the specific field of the path corresponding to the unique path identifier in the current data packet through the RAM address mapping table;

[0035] The TCAM unit is used to predict the next - hop path according to the information related to the specific field and pre - load the extraction instruction of the unique path identifier.

[0036] In an embodiment of the present invention, the flow classification module further includes a RAM unit, and the RAM unit stores the field extraction instructions corresponding to all paths in each parsing sub - graph;

[0037] The field extraction module includes: a field extraction engine and a structured metadata output unit;

[0038] The field extraction engine is used to locate the physical offset and length of the specific field from the current data packet according to the field extraction instruction and extract the specific field;

[0039] The structured metadata output unit is used to generate a protocol - independent standardized metadata structure according to the specific field and route the standardized metadata structure to the specified storage area of the PHV in the PHV format through the second programmable cross - switch.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] The present invention provides a hierarchical TCAM packet parsing system optimized based on parsing graph. Structurally, it can be divided into a software side, a hardware side, a software-hardware interface, and an external physical access port. Among them, the software side includes a software computing configuration module, which is used to optimize the graph topology of the protocol parsing graph, generate multiple independent parsing sub-graphs, generate a hardware resource configuration table corresponding to each parsing sub-graph according to the key bit set corresponding to each parsing sub-graph, and distribute the hardware resource configuration table to the key bit extraction unit, mapping table matching unit, flow classification module, and field extraction module on the hardware side. In this way, the protocol independence of the hardware side is achieved, which is used to ensure the recognition and parsing of heterogeneous packets in the data center or the new generation of multi-modal networks. At the same time, the software computing configuration module abstracts the protocol parsing logic of any scenario into a programmable data plane description model through the P4 language, and realizes the deep decoupling of software and hardware based on compiler hierarchical mapping and hardware resource virtualization.

[0042] In addition, the key bit extraction unit and the mapping table matching unit achieve a cross-connection ability similar to Crossbar through a multi-level hierarchical extraction strategy and a bit dynamic mapping table. The flow classification module reconstructs the traditional tree-like / chain flow table structure into a flattened classification model through multi-dimensional key bit joint retrieval and rule space plane mapping.

[0043] In summary, the present invention decomposes the complex protocol parsing graph into parsing sub-graphs through a graph partitioning algorithm, adopts a multi-level unit fusion architecture at the hardware level to achieve pipelined protocol parsing, and combines the key bit matrix compression technology to significantly reduce the TCAM storage requirements, effectively solving the timing and storage bottlenecks in large-scale packet header parsing.

[0044] The following will further describe the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0045] Figure 1 is a schematic structural diagram of a hierarchical TCAM packet parsing and field extraction system optimized based on parsing graph provided by an embodiment of the present invention;

[0046] Figure 2 is a protocol parsing graph provided by an embodiment of the present invention;

[0047] Figure 3 is for Figure 2 the parsing sub-graph obtained after graph topology optimization of the shown protocol parsing graph;

[0048] Figure 4 is an example diagram of a partial 1-level bit string matrix provided by an embodiment of the present invention;

[0049] Figure 5 is an example diagram of a 2-level bit string matrix provided by an embodiment of the present invention;

[0050] Figure 6 It is an example diagram of the key bit set for parsing sub - graphs provided by an embodiment of the present invention. Detailed implementation manners

[0051] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0052] Figure 1 It is a schematic structural diagram of a hierarchical TCAM packet parsing and field extraction system optimized based on a parsing graph provided by an embodiment of the present invention. As Figure 1 shown, an embodiment of the present invention provides a hierarchical TCAM packet parsing and field extraction system optimized based on a parsing graph. Structurally, the system can be divided into a software side, a hardware side, a software - hardware interface, and an external physical access port. The software side is used to generate hardware configuration information. The software - hardware interface transmits the hardware configuration information to the hardware side. The hardware side configures the logical structure of the target circuit according to the hardware configuration information to achieve dynamic reconstruction of the protocol parsing function.

[0053] Optionally, the software side includes a software calculation configuration module, and the hardware side includes a multi - level extraction mapping module, a flow classification module, and a field extraction module.

[0054] In this embodiment, the software calculation configuration module is used to perform graph topology optimization on the protocol parsing graph to generate multiple independent parsing sub - graphs; according to the key bit set corresponding to each parsing sub - graph, generate a hardware resource configuration table corresponding to each parsing sub - graph, and distribute the hardware resource configuration table to the multi - level extraction mapping module, the flow classification module, and the field extraction module.

[0055] Figure 2 It is a protocol parsing graph provided by an embodiment of the present invention. Please refer to Figure 2 , it should be noted that the protocol parsing graph is a directed acyclic graph, and each vertex is uniquely mapped to a network protocol type, such as Figure 2For the Ethernet, VLAN (Virtual Local Area Network), IPv4 (Internet Protocol version 4), TCP (Transmission Control Protocol), UDP (User Datagram Protocol), and ICMP (Internet Control Message Protocol) shown, the inheritance relationships between the protocols are represented by connecting lines. Repeated protocols can be distinguished by numeric suffixes. For VLAN1 and VLAN2, a directed connection from the source node to the destination node is established if and only if the source node protocol header contains a specific field that can point to the destination node protocol type, and circular dependencies are not allowed.

[0056] The multi-level extraction and mapping module corresponds to multiple parsing sub-graphs respectively; the key bit extraction unit in each level of the extraction and mapping module is used to obtain the byte data block containing the key bits of the parsing sub-graph according to the hardware resource configuration table, separate the key bits from it, and aggregate the key bits of all parsing sub-graphs using the first programmable crossbar, and output the formed key bit set to the mapping table matching unit in this level of the extraction and mapping module.

[0057] The mapping table matching unit in each level of the extraction and mapping module is used to use the key bit set as the index address and identify the protocol parsing paths corresponding to each parsing sub-graph based on the index address.

[0058] The flow classification module is used to integrate the protocol parsing paths corresponding to all parsing sub-graphs, generate a complete protocol parsing path topology, input the key bit sets of all parsing sub-graphs as a combined index into the TCAM action table, and determine the specific fields to be extracted from the current data packet from the external physical access port in combination with the complete protocol parsing path topology.

[0059] The field extraction module is used to locate the physical offset and length of the specific field from the current data packet according to the field extraction instruction, and route the specific field to the specified storage area of the PHV through the second programmable crossbar.

[0060] PHV (Packet Header Vector) is the core data structure in the network programmable data plane, which is used to uniformly carry the field information and processing metadata extracted from the packet header in the packet processing pipeline. When the current data packet enters the processing pipeline, the parser parses the packet header layer by layer according to the protocol specifications and stores the key fields of each layer in a structured manner into the PHV to form a complete context description vector.

[0061] In this embodiment, the software calculation configuration module includes a parsing graph optimization unit and a key bit selection unit;

[0062] The parsing graph optimization unit is used to perform graph topology optimization on the protocol parsing graph constructed based on P4 code by using a multi-subgraph partitioning algorithm, and generate a plurality of mutually independent parsing subgraphs;

[0063] The key bit selection unit is used to locate the corresponding key bit set according to the structural characteristics of each parsing subgraph, and generate a hardware resource configuration table corresponding to each parsing subgraph according to the physical position of each key bit in the key bit set and the semantic attributes of the nodes in the parsing subgraph corresponding to each key bit; and distribute the hardware resource configuration table to the key bit extraction unit, the mapping table matching unit, the flow classification module and the field extraction module through a software-hardware interface.

[0064] Furthermore, the parsing graph optimization unit is specifically used to perform graph topology optimization on the protocol parsing graph constructed based on P4 code by using a multi-subgraph partitioning algorithm, obtain a plurality of mutually independent parsing subgraphs, traverse all paths in each parsing subgraph, and generate a bit string encoding corresponding to each path according to a preset rule. It should be understood that P4 (Programming Protocol-independent Packet Processors) is a high-level programming language used to define the behavior of the network data plane. Its core goal is to implement protocol-independent packet processing logic programming. By abstracting the underlying hardware details, P4 enables devices such as switching chips, FPGAs or intelligent network cards to implement an efficient and reconfigurable packet processing pipeline through software programming.

[0065] Exemplarily, the parsing graph optimization unit generates a plurality of mutually independent parsing subgraphs according to the following steps:

[0066] S1. Calculate the in-degree, out-degree and total degree of each vertex in the protocol parsing graph, and determine the maximum-degree vertex with the highest connection density in the protocol parsing graph.

[0067] Here, "degree" refers to the number of edges directly connected to a node, "out-degree" refers to the number of edges extending outwards from a node, and "in-degree" refers to the number of edges connected to a node from the outside.

[0068] S2. Generate a topologically equivalent copy node for the maximum-degree vertex and assign edge attributes, and perform an edge separation operation on the maximum-degree vertex and the copy node based on semantic attributes to separate the in-edges and out-edges of the maximum-degree vertex and the copy node, and obtain a plurality of parsing subgraphs.

[0069] S3. Update the vertex degrees, vertex sets, and edge sets in each parsed subgraph, and verify the segmentation status of the parsed subgraph through a connectivity detection algorithm; if there are no shared edges between the parsed subgraphs and the vertex scales of the parsed subgraphs meet the second preset threshold, it is determined as an effective segmentation; otherwise, use a community detection algorithm to further segment the parsed subgraphs that have not been effectively segmented.

[0070] Figure 3 is the Figure 2 parsed subgraph obtained after graph topology optimization of the protocol parsing graph shown. Please combine with Figures 2 - 3 , it can be seen that Figure 2 the protocol parsing graph shown includes a total of 3×3 = 9 paths, and this protocol parsing graph is divided into Figure 3 two parsed subgraphs shown, and the number of paths is reduced from 9 to 3 + 3 = 6.

[0071] Figure 4 is an example graph of a partial 1-level bit string matrix provided by an embodiment of the present invention, Figure 5 is an example graph of a 2-level bit string matrix provided by an embodiment of the present invention, Figure 6 is an example graph of the key bit set of the parsed subgraph provided by an embodiment of the present invention. In this embodiment, the key bit selection unit is specifically configured to retain the original values of the core flag bits indicating the protocol layer inheritance relationship in the bit string encoding, replace the remaining non-key bits with wildcards X, and generate an original bit string as shown in Figure 4 ; then, as shown in Figure 5 , by filling the wildcards X, make the lengths of the original bit strings consistent to form a 1-level bit string matrix; further, sequentially remove the all-identical columns, fuzzy columns, and duplicate columns in the 1-level bit string matrix to generate a compressed 2-level bit string matrix; based on the information entropy evaluation algorithm, quantify the information contribution degree of each bit position in the original bit string to path discrimination; based on the greedy iteration strategy, remove the low-discrimination bit positions with information contribution degrees lower than the first preset threshold from the 2-level bit string until the remaining bit positions can uniquely identify all paths or reach the theoretical minimum number of bits, and obtain the Figure 6 key bit set of the parsed subgraph shown.

[0072] The key bit extraction unit in each level extraction mapping module is specifically configured to obtain the byte data block containing the key bits in byte-level coarse-grained manner according to the physical positions of the key bits of the parsed subgraph in the received hardware resource configuration table, further separate the key bits from the byte data block in bit-level fine-grained manner, and aggregate the key bits of all parsed subgraphs using the first programmable crossbar, and output the formed key bit set to the mapping table matching unit in this level extraction mapping module.

[0073] Optionally, the key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit;

[0074] The byte address extraction subunit is configured to strip the lower 3-bit addresses of each key bit based on the shift register parameters provided in the hardware resource configuration table, generate a byte-aligned physical address, and extract the byte data block containing the key bit according to the physical address;

[0075] The bit address extraction subunit is configured to perform a bit-plane decomposition operation on the byte data block, and grab the key bits specified by the mask from the byte data block through a combination logic of a bit mask and a shifter; aggregate the key bits of all parsing subgraphs by using a first programmable crossbar, and output the formed set of key bits to the mapping table matching unit in this-level extraction and mapping module.

[0076] In other embodiments of the present application, the key bit extraction unit further includes an arbiter;

[0077] The arbiter is configured to sort and schedule conflicting key bits based on the TCAM rule priority field when the key bits of multiple parsing subgraphs are located in the same byte data block.

[0078] The mapping table matching unit in each-level extraction and mapping module includes a heterogeneous TCAM storage block, and the paths in the parsing subgraph corresponding to this-level extraction and mapping module are stored in the heterogeneous TCAM storage block;

[0079] Specifically, the mapping table matching unit is configured to use the set of key bits as an index address, input it into the heterogeneous TCAM storage block for matching, and obtain the protocol parsing path corresponding to the parsing subgraph.

[0080] Furthermore, the flow classification module includes a matching unit and a TCAM unit;

[0081] The matching unit is configured to aggregate the protocol parsing paths corresponding to each parsing subgraph according to the preset weights of the protocol levels, generate a complete protocol parsing path topology; input the combined index into the heterogeneous TCAM storage block, match it with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and obtain the information related to the specific field of the path corresponding to the unique path identifier in the current data packet through the RAM address mapping table;

[0082] The TCAM unit is configured to predict the next-hop path according to the information related to the specific field, and pre-load the extraction instruction of the unique path identifier.

[0083] The flow classification module further includes a RAM unit, and the RAM unit stores the field extraction instructions corresponding to all paths in each parsing subgraph;

[0084] The field extraction module includes: a field extraction engine and a structured metadata output unit;

[0085] The field extraction engine is used to locate the physical offset and length of a specific field from the current data packet according to the field extraction instruction, and extract the specific field;

[0086] The structured metadata output unit is used to generate a protocol-independent standardized metadata structure based on the specific field, and route the standardized metadata structure to the specified storage area of the PHV in the PHV format through the second programmable crossbar.

[0087] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0088] The present invention provides a hierarchical TCAM packet parsing system based on parsing graph optimization, which can be structurally divided into a software side, a hardware side, a software-hardware interface, and an external physical access port. Among them, the software side includes a software computing configuration module, which is used to optimize the graph topology of the protocol parsing graph, generate multiple independent parsing subgraphs, generate a hardware resource configuration table corresponding to each parsing subgraph according to the key bit set corresponding to each parsing subgraph, and distribute the hardware resource configuration table to the key bit extraction unit, mapping table matching unit, flow classification module, and field extraction module on the hardware side. In this way, the protocol independence of the hardware side is realized, which is used to ensure the recognition and parsing of heterogeneous packets in the data center or the new generation of multimodal networks. At the same time, the software computing configuration module abstracts the protocol parsing logic of any scenario into a programmable data plane description model through the P4 language, and realizes the deep decoupling of software and hardware based on compiler hierarchical mapping and hardware resource virtualization.

[0089] In addition, the key bit extraction unit and the mapping table matching unit achieve a cross-connection ability similar to that of a Crossbar through a multi-level hierarchical extraction strategy and a bit position dynamic mapping table. The flow classification module reconstructs the traditional tree-like / chain flow table structure into a flattened classification model through multi-dimensional key bit joint retrieval and rule space plane mapping.

[0090] In summary, the present invention decomposes the complex protocol parsing graph into parsing subgraphs through a graph partitioning algorithm, adopts a multi-level unit fusion architecture at the hardware level to realize pipelined protocol parsing, and combines the key bit matrix compression technology to significantly reduce the TCAM storage requirement, effectively solving the timing and storage bottlenecks in large-scale packet header parsing.

[0091] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

[0092] The descriptions with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0093] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited only to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A hierarchical TCAM packet parsing and field extraction system based on parse graph optimization, characterized in that Comprising: A software calculation configuration module, configured to perform graph topology optimization on a protocol parsing graph to generate a plurality of mutually independent parsing subgraphs; According to the key bit sets corresponding to each of the parsing subgraphs, generate a hardware resource configuration table corresponding to each of the parsing subgraphs, and distribute the hardware resource configuration table to a multi-level extraction mapping module, a flow classification module, and a field extraction module; A multi-level extraction mapping module corresponding to a plurality of parsing subgraphs respectively; a key bit extraction unit in each level of extraction mapping module is configured to obtain a byte data block containing the key bits of the parsing subgraph according to the hardware resource configuration table, separate the key bits therefrom, and aggregate the key bits of all parsing subgraphs by using a first programmable crossbar, and output the formed key bit set to a mapping table matching unit in this level of extraction mapping module; A mapping table matching unit in each level of extraction mapping module is configured to use the key bit set as an index address, and identify the protocol parsing paths corresponding to each parsing subgraph based on the index address; The flow classification module is configured to integrate the protocol parsing paths corresponding to all parsing subgraphs, generate a complete protocol parsing path topology, use the key bit sets of all parsing subgraphs as a combined index to input to a TCAM action table, and in combination with the complete protocol parsing path topology, determine specific fields to be extracted from a current data packet from an external physical access port; The field extraction module is configured to locate the physical offset and length of a specific field from the current data packet according to a field extraction instruction, and route the specific field to a specified storage area of a PHV through a second programmable crossbar.

2. The hierarchical TCAM packet parsing and field extraction system optimized based on the parsing diagram according to claim 1, wherein The software calculation configuration module includes a parsing graph optimization unit and a key bit selection unit; The parsing graph optimization unit is configured to perform graph topology optimization on a protocol parsing graph constructed based on P4 code by using a multi-subgraph partitioning algorithm to generate a plurality of mutually independent parsing subgraphs; The key bit selection unit is configured to locate the corresponding key bit sets according to the structural characteristics of each parsing subgraph, and generate a hardware resource configuration table corresponding to each parsing subgraph according to the physical positions of each key bit in the key bit set and the semantic attributes of the nodes in the parsing subgraph corresponding to each key bit; distribute the hardware resource configuration table to the key bit extraction unit, the mapping table matching unit, the flow classification module, and the field extraction module through a software and hardware interface.

3. The hierarchical TCAM message parsing and field extraction system based on parsing graph optimization according to claim 2, wherein The parsing graph optimization unit is specifically configured to perform graph topology optimization on a protocol parsing graph constructed based on P4 code by using a multi-subgraph partitioning algorithm to obtain a plurality of mutually independent parsing subgraphs, traverse all paths in each of the parsing subgraphs, and generate a bit string encoding corresponding to each path according to a preset rule; The key bit selection unit is specifically configured to retain the original values of the core flag bits indicating the protocol layer inheritance relationship in the bit string encoding, replace the remaining non-critical bits with wildcards X to generate an original bit string; make the lengths of the original bit strings consistent by filling with wildcards X to form a first-level bit string matrix; sequentially remove the all-identical columns, ambiguous columns, and duplicate columns in the first-level bit string matrix to generate a compressed second-level bit string matrix; quantify the information contribution degree of each bit in the original bit string to path differentiation based on the information entropy evaluation algorithm; and based on the greedy iteration strategy, remove the low-differentiation bit positions with information contribution degree lower than the first preset threshold from the second-level bit string until the remaining bit positions can uniquely identify all paths or reach the theoretical minimum number of bits, to obtain the key bit set of the parsing subgraph.

4. The hierarchical TCAM message parsing and field extraction system optimized based on the parsing diagram according to claim 3, characterized in that, The parsing graph optimization unit generates multiple independent parsing subgraphs according to the following steps: Calculate the in-degree, out-degree, and total degree of each vertex in the protocol parsing graph, and determine the maximum-degree vertex with the highest connection density in the protocol parsing graph; Generate a topologically equivalent copy node for the maximum-degree vertex and assign edge attributes, and perform edge separation operations on the maximum-degree vertex and the copy node based on the semantic attributes, separating the in-edges and out-edges of the maximum-degree vertex and the copy node to obtain multiple parsing subgraphs; Update the vertex degrees, vertex sets, and edge sets in each parsing subgraph, and verify the segmentation status of the parsing subgraph through the connectivity detection algorithm; If there are no shared edges between the parsing subgraphs and the vertex scales of the parsing subgraphs meet the second preset threshold, it is determined as effective segmentation; otherwise, use the community detection algorithm to further segment the parsing subgraphs that have not been effectively segmented.

5. The hierarchical TCAM packet parsing and field extraction system based on parsing graph optimization according to claim 1, wherein The key bit extraction unit in each level extraction mapping module is specifically configured to obtain the byte data block containing the key bits in a byte-level coarse-grained manner according to the physical positions of the key bits of the parsing subgraph in the received hardware resource configuration table, further separate the key bits from the byte data block in a bit-level fine-grained manner, and aggregate the key bits of all parsing subgraphs using the first programmable crossbar, and output the formed key bit set to the mapping table matching unit in this level extraction mapping module.

6. The hierarchical TCAM message parsing and field extraction system optimized based on the parsing graph according to claim 5, characterized in that, The key bit extraction unit includes: a byte address extraction subunit and a bit address extraction subunit; The byte address extraction subunit is configured to strip the low 3-bit addresses of each key bit based on the shift register parameters provided by the hardware resource configuration table to generate a byte-aligned physical address, and extract the byte data block containing the key bits according to the physical address; The bit address extraction subunit is configured to perform bit-plane decomposition operations on the byte data block, and grab the key bits specified by the mask from the byte data block through the combination logic of the bit mask and the shifter; aggregate the key bits of all parsing subgraphs by using the first programmable crossbar, and output the formed set of key bits to the mapping table matching unit in the extraction mapping module at this level.

7. The hierarchical TCAM message parsing and field extraction system optimized based on the parsing graph according to claim 6, characterized in that, The key bit extraction unit further includes an arbiter; The arbiter is configured to sort and schedule the conflicting key bits based on the TCAM rule priority field when the key bits of multiple parsing subgraphs are located in the same byte data block.

8. The hierarchical TCAM packet parsing and field extraction system optimized based on the parsing graph according to claim 1, characterized in that, The mapping table matching unit in each level of the extraction mapping module includes a heterogeneous TCAM storage block, and the paths in the parsing subgraph corresponding to the extraction mapping module at this level are stored in the heterogeneous TCAM storage block; The mapping table matching unit is specifically configured to use the set of key bits as an index address, input it into the heterogeneous TCAM storage block for matching, and obtain the protocol parsing path corresponding to the parsing subgraph.

9. The hierarchical TCAM message parsing and field extraction system optimized based on the parsing graph according to claim 1, characterized in that, The flow classification module includes a matching unit and a TCAM unit; The matching unit is configured to aggregate the protocol parsing paths corresponding to each parsing subgraph according to the preset weights of the protocol levels to generate a complete protocol parsing path topology; input the combined index into the heterogeneous TCAM storage block, match it with the complete protocol parsing path topology to obtain the unique path identifier of the protocol parsing graph, and obtain the relevant information of the specific field of the path corresponding to the unique path identifier in the current data packet through the RAM address mapping table; The TCAM unit is configured to predict the next-hop path according to the relevant information of the specific field, and pre-load the extraction instruction of the unique path identifier.

10. The hierarchical TCAM packet parsing and field extraction system optimized based on the parsing diagram according to claim 1, wherein The flow classification module further includes a RAM unit, and the RAM unit stores the field extraction instructions corresponding to all paths in each parsing subgraph; The field extraction module includes: a field extraction engine and a structured metadata output unit; The field extraction engine is configured to locate the physical offset and length of the specific field from the current data packet according to the field extraction instruction, and extract the specific field; The structured metadata output unit is configured to generate a protocol-independent standardized metadata structure according to the specific field, and route the standardized metadata structure to the specified storage area of the PHV in the PHV format through the second programmable crossbar.

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