Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and a storage system. The semiconductor device includes a semiconductor pillar array and a gate structure. The semiconductor column array comprises a plurality of semiconductor columns which are arranged in an array mode in the first direction and the second direction and extend in the third direction. The plurality of semiconductor columns comprise a plurality of rows of semiconductor columns arranged along a first direction and a plurality of columns of semiconductor columns arranged along a second direction. Any two of the first direction, the second direction and the third direction intersect with each other. A gate structure is disposed around sidewalls of the plurality of semiconductor pillars of the column of semiconductor pillars extending in the third direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is an important memory. The storage unit of a dynamic random access memory mainly includes a storage capacitor and a transistor connected in series with the storage capacitor. Among them, the storage capacitor is used to store data, and the transistor is used to control the storage of data in the storage capacitor.

[0003] Currently, the performance of dynamic random access memories needs to be further improved. How to improve the performance of dynamic random access memories is a technical problem to be solved. Summary of the Invention

[0004] The present application provides a semiconductor device, a manufacturing method thereof, and a storage system to improve the performance of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, including:

[0006] A semiconductor pillar array, including a plurality of semiconductor pillars arranged in an array along a first direction and a second direction and extending along a third direction. The plurality of semiconductor pillars include multiple rows of semiconductor pillars arranged along the first direction and multiple columns of semiconductor pillars arranged along the second direction. Any two of the first direction, the second direction, and the third direction intersect; and

[0007] A gate structure, where one gate structure is disposed around the sidewalls of the plurality of semiconductor pillars in a column of the semiconductor pillars extending along the third direction.

[0008] In some embodiments, each semiconductor pillar includes a first end and a second end opposite to each other in the third direction;

[0009] The semiconductor device further includes:

[0010] A capacitor array, located on one side of the semiconductor pillar array in the third direction, and including a plurality of capacitors arranged in an array along the first direction and the second direction. One capacitor is connected to the first end of one semiconductor pillar; and

[0011] A capacitor isolation structure, filled between adjacent capacitors.

[0012] In some embodiments, one capacitor includes:

[0013] A first electrode extending along the third direction and contacting the capacitor isolation structure and connected to the first end of the semiconductor column;

[0014] a second electrode extending along the third direction, wherein the first electrode surrounds a side wall of the second electrode extending along the third direction and a bottom wall of the second electrode close to the semiconductor column; and

[0015] The capacitor dielectric layer is located between the first electrode and the second electrode.

[0016] In some embodiments, the semiconductor device further comprises:

[0017] The capacitor lead-out structure is located on a side of the capacitor array away from the semiconductor pillar array in the third direction and is connected to the second electrodes of the plurality of capacitors.

[0018] In some embodiments, the plurality of capacitors include a plurality of rows of capacitors arranged along the first direction and a plurality of columns of capacitors arranged along the second direction;

[0019] The capacitive isolation structure comprises:

[0020] a plurality of first capacitor isolation portions extending along the first direction and arranged along the second direction, each first capacitor isolation portion being located between two adjacent columns of the capacitors; and

[0021] A plurality of second capacitor isolation portions extending along the second direction and arranged along the first direction, each of the second capacitor isolation portions being located between two adjacent rows of capacitors.

[0022] In some embodiments, the plurality of second capacitor isolation parts intersect and connect with the plurality of first capacitor isolation parts.

[0023] In some embodiments, at least one of the first capacitive isolation portion and the second capacitive isolation portion includes a curved sidewall in contact with the capacitor.

[0024] In some embodiments, a plurality of the gate structures are arranged along the second direction;

[0025] The semiconductor device also includes a plurality of gate isolation structures extending along the first direction and the third direction and arranged along the second direction, each of the gate isolation structures being arranged between two adjacent gate structures and between two adjacent columns of the semiconductor columns, and the plurality of gate isolation structures being respectively connected to the plurality of the first capacitor isolation parts.

[0026] In some embodiments, the semiconductor device further comprises:

[0027] A plurality of bit lines extending along the second direction and arranged along the first direction, the plurality of bit lines are located on a side of the semiconductor column array away from the capacitor array, and one bit line is connected to the second ends of a plurality of semiconductor columns in a row of the semiconductor columns.

[0028] In some embodiments, the plurality of bit lines are distributed in a step-wise manner along the third direction.

[0029] In some embodiments, the semiconductor device further includes: a protection layer covering the plurality of bit lines.

[0030] In some embodiments, the semiconductor device further includes: a base layer located on one side of the semiconductor column array in the first direction, and the semiconductor column array and the gate structure are located on the base layer.

[0031] In some embodiments, a plurality of the gate structures are arranged at intervals along the second direction, and one of the gate structures includes:

[0032] a gate conductive portion extending along the first direction and disposed around side walls of a plurality of semiconductor pillars in a row of the semiconductor pillars extending along the third direction; and

[0033] A plurality of gate insulating parts are arranged at intervals, each of the gate insulating parts is arranged around a side wall of the semiconductor column extending along the third direction and is located between the gate conductive part and one of the semiconductor columns.

[0034] In some embodiments, the gate conductive portion includes:

[0035] A first gate conductive portion extending along the first direction and located between two adjacent rows of semiconductor pillars; and

[0036] A plurality of second gate conductive portions extend along the third direction and are connected to the first gate conductive portion, and are alternately arranged with a plurality of the semiconductor columns in a column of the semiconductor columns in the first direction, and a size of one of the second gate conductive portions along the third direction is greater than a size of the first gate conductive portion along the third direction.

[0037] In some embodiments, one of the first gate conductive portions comprises:

[0038] a gate conductive middle portion extending along the first direction and the third direction; and

[0039] The two gate conductive end portions extend along the first direction and the second direction and are respectively connected to two opposite ends of the gate conductive middle portion in the third direction.

[0040] In some embodiments, the semiconductor device further includes a plurality of gate isolation structures arranged at intervals along the second direction, and each gate isolation structure is located between two adjacent gate structures and between two adjacent columns of semiconductor pillars;

[0041] One of the gate isolation structures includes:

[0042] A first gate isolation portion extending along the first direction and located between two adjacent gate conductive intermediate portions of two adjacent gate conductive portions in the second direction; and

[0043] Two second gate isolation portions extending along the first direction and respectively connected to opposite ends of one first gate isolation portion in the third direction. Each second gate isolation portion is located between adjacent gate conductive ends of two adjacent gate conductive portions in the second direction, and the dimension of the second gate isolation portion along the second direction is smaller than the dimension of the first gate isolation portion along the second direction.

[0044] In some embodiments, the semiconductor device further includes:

[0045] A semiconductor pillar protrusion array including a plurality of semiconductor pillar protrusion columns arranged in an array along the second direction and the third direction. Each semiconductor pillar protrusion column includes a plurality of semiconductor pillar protrusions arranged at intervals along the first direction. One semiconductor pillar protrusion is adjacent to and connected to one side wall of one semiconductor pillar extending along the third direction;

[0046] Two sets of semiconductor pillar protrusion columns adjacent and spaced along the second direction are provided between two adjacent columns of semiconductor pillars. One set of semiconductor pillar protrusion columns includes two semiconductor pillar protrusion columns spaced along the third direction. A first gate conductive portion is provided between the two semiconductor pillar protrusion columns of one set of semiconductor pillar protrusion columns. The plurality of semiconductor pillar protrusions of the two semiconductor pillar protrusion columns of one set of semiconductor pillar protrusion columns are connected to the plurality of semiconductor pillars of one column of semiconductor pillars;

[0047] Each second gate isolation portion is disposed between two semiconductor pillar protrusion columns that are adjacent in the second direction and located between two adjacent columns of semiconductor pillars.

[0048] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, the method including:

[0049] Forming a stacked structure on a surface of a base layer in a first direction, the stacked structure including a plurality of semiconductor layers and a plurality of insulating layers alternately arranged along the first direction; and

[0050] Form a plurality of first gate trenches that penetrate the stacked structure along the first direction and are arranged at intervals along the second direction. The remaining plurality of semiconductor layers include a plurality of initial semiconductor pillars that are arranged in an array along the first direction and the second direction and extend along the third direction. Each of the initial semiconductor pillars includes a first end and a second end that are opposite to each other in the third direction.

[0051] In some embodiments, the method further includes: removing a part of the insulating layer around each of the first gate trenches through the plurality of first gate trenches to form a plurality of second gate trenches, each of the second gate trenches penetrating the insulating layer between two adjacent first gate trenches along the second direction; and

[0052] Form a gate structure in the first gate trenches and the second gate trenches.

[0053] In some embodiments, forming the gate structure in the first gate trenches and the second gate trenches includes:

[0054] Form a plurality of spaced-apart gate insulating portions, each of the gate insulating portions being located in the first gate trenches and the second gate trenches and surrounding the sidewall of an initial semiconductor pillar extending along the third direction;

[0055] Form an initial gate conductive structure that fills the plurality of second gate trenches and is located on the sidewalls of the plurality of first gate trenches. The plurality of gate insulating portions are located between the initial gate conductive structure and the plurality of initial semiconductor pillars; and

[0056] Disconnect the initial gate conductive structure into a plurality of gate conductive portions that extend along the first direction and are arranged along the second direction. One of the gate conductive portions is disposed around the sidewalls of the plurality of initial semiconductor pillars of a column of the initial semiconductor pillars extending along the third direction.

[0057] In some embodiments, after forming the initial gate conductive structure that fills the plurality of second gate trenches and is located on the sidewalls of the plurality of first gate trenches, the method further includes:

[0058] Respectively fill a plurality of insulating filling portions in the remaining spaces of the plurality of first gate trenches;

[0059] The disconnecting the initial gate conductive structure into a plurality of gate conductive portions arranged along the second direction includes:

[0060] Form a plurality of disconnect trenches that penetrate the plurality of insulating filling portions along the first direction and disconnect the initial gate conductive structure. Each of the disconnect trenches extends along the third direction and is located between two adjacent gate conductive portions;

[0061] The method further includes: filling a disconnection part in the disconnection groove.

[0062] In some embodiments, the plurality of initial semiconductor pillars include multiple rows of the initial semiconductor pillars arranged along the first direction and multiple columns of the initial semiconductor pillars arranged along the second direction, and the method further includes:

[0063] forming a first through groove that penetrates the stacked structure along the first direction and extends along the second direction, the first through groove being located on one side of the plurality of initial semiconductor pillars in the third direction and exposing a first end of the plurality of initial semiconductor pillars in the third direction;

[0064] conductifying the first ends of the plurality of initial semiconductor pillars to form one of a source electrode and a drain electrode; and

[0065] forming a plurality of bit lines that extend along the second direction and are spaced apart along the first direction on one side of one of the source electrode and the drain electrode in the third direction, each bit line being connected to one of the source electrode and the drain electrode, and the first through groove exposing the plurality of bit lines.

[0066] In some embodiments, the method further includes: forming a protective layer that fills the first through groove and covers the plurality of bit lines.

[0067] In some embodiments, the method further includes:

[0068] forming a plurality of isolation grooves that penetrate the stacked structure along the first direction and are arranged along the second direction, the plurality of isolation grooves being located on one side of the plurality of first gate grooves in the third direction and being spaced apart from the plurality of first gate grooves, and the plurality of isolation grooves being adjacent to the second ends of the plurality of initial semiconductor pillars;

[0069] respectively filling a plurality of capacitive isolation parts in the plurality of isolation grooves and removing the semiconductor layer around the capacitive isolation parts except for the plurality of initial semiconductor pillars, and the plurality of capacitive isolation parts and the remaining insulating layer define a plurality of capacitor accommodation grooves that are spaced apart;

[0070] conductifying the second ends of the plurality of initial semiconductor pillars to form the other of the source electrode and the drain electrode; and

[0071] respectively forming a plurality of capacitors in the plurality of capacitor accommodation grooves, each capacitor being connected to the other of the source electrode and the drain electrode.

[0072] In some embodiments, the forming a plurality of capacitors in the plurality of capacitor accommodation grooves includes:

[0073] Form a plurality of first electrodes arranged at intervals in a plurality of the capacitor accommodating grooves respectively, at least a part of each of the first electrodes is located on the groove wall of the capacitor accommodating groove and is connected to the other one of the source electrode and the drain electrode;

[0074] Form a capacitive dielectric layer covering the plurality of first electrodes in the plurality of the capacitor accommodating grooves; and

[0075] Form a second electrode covering the capacitive dielectric layer and filling the plurality of the capacitor accommodating grooves.

[0076] In some embodiments, before removing the semiconductor layer around the capacitive isolation portions except for the plurality of initial semiconductor pillars, the method further includes:

[0077] Form a second through groove penetrating the stacked structure along the first direction and extending along the second direction, the second through groove is located on one side of the plurality of isolation grooves away from the first gate groove in the third direction, and exposes the plurality of capacitive isolation portions;

[0078] The method further includes: during the process of forming the second electrode, form a capacitive lead-out structure filling the second through groove, and the capacitive lead-out structure is connected to the second electrode.

[0079] In a third aspect, the present application further provides a storage system, the storage system includes:

[0080] The semiconductor device of any of the above embodiments;

[0081] A controller, the controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

[0082] In the semiconductor device of some embodiments of the present application, a gate structure is arranged along the side walls of the plurality of semiconductor pillars in a column extending in the third direction around a column of semiconductor pillars. With such an arrangement, the control ability of the gate structure over the channels of the semiconductor pillars can be improved, and the leakage current of the transistor including the gate structure and the semiconductor pillars in the off state can be reduced, improving the performance of the semiconductor device.

[0083] In the manufacturing method of the semiconductor device of some embodiments of the present application, a stacked structure is formed on a base layer, the stacked structure includes a plurality of semiconductor layers and a plurality of insulating layers alternately arranged along a first direction; then, a plurality of first gate grooves penetrating the stacked structure along the first direction and arranged at intervals along a second direction are formed, and the remaining semiconductor layers include a plurality of initial semiconductor pillars stacked along the first direction. By adopting this method, a plurality of initial semiconductor pillars arranged in a stacked manner can be formed on the base layer, which is convenient for forming storage units arranged in a stacked manner and improving the storage density of the semiconductor device. And the process of forming the first gate grooves is simple, which is convenient for breaking through the limitation of the lithography size. Brief Description of the Drawings

[0084] Figure 1 Schematic perspective view of a partial structure of a semiconductor device according to some embodiments provided by the present application;

[0085] Figure 2 Along Figure 1 Schematic cross-sectional view taken along the X-X' tangent in;

[0086] Figure 3 Along Figure 1 Schematic cross-sectional view taken along the Y1-Y1' tangent in;

[0087] Figure 4 Along Figure 1 Schematic cross-sectional view taken along the Y2-Y2' tangent in;

[0088] Figure 5 Along Figure 1 Schematic cross-sectional view taken along the Z-Z' tangent in;

[0089] Figure 6 Schematic cross-sectional view taken along the X-X' tangent shown in a semiconductor device according to some other embodiments provided by the present application; Figure 1 ;

[0090] Figure 7 Schematic flow chart of a manufacturing method of a semiconductor device according to some embodiments provided by the present application;

[0091] Figures 8A to 8B , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11E Schematic structural views of the manufacturing process of a semiconductor device according to some embodiments provided by the present application;

[0092] Figure 12 Schematic structural view of a semiconductor device according to some other embodiments provided by the present application;

[0093] Figures 13A to 13D Schematic structural views of the manufacturing process of a semiconductor device according to some other embodiments provided by the present application;

[0094] Figure 14 Block diagram of a storage system according to some embodiments provided by the present application;

[0095] Figure 15 Block diagram of a storage system according to some other embodiments provided by the present application;

[0096] Figure 16 Block diagram of an electronic device according to some embodiments provided by the present application.

[0097] Reference numerals are as follows:

[0098] 100, semiconductor device;

[0099] 11, semiconductor pillar array; 111, semiconductor pillar; 112, initial semiconductor pillar; 1121, 113, first end; 1122, 114, second end; 115, channel portion; 116, sidewall;

[0100] 12, semiconductor pillar protrusion array; 121, semiconductor pillar protrusion; 122, semiconductor pillar protrusion row;

[0101] 13, gate structure; 131, gate conductive portion; 132, first gate conductive portion; 1321, gate conductive intermediate portion; 1322, gate conductive end portion; 133, second gate conductive portion; 134, initial gate conductive structure;

[0102] 14, gate insulating portion;

[0103] 15, gate isolation structure; 151, first gate isolation portion; 152, second gate isolation portion;

[0104] 16, capacitor array; 161, capacitor; 162, first electrode; 1621, first electrode curved sidewall; 163, second electrode; 1631, second electrode curved sidewall; 164, capacitive dielectric layer; 165, capacitive lead-out structure;

[0105] 17, capacitive isolation structure; 171, first capacitive isolation portion; 171a, insulating curved sidewall; 172, second capacitive isolation portion;

[0106] 18, bit line; 181, bit line conductive layer; 19, protective layer; 21, base layer;

[0107] z, first direction; x, second direction; y, third direction;

[0108] 3, stacked structure; 31, insulating layer; 32, semiconductor layer;

[0109] 41, first gate groove; 42, second gate groove;

[0110] 51, first mask layer; 511, first mask opening; 52, second mask layer; 521, second mask opening; 53, third mask layer; 531, third mask opening; 54, fourth mask layer; 541, fourth mask opening; 55, fifth mask layer; 551, fifth mask opening;

[0111] 61, first through groove; 62, second through groove; 63, isolation groove; 64, bit line accommodation groove; 65, capacitor accommodation groove; 66, disconnection groove;

[0112] 71, insulation filling part; 72, capacitance isolation part; 73, disconnection part;

[0113] 200, memory; 300, controller; 400, storage system; 500, electronic device; 600, host. Detailed implementation manners

[0114] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0115] Please refer to Figures 1 to 6 as shown Figure 1 which is a partial three-dimensional structural schematic diagram of a semiconductor device according to some embodiments provided by the present application, Figure 2 is a cross-sectional structural schematic diagram taken along the X-X' tangent in Figure 1 , Figure 3 is a cross-sectional structural schematic diagram taken along the Y1-Y1' tangent in Figure 1 , Figure 4 is a cross-sectional structural schematic diagram taken along the Y2-Y2' tangent in Figure 1 , Figure 5 is a cross-sectional structural schematic diagram taken along the Z-Z' tangent in Figure 1 . Figure 6 is a cross-sectional structural schematic diagram of a semiconductor device according to some other embodiments provided by the present application taken along the X-X' tangent shown in Figure 1 .

[0116] As Figures 1 to 5 shown, the semiconductor device 100 includes a semiconductor pillar array 11. The semiconductor pillar array 11 includes a plurality of semiconductor pillars 111 arranged in an array along a first direction z and a second direction y and extending along a third direction x. The semiconductor pillar array 11 includes multiple rows of semiconductor pillars 111 arranged at intervals along the first direction z and multiple columns of semiconductor pillars 111 arranged at intervals along the second direction y. As Figure 2 shown, a column of semiconductor pillars 111 includes at least two semiconductor pillars 111 arranged side by side and at intervals along the first direction z. As Figure 5 shown, a row of semiconductor pillars 111 includes at least two semiconductor pillars 111 arranged side by side and at intervals along the second direction y.

[0117] Exemplarily, as Figure 1As shown, the semiconductor pillar array 11 includes three rows of semiconductor pillars 111 and five columns of semiconductor pillars 111. One row of semiconductor pillars 111 includes five semiconductor pillars 111 arranged side by side and spaced apart along the second direction y. One column of semiconductor pillars 111 includes three semiconductor pillars 111 arranged side by side and spaced apart along the first direction z. It can be understood that the number of rows of semiconductor pillars 111 can be greater than 3, and the number of columns of semiconductor pillars 111 can be greater than 5.

[0118] Each semiconductor pillar 111 is columnar. The shape of each semiconductor pillar 111 can be a cuboid, but is not limited thereto. The shape of the cross-section of each semiconductor pillar 111 parallel to the first direction z and the second direction y can be a rectangle, but is not limited thereto. Each semiconductor pillar 111 can have four side walls 116 extending along the third direction x, and two adjacent side walls 116 are connected.

[0119] Each semiconductor pillar 111 includes a first end 113 and a second end 114 opposite to each other in the third direction x. One of the first end 113 and the second end 114 of the semiconductor pillar 111 is a source electrode, and the other of the first end 113 and the second end 114 of the semiconductor pillar 111 is a drain electrode. The second ends 114 of the multiple semiconductor pillars 111 in one row of semiconductor pillars 111 can be connected to each other, as Figure 5 shown. The first ends 113 of two adjacent semiconductor pillars 111 in one row of semiconductor pillars 111 can be spaced apart, as Figure 1 and Figure 5 shown. Each semiconductor pillar 111 further includes a channel portion 115 located between the first end 113 and the second end 114.

[0120] In some embodiments, the semiconductor pillar 111 can include at least one of single-crystalline silicon, polycrystalline silicon, metal oxide, and silicon germanium. The metal oxide includes but is not limited to indium gallium zinc oxide. In a specific embodiment, the semiconductor pillar 111 can include single-crystalline silicon to reduce the leakage current of the transistor including the semiconductor pillar 111. In another specific embodiment, the semiconductor pillar 111 can include polycrystalline silicon. Thus, the transistor including the semiconductor pillar 111 can be paired with a non-volatile storage medium (such as a ferroelectric capacitor) to form a non-volatile memory cell.

[0121] Any two of the first direction z, the second direction y, and the third direction x intersect. In a specific embodiment, any two of the first direction z, the second direction y, and the third direction x can be perpendicular to each other, but is not limited thereto.

[0122] As Figure 1 and Figure 5As shown, the semiconductor device 100 further includes a semiconductor pillar protrusion array 12. The semiconductor pillar protrusion array 12 includes a plurality of semiconductor pillar protrusion columns 122 arranged in an array along the second direction y and the third direction x. Each semiconductor pillar protrusion column 122 includes a plurality of semiconductor pillar protrusions 121 spaced apart along the first direction z. The plurality of semiconductor pillar protrusions 121 of each semiconductor pillar protrusion column 122 are connected to the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111 one-to-one. Each semiconductor pillar protrusion 121 is adjacent to and connected to a side wall 116 extending along the third direction x of a semiconductor pillar 111.

[0123] As Figure 1 shown, two sets of semiconductor pillar protrusion columns 122 that are adjacent and spaced apart along the second direction y are provided between two adjacent columns of semiconductor pillars 111. One set of semiconductor pillar protrusion columns 122 includes two semiconductor pillar protrusion columns 122 spaced apart along the third direction x, as Figure 5 shown. The plurality of semiconductor pillar protrusions 121 of the two semiconductor pillar protrusion columns 122 of one set of semiconductor pillar protrusion columns are connected to the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111. Two adjacent semiconductor pillar protrusions 121 in the third direction x are connected to a portion between the first end 113 and the second end 114 of a semiconductor pillar 111.

[0124] In some embodiments, the dimension of a semiconductor pillar protrusion 121 along the first direction z is equal to the dimension of a semiconductor pillar 111 along the first direction z. The dimension of a semiconductor pillar protrusion 121 along the third direction x is less than the dimension of a semiconductor pillar 111 along the third direction x. The semiconductor pillar protrusion 121 and the semiconductor pillar 111 may include the same material.

[0125] As Figure 1 shown, the semiconductor device 100 further includes a plurality of gate structures 13. The plurality of gate structures 13 are spaced apart along the second direction y. As Figure 3 shown, a gate structure 13 is disposed around the side walls 116 extending along the third direction x of the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111. Therefore, the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111 share one gate structure 13.

[0126] In some embodiments, a gate structure 13 may be disposed around one side wall extending along the third direction x of each of the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111. In some embodiments, a gate structure 13 may be disposed around two or more side walls extending along the third direction x of each of the plurality of semiconductor pillars 111 of a column of semiconductor pillars 111.

[0127] As Figure 1 and Figure 3As shown, in a specific embodiment, a gate structure 13 may be disposed around four sidewalls extending along a third direction x of each of a plurality of semiconductor pillars 111 in a column of semiconductor pillars 111. That is, the gate structure 13 may be a gate all around (GAA) structure. In this way, the gate structure 13 may have a larger gate control area to achieve better channel control and a smaller subthreshold swing. During the off state of the transistor including the gate structure 13, since the channel is completely depleted, the leakage current of the transistor can be reduced.

[0128] As Figure 1 , Figure 3 and Figure 5 shown, a gate structure 13 includes a gate conductive portion 131 and a gate insulating portion 14. The gate insulating portion 14 serves to isolate the gate conductive portion 131 from the semiconductor pillar 111.

[0129] As Figure 3 shown, each gate insulating portion 14 is disposed around a sidewall 116 of a semiconductor pillar 111 extending along the third direction x and is located between the gate conductive portion 131 and a semiconductor pillar 111. In some embodiments, each gate insulating portion 14 is disposed around one or more sidewalls of a semiconductor pillar 111 extending along the third direction x. In a specific embodiment, a plurality of gate insulating portions 14 may be spaced apart, and each gate insulating portion 14 is disposed around four sidewalls 116 of a semiconductor pillar 111 extending along the third direction x. The gate insulating portion 14 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high-k dielectric material. For example, the gate insulating portion 14 may include silicon oxide.

[0130] A gate conductive portion 131 extends along a first direction z and is disposed around sidewalls of a plurality of semiconductor pillars 111 in a column of semiconductor pillars 111 extending along the third direction x. In some embodiments, a gate conductive portion 131 is disposed around one or more sidewalls of a plurality of semiconductor pillars 111 in a column of semiconductor pillars 111 extending along the third direction x and is located on a surface of the gate insulating portion 14 facing away from the semiconductor pillar 111.

[0131] In a specific embodiment, a gate conductive portion 131 is disposed around four sidewalls 116 of a plurality of semiconductor pillars 111 in a column of semiconductor pillars 111 extending along the third direction x and is in contact with a surface of the gate insulating portion 14 facing away from the semiconductor pillar 111.

[0132] In some embodiments, the gate conductive portion 131 may include a conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate conductive portion 131 may include doped polysilicon. In some embodiments, the gate conductive portion 131 may include multiple conductive layers, such as a W layer over a TiN layer.

[0133] As Figure 1 and Figure 3 shown, a gate conductive portion 131 may include a first gate conductive portion 132 and multiple second gate conductive portions 133 connected to the first gate conductive portion 132. The first gate conductive portion 132 extends along a first direction z and is located between two adjacent columns of semiconductor pillars 111, and multiple semiconductor pillars 111 of one column of semiconductor pillars 111 share the first gate conductive portion 132.

[0134] As Figure 5 shown, one first gate conductive portion 132 is provided between two semiconductor pillar protrusion columns 122 of a group of semiconductor pillar protrusion columns 122, and a gate insulating portion 14 is provided between the first gate conductive portion 132 and multiple semiconductor pillar protrusions 121 of the semiconductor pillar protrusion column 122.

[0135] As Figure 3 shown, multiple second gate conductive portions 133 extend along a third direction x and are connected to the first gate conductive portion 132, and are alternately arranged with multiple semiconductor pillars 111 of one column of semiconductor pillars 111 in the first direction z. Therefore, some of the second gate conductive portions 133 are located between two adjacent semiconductor pillars 111 of one column of semiconductor pillars 111, and each of the second gate conductive portions 133 in this part is shared by two adjacent semiconductor pillars 111 of one column of semiconductor pillars 111.

[0136] As Figure 5 shown, in a specific embodiment, a gate conductive portion 131 includes two first gate conductive portions 132 and multiple second gate conductive portions 133. In a second direction y, the two first gate conductive portions 132 of a gate conductive portion 131 are located on opposite sides of one column of semiconductor pillars 111. The multiple second gate conductive portions 133 of a gate conductive portion 131 are alternately arranged with multiple semiconductor pillars 111 of one column of semiconductor pillars 111, as Figure 1 and Figure 3 shown. Each of the multiple second gate conductive portions 133 is connected to the two first gate conductive portions 132 at both ends in the second direction y, as Figure 3 shown.

[0137] As Figure 2 and Figure 5As shown, in some embodiments, the dimension L1 of the second gate conductive portion 133 in the third direction x may be greater than the dimension L2 of the first gate conductive portion 132 in the third direction x. In some embodiments, the dimension L1 of the second gate conductive portion 133 in the third direction x may also be less than or equal to the dimension L2 of the first gate conductive portion 132 in the third direction x.

[0138] As Figure 1 and Figure 5 shown, a first gate conductive portion 132 includes a gate conductive intermediate portion 1321 and two gate conductive end portions 1322 respectively connected to opposite ends of the gate conductive intermediate portion 1321 in the third direction x. The gate conductive intermediate portion 1321 extends in the first direction z and the third direction x. The gate conductive end portions 1322 extend in the first direction z and the second direction y. Therefore, the gate conductive end portions 1322 are perpendicular to and connected to the gate conductive intermediate portion 1321.

[0139] The dimension of the gate conductive intermediate portion 1321 in the third direction x is greater than the dimension of the gate conductive end portions 1322 in the third direction x. The dimension of the gate conductive end portions 1322 in the second direction y is greater than the dimension of the gate conductive intermediate portion 1321 in the second direction y. Therefore, a portion of a gate conductive end portion 1322 in the second direction y is located on a side of the gate conductive intermediate portion 1321 facing away from the semiconductor pillar 111 adjacent to the gate conductive intermediate portion 1321.

[0140] As Figure 1 , Figure 3 and Figure 5 shown, the semiconductor device 100 further includes a plurality of gate isolation structures 15 arranged at intervals in the second direction y. Each gate isolation structure 15 not only serves to isolate two adjacent gate structures 13, but also serves to isolate the first ends 113 of a plurality of semiconductor pillars 111 in two adjacent columns of semiconductor pillars 111. Each gate isolation structure 15 is located between two adjacent gate structures 13 and between two adjacent columns of semiconductor pillars 111. Each gate isolation structure 15 is also located between two adjacent semiconductor pillar protrusion columns 122 in the second direction y. The gate isolation structure 15 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high-k dielectric material.

[0141] As Figure 5As shown, a gate isolation structure 15 includes a first gate isolation portion 151 and two second gate isolation portions 152. A first gate isolation portion 151 extends along a first direction z and is located between adjacent two gate conduction intermediate portions 1321 of two adjacent gate conduction portions 131 in a second direction y. Two second gate isolation portions 152 extend along the first direction z and are respectively connected to opposite ends of a first gate isolation portion 151 in a third direction x. Each second gate isolation portion 152 is located between adjacent gate conduction end portions 1322 of two adjacent gate conduction portions 131 in the second direction y. In the second direction y, each second gate isolation portion 152 is further disposed between two semiconductor pillar protrusion columns 122 that are located between adjacent two semiconductor pillars 111 and are adjacent in the second direction y.

[0142] In some embodiments, the dimension L3 of the first gate isolation portion 151 in the second direction y is greater than the dimension L4 of the second gate isolation portion 152 in the second direction y, as Figure 5 shown. In some embodiments, the dimension of a second gate isolation portion 152 adjacent to the first end 113 of the semiconductor pillar 111 in the third direction x is greater than the dimension of another second gate isolation portion 152 adjacent to the second end 114 of the semiconductor pillar 111 in the third direction x.

[0143] As Figure 1 、 Figure 2 、 Figure 4 and Figure 5 shown, the semiconductor device 100 further includes a capacitor array 16 and a capacitance isolation structure 17. The capacitor array 16 is located on one side of the semiconductor pillar array 11 in the third direction x and includes a plurality of capacitors 161 arranged in an array along the first direction z and the second direction y. A capacitor 161 is connected to the first end 113 of a semiconductor pillar 111. The plurality of capacitors 161 includes multiple rows of capacitors 161 arranged along the first direction z and multiple columns of capacitors 161 arranged along the second direction y. The capacitance isolation structure 17 is filled between adjacent capacitors 161 to isolate adjacent capacitors 161.

[0144] A capacitor 161 includes a first electrode 162, a second electrode 163, and a capacitive dielectric layer 164. The first electrode 162 extends along a third direction x, contacts the capacitive isolation structure 17, and is connected to the first end 113 of the semiconductor pillar 111. The second electrode 163 extends along the third direction x, and the first electrode 162 surrounds the side wall of the second electrode 163 extending along the third direction x and the bottom wall of the second electrode 163 close to the semiconductor pillar 111. The capacitive dielectric layer 164 is located between the first electrode 162 and the second electrode 163. Thus, compared with the planar capacitor 161, the capacitor 161 in the present application has a larger facing area between the first electrode 162 and the second electrode 163, which is beneficial to improving the capacitance value of the capacitor 161. Moreover, the first electrode 162 can be formed on the side wall of the capacitive isolation structure 17 first, reducing the risk of collapse of the capacitor 161.

[0145] The second electrode 163 is columnar. In some embodiments, the second electrode 163 can be in the shape of a rectangular column or a cylindrical column. In some embodiments, the first electrode 162 and the second electrode 163 include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0146] In some embodiments, the capacitive dielectric layer 164 can include at least one of silicon oxide, silicon nitride, and high-k dielectrics. The high-k dielectrics include but are not limited to at least one of aluminum oxide, hafnium dioxide, tantalum pentoxide, zirconium dioxide, and titanium dioxide. In the case where the semiconductor pillar 111 can include polysilicon, the capacitor 161 can also be a ferroelectric capacitor. Correspondingly, the capacitive dielectric layer 164 can include a ferroelectric layer. The material of the ferroelectric layer includes but is not limited to lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT).

[0147] As Figure 1 、 Figure 2 and Figure 4 shown, the capacitive isolation structure 17 includes a plurality of first capacitive isolation portions 171 extending along a first direction z and arranged along a second direction y, and a plurality of second capacitive isolation portions 172 extending along the second direction y and arranged along the first direction z.

[0148] Each first capacitive isolation portion 171 is located between two adjacent columns of capacitors 161 to isolate two adjacent capacitors 161 in the second direction y. Each first capacitive isolation portion 171 is also located between the first ends 113 of two adjacent semiconductor pillars 111 in the second direction y to isolate the first ends 113 of two adjacent semiconductor pillars 111 in the second direction y. Therefore, each first capacitive isolation portion 171 can function to isolate two adjacent columns of semiconductor pillars 111 and two adjacent columns of capacitors 161.

[0149] The first capacitor isolation part 171 contacts two semiconductor pillar protrusion columns 122 in the second direction y at one end close to the gate structure 13 in the third direction x.

[0150] A plurality of gate isolation structures 15 are respectively connected to the plurality of first capacitor isolation parts 171 one by one. Specifically, as Figure 1 and Figure 5 shown, the second gate isolation part 152 on the side of the gate isolation structure 15 close to the capacitor 161 penetrates through part of the first capacitor isolation part 171 in the third direction x. In this way, the gate isolation structure 15 can better isolate two adjacent semiconductor pillar protrusion columns 122 in the second direction y, and further better isolate the first ends 113 of two adjacent semiconductor pillars 111 in the second direction y.

[0151] The dimension L5 of the first capacitor isolation part 171 in the second direction y can be greater than the dimension L4 of the second gate isolation part 152 in the second direction y, so that the second gate isolation part 152 can penetrate through part of the first capacitor isolation part 171. The dimension L5 of the first capacitor isolation part 171 in the second direction y can also be greater than the dimension L3 of the first gate isolation part 151 in the second direction y.

[0152] Each second capacitor isolation part 172 is located between two adjacent capacitors 161 in the first direction z to isolate two adjacent capacitors 161 in the first direction z. Each second capacitor isolation part 172 can also be located between two adjacent rows of semiconductor pillars 111 to isolate two adjacent semiconductor pillars 111 in the first direction z, as Figure 1 and Figure 2 shown. Therefore, the second capacitor isolation part 172 functions to isolate two adjacent rows of semiconductor pillars 111 and two adjacent rows of capacitors 161.

[0153] One end of the second capacitor isolation part 172 close to the gate structure 13 in the third direction x contacts the second gate conducting part 133 of the gate conducting part 131.

[0154] In some embodiments, the dimension of the second capacitor isolation part 172 in the first direction z can be equal to the dimension of the second gate conducting part 133 in the first direction z. In other embodiments, the dimension of the second capacitor isolation part 172 in the first direction z can also be greater than the dimension of the second gate conducting part 133 in the first direction z.

[0155] In some embodiments, the dimension of the second capacitor isolation part 172 in the third direction x is greater than the dimension of the first capacitor isolation part 171 in the third direction x. In this way, the second capacitor isolation part 172 can isolate two adjacent capacitors 161 in the first direction z and can also isolate two adjacent semiconductor pillars 111 in the first direction z.

[0156] In some embodiments, the plurality of second capacitor isolation portions 172 intersect and connect with the plurality of first capacitor isolation portions 171. In this way, the stability of the capacitor isolation structure 17 is improved, thereby improving the structural stability of the capacitor 161 and reducing the risk of collapse of the capacitor 161.

[0157] In some embodiments, the capacitor isolation structure 17 includes at least one of silicon oxide, silicon nitride, and a high-k dielectric. In some embodiments, the material of the capacitor isolation structure 17 may be different from the material of the capacitor dielectric layer 164, for example, the capacitor isolation structure 17 includes silicon oxide, and the capacitor dielectric layer 164 includes a high-k dielectric. In some embodiments, the material of the capacitor isolation structure 17 may be the same as the material of the gate isolation structure 15.

[0158] like Figure 1 , Figure 2 as well as Figure 5 As shown, the semiconductor device 100 further includes a capacitor lead-out structure 165, which is located on the side of the capacitor array 16 away from the semiconductor pillar array 11 in the third direction x, and is connected to the second electrodes 163 of the plurality of capacitors 161. The capacitor lead-out structure 165 extends along the first direction z and the second direction y. A capacitor dielectric layer 164 is provided between the capacitor lead-out structure 165 and the capacitor isolation structure 17. The capacitor lead-out structure 165 and the second electrode 163 include the same material.

[0159] like Figure 1 , Figure 2 as well as Figure 5 As shown, the semiconductor device 100 further includes a plurality of bit lines 18 extending along the second direction y and arranged along the first direction z. The plurality of bit lines 18 are located on a side of the semiconductor pillar array 11 away from the capacitor array 16, and one bit line 18 is connected to the second ends 114 of a plurality of semiconductor pillars 111 in a row of semiconductor pillars 111. The bit line 18 includes a conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0160] In some embodiments, the semiconductor device 100 further includes a plurality of bit line contacts (not shown), which are respectively connected to the plurality of bit lines 18. The plurality of bit line contacts may be located on one side or both sides of the semiconductor pillar array 11 in the first direction z.

[0161] In some embodiments, Figure 1 and Figure 2 As shown, the plurality of bit lines 18 are aligned or substantially aligned along the first direction z to simplify the manufacturing process of the plurality of bit lines 18 .

[0162] In other embodiments, Figure 6As shown, multiple bit lines 18 are arranged in a stepped manner along the third direction x, so as to facilitate the connection of multiple misaligned bit line contacts to the multiple stepped bit lines 18, simplifying the manufacturing process of the bit line contacts. When the multiple bit lines 18 are arranged in a stepped manner along the third direction x, the dimensions of the multiple bit lines 18 along the third direction x can increase.

[0163] As Figure 1 , Figure 2 , Figure 5 and Figure 6 shown, the semiconductor device 100 further includes a protective layer 19, and the protective layer 19 covers the multiple bit lines 18. The protective layer 19 serves to protect the bit lines 18 and also serves to isolate adjacent bit lines 18. The protective layer 19 is located between adjacent bit lines 18 and covers the surface of the bit lines 18 facing away from the second end 114 of the semiconductor pillar 111. The protective layer 19 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high-k dielectric material.

[0164] In some embodiments, the semiconductor device 100 further includes multiple word line contacts (not shown), and each word line contact is connected to a gate conductive portion 131. The multiple word line contacts can be located on one or both sides of the semiconductor pillar array 11 in the first direction z.

[0165] The above-mentioned one semiconductor pillar 111 and the part of the gate structure 13 surrounding the semiconductor pillar 111 constitute a transistor. A transistor is connected to a capacitor 161 to form a memory cell.

[0166] In some embodiments, the semiconductor device 100 further includes a base layer 21. The base layer 21 is located on one side of the semiconductor pillar array 11 in the first direction z, and the semiconductor pillar array 11 and the gate structure 13 are located on the base layer 21. Thus, the extending direction of each transistor and each capacitor 161 intersects with the thickness direction of the base layer 21, and each transistor and each capacitor 161 are horizontally arranged on the base layer 21. Moreover, multiple transistors and multiple capacitors 161 are stacked on the base layer 21 in the first direction z, that is, a stacked design of the memory cells is realized, which can increase the number of memory cells on the base layer 21, and thus is beneficial to reducing the size of the semiconductor device 100. The base layer 21 can include a semiconductor layer, and the semiconductor layer can include semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), etc. The base layer 21 can include a semiconductor layer and one or more film layers provided on the semiconductor layer, and the film layers include insulating layers.

[0167] In some other embodiments, the semiconductor device 100 further does not include the base layer 21, that is, the base layer 21 can be removed after forming structures such as transistors and capacitors 161. In this way, the gate conductive part 131 and the bit line 18 can be led out from either side of the two sides of the semiconductor device 100 in the first direction z, and the process windows of the bit line contacts connected to the bit line 18 and the word line contacts connected to the gate conductive part 131 are larger, which is beneficial to simplifying the manufacturing process of the semiconductor device 100.

[0168] In summary, in the above semiconductor device 100, the transistors and the capacitors 161 are both horizontally placed on the base layer 21, and a plurality of transistors and a plurality of capacitors 161 are stacked, which is beneficial to increasing the number of memory cells and the storage density of the semiconductor device 100. Moreover, the gate-all-around structure can enhance the gate control ability of the gate conductive part 131 and reduce the leakage current of the transistor. In addition, the structure of the capacitor 161 is more stable, and the risk of collapse of the capacitor 161 is reduced.

[0169] Please refer to Figure 7 shown, which is a schematic flow chart of a manufacturing method of a semiconductor device according to some embodiments provided by the present application. The following will be described in detail with reference to Figure 7 、 Figures 8A to 8B 、 Figures 9A to 9C 、 Figures 10A to 10C 、 Figures 11A to 11E ,the manufacturing process of the above Figure 1 shown semiconductor device 100.

[0170] First, referring to Figure 8A and Figure 8B shown, the manufacturing method of the semiconductor device 100 includes the following steps:

[0171] Step S101: Form a stacked structure 3 on the surface of the base layer 21 in the first direction z, where the stacked structure 3 includes a plurality of semiconductor layers 32 and a plurality of insulating layers 31 alternately arranged along the first direction z; and

[0172] Step S102: Form a plurality of first gate trenches 41 that penetrate the stacked structure 3 along the first direction z and are arranged at intervals along the second direction. The remaining plurality of semiconductor layers 32 include a plurality of initial semiconductor pillars 112 arranged in an array along the first direction z and the second direction y and extending along the third direction x. The initial semiconductor pillars 112 include a first end 1121 and a second end 1122 that are opposite to each other in the third direction x.

[0173] In some embodiments of the application, through the above-mentioned step S101 and step S102, a plurality of initial semiconductor pillars 112 stacked in the first direction z are formed on the base layer 21, which facilitates the formation of a plurality of transistors stacked in the first direction z on the base layer 21, so as to improve the storage density of the semiconductor device 100. Moreover, the process requirements for forming the first gate trench 41 are relatively simple, which reduces the manufacturing difficulty of the plurality of initial semiconductor pillars 112 and is conducive to breaking through the limitation of the lithography size.

[0174] As Figure 8A shown, the above-mentioned step S101 is executed.

[0175] After executing the above-mentioned step S101, in the first direction z, the semiconductor layer 32 can be located between two adjacent insulating layers 31, and the insulating layer 31 plays a role in protecting and isolating the semiconductor layer 32. The film layer of the stacked structure 3 closest to the base layer 21 is the insulating layer 31, and the film layer of the stacked structure 3 farthest from the base layer 21 is also the insulating layer 31.

[0176] In some embodiments, the base layer 21 may include a semiconductor layer, and the semiconductor layer may include semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), etc. The base layer 21 may include a semiconductor layer and one or more film layers provided on the semiconductor layer, and the film layer includes an insulating layer. The first direction z is the thickness direction of the base layer 21.

[0177] In some embodiments, the semiconductor layer 32 of the stacked structure 3 may include at least one of single crystal silicon, polycrystalline silicon, metal oxide, and silicon germanium. The metal oxide includes but is not limited to indium gallium zinc oxide. In a specific embodiment, the semiconductor layer 32 of the stacked structure 3 includes single crystal silicon. In another specific embodiment, the semiconductor layer 32 of the stacked structure 3 includes polycrystalline silicon. Since the semiconductor layer 32 of the stacked structure 3 may include single crystal silicon or polycrystalline silicon, the channel of the semiconductor device 100 can be compatible with single crystal silicon or polycrystalline silicon channels, thereby expanding the application fields of the semiconductor device 100.

[0178] In some embodiments, the insulating layer 31 of the stacked structure 3 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or high-k dielectric material. For example, the insulating layer 31 includes silicon oxide.

[0179] The insulating layer 31 and the semiconductor layer 32 of the stacked structure 3 can be formed by a thin film deposition process. The thin film deposition process includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof.

[0180] As Figure 8B shown, the above-mentioned step 102 is executed.

[0181] In some embodiments, step 102 includes the following steps:

[0182] Step 1021: Form a first mask layer 51 on the surface of the stack structure 3 facing away from the base layer 21. The first mask layer 51 includes a plurality of first mask openings 511 arranged at intervals along the second direction y; and

[0183] Step 1022: Remove a part of the stack structure 3 through the plurality of first mask openings 511 to form a plurality of first gate trenches 41 penetrating the stack structure 3. The remaining semiconductor layer 32 includes a plurality of initial semiconductor pillars 112.

[0184] In some embodiments, the shape of the cross-section of the first gate trench 41 parallel to the second direction y and the third direction x can be rectangular or trapezoidal. The shape of the cross-section of the first gate trench 41 parallel to the first direction z and the second direction y can be rectangular, trapezoidal or inverted trapezoidal. The shape of the cross-section of the first gate trench 41 parallel to the first direction z and the third direction x can be rectangular, trapezoidal or inverted trapezoidal.

[0185] In some embodiments, the plurality of initial semiconductor pillars 112 include multiple rows of initial semiconductor pillars 112 arranged along the first direction z and multiple columns of initial semiconductor pillars 112 arranged along the second direction y. One row of initial semiconductor pillars 112 includes a plurality of initial semiconductor pillars 112 arranged at intervals along the second direction y. One column of initial semiconductor pillars 112 includes a plurality of initial semiconductor pillars 112 arranged at intervals along the first direction z. Each initial semiconductor pillar 112 extends along the third direction x. Each initial semiconductor pillar 112 is columnar. Each initial semiconductor pillar 112 includes four side surfaces extending along the third direction x, and any two adjacent ones of the four side surfaces are connected.

[0186] In some embodiments, a part of the stack structure 3 can be removed through the plurality of first mask openings 511 by an etching process. The etching process includes but is not limited to at least one of dry etching and wet etching.

[0187] Next, referring to Figures 9A to 9C and Figure 11E as shown, the manufacturing method of the semiconductor device 100 further includes the following steps:

[0188] Step S201: Remove a part of the insulating layer 31 around each first gate trench 41 through the plurality of first gate trenches 41 to form a plurality of second gate trenches 42. Each second gate trench 42 penetrates the insulating layer 31 between two adjacent first gate trenches 41 along the second direction y; and

[0189] Step S202: Form a gate structure 13 in the first gate trench 41 and the second gate trench 42.

[0190] As Figure 9A shown, step S201 is executed.

[0191] After step S201 is completed, a plurality of second gate trenches 42 expose sidewalls of a plurality of initial semiconductor pillars 112 extending along the third direction x, and two adjacent first gate trenches 41 are connected through the second gate trenches 42. The plurality of initial semiconductor pillars 112 of a column of initial semiconductor pillars 112 and the plurality of second gate trenches 42 are alternately arranged along the first direction z.

[0192] In some embodiments, a part of the insulating layer 31 around each first gate trench 41 can be removed by an etching process.

[0193] As Figure 9B and Figure 9C shown, the above step S202 includes:

[0194] Step S2021, forming a plurality of gate insulating parts 14 arranged at intervals, each gate insulating part 14 being located in the first gate trench 41 and the second gate trench 42 and surrounding a sidewall of an initial semiconductor pillar 112 extending along the third direction x; and

[0195] Step S2022, forming an initial gate conductive structure 134 that fills the plurality of second gate trenches 42 and is located on sidewalls of the plurality of first gate trenches 41, and the plurality of gate insulating parts 14 are located between the initial gate conductive structure 134 and the plurality of initial semiconductor pillars 112.

[0196] As Figure 9B shown, for the above step S2021, in some embodiments, the initial semiconductor pillar 112 and the base layer 21 can be heated in an oxygen atmosphere so that sidewalls of each initial semiconductor pillar 112 extending along the third direction x and the part of the base layer 21 exposed by the second gate trench 42 are oxidized to form the gate insulating part 14. In some other embodiments, the gate insulating part 14 can also be deposited on the sidewalls of the initial semiconductor pillar 112 and the base layer 21 by the above thin film deposition process.

[0197] In some embodiments, the dimension of the gate insulating part 14 along the first direction z is smaller than the dimension of the second gate trench 42 along the first direction z. Therefore, after the gate insulating part 14 is formed, the second gate trench 42 is not completely filled. In some embodiments, the gate insulating part 14 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high-k dielectric material. For example, the gate insulating part 14 can include silicon oxide.

[0198] As Figure 9CAs shown, for the above-mentioned step S2022, in some embodiments, the initial gate conductive structure 134 that fills the second gate trench 42 and is located on the sidewall of the first gate trench 41 can be formed by using the above-mentioned thin film deposition process. The part of the initial gate conductive structure 134 located in the plurality of first gate trenches 41 and the plurality of second gate trenches 42 is continuous. The initial gate conductive structure 134 can include doped polysilicon, that is, polysilicon. The initial gate conductive structure 134 can also include a plurality of conductive layers, such as a W layer above a TiN layer.

[0199] It can be seen from this that through the above-mentioned steps S2021 to S2022, a plurality of gate insulating parts 14 and an initial gate conductive structure 134 arranged at intervals can be formed in the first gate trench 41 and the second gate trench 42. The plurality of gate insulating parts 14 are located between the initial gate conductive structure 134 and the sidewalls of the plurality of initial semiconductor pillars 112 extending along the third direction x.

[0200] Please continue to refer to Figure 9C As shown, after forming the initial gate conductive structure 134 that fills the plurality of second gate trenches 42 and is located on the sidewalls of the plurality of first gate trenches 41, the above method further includes the following steps:

[0201] Step S203, filling the remaining spaces in the plurality of first gate trenches 41 with a plurality of insulating filling parts 71 respectively.

[0202] In some embodiments, the insulating filling part 71 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or a high-k dielectric material. For example, the insulating filling part 71 can include silicon oxide.

[0203] Please refer to again Figure 9C As shown, after filling the remaining spaces in the plurality of first gate trenches 41 with a plurality of insulating filling parts 71 respectively, the above method further includes the following steps:

[0204] Step S204, removing the first mask layer 51 and the insulating layer 31 of the stack structure 3 far from the base layer 21.

[0205] Next, please refer to Figures 10A to 10C As shown, the manufacturing method of the above semiconductor device 100 further includes the following steps:

[0206] Step S301, forming a first through trench 61 that penetrates the stack structure 3 along the first direction z and extends along the second direction y. The first through trench 61 is located on one side of the plurality of initial semiconductor pillars 112 in the third direction x and exposes the first ends of the plurality of initial semiconductor pillars 112 in the third direction x;

[0207] Step S302, conductivize the first ends 1121 of the multiple initial semiconductor pillars 112 to form one of the source and the drain; and

[0208] Step S303, form a plurality of bit lines 18 extending along the second direction y and spaced apart along the first direction z on one side of the source and the drain in the third direction x, each bit line 18 being connected to one of the source and the drain, and the first through groove 61 exposing the plurality of bit lines 18.

[0209] As Figure 10A shown, perform the above step S301.

[0210] In some embodiments, the above step S301 includes the following steps:

[0211] Step S3011, form a second mask layer 52 on the surface of the stacked structure 3 away from the base layer 21, the second mask layer 52 including a second mask opening 521 located at one end of the second mask layer 52 in the third direction x and exposing one end of the stacked structure 3 in the third direction x; and

[0212] Step S3012, remove a part of the stacked structure 3 through the second mask opening 521 to form a first through groove 61 penetrating the stacked structure 3.

[0213] In some embodiments, the first through groove 61 exposes the first ends 1121 of the plurality of initial semiconductors in the third direction x and the base layer 21. The first through groove 61 extends along the first direction z and the second direction y.

[0214] Please continue to refer to Figure 10A shown, perform the above step S302.

[0215] In some embodiments, the first ends 1121 of the plurality of initial semiconductor pillars 112 can be processed by ion doping to form one of the source and the drain.

[0216] Please refer to Figure 10B shown, in some embodiments, after forming one of the source and the drain, remove a part of the source and the drain through the first through groove 61 to form a bit line accommodation groove 64.

[0217] In some embodiments, the bit line accommodation groove 64 extends along the second direction y, and the plurality of bit line accommodation grooves 64 and the plurality of insulating layers 31 are alternately arranged along the first direction z. In some embodiments, the plurality of bit line accommodation grooves 64 are aligned or substantially aligned along the first direction z. In other embodiments, the plurality of bit line accommodation grooves 64 can also be arranged in a stepped manner along the third direction x. At this time, the sizes of the plurality of bit line accommodation grooves 64 increase or decrease along the third direction x.

[0218] Please refer to Figure 10B and Figure 10C as shown, and perform the above step S303.

[0219] In some embodiments, the above step S303 includes the following steps:

[0220] Step S3031, forming a bit line filling groove 18 accommodating groove and a first through groove 61, and covering the bit line conductive layer 181 of the second mask layer; and

[0221] Step S3032, removing the part of the bit line conductive layer 181 outside the bit line accommodating groove 64, and forming a plurality of bit lines 18 extending along the second direction y and spaced apart along the first direction z.

[0222] After the above step S303, a plurality of bit lines 18 are formed, and each bit line 18 is connected to one of the source and drain of a row of initial semiconductor pillars 112. Moreover, by forming the bit line accommodating groove 64 and then forming a plurality of bit lines 18, the bonding force between the bit lines 18 and the source and drain can be improved.

[0223] In some embodiments, as Figure 10C shown, when the plurality of bit line accommodating grooves 64 are aligned or substantially aligned along the first direction z, the plurality of bit lines 18 are aligned or substantially aligned along the first direction z to simplify the manufacturing process of the plurality of bit line accommodating grooves and the plurality of bit lines 18. In other embodiments, the plurality of bit lines 18 can be distributed in a stepped manner along the third direction x to simplify the manufacturing process of the bit line contacts connected to the plurality of bit lines 18.

[0224] In some embodiments, the bit line 18 includes a conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide.

[0225] Please continue to refer to Figure 10C as shown, the manufacturing method of the above semiconductor device 100 further includes the following step: Step S304, forming a protective layer 19 that fills the first through groove 61 and covers the plurality of bit lines 18.

[0226] In some embodiments, the protective layer 19 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high-k dielectric material. The material of the protective layer 19 is the same as that of the insulating layer 31. For example, the protective layer 19 includes silicon oxide.

[0227] Please refer to again Figure 10CAs shown, in some embodiments, after forming a protective layer 19 that fills the first through-slot 61 and covers the multiple bit lines 18, the manufacturing method of the semiconductor device 100 further includes the following steps: removing the second mask layer 52.

[0228] Next, please refer to Figures 11A to 11D As shown, the manufacturing method of the above semiconductor device 100 further includes the following steps:

[0229] Step S401: Forming a plurality of isolation slots 63 that penetrate the stacked structure 3 along the first direction z and are arranged along the second direction y. The plurality of isolation slots 63 are located on one side of the plurality of first gate slots 41 in the third direction x and are spaced apart from the plurality of first gate slots 41. The plurality of isolation slots 63 are adjacent to the second ends of the plurality of initial semiconductor pillars 112.

[0230] Step S402: Filling a plurality of capacitive isolation portions in the plurality of isolation slots 63 respectively, and removing the semiconductor layer 32 around the capacitive isolation portions except for the plurality of initial semiconductor pillars 112. The plurality of capacitive isolation portions and the remaining insulating layer 31 define a plurality of spaced-apart capacitor 161 accommodation slots.

[0231] Step S403: Conductifying the second ends of the plurality of initial semiconductor pillars 112 to form the other one of the source and the drain; and

[0232] Step S404: Forming a plurality of capacitors 161 in the plurality of capacitor 161 accommodation slots respectively, and each capacitor 161 is connected to the other one of the source and the drain.

[0233] As Figure 11A shown, the above step S401 is executed.

[0234] In some embodiments, the above step S401 includes the following steps:

[0235] Step S4011: Forming a third mask layer 53 on the surface of the stacked structure 3 away from the base layer 21. The third mask layer 53 includes a plurality of third mask openings 531 spaced apart along the second direction y; and

[0236] Step S4012: Removing a part of the stacked structure 3 through the plurality of third mask openings 531 to form a plurality of isolation slots 63 that penetrate the stacked structure 3.

[0237] In some embodiments, an isolation groove 63 is adjacent to and spaced from a first gate groove 41 in the third direction x. The dimension of the isolation groove 63 in the second direction y may be greater than that of the first gate groove 41 in the second direction y. The shape of the cross-section of the isolation groove 63 parallel to the second direction y and the third direction x may be rectangular. The shape of the cross-section of the isolation groove 63 parallel to the first direction z and the third direction x may be at least one of rectangular, trapezoidal, or inverted trapezoidal. The shape of the cross-section of the isolation groove 63 parallel to the first direction z and the second direction y may be at least one of rectangular, trapezoidal, or inverted trapezoidal.

[0238] As Figure 11B and Figure 11C shown, the above-mentioned step S402 is executed.

[0239] As Figure 11B shown, after filling a plurality of capacitive isolation portions 72 in a plurality of isolation grooves 63 respectively, the plurality of capacitive isolation portions 72 intersect and connect with the remaining plurality of insulating layers 31. In some embodiments, the material of the capacitive isolation portion 72 is the same as that of the insulating layer 31 to improve the connection force between the capacitive isolation portion 72 and the insulating layer 31. For example, the capacitive isolation portion 72 includes silicon oxide.

[0240] The shape of the capacitive isolation portion 72 is the same as that of the isolation groove 63. In some embodiments, the shape of the cross-section of the capacitive isolation portion 72 parallel to the second direction y and the third direction x may be rectangular. The shape of the cross-section of the capacitive isolation portion 72 parallel to the first direction z and the third direction x may be rectangular. The shape of the cross-section of the capacitive isolation portion 72 parallel to the first direction z and the second direction y may be rectangular.

[0241] Please continue to refer to Figure 11B shown, the above method further includes the following steps: after filling a plurality of capacitive isolation portions 72 in a plurality of isolation grooves 63 respectively, the third mask layer 53 is removed.

[0242] As Figure 11C shown, after filling a plurality of capacitive isolation portions 72 in a plurality of isolation grooves 63 respectively, and before removing the semiconductor layer 32 around the capacitive isolation portion 72 except for the plurality of initial semiconductor pillars 112, the above method further includes:

[0243] forming a fourth mask layer 54 on the surface of the stacked structure 3 away from the base layer 21, the fourth mask layer 54 includes a fourth mask opening 541, and the fourth mask opening 541 is located at one end of the fourth mask layer 54 facing away from the first through groove 61; and

[0244] Using the fourth mask layer 54 as a mask, a second through-slot 62 is formed that penetrates the stacked structure 3 along the first direction z and extends along the second direction y. The second through-slot 62 is located on a side of the plurality of capacitor isolation portions 72 away from the first gate slot 41 in the third direction x and exposes the plurality of capacitor isolation portions 72.

[0245] Please continue to refer to Figure 11C As shown, removing the semiconductor layer 32 around the capacitor isolation portions 72 except for the plurality of initial semiconductor pillars 112 includes: removing the semiconductor layer 32 around the capacitor isolation portions 72 except for the plurality of initial semiconductor pillars 112 through the second through-slot 62. In some embodiments, any one of dry etching or wet etching can be used to remove the semiconductor layer 32 around the capacitor isolation portions 72 except for the plurality of initial semiconductor pillars 112, forming a capacitor accommodation slot 65.

[0246] In some embodiments, the plurality of capacitor accommodation slots 65 are spaced apart, and each capacitor accommodation slot 65 exposes the second end 1122 of one initial semiconductor pillar 112.

[0247] As Figure 11D shown, perform the above step S403.

[0248] In some embodiments, ion doping can be used to conductify the second ends 1122 of the plurality of initial semiconductor pillars 112 through the plurality of capacitor accommodation slots 65 to form the other of the source and the drain, and the unconductified portions of the plurality of initial semiconductor pillars 112 form a channel portion. One of the source and the drain, the channel portion, and the other of the source and the drain constitute a semiconductor pillar 111.

[0249] As Figure 11D shown, perform the above step S404.

[0250] In some embodiments, the above step 404 includes the following steps:

[0251] Form a plurality of spaced-apart first electrodes 162 in the plurality of capacitor accommodation slots 65 respectively, and at least a part of each first electrode 162 is located on the slot wall of the capacitor accommodation slot 65 and is connected to the other of the source and the drain;

[0252] Form a capacitive dielectric layer 164 covering the plurality of first electrodes 162 in the plurality of capacitor accommodation slots 65; and

[0253] Form a second electrode 163 covering the capacitive dielectric layer 164 and filling the plurality of capacitor accommodation slots 65.

[0254] In some embodiments of the present application, since a stable capacitive isolation structure 17 is formed at the intersection between the capacitive isolation portion 72 and the insulating layer 31, a capacitor 161 can be formed in the capacitor accommodation groove 65 defined by the capacitive isolation structure 17, which can reduce the risk of collapse during the manufacturing process of the capacitor 161.

[0255] In some embodiments, the first electrode 162, the capacitive dielectric layer 164, and the second electrode 163 can be formed respectively by the above-mentioned thin film deposition process. The plurality of first electrodes 162 are spaced apart from each other and are connected to the other of the source electrode and the drain electrode. The capacitive dielectric layer 164 is continuous. The plurality of second electrodes 163 are columnar.

[0256] Please continue to refer to Figure 11D As shown, the above method further includes the following steps: during the formation of the second electrode 163, a capacitive lead-out structure 165 filling the second through groove 62 is formed, and the capacitive lead-out structure 165 is connected to one second electrode 163.

[0257] As Figure 11D shown, after the formation of the capacitive lead-out structure 165, the above method further includes the following steps: removing the fourth mask layer 54.

[0258] Please refer to Figure 11E and Figure 1 shown, after the formation of the capacitive lead-out structure 165 filling the second through groove 62, continue to execute the above step S202. The above step S202 further includes step S2023, and step S2023 includes:

[0259] Forming a fifth mask layer 55, the fifth mask layer 55 includes a fifth mask opening 551, and the orthographic projection of the fifth mask opening 551 on the base layer 21 overlaps with the orthographic projections of the capacitive isolation portion 72, the insulating filling portion 71, and the initial gate conductive structure 134 on the base layer 21; and

[0260] Using the fifth mask opening 551 as a mask, forming a plurality of disconnection grooves 66 that penetrate through a plurality of insulating filling portions 71 along the first direction z and disconnect the initial gate conductive structure 134. The insulating filling portions 71 also extend into the capacitive isolation portion 72 along the third direction x, and each disconnection groove 66 extends along the third direction x and is located between two adjacent gate conductive portions 131.

[0261] In some embodiments of the present application, through step S2023, by forming the disconnection grooves 66, the disconnection grooves 66 disconnect the initial gate conductive structure 134 into a plurality of gate conductive portions 131. And the disconnection grooves 66 extend into the capacitive isolation portion 72, disconnecting a part of the semiconductor layer 32. While forming a plurality of semiconductor column protrusions 121, the first end 1121 of the semiconductor column 111 can be disconnected.

[0262] In some embodiments, please continue to refer to Figure 1 As shown, the above method further includes the following steps: filling the disconnection groove 66 with a disconnection portion 73.

[0263] In the third direction x, the disconnection portion 73 penetrates through the insulation filling portion 71 and extends into the capacitor isolation portion 72. The dimension of the disconnection portion 73 in the second direction y is smaller than the dimension of the insulation filling portion 71 in the second direction y. The dimension of the disconnection portion 73 in the second direction y is smaller than the dimension of the capacitor isolation portion 72 in the second direction y.

[0264] In some embodiments, the material of the disconnection portion 73 is the same as the materials of the insulation filling portion 71 and the capacitor isolation portion 72. For example, the disconnection portion 73 includes silicon oxide.

[0265] In the manufacturing method of a semiconductor device according to some embodiments of the present application, by forming a stacked structure on a base layer and forming structures such as a first gate groove, a second gate groove, and an isolation groove on the stacked structure to form transistors stacked along a first direction and capacitors connected to the transistors, the number of transistors and capacitors in the semiconductor device can be increased, and thus the number of memory cells in the semiconductor device can be increased. Moreover, by forming a plurality of capacitors in the capacitor accommodation groove, the risk of capacitor collapse can be reduced.

[0266] Please refer to Figure 12 As shown, which is a schematic structural diagram of a semiconductor device according to some other embodiments provided by the present application. Figure 12 The semiconductor device 100 shown is basically similar to the semiconductor device 100 shown in Figure 1 The differences include that at least one of the first capacitor isolation portion 171 and the second capacitor isolation portion 172 includes a curved sidewall in contact with the capacitor 161. In this way, the first electrode 162 and the second electrode 163 of the capacitor 161 also have a curved structure, which can increase the facing area between the first electrode 162 and the second electrode 163 and increase the capacitance value of the capacitor 161. On the basis of the increase in the capacitance value of the capacitor 161, the volume of the capacitor 161 can be reduced to increase the number of capacitors 161, thereby further improving the storage density of the semiconductor device 100.

[0267] As Figure 12As shown, in some embodiments, the first capacitance isolation portion 171 includes an insulating curved sidewall 171a in contact with the capacitor 161, and the insulating curved sidewall 171a extends along the first direction z. Thus, the first electrode 162 includes a first electrode curved sidewall 1621 in contact with the insulating curved sidewall 171a, the second electrode 163 includes a second electrode curved sidewall 1631 adapted to the first electrode curved sidewall 1621, and the capacitive dielectric layer includes a curved dielectric portion located between the first electrode curved sidewall 1621 and the second electrode curved sidewall 1631. The facing area between the first electrode 162 and the second electrode 163 increases, thereby increasing the capacitance value of the capacitor 161. The first capacitance isolation portion 171 may further include a planar sidewall connected to the insulating curved sidewall 171a.

[0268] In some embodiments, the shapes of the insulating curved sidewall 171a, the first electrode curved sidewall 1621, and the second electrode curved sidewall 1631 may be the same. The insulating curved sidewall 171a may include at least one of a circular arc curved sidewall and an elliptical arc curved sidewall. The insulating curved sidewall 171a protrudes outward toward the capacitor.

[0269] In some embodiments, the first capacitance isolation portion 171 may include a plurality of continuous insulating curved sidewalls 171a. The shapes of the plurality of continuous insulating curved sidewalls 171a may be the same or different.

[0270] In some embodiments, the first capacitance isolation portion 171 may be symmetrically disposed in the second direction y. In some embodiments, the first capacitance isolation portion 171 may be symmetrically disposed in the third direction x.

[0271] In some other embodiments, the second capacitance isolation portion 172 may include a curved sidewall in contact with the capacitor 161. In some other embodiments, both the first capacitance isolation portion 171 and the second capacitance isolation portion 172 may include curved sidewalls in contact with the capacitor 161.

[0272] In the semiconductor device according to some other embodiments of the present application, at least one of the first capacitance isolation portion 171 and the second capacitance isolation portion 172 includes a curved sidewall in contact with the capacitor 161. Thus, the first electrode 162 and the second electrode 163 of the capacitor 161 also have a curved structure, which can increase the facing area between the first electrode 162 and the second electrode 163 and increase the capacitance value of the capacitor 161. On the basis of increasing the capacitance value of the capacitor 161, the volume of the capacitor 161 can be reduced to increase the number of capacitors 161, thereby further improving the storage density of the semiconductor device 100.

[0273] Please refer to Figures 13A to 13D , which is a schematic structural diagram of the manufacturing process of the semiconductor device according to some other embodiments provided by the present application.

[0274] As Figure 13A shown, step S401 is performed.

[0275] Figure 13A The structure shown is substantially similar to Figure 11A the structure shown, and the differences between the two include that Figure 13A each isolation groove 63 of the structure shown includes a curved sidewall.

[0276] In some embodiments, the curved sidewall includes at least one of an arc-shaped curved sidewall and an elliptical arc-shaped curved surface. In some embodiments, the isolation groove 63 may further include a planar sidewall connected to the curved sidewall.

[0277] As Figures 13B to 13D shown, steps S402 to S404 are performed.

[0278] Figures 13B to 13D The corresponding process is substantially the same as Figures 11A to 11D that of, the differences being that, since the isolation groove 63 includes a curved sidewall, the capacitance isolation portion 72 filled in the isolation groove 63 also includes a curved sidewall, and correspondingly, the first capacitance isolation portion 171 formed via the capacitance isolation portion 72 includes an insulating curved sidewall 171a in contact with the capacitor 161.

[0279] As Figure 12 shown, step S2023 is performed. From Figure 13D the structure shown to obtain Figure 12 the structure shown, reference may be made to the description of the relevant steps of obtaining Figure 11D the structure shown above, which will not be elaborated here. Figure 1 shown.

[0280] In addition, referring to Figure 14 and Figure 15 shown, based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the above embodiments.

[0281] Among them, the storage system 400 can be applied to and encapsulated in different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having a storage.

[0282] In some embodiments, referring to Figure 14 as shown, the storage system 400 may include a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0283] Among them, the three-dimensional memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a three-dimensional memory, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0284] In other embodiments, referring to Figure 15 as shown, the storage system 400 may include multiple memories 200 and a controller 300. The storage system 400 is integrated into a Solid State Drive (SSD).

[0285] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low-duty-cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0286] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high-duty-cycle environment of an SSD or an eMMC, and the SSD or eMMC is used for data storage in mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0287] In some embodiments, the controller 300 may be configured to manage the data stored in the memory 200 and communicate with external devices (such as a host). In some embodiments, the controller 300 may also be configured to control the operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding the data stored in or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 300 is also configured to process the error correction code for the data read from or written to the memory 200.

[0288] Of course, the controller 300 can also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 can communicate with external devices (such as a host) through at least one of various interface protocols.

[0289] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0290] Please refer to Figure 16 , some embodiments of the present application also provide an electronic device 500. The electronic device 500 can be any one of a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device (such as a smart watch, smart bracelet, smart glasses, etc.), mobile power supply, game console, digital multimedia player, etc.

[0291] The electronic device 500 may include the above storage system 400 and the host 600, and the host 600 includes at least one of a Central Processing Unit (CPU) and a cache.

[0292] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor column array, comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction and extending along a third direction, wherein the plurality of semiconductor columns comprise a plurality of rows of semiconductor columns arranged along the first direction and a plurality of columns of semiconductor columns arranged along the second direction, and any two of the first direction, the second direction and the third direction intersect; as well as A gate structure is provided around side walls of a plurality of semiconductor pillars in a column of the semiconductor pillars extending along the third direction.

2. The semiconductor device according to claim 1, wherein, Each of the semiconductor pillars includes a first end and a second end opposite to each other in the third direction; The semiconductor device further comprises: a capacitor array, located on one side of the semiconductor column array in the third direction, and comprising a plurality of capacitors arranged in an array along the first direction and the second direction, wherein one of the capacitors is connected to the first end of one of the semiconductor columns; and The capacitor isolation structure is filled between adjacent capacitors.

3. The semiconductor device according to claim 2, wherein, One of the capacitors comprises: A first electrode extending along the third direction and contacting the capacitor isolation structure and connected to the first end of the semiconductor column; a second electrode extending along the third direction, wherein the first electrode surrounds a side wall of the second electrode extending along the third direction and a bottom wall of the second electrode close to the semiconductor column; and The capacitor dielectric layer is located between the first electrode and the second electrode.

4. The semiconductor device according to claim 3, wherein The semiconductor device further comprises: The capacitor lead-out structure is located on a side of the capacitor array away from the semiconductor pillar array in the third direction and is connected to the second electrodes of the plurality of capacitors.

5. The semiconductor device according to claim 2, wherein, The plurality of capacitors include a plurality of rows of capacitors arranged along the first direction and a plurality of columns of capacitors arranged along the second direction; The capacitive isolation structure comprises: a plurality of first capacitor isolation portions extending along the first direction and arranged along the second direction, each first capacitor isolation portion being located between two adjacent columns of the capacitors; as well as A plurality of second capacitor isolation portions extending along the second direction and arranged along the first direction, each of the second capacitor isolation portions being located between two adjacent rows of capacitors.

6. The semiconductor device according to claim 5, characterized in that, The plurality of second capacitor isolation parts intersect and are connected to the plurality of first capacitor isolation parts.

7. The semiconductor device according to claim 5, wherein At least one of the first capacitive isolation portion and the second capacitive isolation portion includes a curved sidewall in contact with the capacitor.

8. The semiconductor device according to claim 5, wherein A plurality of the gate structures are arranged along the second direction; The semiconductor device also includes a plurality of gate isolation structures extending along the first direction and the third direction and arranged along the second direction, each of the gate isolation structures being arranged between two adjacent gate structures and between two adjacent columns of the semiconductor columns, and the plurality of gate isolation structures being respectively connected to the plurality of the first capacitor isolation parts.

9. The semiconductor device according to claim 2, wherein The semiconductor device further comprises: A plurality of bit lines extending along the second direction and arranged along the first direction, the plurality of bit lines are located on a side of the semiconductor column array away from the capacitor array, and one bit line is connected to the second ends of a plurality of semiconductor columns in a row of the semiconductor columns.

10. The semiconductor device according to claim 9, characterized in that, A plurality of the bit lines are arranged in a stepped manner along the third direction.

11. The semiconductor device according to claim 9, wherein The semiconductor device further includes: A protective layer covering a plurality of the bit lines.

12. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A base layer located on one side of the semiconductor pillar array in the first direction, and the semiconductor pillar array and the gate structure are located on the base layer.

13. The semiconductor device according to claim 1, characterized in that, A plurality of the gate structures are arranged at intervals along the second direction, and one of the gate structures includes: A gate conductive portion extending along the first direction and disposed around sidewalls of a plurality of the semiconductor pillars in a column of the semiconductor pillars extending along the third direction; and A plurality of gate insulating portions disposed at intervals, each gate insulating portion surrounding a sidewall of a semiconductor pillar extending along the third direction and located between the gate conductive portion and a semiconductor pillar.

14. The semiconductor device according to claim 13, wherein, The gate conductive portion includes: A first gate conductive portion extending along the first direction and located between two adjacent columns of the semiconductor pillars; and A plurality of second gate conductive portions extending along the third direction and connected to the first gate conductive portion, and alternately arranged with a plurality of the semiconductor pillars in a column of the semiconductor pillars in the first direction, and a size of one of the second gate conductive portions along the third direction is greater than a size of the first gate conductive portion along the third direction.

15. The semiconductor device according to claim 14, wherein, One of the first gate conductive portions includes: A gate conductive intermediate portion extending along the first direction and the third direction; and Two gate conductive end portions extending along the first direction and the second direction, and respectively connected to opposite ends of the gate conductive intermediate portion in the third direction.

16. The semiconductor device according to claim 15, wherein, The semiconductor device further includes a plurality of gate isolation structures arranged at intervals along the second direction, each of the gate isolation structures being located between two adjacent gate structures and between two adjacent columns of the semiconductor pillars; One of the gate isolation structures includes: A first gate isolation portion extending along the first direction and located between two adjacent gate conductive intermediate portions of two adjacent gate conductive portions in the second direction; And Two second gate isolation portions extending along the first direction and respectively connected to opposite ends of the first gate isolation portion in the third direction, each of the second gate isolation portions being located between adjacent gate conductive end portions of two adjacent gate conductive portions in the second direction, and a size of the second gate isolation portion along the second direction is less than a size of the first gate isolation portion along the second direction.

17. The semiconductor device according to claim 15, wherein, The semiconductor device further includes: A semiconductor pillar protrusion array including a plurality of semiconductor pillar protrusion columns arranged in an array along the second direction and the third direction, each semiconductor pillar protrusion column including a plurality of semiconductor pillar protrusions arranged at intervals along the first direction, and one of the semiconductor pillar protrusions is adjacent to and connected to a sidewall of a semiconductor pillar extending along the third direction. Between two adjacent columns of the semiconductor pillars, there are provided two sets of semiconductor pillar protrusion columns which are adjacent and spaced along the second direction. One set of semiconductor pillar protrusion columns includes two semiconductor pillar protrusion columns which are spaced along the third direction. Between the two semiconductor pillar protrusion columns of one set of semiconductor pillar protrusion columns, there is provided one first gate conductive part. The multiple semiconductor pillar protrusions of the two semiconductor pillar protrusion columns of one set of semiconductor pillar protrusion columns are connected to the multiple semiconductor pillars of one column of semiconductor pillars; and Each second gate isolation part is disposed between two semiconductor pillar protrusion columns which are located between two adjacent columns of semiconductor pillars and are adjacent in the second direction.

18. A method for manufacturing a semiconductor device, characterized in that, The method includes: Forming a stacked structure on the surface of the base layer in the first direction, the stacked structure including multiple semiconductor layers and multiple insulating layers which are alternately arranged along the first direction; and Forming multiple first gate trenches which penetrate the stacked structure along the first direction and are spaced along the second direction. The remaining multiple semiconductor layers include multiple initial semiconductor pillars which are arranged in an array along the first direction and the second direction and extend along the third direction. Each initial semiconductor pillar includes a first end and a second end which are opposite to each other in the third direction.

19. The manufacturing method of the semiconductor device according to claim 18, characterized in that, The method further includes: Removing a part of the insulating layer around each first gate trench through the multiple first gate trenches to form multiple second gate trenches. Each second gate trench penetrates the insulating layer between two adjacent first gate trenches along the second direction; and Forming a gate structure in the first gate trenches and the second gate trenches.

20. The manufacturing method of the semiconductor device according to claim 19, characterized in that, The forming a gate structure in the first gate trenches and the second gate trenches includes: Forming multiple spaced gate insulating parts. Each gate insulating part is located in the first gate trenches and the second gate trenches and extends along the side wall of an initial semiconductor pillar along the third direction; Forming an initial gate conductive structure which fills the multiple second gate trenches and is located on the side walls of the multiple first gate trenches. The multiple gate insulating parts are located between the initial gate conductive structure and the multiple initial semiconductor pillars; and Disconnecting the initial gate conductive structure into multiple gate conductive parts which extend along the first direction and are arranged along the second direction. One gate conductive part is disposed around the side walls of the multiple initial semiconductor pillars of one column of initial semiconductor pillars along the third direction.

21. The manufacturing method of the semiconductor device according to claim 20, wherein, After forming the initial gate conductive structure which fills the multiple second gate trenches and is located on the side walls of the multiple first gate trenches, the method further includes: Respectively filling multiple insulating filling parts in the remaining spaces of the multiple first gate trenches; The disconnecting the initial gate conductive structure into multiple gate conductive parts arranged along the second direction includes: Forming multiple disconnecting trenches which penetrate the multiple insulating filling parts along the first direction and disconnect the initial gate conductive structure. Each disconnecting trench extends along the third direction and is located between two adjacent gate conductive parts; The method further includes: filling a disconnection portion in the disconnection groove.

22. The manufacturing method of the semiconductor device according to claim 18, characterized in that, The plurality of initial semiconductor pillars include multiple rows of the initial semiconductor pillars arranged along the first direction and multiple columns of the initial semiconductor pillars arranged along the second direction. The method further includes: forming a first through groove that penetrates the stacked structure along the first direction and extends along the second direction, the first through groove being located on one side of the plurality of initial semiconductor pillars in the third direction and exposing a first end of the plurality of initial semiconductor pillars in the third direction; conductifying a first end of the plurality of initial semiconductor pillars to form one of a source electrode and a drain electrode; and forming a plurality of bit lines that extend along the second direction and are spaced apart along the first direction on one side of one of the source electrode and the drain electrode in the third direction, each bit line being connected to one of the source electrode and the drain electrode, and the first through groove exposing the plurality of bit lines.

23. The manufacturing method of the semiconductor device according to claim 22, wherein, The method further includes: forming a protective layer that fills the first through groove and covers the plurality of bit lines.

24. The manufacturing method of the semiconductor device according to claim 18, wherein, The method further includes: forming a plurality of isolation grooves that penetrate the stacked structure along the first direction and are arranged along the second direction, the plurality of isolation grooves being located on one side of the plurality of first gate grooves in the third direction and being spaced apart from the plurality of first gate grooves, and the plurality of isolation grooves being adjacent to a second end of the plurality of initial semiconductor pillars; respectively filling a plurality of capacitive isolation portions in the plurality of isolation grooves, and removing the semiconductor layer around the capacitive isolation portions except for the plurality of initial semiconductor pillars, the plurality of capacitive isolation portions and the remaining insulating layer defining a plurality of capacitor accommodation grooves that are spaced apart; conductifying a second end of the plurality of initial semiconductor pillars to form the other of the source electrode and the drain electrode; and respectively forming a plurality of capacitors in the plurality of capacitor accommodation grooves, each capacitor being connected to the other of the source electrode and the drain electrode.

25. The manufacturing method of the semiconductor device according to claim 24, wherein, The forming a plurality of capacitors in the plurality of capacitor accommodation grooves includes: respectively forming a plurality of first electrodes that are spaced apart in the plurality of capacitor accommodation grooves, at least a part of each first electrode being located on the groove wall of the capacitor accommodation groove and being connected to the other of the source electrode and the drain electrode; forming a capacitive dielectric layer that covers the plurality of first electrodes in the plurality of capacitor accommodation grooves; and forming a second electrode that covers the capacitive dielectric layer and fills the plurality of capacitor accommodation grooves.

26. The manufacturing method of the semiconductor device according to claim 24, characterized in that, Before removing the semiconductor layer around the capacitive isolation portions except for the plurality of initial semiconductor pillars, the method further includes: forming a second through groove that penetrates the stacked structure along the first direction and extends along the second direction, the second through groove being located on a side of the plurality of isolation grooves away from the first gate grooves in the third direction and exposing the plurality of capacitive isolation portions; The method further includes: during the process of forming the second electrode, forming a capacitive lead-out structure that fills the second through groove, the capacitive lead-out structure being connected to the second electrode.

27. A storage system, characterized in that, The storage system includes: a semiconductor device according to any one of claims 1-17; A controller, the controller being connected to the semiconductor device and used for controlling the semiconductor device to store data.

Images