Semiconductor device

Abstract

A semiconductor device may include: a substrate; an active pattern on the substrate; and a word line structure across the active pattern. The word line structure may include: a word line; a capping pattern on the word line; and a protective insulating pattern between the word line and the capping pattern.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority of Korean Patent Application No. 10 - 2024 - 0002221, filed with the Korean Intellectual Property Office on January 5, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present inventive concept relates to semiconductor devices, and more particularly, to semiconductor memory devices. Background art

[0004] Semiconductor devices are regarded as an important part of the electronics industry due to their small size, multi - functionality, and / or low cost. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory and logic elements.

[0005] Due to the growing demand for high speed and / or low power consumption of electronic devices in recent years, semiconductor devices need to have a fast operation speed and / or a low operation voltage. To meet this requirement, the integration density of semiconductor devices must be increased. As the integration density of semiconductor devices increases, the electrical characteristics and reliability characteristics of semiconductor devices may deteriorate. Therefore, many studies are being conducted to improve the electrical characteristics and reliability characteristics of semiconductor devices. Summary of the invention

[0006] Some example embodiments of the present inventive concept provide semiconductor devices having improved electrical characteristics and reliability characteristics.

[0007] According to some example embodiments of the present inventive concept, a semiconductor device may include: a substrate; an active pattern on the substrate; and a word - line structure spanning the active pattern. The word - line structure may include: a word - line; a capping pattern on the word - line; and a protective insulating pattern between the word - line and the capping pattern.

[0008] According to some example embodiments of the present inventive concept, a semiconductor device may include: a substrate; a device isolation pattern on the substrate; an active pattern on the substrate, the active pattern being surrounded by the device isolation pattern; and a word - line structure spanning the device isolation pattern and the active pattern in a first direction, the first direction being parallel to the top surface of the substrate. The word - line structure may include: a word - line; a capping pattern on the word - line; a protective insulating pattern on the word - line such that the protective insulating pattern surrounds the bottom surface and side surfaces of the capping pattern. The word - line may have a first width in a second direction, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction, and the bottom surface of the capping pattern may have a second width in the second direction. The second width may be less than the first width.

[0009] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a device isolation pattern on the substrate; an active pattern on the substrate, the active pattern being surrounded by the device isolation pattern; a word line structure extending across the active pattern and the device isolation pattern in a first direction parallel to a top surface of the substrate; a bit line on the active pattern and extending in a second direction intersecting the first direction; a bit line contact between the active pattern and the bit line; a storage node contact on the active pattern; a landing pad on the storage node contact; and a capacitor on the landing pad. The word line structure may include: a first conductive pattern; a second conductive pattern on the first conductive pattern; a capping pattern on the second conductive pattern; and a protective insulating pattern between the second conductive pattern and the capping pattern. The protective insulating pattern may include: a first vertical portion; a second vertical portion; and a horizontal portion connecting the first vertical portion to the second vertical portion. The first vertical portion and the second vertical portion may contact side surfaces of the capping pattern, and the horizontal portion may contact a bottom surface of the capping pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor device according to some example embodiments of the inventive concept.

[0011] Figure 2 is a plan view illustrating a semiconductor device according to some example embodiments of the inventive concept and corresponding to Figure 1 section “P1”.

[0012] Figure 3A , Figure 3B and Figure 3C are cross-sectional views illustrating a semiconductor device according to some example embodiments of the inventive concept taken along lines A-A', B-B', and C-C' of Figure 2 respectively.

[0013] Figure 4 is an enlarged view corresponding to Figure 3A section “P2” of

[0014] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A ,Figure 12B , Figure 13A and Figure 13B are cross-sectional views showing processes of manufacturing semiconductor devices according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0015] Some example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. The drawings and the description are to be considered illustrative in nature and not restrictive. Throughout the specification, like reference numerals represent like elements. The dimensions and thicknesses of each component in the drawings are arbitrarily shown for better understanding and convenient description, and the following embodiments are not limited thereto.

[0016] Throughout the specification, the term "connected" not only means that two or more components are directly connected, but also means that two or more components are indirectly connected through another component. Additionally, unless explicitly described to the contrary, the words "comprising" and variants such as "containing" or "including" will be understood to imply the inclusion of the stated elements, but not the exclusion of any other elements.

[0017] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Further, when an element is referred to as being "above" or "on" a reference element, it can be above or below the reference element and is not necessarily referred to as being "above" or "on" in the opposite direction of gravity.

[0018] Moreover, throughout the specification, the phrase "in a plan view" or "on a plane" means observing the target portion from the top, and the phrase "in a cross-sectional view" or "on a cross-section" means observing a cross-section formed by vertically cutting the target portion from the side.

[0019] It should be understood that elements and / or their characteristics (e.g., structure, surface, direction, etc.) referred to as "perpendicular", "parallel", "coplanar", etc. with respect to other elements and / or their characteristics (e.g., structure, surface, direction, etc.) can be "perpendicular", "parallel", "coplanar", etc. respectively with respect to other elements and / or their characteristics, or can be "substantially perpendicular", "substantially parallel", "substantially coplanar".

[0020] Elements and / or their characteristics (e.g., structures, surfaces, orientations, etc.) that are "substantially perpendicular", "substantially parallel", or "substantially coplanar" relative to other elements and / or their characteristics are to be understood as being "perpendicular", "parallel", or "coplanar" respectively relative to other elements and / or their characteristics within manufacturing tolerances and / or material tolerances, and / or having a deviation in size and / or angle relative to other elements and / or their characteristics from "perpendicular", "parallel", or "coplanar" that is equal to or less than 10% (e.g., a tolerance of ±10%).

[0021] It should be understood that an element and / or its characteristic may be described herein as "equivalent", "identical", or "equal" to another element, and it should also be understood that an element and / or its characteristic described herein as "equivalent", "identical", or "equal" to another element may be "equivalent", "identical", or "equal" or "substantially equivalent", "substantially identical", or "substantially equal" to the other element and / or its characteristic. An element and / or its characteristic that is "substantially equivalent", "substantially identical", or "substantially equal" to another element and / or its characteristic is to be understood as including an element and / or its characteristic that is equivalent, identical, or equal to the other element and / or its characteristic within manufacturing tolerances and / or material tolerances. An element and / or its characteristic that is equivalent or substantially equivalent, equal or substantially equal, and / or identical or substantially identical to another element and / or its characteristic may be the same or substantially the same in structure, the same or substantially the same in function, and / or the same or substantially the same in composition. Although the terms "identical", "equal", or "equivalent" are used in the description of some example embodiments, it should be understood that there may be some imprecision. Thus, when an element or characteristic is said to be equivalent, equal, or identical to another element or characteristic, it should be understood that the element or characteristic is the same as the other element or characteristic within the required manufacturing or operating tolerances (e.g., ±10%).

[0022] It should be understood that the "substantially" identical, equal, and / or equivalent elements and / or their characteristics described herein encompass elements and / or their characteristics having a relative difference in magnitude that is equal to or less than 10%. Additionally, whether or not the element and / or its characteristic is modified with "substantially", it should be understood that these elements and / or their characteristics are to be interpreted as including the manufacturing or operating tolerances (e.g., ±10%) of the element and / or its characteristic.

[0023] When the terms "about" or "substantially" are used in combination with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operating tolerances in the vicinity of the stated numerical value (e.g., ±10%). In addition, when the words "about" and "substantially" are used in combination with a geometric shape, it is intended that the precision of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. Further, whether the numerical value or the shape is modified with "about" or "substantially", it should be understood that these values and shapes should be interpreted to include manufacturing or operating tolerances in the vicinity of the stated numerical value or shape (e.g., ±10%). When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0024] As described herein, when describing an operation to be performed or describing an effect such as a structure being established "by" or "via" performing additional operations, it should be understood that the operation and / or the effect / structure can be performed "based on" the additional operations, which can include performing the additional operations alone or in combination with other additional operations.

[0025] Figure 1 is a block diagram of a semiconductor device showing some example embodiments according to the inventive concept.

[0026] Referring to Figure 1 , the semiconductor device may include a cell block CB and a peripheral block PB surrounding each cell block CB. Each cell block CB may include cell circuits, such as memory integrated circuits. The peripheral block PB may include various peripheral circuits for operating the cell circuits, and the peripheral circuits may be electrically connected to the cell circuits.

[0027] The peripheral block PB may include a sense amplifier circuit SA and a sub-word line driver circuit SWD. In some example embodiments, the sense amplifier circuits SA may be arranged to face each other with a cell block CB therebetween, and the sub-word line driver circuits SWD may be arranged to face each other with a cell block CB therebetween. The peripheral block PB may also include power and ground circuits for driving the sense amplifiers, but the inventive concept is not limited to this example.

[0028] Figure 2 is a plan view of a semiconductor device showing some example embodiments according to the inventive concept and corresponding to Figure 1 the portion "P1". Figure 3A , Figure 3B and Figure 3C are cross-sectional views of a semiconductor device showing some example embodiments according to the inventive concept taken along the lines A-A', B-B' and C-C' of Figure 2 respectively. Figure 4 is according to some example embodiments of the inventive concept and related to Figure 3AAn enlarged view corresponding to a portion “P2”.

[0029] Referring to Figure 2 and Figures 3A to 3C , a substrate 100 can be provided. The substrate 100 can be a semiconductor substrate (e.g., a silicon wafer, a germanium wafer, or a silicon-germanium wafer).

[0030] A device isolation pattern 120 can be provided on the substrate 100 to define an active pattern ACT (e.g., such that an outer surface of the device isolation pattern 120 contacts the substrate 100). The active pattern ACT can be provided on Figure 1 a cell block CB of . The active patterns ACT can be spaced apart from each other in a first direction D1 and a second direction D2. The active patterns ACT can be strip patterns or island patterns that are spaced apart from each other and elongated in a third direction D3.

[0031] In the present specification, the first direction D1 can be defined as a direction parallel to a top surface of the substrate 100 and / or an in-plane direction of the substrate 100. The second direction D2 can be defined as a direction parallel to the top surface of the substrate 100 and / or the in-plane direction of the substrate 100 and perpendicular to the first direction D1. The third direction D3 can be defined as a direction parallel to the top surface of the substrate 100 and / or the in-plane direction of the substrate 100 and not parallel to the first direction D1 and the second direction D2. The fourth direction D4 can be defined as a direction perpendicular to the top surface of the substrate 100 and / or the in-plane direction of the substrate 100.

[0032] The active pattern ACT can have a shape protruding in the fourth direction D4. In some exemplary embodiments, the device isolation pattern 120 can be provided in the substrate 100, and the active pattern ACT can be a portion of the substrate 100 surrounded by the device isolation pattern 120. For convenience of explanation, unless otherwise specified, the term “substrate 100” can refer to a remaining portion of the substrate 100 other than the active pattern ACT, such that the active pattern ACT can be referred to as being “on” the substrate 100 (e.g., a remaining portion of the substrate 100 other than the device isolation pattern 120 and a portion of the substrate 100 surrounded by the device isolation pattern 120).

[0033] The device isolation pattern 120 can be formed of at least one insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof) or include at least one insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof). The device isolation pattern 120 can be a single layer made of a single material or a composite layer including two or more materials.

[0034] Each active pattern ACT may include a pair of edge portions 111 and a central portion 112. The pair of edge portions 111 may be opposite ends of the active pattern ACT in the third direction D3. The central portion 112 may be a portion of the active pattern ACT located between the pair of edge portions 111, and specifically, the central portion 112 may be a portion of the active pattern ACT located between a pair of word line structures WLS, which will be described below. The pair of edge portions 111 and / or the central portion 112 may be doped with impurities to have n-type or p-type conductivity.

[0035] The word line structure WLS may be disposed to straddle the active pattern ACT. In some example embodiments, the word line structure WLS may be disposed to straddle the active pattern ACT and the device isolation pattern 120 in the first direction D1. In some example embodiments, a plurality of word line structures WLS may be provided. The word line structures WLS may be spaced apart from each other in the second direction D2. In some example embodiments, a pair of word line structures WLS adjacent to each other in the second direction D2 may be disposed to straddle one active pattern ACT, and each word line structure WLS may at least partially overlap the one active pattern ACT in the fourth direction D4.

[0036] The word line structure WLS may be disposed in a trench region TR, which is formed to straddle the active pattern ACT and the device isolation pattern 120. The trench region TR may extend in the first direction D1. The trench region TR may include a first trench region TR1 and a second trench region TR2. The bottom surface of the first trench region TR1 may be disposed at a level higher than the bottom surface of the second trench region TR2. In this specification, the term "level" may be defined as the height measured from the bottom surface of the substrate 100 (e.g., the distance measured from the bottom surface of the substrate 100 in the fourth direction D4). The first trench region TR1 may be disposed on the active pattern ACT, and the second trench region TR2 may be disposed on the device isolation pattern 120.

[0037] Each word line structure WLS may include a word line WL, a protective insulating pattern OL, and a gate capping pattern GC. The word line structure WLS may be disposed in the trench region TR that straddles the active pattern ACT and the device isolation pattern 120.

[0038] The word line WL may be disposed at the lowermost portion of the word line structure WLS. In this specification, the word line WL may be referred to as the gate electrode WL. The word line WL may include a first conductive pattern GE1 and a second conductive pattern GE2, which are sequentially stacked on the trench region TR (e.g., on the bottom surface of the trench region TR).

[0039] The first conductive pattern GE1 may include a metal material and a nitride material including the metal material (e.g., a separate nitride material). In some example embodiments, the metal material may be formed of or include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), ruthenium (Ru), or iridium (Ir). The second conductive pattern GE2 may be formed of or include doped polysilicon.

[0040] The gate capping pattern GC may be disposed on the word line WL to fill the upper portion of the trench region TR. In some example embodiments, the gate capping pattern GC may be formed of or include silicon nitride.

[0041] The protective insulating pattern OL may be disposed on the word line WL to surround the bottom surface and side surfaces of the gate capping pattern GC (e.g., contacting some or all of the bottom surface and side surfaces of the gate capping pattern GC). For example, the protective insulating pattern OL may be disposed between the word line WL and the gate capping pattern GC (e.g., directly or indirectly disposed between the word line WL and the gate capping pattern GC). The second conductive pattern GE2 may be spaced apart from the gate capping pattern GC with the protective insulating pattern OL interposed therebetween. The protective insulating pattern OL may include an insulating material, and in some example embodiments, it may be formed of or include silicon oxide (e.g., SiO2).

[0042] The gate insulating pattern GI may be disposed to conformally cover the inner surface of the trench region TR. Specifically, the gate insulating pattern GI may be interposed between the word line WL and the active pattern ACT, between the protective insulating pattern OL and the active pattern ACT, between the word line WL and the device isolation pattern 120, and between the protective insulating pattern OL and the device isolation pattern 120. In other words, the protective insulating pattern OL may be disposed between the gate insulating pattern GI and the gate capping pattern GC. As Figure 3A and Figure 4 shown, the top surface of the protective insulating pattern OL may be located at the same or substantially the same level as the top surfaces of the gate insulating pattern GI and the gate capping pattern GC. The gate insulating pattern GI may be formed of or include at least one of silicon oxide, a high-k dielectric material, or a combination thereof.

[0043] Referring to Figure 4 , the protective insulating pattern OL may include a first vertical portion V1, a second vertical portion V2, and a horizontal portion H connecting the first vertical portion V1 to the second vertical portion V2.

[0044] The first vertical portion V1 and the second vertical portion V2 may be disposed on the word line WL to contact separate side surfaces of the gate capping pattern GC, respectively. The first vertical portion V1 and the second vertical portion V2 may be disposed between the gate insulating pattern GI and the gate capping pattern GC (e.g., directly or indirectly between the gate insulating pattern GI and the gate capping pattern GC).

[0045] The horizontal portion H may be disposed between the second conductive pattern GE2 and the gate capping pattern GC (e.g., directly or indirectly between the second conductive pattern GE2 and the gate capping pattern GC). The top surface of the horizontal portion H may contact the bottom surface of the gate capping pattern GC. The bottom surface of the horizontal portion H may contact the top surface of the second conductive pattern GE2. In other words, the second conductive pattern GE2 may be disposed between the first conductive pattern GE1 and the horizontal portion H (e.g., directly or indirectly between the first conductive pattern GE1 and the horizontal portion H).

[0046] The word line WL may have a first width W1 in the second direction D2. The bottom surface of the gate capping pattern GC may have a second width W2 in the second direction D2. Since the protective insulating pattern OL surrounds the gate capping pattern GC, the second width W2 may be less than the first width W1. That is, the maximum width of the gate capping pattern GC in the second direction D2 may be less than the maximum width of the word line WL in the second direction D2.

[0047] Here, the thickness TH of the protective insulating pattern OL may be 5% to 40% of the first width W1. The first width W1 may be substantially equal to the sum of the second width W2 and twice the thickness TH of the protective insulating pattern OL.

[0048] When measured in the second direction D2, the sum of the thickness TH of the protective insulating pattern OL and the thickness GI-t of the gate insulating pattern GI (e.g., the first portion GI-1 of the gate insulating pattern GI located above the word line WL in the fourth direction D4) disposed on the word line WL may be greater than the thickness of the gate insulating pattern GI (e.g., the second portion GI-2 of the gate insulating pattern GI located below the protective insulating pattern OL in the fourth direction D4) disposed below the protective insulating pattern OL.

[0049] The buffer pattern 210 may be disposed on the substrate 100. The buffer pattern 210 may cover the active pattern ACT, the device isolation pattern 120, and the word line structure WLS. Here, the buffer pattern 210 may be in contact with the protective insulating pattern OL. In some example embodiments, the buffer pattern 210 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The buffer pattern 210 may be a single layer made of a single material, or a composite layer including two or more materials.

[0050] The bit line contact DC may be disposed on each active pattern ACT, and in some example embodiments, a plurality of bit line contacts DC may be disposed. The bit line contact DC may be respectively connected to the central portion 112 of the active pattern ACT. In this specification, the expression "A is connected to B" may be used not only to mean "A is in contact with B", but also to mean "A is electrically connected to B", even though they are not in physical contact with each other. The bit line contacts DC may be spaced apart from each other in the first direction D1 and the second direction D2. The bit line contact DC may be interposed between each active pattern ACT and a corresponding one of the bit lines BL, which will be described below. Each bit line contact DC may connect a corresponding one of the bit lines BL to the central portion 112 of a corresponding one of the active patterns ACT.

[0051] The bit line contact DC may be respectively disposed in the first recessed region RS1. The first recessed region RS1 may be disposed in the upper portion of the active pattern ACT and the upper portion of the device isolation pattern 120 adjacent to the upper portion of the active pattern ACT. The first recessed regions RS1 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0052] The gap-fill insulating pattern 250 may fill each first recessed region RS1. The gap-fill insulating pattern 250 may fill the internal space of the first recessed region RS1. As an example, the gap-fill insulating pattern 250 may cover at least a part of the inner surface of the first recessed region RS1 and the side surface of the bit line contact DC (e.g., in the first recessed region RS1). The gap-fill insulating pattern 250 may be formed of at least one of silicon oxide, silicon nitride, or a combination thereof, or may include at least one of silicon oxide, silicon nitride, or a combination thereof. The gap-fill insulating pattern 250 may be a single layer made of a single material, or a composite layer including two or more materials.

[0053] The bit line BL can be disposed on the bit line contact portion DC. The bit line BL can extend along the second direction D2. The bit line BL can be disposed on the bit line contact portion DC, and the bit line contact portion DC is arranged along the second direction D to form a line. In some example embodiments, a plurality of bit lines BL can be provided. The bit lines BL can be spaced apart from each other in the first direction D1. The bit line BL can include a metal material. For example, the bit line BL can be formed of or include at least one of tungsten, rubidium, molybdenum, titanium, or a combination thereof.

[0054] The polysilicon pattern 310 can be disposed between the bit line BL and the buffer pattern 210, and between the bit line contact portions DC adjacent to each other in the second direction D2. In some example embodiments, a plurality of polysilicon patterns 310 can be provided. The polysilicon patterns 310 can be spaced apart from each other in the first direction D1 and the second direction D2. The top surface of the polysilicon pattern 310 can be located at substantially the same height as the top surface of the bit line contact portion DC and can be coplanar with the top surface of the bit line contact portion DC. The polysilicon pattern 310 can be formed of or include doped polysilicon.

[0055] The first barrier pattern 320 can be disposed between the bit line BL and the bit line contact portion DC, and between the bit line BL and the polysilicon pattern 310. The first barrier pattern 320 can extend along the bit line BL or the second direction D2. In some example embodiments, a plurality of first barrier patterns 320 spaced apart from each other can be provided. The first barrier patterns 320 can be spaced apart from each other in the first direction D1. The first barrier pattern 320 can be formed of or include at least one of conductive metal nitride materials (e.g., titanium nitride and tantalum nitride). A first ohmic pattern (not shown) can additionally be interposed between the bit line BL and the bit line contact portion DC, and between the bit line BL and the polysilicon pattern 310. The first ohmic pattern can be formed of or include at least one metal silicide material.

[0056] The bit line capping pattern 350 can be disposed on the top surface of the bit line BL. On the top surface of the bit line BL, the bit line capping pattern 350 can extend along the second direction D2. In some example embodiments, a plurality of bit line capping patterns 350 can be provided. The bit line capping patterns 350 can be spaced apart from each other in the first direction D1. The bit line capping pattern 350 can vertically overlap the bit line BL. The bit line capping pattern 350 can be composed of a single layer or multiple layers.

[0057] The bit line spacer 360 may be disposed on the side surfaces of the bit line BL and the bit line capping pattern 350. The bit line spacer 360 may cover the side surfaces of the bit line BL and the bit line capping pattern 350. The bit line spacer 360 on the side surface of the bit line BL may extend in the second direction D2. In some example embodiments, a plurality of bit line spacers 360 may be provided. The bit line spacers 360 may be spaced apart from each other in the first direction D1.

[0058] Each bit line spacer 360 may include a plurality of spacers. As an example, each bit line spacer 360 may include a first spacer 362, a second spacer 364, and a third spacer 366. The first spacer 362 may be disposed on the side surfaces of the bit line BL and the bit line capping pattern 350. The third spacer 366 may be disposed on the side surfaces of the storage node contact BC and the second barrier pattern 410, which will be described below. The second spacer 364 may be interposed between the first spacer 362 and the third spacer 366. In some example embodiments, each of the first through third spacers 362, 364, and 366 may be independently formed of or include at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In some example embodiments, the second spacer 364 may include an air gap that separates the first spacer 362 from the third spacer 366.

[0059] The capping spacer 370 may be placed on the bit line spacer 360. In some example embodiments, the capping spacer 370 may be formed of or include silicon nitride.

[0060] The storage node contact BC may be disposed between adjacent bit lines BL in the bit line BL. As an example, the storage node contact BC may be interposed between adjacent bit line spacers 360 among the bit line spacers 360. In some example embodiments, a plurality of storage node contacts BC may be provided. The storage node contacts BC may be spaced apart from each other in the first direction D1 and the second direction D2. The storage node contacts BC may be spaced apart from each other in the first direction D1 by the fence pattern FN on the word line structure WLS. The fence pattern FN may be disposed between adjacent bit lines BL in the bit line BL. In some example embodiments, a plurality of fence patterns FN may be provided. The fence patterns FN may be spaced apart from each other in the first direction D1 and the second direction D2. The fence patterns FN adjacent to each other in the first direction D1 may be spaced apart from each other with the bit line BL interposed therebetween. The fence patterns FN adjacent to each other in the second direction D2 may be spaced apart from each other with the storage node contact BC interposed therebetween. In some example embodiments, the fence pattern FN may be formed of or include silicon nitride.

[0061] The storage node contact portion BC may fill and be disposed in a second recessed region RS2 provided on an edge portion 111 of the active pattern ACT. The storage node contact portion BC may be connected to the edge portion 111. The storage node contact portion BC may be formed of at least one of doped or undoped polysilicon, a metal material, or a combination thereof, or may include at least one of doped or undoped polysilicon, a metal material, or a combination thereof.

[0062] The second barrier pattern 410 may conformally cover the bit line spacer portion 360 and the storage node contact portion BC. The second barrier pattern 410 may be formed of at least one of metal nitride materials (e.g., titanium nitride and tantalum nitride), or may include at least one of metal nitride materials (e.g., titanium nitride and tantalum nitride). A second ohmic pattern (not shown) may also be interposed between the second barrier pattern 410 and the storage node contact portion BC. The second ohmic pattern may be formed of at least one of metal silicide materials, or may include at least one of metal silicide materials.

[0063] The landing pad LP may be disposed on the storage node contact portion BC. In some example embodiments, a plurality of landing pads LP may be provided. The landing pads LP may be spaced apart from each other in a first direction D1 and a second direction D2. The landing pads LP may be electrically connected to corresponding storage node contact portions BC. The landing pads LP may cover a top surface of the bit line capping pattern 350. A lower region of the landing pad LP may vertically overlap the storage node contact portion BC. An upper region of the landing pad LP may be offset from the lower region in the first direction D1. The landing pad LP may be formed of at least one of metal materials (e.g., tungsten, titanium, and tantalum), or may include at least one of metal materials (e.g., tungsten, titanium, and tantalum).

[0064] The filling pattern 440 may be provided to surround the landing pad LP. The filling pattern 440 may be interposed between adjacent landing pads LP among the landing pads LP. When observed in a plan view, the filling pattern 440 may be provided in a grid shape having holes, and in this case, the landing pads LP may be disposed in the holes to penetrate the filling pattern 440. As an example, the filling pattern 440 may be formed of at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, or may include at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. As another example, the filling pattern 440 may include a blank space (i.e., an air gap) having an air layer.

[0065] The data storage pattern DSP may be disposed on the landing pad LP. In some example embodiments, a plurality of data storage patterns DSP may be disposed. The data storage patterns DSP may be spaced apart from each other in the first direction D1 and the second direction D2. Each data storage pattern DSP may be connected to a corresponding one of the edge portions 111 through a corresponding one of the landing pads LP and a corresponding one of the storage node contacts BC.

[0066] In some example embodiments, the data storage pattern DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device may be a dynamic random access memory device (DRAM). As another example, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor memory device may be a magnetic random access memory device (MRAM). As other examples, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor memory device may be a phase change random access memory device (PRAM) or a resistance random access memory device (ReRAM). However, the inventive concept is not limited to these examples, and the data storage pattern DSP may include various structures and / or materials that can be used to store data therein.

[0067] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B 1 is a cross-sectional view showing a process of manufacturing a semiconductor device according to some example embodiments of the present inventive concept. In detail, Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A is with Figure 2 A cross-sectional view corresponding to the line AA'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B ,Figure 10B , Figure 11B , Figure 12B and Figure 13B is a cross-sectional view corresponding to line B-B' of Figure 2 .

[0068] Referring to Figure 5A and Figure 5B , the substrate 100 can be fabricated. The device isolation pattern 120 can be formed to be embedded in the upper portion of the substrate 100. Forming the device isolation pattern 120 can include: patterning the upper portion of the substrate 100 to form isolation trenches; and forming the device isolation pattern 120 to fill the isolation trenches. The remaining portion of the upper portion of the substrate 100 surrounded by the device isolation pattern 120 can be defined as the active pattern ACT. Impurity regions can be formed in the active pattern ACT. Forming the impurity regions can include: implanting impurities into the active pattern ACT through an ion implantation process.

[0069] A mask layer (not shown) and a carbon thin layer (not shown) can be formed on the active pattern ACT and the device isolation pattern 120. The mask layer (not shown) can be formed closer to the substrate 100 than the carbon thin layer (not shown). Subsequently, a carbon thin pattern ACL and a mask pattern MP can be formed by patterning the carbon thin layer (not shown) and the mask layer (not shown). The carbon thin pattern ACL and the mask pattern MP can define the region where the word line structure WLS will be formed.

[0070] Referring to Figure 6A and Figure 6B , the upper portion of the active pattern ACT and the upper portion of the device isolation pattern 120 can be etched using the carbon thin pattern ACL as an etch mask. A trench region TR can be formed on the substrate 100 through an etching process. The trench region TR can extend along a first direction D1 and can be spaced apart from each other in a second direction D2. Here, the bottom surface of each trench region TR can be formed to have an uneven shape. In some example embodiments, the trench region TR can include a first trench region TR1 on the active pattern ACT and a second trench region TR2 on the device isolation pattern 120. The bottom surface of the first trench region TR1 can be formed at a level higher than the bottom surface of the second trench region TR2. When the etching process is performed, the etching rates of the active pattern ACT and the device isolation pattern 120 may be different from each other, and thus, the bottom surfaces of the first trench region TR1 and the second trench region TR2 can be formed at different levels.

[0071] Due to the trench region TR, each active pattern ACT can be divided into a central portion 112 and a pair of edge portions 111, as Figure 3CAs shown, a pair of edge portions 111 may be defined in the opposite edge regions of each active pattern ACT. A central portion 112 may be defined between a pair of trench regions TR. Thereafter, the thin carbon pattern ACL may be removed.

[0072] A gate insulating layer GIL may be conformally formed on the substrate 100. Specifically, the gate insulating layer GIL may conformally cover (e.g., may contact) the inner surfaces of the trench regions TR, and may extend along the side surfaces of the active patterns ACT and the side surfaces of the device isolation pattern 120 (e.g., on the side surfaces of the active patterns ACT and the device isolation pattern 120, directly on the side surfaces of the active patterns ACT and the device isolation pattern 120, etc.) to cover the top surface and the side surfaces of the mask pattern MP. The gate insulating layer GIL may be formed using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0073] Referring to Figure 7A and Figure 7B , a first conductive layer GEL1 may be formed to fill the trench regions TR. In some exemplary embodiments, the first conductive layer GEL1 may be formed to fill the trench regions TR and cover the mask pattern MP and the gate insulating layer GIL. Forming the first conductive layer GEL1 may include performing a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0074] Referring to Figure 8A and Figure 8B , the upper portion of the first conductive layer GEL1 may be etched to form a plurality of first conductive patterns GE1. Etching the upper portion of the first conductive layer GEL1 may include performing an etch-back process on the first conductive layer GEL1. Thus, the first conductive patterns GE1 may be formed to fill the lower portions of the trench regions TR. The top surfaces of the first conductive patterns GE1 may be placed at the same or substantially the same level (e.g., may be coplanar or substantially coplanar with each other), but the inventive concept is not limited to this example. As a result of the etching process, the gate insulating layer GIL on the top surface of the mask pattern MP and a portion of the mask pattern MP may be removed.

[0075] Referring to Figure 9A and Figure 9B , a second conductive layer GEL2 may be formed in the trench regions TR and on the first conductive patterns GE1. The second conductive layer GEL2 may fill the trench regions TR on the first conductive patterns GE1 and may cover the top surface of the mask pattern MP. Forming the second conductive layer GEL2 may include performing a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0076] Referring toFigure 10A and Figure 10B , the upper portion of the second conductive layer GEL2 may be etched to form a plurality of second conductive patterns GE2. Etching the upper portion of the second conductive layer GEL2 may include performing an etch-back process on the second conductive layer GEL2. Accordingly, the second conductive patterns GE2 may fill the trench regions TR on the first conductive patterns GE1. The top surfaces of the second conductive patterns GE2 may be formed at the same or substantially the same level, but the inventive concept is not limited to this example. As a result of the etching process, the mask pattern MP and a portion of the side surface of the gate insulating layer GIL covering the mask pattern MP may be removed. As a result of forming the second conductive patterns GE2, a word line WL including the first conductive patterns GE1 and the second conductive patterns GE2 may be formed. As a result of partially removing the gate insulating layer GIL, a gate insulating pattern GI may be formed. Figure 10A and Figure 10B An example is shown in which the mask pattern MP on the substrate 100 is completely removed by an etching process, but the inventive concept is not limited to this example. Although not shown, a portion of the mask pattern MP may remain on the substrate 100 after the etching process, and in this case, the thickness of the remaining mask pattern MP may be measured after forming the second conductive patterns GE2.

[0077] Referring to Figure 11A and Figure 11B , a protective insulating layer OLL may be formed on the word line WL. Specifically, the protective insulating layer OLL may cover the top surface of the second conductive patterns GE2, the upper portion of the side surface of the gate insulating pattern GI, the top surface of the device isolation pattern 120, and the top surface of the active pattern ACT. Here, the protective insulating layer OLL may be used as an etching mask in an etch-back process for the gate capping layer GCL (which will be described with reference to Figure 13A and Figure 13B ), and the thickness of the protective insulating layer OLL may correspond to the thickness of the etching mask that may be configured or required to protect the substrate 100 during the etch-back process. Forming the protective insulating layer OLL may include performing an atomic layer deposition (ALD) process. Thereafter, a heat treatment process may be performed on the word line WL and the protective insulating layer OLL.

[0078] Referring to Figure 12A and Figure 12B , a gate capping layer GCL may be formed on the protective insulating layer OLL. Specifically, the gate capping layer GCL may fill the remaining space of the trench regions TR except for the protective insulating layer OLL and the word line WL, and may cover the uppermost surface of the protective insulating layer OLL.

[0079] Referring to Figure 13A and Figure 13B, the upper portion of the gate capping layer GCL can be etched to form a plurality of gate capping patterns GC. Etching the upper portion of the gate capping layer GCL can include performing an etch-back process on the gate capping layer GCL. Accordingly, the gate capping patterns GC can be formed on the second conductive pattern GE2 to fill the trench region TR. An etching process can be performed to remove a portion of the protective insulating layer OLL that is placed (e.g., directly or indirectly located) on the top surfaces of the device isolation pattern 120 and the active pattern ACT. As a result of partially removing the protective insulating layer OLL, a protective insulating pattern OL can be formed. The word line WL, the protective insulating pattern OL, and the gate capping patterns GC can form a word line structure WLS.

[0080] Thereafter, referring to Figure 13A , Figure 13B and Figures 3A to 3C , a buffer layer (not shown) and a polysilicon layer (not shown) can be formed to cover the active pattern ACT and the device isolation pattern 120, and a first recessed region RS1 can be formed on each of the active pattern ACT and the device isolation pattern 120. Here, the buffer layer and the polysilicon layer can be partially removed to form a buffer pattern 210 and a polysilicon pattern 310.

[0081] A bit line contact portion DC, a first barrier pattern 320, a bit line BL, and a bit line capping pattern 350 can be formed on the first recessed region RS1. Forming the bit line contact portion DC, the first barrier pattern 320, the bit line BL, and the bit line capping pattern 350 can include forming a bit line contact layer (not shown) to fill the first recessed region RS1; sequentially forming a first barrier layer (not shown), a bit line layer (not shown), and a bit line capping layer (not shown) on the bit line contact layer; and etching the bit line contact layer, the first barrier layer, the bit line layer, and the bit line capping layer to form the bit line contact portion DC, the first barrier pattern 320, the bit line BL, and the bit line capping pattern 350. Here, a portion of the polysilicon pattern 310 can also be etched. During this process, the inside of the first recessed region RS1 can be partially exposed to the outside. Thereafter, a gap-fill insulating pattern 250 can be formed to fill the remaining portion of the first recessed region RS1. In the process of forming the bit line BL, a first ohmic pattern (not shown) can also be formed between the bit line BL and the bit line contact portion DC and between the bit line BL and the polysilicon pattern 310.

[0082] A bit line spacer 360 can be formed to cover the side surfaces of the bit line BL and the bit line capping pattern 350. Forming the bit line spacer 360 can include sequentially forming a first spacer 362, a second spacer 364, and a third spacer 366 to conformally cover the side surfaces of the bit line BL and the bit line capping pattern 350.

[0083] A storage node contact BC and a fence pattern FN may be formed between adjacent bit lines BL in a bit line BL. The storage node contacts BC and the fence patterns FN may be alternately arranged along a second direction D2. Each storage node contact BC may be formed to fill a second recess region RS2 and may be electrically connected to a corresponding edge portion 111 of the active pattern ACT in the second recess region RS2. The fence pattern FN may be formed at a position vertically overlapping with the word line structure WLS. In some example embodiments, the storage node contacts BC may be formed first, and then the fence patterns FN may be formed between the storage node contacts BC. In some example embodiments, the fence patterns FN may be formed first, and then the storage node contacts BC may be formed between the fence patterns FN.

[0084] During the formation of the storage node contact BC, an upper portion of the bit line spacer 360 may be partially removed. In this case, a capping spacer 370 may be additionally formed in a region formed by removing the bit line spacer 360. Thereafter, a second blocking pattern 410 may be formed to conformally cover the bit line spacer 360, the capping spacer 370, and the storage node contact BC.

[0085] A landing pad LP may be formed on the storage node contact BC. Forming the landing pad LP may include: sequentially forming a landing pad layer (not shown) and a mask pattern (not shown) to cover a top surface of the storage node contact BC; and performing an anisotropic etching process using the mask pattern as an etching mask to form a plurality of landing pads LP from the landing pad layer. Additionally, the second blocking pattern 410, the bit line spacer 360, and the bit line capping pattern 350 may be partially etched by an etching process and may be exposed to the outside. An upper portion of the landing pad LP may be offset from the storage node contact BC in a first direction D1.

[0086] In some example embodiments, an etching process may be performed on the landing pad layer to expose the second spacer 364. The second spacer 364 may be further etched through an exposed portion of the second spacer 364, and in this case, a final structure of the second spacer 364 may include an air gap. However, the inventive concept is not limited to this example.

[0087] Thereafter, a filling pattern 440 may be formed to cover an exposed surface of the resulting structure and surround each landing pad LP, and data storage patterns DSP may be formed on the landing pads LP, respectively.

[0088] In a semiconductor manufacturing process according to a comparative example, when forming a trench region that is a space of a word line structure, a relatively thick mask layer may be formed to prevent damage to a substrate in a subsequent etching process (e.g., see Figure 5A)。However, if the mask layer is thick, it may be difficult to form a trench region having a uniform etch profile (e.g., Figure 3A , Figure 3B , Figure 4 , Figure 6A and Figure 6B , Figure 13A and Figure 13B shown TR). At least as Figure 13A shown, a trench region TR having a uniform etch profile may have a symmetric profile in a plane extending at least along a second direction D2 and a fourth direction D4, such that the trench region TR has mirror symmetry (also referred to as reflection symmetry) at least in the second direction D2 about an axis of symmetry or a plane of symmetry AA extending along the fourth direction D4. The axis of symmetry or the plane of symmetry AA may extend along the center line of the trench region TR (e.g., coaxial therewith), such that the axis of symmetry or the plane of symmetry AA is equidistant from opposite first inner surface TRs1 and second inner surface TRs2 of the trench region TR in the second direction D2. As shown, the first inner surface TRs1 may be defined by an inner surface of the device isolation pattern 120, and the second inner surface TRs2 may be defined by an inner surface of the active pattern ACT. For example, based on the mask layer (e.g., the mask pattern MP for forming Figure 5A being thicker in the fourth direction D4, the trench region (TR) may have an asymmetric cross-section (e.g., an asymmetric profile at least in a plane extending along the second direction D2 and the fourth direction D4), such that the trench region TR may lack mirror symmetry in the second direction D2 about any axis or plane extending along the fourth direction D4 between the opposite first inner surface TRs1 and second inner surface TRs2 of the trench region TR. Accordingly, the word line WL filling the trench region TR having an asymmetric cross-section may also be formed to have an asymmetric cross-section (e.g., an asymmetric profile at least in a plane extending along the second direction D2 and the fourth direction D4), and this may lead to deterioration of electrical / operational characteristics of the semiconductor device. In addition, in the process of forming the word line, a part of a side surface of the gate insulating pattern GI may be damaged, and this may cause a leakage current problem.

[0089] In contrast, in a semiconductor manufacturing process according to some example embodiments of the inventive concept, a word line WL may be formed, and then, on a top surface of the word line (e.g., as Figures 3A to 3B , Figure 4 , and Figures 11A to 11BAs shown, a protective insulating layer OLL is formed on the side surface of the gate insulating pattern GI and the active pattern ACT. The protective insulating layer OLL can prevent the top surface of the substrate 100 from being damaged in the step of etching the gate capping layer (e.g., the step shown in Figure 13A and Figure 13B ), or reduce or minimize such damage. Therefore, in the process of forming the trench region TR, a mask with a reduced thickness in the fourth direction D4 can be used (e.g., forming a mask pattern MP in Figure 5A ), and thus, the trench region TR can be formed to have a uniform cross-section or a symmetric cross-section (e.g., a symmetric profile in a plane extending at least along the second direction D2 and the fourth direction D4), at least as shown in Figure 13A . Therefore, at least as shown in Figure 13A , based on the presence of the protective insulating layer OLL during the etching step (e.g., as shown in Figure 13A and Figure 13B ), the trench region TR can be formed to have a mirror symmetry (also called reflection symmetry) that intersects or surrounds the axis of symmetry or the plane of symmetry AA, which extends along the center line of the trench region TR in the fourth direction D4 and is equidistant between the opposite first inner surface TRs1 and the second inner surface TRs2 of the trench region TR in the second direction D2. Therefore, as shown in Figure 13A as well as Figure 3A and Figure 4 further shows, the word line WL filling such a trench region TR can also be formed to have a uniform cross-section (e.g., a symmetric profile at least in a plane extending along the second direction D2 and the fourth direction D4), such that the word line WL has a mirror symmetry in the second direction D2 that surrounds or intersects the axis of symmetry or the plane of symmetry AA extending through the trench TR in the fourth direction D4 (e.g., equidistant between the opposite inner surfaces TRs1 and TRs2 of the trench TR). This symmetric structure of the word line WL can reduce, minimize, or prevent the deterioration of the electrical / operating characteristics of the semiconductor device. Therefore, based on including the protective insulating pattern OL (such as shown in Figure 13A and Figure 13BAs shown, during the upper portion of the etching of the gate capping layer GCL, by partially removing the protective insulating layer OLL (formed), the performance and reliability of the semiconductor device can be improved, which is beneficial for forming a word line WL having mirror symmetry in the second direction D2. In addition, even if the side surface of the gate insulating pattern GI is damaged during the formation of the word line, the protective insulating layer OLL (which forms the protective insulating pattern) can reduce, minimize, or prevent a leakage current problem caused by the damage of the gate insulating pattern, thereby further improving the performance and reliability of the semiconductor device based on including the protective insulating pattern OL. In addition, based on performing a heat treatment process on the word line, the protective insulating layer can prevent impurities in the polysilicon from diffusing to the outside (or reduce or minimize such diffusion), and this can improve the electrical characteristics and reliability characteristics of the semiconductor device based on the semiconductor device including the protective insulating pattern OL.

[0090] According to some example embodiments of the inventive concept, a semiconductor device may include a protective insulating pattern between a word line and a gate capping pattern. The gate insulating pattern may be damaged due to the process of forming the gate capping pattern, but the protective insulating pattern together with the gate insulating pattern can be used to reduce, minimize, or prevent leakage current. In addition, the protective insulating pattern can prevent impurities included in the word line from diffusing to the outside of the word line (or reduce or minimize such diffusion). Therefore, based on the semiconductor device including the protective insulating pattern, the electrical characteristics and reliability characteristics of the semiconductor device can be improved.

[0091] Although some example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate; An active pattern on the substrate; And A word line structure spanning the active pattern, Wherein the word line structure comprises: A word line; A capping pattern on the word line; and A protective insulating pattern between the word line and the capping pattern.

2. The semiconductor device according to claim 1, wherein The word line comprises a first conductive pattern and a second conductive pattern, The second conductive pattern is between the first conductive pattern and the protective insulating pattern, and The second conductive pattern is in contact with the protective insulating pattern.

3. The semiconductor device according to claim 2, wherein, The second conductive pattern is spaced apart from the capping pattern, and the protective insulating pattern is between the second conductive pattern and the capping pattern.

4. The semiconductor device according to claim 2, wherein The first conductive pattern comprises both a metal material and a separate nitride material, the separate nitride material being a nitride of the metal material, The metal material comprises at least one of titanium Ti, molybdenum Mo, tungsten W, copper Cu, aluminum Al, tantalum Ta, ruthenium Ru, or iridium Ir, The second conductive pattern comprises doped polysilicon, and The protective insulating pattern comprises silicon oxide.

5. The semiconductor device according to claim 1, further comprising: A gate insulating pattern extending into the region between the active pattern and the word line, wherein the protective insulating pattern is in contact with the gate insulating pattern.

6. The semiconductor device according to claim 5, further comprising: A device isolation layer surrounding the active pattern, Wherein the gate insulating pattern is between the device isolation layer and the protective insulating pattern, and the gate insulating pattern is between the active pattern and the protective insulating pattern.

7. A semiconductor device, comprising: A substrate; A device isolation pattern on the substrate; An active pattern on the substrate, the active pattern being surrounded by the device isolation pattern; And A word line structure spanning the device isolation pattern and the active pattern in a first direction, the first direction being parallel to the top surface of the substrate, Wherein the word line structure comprises: A word line; A capping pattern on the word line; and A protective insulating pattern on the word line, the protective insulating pattern surrounding the bottom surface and side surfaces of the capping pattern, Wherein the word line has a first width in a second direction, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction, Wherein the bottom surface of the capping pattern has a second width in the second direction, and Wherein the second width is less than the first width.

8. The semiconductor device according to claim 7, wherein The thickness of the protective insulating pattern is 5% to 40% of the length of the first width.

9. The semiconductor device according to claim 8, wherein, The length of the first width is equal to the sum of the length of the second width and twice the thickness of the protective insulating pattern.

10. The semiconductor device according to claim 7, further comprising: A buffer pattern covering each of the active pattern, the device isolation pattern, and the word line, Wherein the buffer pattern is in contact with the protective insulating pattern.

11. The semiconductor device according to claim 7, further comprising: A gate insulating pattern extending into the space between the active pattern and the word line, wherein the height of the top surface of the protective insulating pattern is equal to the height of the top surface of the gate insulating pattern.

12. The semiconductor device according to claim 11, wherein, The protective insulating pattern is between the gate insulating pattern and the capping pattern.

13. The semiconductor device according to claim 11, wherein, Both the gate insulating pattern and the protective insulating pattern include silicon oxide.

14. A semiconductor device, comprising: A substrate; A device isolation pattern on the substrate; An active pattern on the substrate, the active pattern being surrounded by the device isolation pattern; A word line structure extending across the active pattern and the device isolation pattern in a first direction parallel to the top surface of the substrate; A bit line on the active pattern and extending in a second direction intersecting the first direction; A bit line contact portion between the active pattern and the bit line; A storage node contact portion on the active pattern; A landing pad on the storage node contact portion; And A capacitor on the landing pad, wherein the word line structure includes: A first conductive pattern, A second conductive pattern on the first conductive pattern, A capping pattern on the second conductive pattern, and A protective insulating pattern between the second conductive pattern and the capping pattern, wherein the protective insulating pattern includes: a first vertical portion; a second vertical portion; and a horizontal portion connecting the first vertical portion to the second vertical portion, wherein both the first vertical portion and the second vertical portion are in contact with the side surface of the capping pattern, and wherein the horizontal portion is in contact with the bottom surface of the capping pattern.

15. The semiconductor device according to claim 14, further comprising: A gate insulating pattern extending into the space between the active pattern and the word line structure, wherein the first vertical portion and the second vertical portion of the protective insulating pattern are between the gate insulating pattern and the capping pattern.

16. The semiconductor device according to claim 14, wherein, The top surfaces of the first vertical portion and the second vertical portion of the protective insulating pattern are at the same height as the top surface of the capping pattern.

17. The semiconductor device according to claim 14, wherein The horizontal portion of the protective insulating pattern is between the second conductive pattern and the capping pattern.

18. The semiconductor device according to claim 14, wherein, The second conductive pattern is between the first conductive pattern and the horizontal portion of the protective insulating pattern.

19. The semiconductor device according to claim 14, wherein, The bottom surface of the horizontal portion of the protective insulating pattern is in contact with the top surface of the second conductive pattern.

20. The semiconductor device according to claim 15, wherein, The sum of the thicknesses of the protective insulating pattern and the first portion of the gate insulating pattern above the word line of the word line structure in the second direction is greater than the thickness of the second portion of the gate insulating pattern below the protective insulating pattern in the second direction.

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