Semiconductor memory device

Abstract

The semiconductor memory device includes a substrate having an active region defined by a device separation trench; a device separation material layer filling the device separation trench and formed of a first material; a word line trench spanning the active region and the device separation material layer and extending in a first horizontal direction; a gate dielectric layer covering an inner wall of the word line trench; and a word line filling a portion of the word line trench on the gate dielectric layer. The device separation material layer includes a doped layer inside the device separation material layer. The doped layer includes a second material different from the first material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Korean Patent Application No. 10-2024-0003113, filed with the Korean Intellectual Property Office on January 8, 2024, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Devices and apparatuses according to the present disclosure relate to semiconductor memory devices, and more particularly, to semiconductor memory devices including buried word lines. BACKGROUND ART

[0003] Recently, as the integration degree of semiconductor memory devices has been gradually increased, a semiconductor memory device structure of a buried channel array transistor (BCAT) in which multiple word lines are buried in a substrate has been proposed. Accordingly, various studies are being conducted to improve and stabilize the operation and reliability of the BCAT. SUMMARY OF THE INVENTION

[0004] One aspect of the present disclosure provides a semiconductor memory device having improved reliability.

[0005] According to one aspect of one or more embodiments, the present disclosure provides a semiconductor memory device including: a substrate having a plurality of active regions defined by device isolation trenches; a device isolation material layer filling the device isolation trenches and formed of a first material; a word line trench spanning the plurality of active regions and the device isolation material layer and extending in a first horizontal direction; a gate dielectric layer covering an inner wall of the word line trench; and a word line filling a part of the word line trench on the gate dielectric layer, wherein the device isolation material layer includes a doped layer inside the device isolation material layer, and the doped layer includes a second material different from the first material.

[0006] According to another aspect of one or more embodiments, the present disclosure provides a semiconductor memory device including: a substrate including a cell array region and a peripheral circuit region; a plurality of active regions defined by device isolation trenches in the cell array region; a device isolation material layer filling the device isolation trenches; a word line trench spanning the plurality of active regions and the device isolation material layer and extending in a first horizontal direction; a gate dielectric layer covering an inner wall of the word line trench; and a word line filling a part of the word line trench on the gate dielectric layer, wherein the device isolation material layer includes a recessed region formed in a vertical direction perpendicular to the substrate, and the recessed region is filled with an ion implantation layer.

[0007] In yet another aspect according to one or more embodiments, the present disclosure provides a semiconductor memory device, comprising: a substrate having a cell array region including a plurality of active regions defined by device isolation trenches, a peripheral circuit region in which at least one logic active region is defined, and an interface region located between the cell array region and the peripheral circuit region; a device isolation material layer filling the device isolation trenches in the cell array region; a plurality of word lines respectively spanning the plurality of active regions and extending in a first horizontal direction; a plurality of bit lines respectively disposed in the plurality of active regions and extending in a second horizontal direction orthogonal to the first horizontal direction; a gate line disposed in at least one logic active region; a plurality of buried contact portions filling a lower portion of the space between the plurality of bit lines and respectively connected to the plurality of active regions; a plurality of landing pads filling an upper portion of the space between the plurality of bit lines and respectively extending to the plurality of bit lines; and a plurality of capacitor structures including an upper electrode, a plurality of lower electrodes respectively contacting the plurality of landing pads, and a capacitor dielectric layer disposed between the upper electrode and the plurality of lower electrodes, wherein the device isolation material layer includes an ion implantation layer that extends from the upper surface of the device isolation material layer toward the substrate into the device isolation material layer to a first depth, and wherein a horizontal cross-section of the ion implantation layer is located within a horizontal cross-section of the device isolation material layer, and the first depth is less than a thickness of the device isolation material layer in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram of a semiconductor memory device according to an embodiment;

[0010] Figure 2 is according to an embodiment of Figure 1 an enlarged layout diagram of region P therein;

[0011] Figures 3A to 12D is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to various embodiments; and

[0012] Figures 13A to 13D is a cross-sectional view of a semiconductor memory device according to various embodiments. DETAILED DESCRIPTION

[0013] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings and diagrams. In the drawings, the same reference numerals are used to describe the same components, and for the sake of brevity, repeated descriptions thereof are omitted. As used in this specification, the phrase "at least one of A, B, or C" includes within its scope "only A", "only B", "only C", "A and B", "B and C", "A and C", and "A, B, and C".

[0014] Since various changes can be made to various embodiments, some embodiments are shown in the figures and described in detail. However, such a description of some embodiments is not intended to limit the scope to a specific practice mode, and it should be understood that all changes, equivalents, and alternatives that do not depart from the spirit and technical scope of the present disclosure are included in the appended claims. In the description of various embodiments, when it is considered that a detailed explanation of some related technologies may unnecessarily confuse the various embodiments, such detailed explanations will be omitted.

[0015] Figure 1 is a layout diagram of a semiconductor memory device 100 according to an embodiment, Figure 2 is according to an embodiment of Figure 1 an enlarged layout diagram of region P in

[0016] Referring to Figure 1 and Figure 2 , the semiconductor memory device 100 may include a substrate 110, and the substrate 110 includes a cell array region MCA and a peripheral circuit region PCA. In some embodiments, the substrate 110 may include a plurality of MCAs and a plurality of PCAs. The cell array region MCA may include a storage cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may include a core region or a peripheral circuit region of the DRAM device. For example, the cell array region MCA may include cell transistors and capacitor structures connected to the cell transistors, and the peripheral circuit region PCA may include peripheral circuit transistors for transmitting signals and / or power to the cell transistors included in the cell array region MCA. In some embodiments, the peripheral circuit transistors may constitute various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and / or a data input / output circuit.

[0017] Device isolation trenches and region isolation trenches may be formed in the substrate 110, and a plurality of device isolation layers may be formed in the device isolation trenches and the region isolation trenches. A plurality of first active regions AC1 may be defined in the cell array region MCA of the substrate 110 through some of the device isolation layers, and a plurality of second active regions AC2 may be defined in the peripheral circuit region PCA through other device isolation layers.

[0018] As Figure 2As shown, in the cell array area MCA, each of the plurality of first active areas AC1 may be arranged to have a main axis in a first diagonal direction (D1 direction) tilted relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of word lines WL may extend parallel to each other along the first horizontal direction (X direction) across the plurality of first active areas AC1. A plurality of bit lines BL may extend parallel to each other along the second horizontal direction (Y direction) on the plurality of word lines WL. A plurality of bit lines BL may be connected to the plurality of first active areas AC1, respectively, via bit line contacts DC.

[0019] The plurality of buried contacts BC may be disposed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of landing pads LP may be formed on the plurality of buried contacts BC, respectively. The plurality of buried contacts BC and the plurality of landing pads LP may form a capacitor structure (see Figures 13A to 13D 200) of the lower electrode (see Figures 13A to 13D 210 ) is connected to the first active region AC1. In an embodiment, each of the plurality of landing pads LP may be disposed to partially overlap the buried contact BC and the bit line BL.

[0020] Figures 3A to 3D , Figures 4A to 4D , Figure 5A and Figure 5B , Figure 6A and Figure 6B , Figures 7A to 7D , Figures 8A to 8D , Figures 9A to 9D , Figures 10A to 10D , Figures 11A to 11D as well as Figures 12A to 12D is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device 100 according to some embodiments, and Figures 13A to 13D is a cross-sectional view of a semiconductor memory device 100 according to some embodiments. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A is along Figure 2 Cross-sectional view taken along the midline AA'. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B ,Figure 12B and Figure 13B is a cross-sectional view taken along the Figure 2 center line B - B'. Figure 3C 、 Figure 4C 、 Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C 、 Figure 12C and Figure 13C is a cross-sectional view taken along the Figure 2 center line C - C'. Figure 3D 、 Figure 4D 、 Figure 7D 、 Figure 8D 、 Figure 9D 、 Figure 10D 、 Figure 11D 、 Figure 12D and Figure 13D is a cross-sectional view taken along the Figure 2 center line D - D'.

[0021] Refer to Figures 3A to 3D collectively. By removing a portion of the substrate 110, device isolation trenches 116T and region isolation trenches (not shown) can be formed in the substrate 110. The device isolation trenches 116T can be formed in the Figure 2 cell array region MCA shown, and the region isolation trenches (not shown) can be formed in the Figure 2 peripheral circuit region PCA shown.

[0022] The substrate 110 can include, for example, silicon (Si), crystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 110 can include a semiconductor element, such as germanium (Ge), or at least one compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). In some embodiments, the substrate 110 can have a silicon-on-insulator (SOI) structure. For example, the substrate 110 can include a buried oxide (BOX) layer. The substrate 110 can include conductive regions, such as wells doped with impurities, or structures doped with impurities.

[0023] A plurality of active regions 118 can be defined by the device isolation trenches 116T in the cell array region MCA in the substrate 110, and a plurality of logic active regions (not shown) are defined in the peripheral region PCA in the substrate 110. In some embodiments, the plurality of active regions 118 and / or the plurality of logic active regions defined by the device isolation trenches 116T can be formed by using extreme ultraviolet (EUV) lithography process. Compared with Figure 2Similar to the first active region AC1 shown, the active region 118 may have a relatively long island shape that has both a short axis and a long axis in a plan view. A plurality of active regions 118 may be arranged in rows in a diagonal direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), or may be arranged in rows in the second horizontal direction (Y direction). The logic active region may have a rectangular shape in a plan view, but is not limited thereto, and in some embodiments, the logic active region may have other planar shapes. The plurality of active regions 118 and the plurality of logic active regions may be spaced apart from each other by region isolation trenches provided therebetween.

[0024] Referring together to Figures 4A to 4D , a device isolation material layer 116P may be formed that fills the region isolation trenches and a portion of the device isolation trenches 116T. The device isolation material layer 116P may include a material such as at least one of silicon oxide, silicon nitride, or silicon oxynitride. For example, the device isolation material layer 116P may include a single layer that includes an oxide layer. In some embodiments, the device isolation material layer 116P may include silicon oxide. In some embodiments, the device isolation material layer 116P may not include silicon nitride. In some embodiments, the device isolation material layer 116P may include silicon oxide but not include silicon nitride.

[0025] The device isolation material layer 116P may be formed using an atomic layer deposition (ALD) process to fill the interior of the device isolation trenches 116T. Since one layer is deposited in each step, the device isolation material layer 116P has good step coverage, but fine gaps may be left after the ALD process is completed. In other words, the device isolation material layer 116P may be formed to substantially fill the device isolation trenches 116T, except for the fine gap portions of the device isolation trenches 116T. As Figure 4A and Figure 4B shown, in some embodiments, in a direction perpendicular to the substrate 110, the fine gaps may be left as vacant spaces s1 (e.g., recessed regions). In some embodiments, the width of the horizontal cross-section of the recessed region may not be greater than the width of the horizontal cross-section of the device isolation trenches 116T, and the upper surface of the recessed region may be coplanar with the upper surface of the device isolation trenches 116T. In some embodiments, the width of the recessed region in the vertical direction may be less than the width of the device isolation trenches 116T in the vertical direction.

[0026] According to various embodiments, "horizontal" or "vertical level" may indicate the height or position in the vertical direction (Z direction) relative to the main surface or upper surface of the substrate 110. In other words, positions at the "same level" or "constant level" may indicate that the positions are at the same height or constant height in the vertical direction (Z direction) relative to the main surface of the substrate 110, and positions at a low / high level may indicate that the positions are at a lower / higher height in the vertical direction (Z direction) relative to the main surface or upper surface of the substrate 110.

[0027] Reference Figure 5A and Figure 5B , an ion implantation process may be performed in the vacant space s1 that can be formed in the device isolation trench 116T. In some embodiments, the implanted ions may be selected from silicon, germanium (Ge), or argon (Ar) or a combination thereof. In some embodiments, the energy for implanting ions may be no greater than about 2.5 keV. According to some embodiments, the concentration of the implanted ions may be in the range of about 0.1*10 16 atoms / cm² to about 0.2*10 16 atoms / cm².

[0028] Reference Figure 6A and Figure 6B , the ion implantation process performed using reference Figure 5A and 5B may form an ion implantation layer 119 in the vacant space (i.e., s1 in Figure 5A and Figure 5B ). Referring to Figure 5A and Figure 5B , the ion implantation process performed may cause an expansion phenomenon of the silicon oxide material contained in the device isolation material layer 116P. As a result, the remaining vacant space s1 in the device isolation material layer 116P may be filled with a doped layer. In an embodiment, the etching tolerance of the device isolation material layer 116P may be enhanced by the ion implantation process. Accordingly, the semiconductor memory device 100 may prevent the formation of excessive depressions by removing the vacant space s1, thereby ensuring the reliability of the semiconductor memory device.

[0029] Reference Figures 7A to 7D, a plurality of word line trenches 120T can be formed in the substrate 110 by removing portions of the plurality of active regions 118 and portions of the device isolation material layer 116P and the ion implantation layer 119. The plurality of word line trenches 120T can extend parallel to each other in a first horizontal direction (X direction) and can have a linear shape, wherein each of the plurality of word line trenches 120T is disposed to cross each of the plurality of active regions 118. In some embodiments, the plurality of word line trenches 120T can have substantially equal spacing therebetween in a second horizontal direction (Y direction). In some embodiments, steps can be formed on the lower surfaces of the plurality of word line trenches 120T.

[0030] Referring together Figures 7A to 7D and Figures 8A to 8D , a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 can be sequentially formed inside the plurality of word line trenches 120T. The plurality of word lines 120 can respectively constitute Figure 2 the plurality of word lines WL shown. The plurality of word lines 120 can extend parallel to each other in a first horizontal direction (X direction) and can have a linear shape, wherein each of the plurality of word lines 120 is disposed to cross the active region 118. In an embodiment, the plurality of word lines 120 can have substantially equal spacing therebetween in a second horizontal direction (Y direction). The upper surface of each of the plurality of word lines 120 can be at a level lower than the upper surface of the substrate 110 (see, for example Figure 8B , Figure 8D ). The bottom surfaces of the plurality of word lines 120 can have an uneven shape, and the plurality of active regions 118 can include transistors having a saddle-shaped fin structure (or saddle-shaped FinFETs).

[0031] Each of the plurality of word lines 120 can have a stacked structure that includes a lower word line layer 120a and an upper word line layer 120b. For example, the lower word line layer 120a can include a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower word line layer 120a can include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer 120b can include doped polysilicon. In some embodiments, the lower word line layer 120a can include a core layer and a barrier layer between the core layer and the gate dielectric layer 122.

[0032] In some embodiments, before or after forming the plurality of word lines 120, impurity ions can be implanted into a portion of the active region 118 of the substrate 110 on both sides of each of the plurality of word lines 120, and source regions and drain regions can be formed inside the plurality of active regions 118.

[0033] The gate dielectric layer 122 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, oxide-nitride-oxide (ONO), or a high-k dielectric having a dielectric constant higher than that of silicon oxide. For example, the gate dielectric layer 122 may have a dielectric constant of about 10 to about 25.

[0034] The upper surfaces of the plurality of buried insulating layers 124 may be substantially at the same level as the upper surface of the substrate 110. The buried insulating layers 124 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride or a combination thereof.

[0035] During the formation of the plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124, portions of the device isolation material layer 116P and the upper side of the ion implantation layer 119 may be removed to form the device isolation layer 116. The plurality of active regions 118 may be defined by the device isolation layer 116 in the cell array region MCA of the substrate 110, and the plurality of logic active regions of the substrate 110 may be defined in the peripheral region PCA.

[0036] Referring together Figures 9A to 9D , a first insulating layer pattern 112 and a second insulating layer pattern 114 covering the device isolation layer 116, the plurality of active regions 118, and the plurality of buried insulating layers 124 may be formed. For example, the first insulating layer pattern 112 and the second insulating layer pattern 114 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. In some embodiments, the first insulating layer pattern 112 and the second insulating layer pattern 114 may be formed by stacking a plurality of insulating layers including the first insulating layer pattern 112 and the second insulating layer pattern 114. In some embodiments, the first insulating layer pattern 112 may include a silicon oxide layer and the second insulating layer pattern 114 may include a silicon nitride layer. In other embodiments, the first insulating layer pattern 112 may include a non-metal dielectric layer and the second insulating layer pattern 114 may include a metal dielectric layer.

[0037] Then, after forming the conductive semiconductor layer 132P on the first insulating layer pattern 112 and the second insulating layer pattern 114, a direct contact hole 134H can be formed, which passes through the conductive semiconductor layer 132P, the first insulating layer pattern 112, and the second insulating layer pattern 114, and exposes the source region in the active region 118, and a direct contact conductive layer 134P filling the direct contact hole 134H can be formed. In some embodiments, the direct contact hole 134H can extend into the active region 118, that is, into the source region. The conductive semiconductor layer 132P can include, for example, doped polysilicon. The direct contact conductive layer 134P can include, for example, doped polysilicon. In some embodiments, the direct contact conductive layer 134P can include an epitaxial silicon layer. In other embodiments, the direct contact conductive layer 134P can include a metal or a metal compound as the conductive material. For example, the direct contact conductive layer 134P can include a metal, such as Ti and / or W, or include a conductive metal that is a compound of a metal such as Ti and / or W and a non-metal such as Si, C, B, and / or N. In some embodiments, the direct contact conductive layer 134P can include TiN, WC, or WSi.

[0038] Referring together Figures 10A to 10D and Figures 9A to 9D , a metal-based conductive layer and an insulating capping layer can be sequentially formed, and the metal-based conductive layer and the insulating capping layer are used to cover the conductive semiconductor layer 132P and the direct contact conductive layer 134P and form a bit line structure 140. In some embodiments, the metal-based conductive layer can include a stacked structure including a first metal-based conductive layer and a second metal-based conductive layer. By etching the first metal-based conductive layer, the second metal-based conductive layer, and the insulating capping layer, a plurality of bit lines 147 including a first metal-based pattern 145 and a second metal-based pattern 146 having a linear shape and a plurality of insulating capping lines 148 can be formed.

[0039] In some embodiments, the first metal-based pattern 145 can include titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based pattern 146 can include W or tungsten silicide (WSi x ). In some embodiments, the first metal-based pattern 145 can perform a diffusion barrier function. In some embodiments, the plurality of insulating capping lines 148 can include a silicon nitride layer.

[0040] A bit line 147 and an insulating capping line 148 covering the bit line 147 can constitute a bit line structure 140. A plurality of bit line structures 140 each including a bit line 147 and an insulating capping line 148 covering the bit line 147 can extend parallel to each other in a second horizontal direction (Y direction) parallel to the main surface of the substrate 110. The plurality of bit lines 147 can respectively constituteFigure 2 The multiple bit lines BL shown in [figure]. In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132, which is a part of the conductive semiconductor layer 132P disposed between the first and second insulating layer patterns 112 and 114 and the first metal base pattern 145.

[0041] In the etching process for forming the multiple bit lines 147, a portion of the conductive semiconductor layer 132P that does not vertically overlap with the bit lines 147 and a portion that directly contacts the conductive layer 134P may be removed together by the etching process to form a plurality of conductive semiconductor patterns 132 and a plurality of direct contact conductive patterns 134. In this case, the first insulating layer pattern 112 and the second insulating layer pattern 114 may be used as an etch stop layer in the etching process for forming the multiple bit lines 147, the plurality of conductive semiconductor patterns 132, and the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 may respectively constitute Figure 2 The multiple direct contact portions DC shown in [figure]. The multiple bit lines 147 may be electrically connected to the multiple active regions 118 via the plurality of direct contact conductive patterns 134 respectively. The conductive semiconductor pattern 132 may include, for example, doped polysilicon. The direct contact conductive pattern 134 may include doped polysilicon, a metal, or a metal compound containing a conductive material. For example, the direct contact conductive pattern 134 may include a metal such as Ti and / or W, or include a conductive metal that is a compound of a metal such as Ti and / or W and a non-metal such as Si, C, B, and / or N. In some embodiments, the direct contact conductive pattern 134 may include TiN, WC, or WSi.

[0042] Both sidewalls of each of the multiple bit line structures 140 may be covered by an insulating spacer structure 150. Each of the multiple insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a dielectric constant lower than that of the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride layer, and the second insulating spacer 154 may include an oxide layer. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride layer, and the second insulating spacer 154 may include a material having an etching selectivity with respect to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include a nitride layer, the second insulating spacer 154 may include an oxide layer, but may be removed in a subsequent process to become an air spacer.

[0043] A plurality of buried contact holes 170H can be formed between a plurality of bit line structures 140. The plurality of buried contact holes 170H can have an internal space defined by an insulating spacer structure 150 and an active region 118, and the insulating spacer structure 150 covers sidewalls of each of two adjacent bit lines 147 among a plurality of bit lines 147.

[0044] The plurality of buried contact holes 170H can be formed by using a plurality of insulating capping lines 148 and an insulating spacer structure 150 covering two sidewalls of each of the plurality of bit line structures 140 as an etching mask to remove a first insulating layer pattern 112, a second insulating layer pattern 114, and portions of the active region 118. In some embodiments, after performing an anisotropic etching process of removing the first insulating layer pattern 112, the second insulating layer pattern 114, and portions of the active region 118 by using a plurality of insulating capping lines 148 and an insulating spacer structure 150 covering two sidewalls of each of the plurality of bit line structures 140 as an etching mask first, the plurality of buried contact holes 170H having an extended space defined by the active region 118 can be formed by performing an isotropic etching process of further removing the remaining portions of the active region 118.

[0045] Referring also to Figures 11A to 11D , a plurality of buried contact portions 170 and a plurality of insulating fences 180 can be formed in a space between a plurality of insulating spacer structures 150 covering two sidewalls of each of the plurality of bit line structures 140. The plurality of buried contact portions 170 and the plurality of insulating fences 180 can be alternately arranged along a space (i.e., in a second horizontal direction (Y direction)) between a pair of insulating spacer structures 150 facing each other among the plurality of insulating spacer structures 150 covering two sidewalls of the plurality of bit line structures 140. For example, the plurality of buried contact portions 170 can include polysilicon. For example, the plurality of insulating fences 180 can include a nitride layer.

[0046] In some embodiments, the plurality of buried contact portions 170 can be arranged in a row in a first horizontal direction (X direction) and a second horizontal direction (Y direction) respectively. Each of the plurality of buried contact portions 170 can extend from the active region 118 in a vertical direction (Z direction) perpendicular to the substrate 110. The plurality of buried contact portions 170 can respectively constitute Figure 2 the plurality of buried contact portions BC shown in

[0047] Multiple buried contact portions 170 may be located in a space defined by a plurality of insulating spacer structures 150 that cover two sidewalls of a plurality of insulating fences 180 and a plurality of bit line structures 140. The multiple buried contact portions 170 may fill a lower portion of the space between the plurality of insulating spacer structures 150 that cover two sidewalls of each of the plurality of bit line structures 140.

[0048] The level of the upper surface of the multiple buried contact portions 170 may be lower than the level of the upper surface of the plurality of insulating capping lines 148. The upper surface of the plurality of insulating fences 180 and the upper surface of the plurality of insulating capping lines 148 may be at the same level with respect to the vertical direction (Z direction).

[0049] The plurality of insulating spacer structures 150 and the plurality of insulating fences 180 may define a plurality of landing pad holes 190H. The multiple buried contact portions 170 may be respectively exposed at the lower surfaces of the plurality of landing pad holes 190H.

[0050] Referring together Figures 12A to 12D thereto, a landing pad material layer may be formed to fill the plurality of landing pad holes 190H and cover the plurality of bit line structures 140. In some embodiments, the landing pad material layer may include a conduction barrier layer and a conductive pad material layer located on the conduction barrier layer. For example, the conduction barrier layer may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conduction barrier layer may have a Ti / TiN stacked structure. In some embodiments, the conductive pad material layer may include W.

[0051] In some embodiments, before forming the landing pad material layer, a metal silicide layer may be formed on the multiple buried contact portions 170. The metal silicide layer may be disposed between the multiple buried contact portions 170 and the landing pad material layer. The metal silicide layer may include cobalt silicide (CoSi x ), nickel silicide (NiSi x ), or manganese silicide (MnSi x ), but is not limited thereto.

[0052] Then, a portion of the landing pad material layer may be removed to fill at least a portion of the plurality of landing pad holes 190H and extend onto the plurality of bit line structures 140 to form a plurality of landing pads 190 separated from each other by recessed portions 190R.

[0053] A plurality of landing pads 190 may be spaced apart from each other by the recessed portions 190R provided therebetween. The plurality of landing pads 190 may be respectively disposed on the plurality of buried contact portions 170 and may respectively extend onto the plurality of bit line structures 140. In some embodiments, the plurality of landing pads 190 may respectively extend onto a plurality of bit lines 147. The plurality of landing pads 190 may be located on the plurality of buried contact portions 170, and the plurality of buried contact portions 170 may be respectively electrically connected to the corresponding plurality of landing pads 190. The buried contact portion 170 and the landing pad 190 corresponding to each other may be collectively referred to as a contact plug. The plurality of landing pads 190 may be connected to the active region 118 through the plurality of buried contact portions 170. The plurality of landing pads 190 may respectively constitute Figure 2 the plurality of landing pads LP shown in

[0054] The buried contact portion 170 may be disposed between two adjacent bit line structures 140, and the landing pad 190 may extend from the space between the two adjacent bit line structures 140 having the buried contact portion 170 therebetween onto one bit line structure 140.

[0055] Referring Figures 13A to 13D to, an insulating structure 195 filling the recessed portion 190R may be formed. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include an oxide, and the etch stop layer may include a nitride. Figures 13A to 13D It is shown that the upper surface of the insulating structure 195 and the upper surface of the landing pad 190 are at the same level, but the embodiments are not limited thereto.

[0056] A plurality of lower electrodes 210 respectively connected to the plurality of landing pads 190 may be formed. The plurality of lower electrodes 210 may be respectively electrically connected to the plurality of landing pads 190. Each of the plurality of lower electrodes 210 may have a columnar shape, i.e., a pillar shape, and the filled interior thereof has a circular horizontal cross-section, but the embodiments are not limited thereto. In some embodiments, each of the plurality of lower electrodes 210 may have a cylindrical shape with a closed lower portion. In some embodiments, the plurality of lower electrodes 210 may be arranged in a honeycomb zigzag pattern with respect to the first horizontal direction (X direction) or the second horizontal direction (Y direction). In some other embodiments, the plurality of lower electrodes 210 may be arranged in a line matrix shape in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). The plurality of lower electrodes 210 may include, for example, silicon doped with impurities, a metal such as W and / or Cu, or a conductive metal compound such as titanium nitride.

[0057] A capacitor dielectric layer 220 and an upper electrode 230 are sequentially formed on a plurality of lower electrodes 210 to form a semiconductor memory device 100. The capacitor dielectric layer 220 and the upper electrode 230 on the plurality of lower electrodes 210 may constitute a plurality of capacitor structures 200. The capacitor dielectric layer 220 may conformally cover the surfaces of the plurality of lower electrodes 210. In some embodiments, the capacitor dielectric layer 220 may be integrally formed to cover the plurality of lower electrodes 210 in a specific region (e.g., in a cell array region (see Figure 2 for the MCA in)).

[0058] The capacitor dielectric layer 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, (Ba,Sr)TiO (BST), SrTiO (STO), BaTiO (BTO), (Pb,Zr,Ti) (PZT)O, (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or a combination thereof.

[0059] The upper electrode 230 may include, for example, W, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO(BSRO), CaRuO (CRO), BaRuO, or La(Sr,Co)O, etc. In some embodiments, the upper electrode 230 may include a metallic material. For example, the upper electrode 230 may include W.

[0060] In Figures 3A to 13D the semiconductor memory device 100 shown, after the device isolation material layer 116P is completely formed inside the device isolation trench 116T, an ion implantation layer 119 may be formed by performing an ion implantation process. However, in some embodiments, the device isolation material layer may be partially formed inside the device isolation trench 116T and the ion implantation process may be performed in the void, and then the ion implantation layer 119 may be obtained by forming the device isolation material layer in the remaining space of the device isolation trench 116T. Before the ion implantation process that can be performed in the above process, the same type of element may be implanted with the same energy and the same concentration, as referenced in Figure 5A , Figure 5B , Figure 6A and Figure 6B described.

[0061] In the semiconductor memory device 100 according to various embodiments, by forming a device isolation material layer 116P in the device isolation trench 116T and performing an ion implantation process into the resulting empty gap, an expansion phenomenon of the semiconductor oxide material contained in the device isolation material layer 116P can be caused. At the same time, the etching tolerance of the device isolation material layer 116P can be enhanced. Therefore, in the semiconductor memory device 100 according to various embodiments, the empty gap that may remain between the device isolation layers 116 can be removed. At the same time, the phenomenon of excessive depression formation in subsequent processes can be prevented, and no defects will occur even in the case of high integration, so the operation reliability can be ensured.

[0062] Although the various embodiments have been specifically shown and described with reference to the accompanying drawings, it should be understood that various changes in form and detail can be made without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor memory device, comprising: a substrate having a plurality of active regions defined by device isolation trenches; a device isolation material layer filling the device isolation trenches and formed of a first material; word line trenches spanning the plurality of active regions and the device isolation material layer and extending in a first horizontal direction; a gate dielectric layer covering inner walls of the word line trenches; and word lines filling a part of the word line trenches on the gate dielectric layer, wherein the device isolation material layer includes a doped layer inside the device isolation material layer, and the doped layer includes a second material different from the first material.

2. The semiconductor memory device according to claim 1, wherein the first material includes silicon oxide, and the second material includes one of the following materials: silicon Si, germanium Ge, argon Ar, or a combination thereof.

3. The semiconductor memory device according to claim 1, wherein, The second material forms the doped layer due to ion implantation into the device isolation material layer.

4. The semiconductor memory device according to claim 3, wherein, The second material is implanted into the device isolation material layer at an energy not greater than 2.5 keV.

5. The semiconductor memory device according to claim 3, wherein, The concentration of the second material injected into the device separation material layer is in the range of 0.1*10 16 atoms / cm² to 0.2*10 16 atoms / cm².

6. The semiconductor memory device according to claim 1, wherein The first material does not include silicon nitride.

7. The semiconductor memory device according to claim 1, wherein, In a vertical direction, an upper surface of the doped layer is coplanar with an upper surface of the device isolation material layer.

8. The semiconductor memory device according to claim 1, wherein Compared with a lower surface of the device isolation material layer, a lower surface of the doped layer is at a higher level in the vertical direction.

9. The semiconductor memory device according to claim 1, wherein: At all vertical levels in a region where the doped layer is formed, a horizontal cross-section of the doped layer is within a horizontal cross-section of the device isolation material layer.

10. The semiconductor memory device according to claim 1, further comprising: a plurality of bit lines respectively disposed on the plurality of active regions and extending in a second horizontal direction orthogonal to the first horizontal direction; a gate line disposed in at least one of the plurality of active regions; a plurality of landing pads filling an upper side portion of a space between the plurality of bit lines and respectively extending to the plurality of bit lines; and a plurality of capacitor structures including an upper electrode, a plurality of lower electrodes respectively in contact with the plurality of landing pads, and a capacitor dielectric layer disposed between the upper electrode and the plurality of lower electrodes.

11. A semiconductor memory device, comprising: a substrate including a cell array region and a peripheral circuit region; a plurality of active regions defined by device isolation trenches in the cell array region; a device isolation material layer filling the device isolation trenches; word line trenches spanning the plurality of active regions and the device isolation material layer and extending in a first horizontal direction; a gate dielectric layer covering inner walls of the word line trenches; and word lines filling a part of the word line trenches on the gate dielectric layer, wherein the device isolation material layer includes a recessed region formed in a vertical direction perpendicular to the substrate, and the recessed region is filled with an ion implantation layer.

12. The semiconductor memory device according to claim 11, wherein, The ion implantation layer includes one of the following materials: silicon Si, germanium Ge, argon Ar, or a combination thereof.

13. The semiconductor memory device according to claim 11, wherein, The concentration of the elements contained in the ion implantation layer is in the range of 0.1×10 16 atoms / cm² to 0.2×10 16 atoms / cm².

14. The semiconductor memory device according to claim 11, wherein: The width of the horizontal cross-section of the recessed region is not greater than the width of the horizontal cross-section of the device isolation material layer, and the upper surface of the recessed region is coplanar with the upper surface of the device isolation material layer.

15. The semiconductor memory device according to claim 11, wherein, The width of the recessed region in the vertical direction is less than the width of the device isolation material layer in the vertical direction.

16. The semiconductor memory device according to claim 11, wherein, The device isolation material layer includes silicon oxide but does not include silicon nitride.

17. The semiconductor memory device according to claim 11, wherein, The recessed region is physically separated from the substrate.

18. A semiconductor memory device, comprising: A substrate having: a cell array region including a plurality of active regions defined by device isolation trenches; A peripheral circuit region in which at least one logic active region is defined; And an interface region between the cell array region and the peripheral circuit region; A device isolation material layer filling the device isolation trenches in the cell array region; A plurality of word lines respectively spanning the plurality of active regions and extending in a first horizontal direction; A plurality of bit lines respectively disposed in the plurality of active regions and extending in a second horizontal direction orthogonal to the first horizontal direction; A gate line disposed in the at least one logic active region; A plurality of buried contact portions filling a lower portion of the space between the plurality of bit lines and respectively connected to the plurality of active regions; A plurality of landing pads filling an upper portion of the space between the plurality of bit lines and respectively extending onto the plurality of bit lines; And A plurality of capacitor structures including an upper electrode, a plurality of lower electrodes respectively in contact with the plurality of landing pads, and a capacitor dielectric layer disposed between the upper electrode and the plurality of lower electrodes, Wherein, the device isolation material layer includes an ion implantation layer, the ion implantation layer extends from the upper surface of the device isolation material layer towards the substrate into the device isolation material layer to a first depth, and Wherein, the horizontal cross-section of the ion implantation layer is within the horizontal cross-section of the device isolation material layer, and the first depth is less than the thickness of the device isolation material layer in the vertical direction.

19. The semiconductor memory device according to claim 18, Among them, The ion implantation layer includes the following materials: silicon Si, germanium Ge, argon Ar, or a combination thereof, and Among them, the doping concentration of the material is in the range of 0.1*10 16 atoms / cm² to 0.2*10 16 atoms / cm².

20. The semiconductor memory device according to claim 18, wherein, The device isolation material layer includes silicon oxide but does not include silicon nitride.

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