Semiconductor layout pattern including high-voltage element and semiconductor structure

Abstract

A semiconductor layout pattern including a high-voltage device includes a substrate including a high-voltage device region and an MRAM (Magnetic Random Access Memory) region adjacent to each other, the MRAM region at least including a plurality of MRAM cells arranged in an array, and the high-voltage device region and the MRAM region are disposed on the substrate. Wherein each MRAM unit comprises two fin-shaped structures which are parallel to each other and are arranged along an X direction, two gate structures which are parallel to each other and are arranged along a Y direction, a drain metal layer positioned between the two gate structures, two source metal layers respectively positioned on the other sides of the two gate structures relative to the drain metal layer, and an MTJ (Magnetic Tunneling Junction) element, and electrically connecting the drain metal layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor layout pattern including high-voltage components and integrating high-voltage components with a magnetic random access memory (MRAM), and a semiconductor structure having a shielding structure. Background Art

[0002] A display random access memory (Display RAM) is a memory specifically used for storing image or video data. It is usually used in a display or a display card to quickly access and display image data. Different from other types of memories, a display random access memory needs to have high-speed read and write capabilities so as to be able to quickly update the image of the display. In addition, a display random access memory usually needs to have high density and low power consumption so as to be able to store more image data in a smaller area.

[0003] A display random access memory usually belongs to a volatile memory, which means that it needs continuous power supply to maintain the data stored therein. If the power supply is interrupted, the data will be lost. Therefore, a display random access memory usually needs to be equipped with a battery or other backup power supply to maintain the integrity of the data when the power is off. In terms of specifications, a display random access memory needs to have sufficient capacity so as to be able to store the image data of the entire display screen. It also needs to have sufficient bandwidth and speed so as to be able to quickly read and write a large amount of data.

[0004] Magnetic random access memory (MRAM) is a non-volatile memory technology that uses magnetization states to represent stored data. Generally, an MRAM includes a plurality of magnetic storage cell bits in an array. Each storage cell basically represents a bit value of data. At least one magnetic element is included in the above storage cell, and the magnetic element may include two magnetic plates (or material layers on a semiconductor substrate), each having a magnetic force direction (or bit direction of magnetic moment) associated therewith, and a thinner non-magnetic layer is further included between the two magnetic plates.

[0005] More specifically, a MRAM device is generally based on a magnetic tunnel junction (MTJ) device. An MTJ device includes at least three basic layers: a free layer, an insulating layer, and a fixed layer. The free layer and the fixed layer are magnetic layers, and the insulating layer is an insulating layer located between the free layer and the fixed layer. Additionally, the magnetization direction of the free layer can rotate freely, but is restricted by the physical size of the layer to point in only one of two directions (parallel or anti-parallel to the magnetic force direction of the fixed layer); the magnetization direction of the fixed layer is fixed in a specific direction. A bit is written by positioning the magnetization direction of the free layer in one of the above two directions. Depending on whether the magnetic moments of the free layer and the fixed layer are in the same or opposite orientations, the resistance of the MTJ device will change accordingly. Therefore, by determining the resistance of the MTJ device, the bit value can be read. Further elaborating, when the magnetization directions of the free layer and the fixed layer are parallel and the magnetic moments have the same polarity, the resistance of the MTJ device is in a low-resistance state. Basically, the value stored in this state is represented as "0". When the magnetization directions of the free layer and the fixed layer are anti-parallel and the magnetic moments have opposite polarities, the resistance of the MTJ device is in a high-resistance state. Basically, the value stored in this state is represented as "1". Summary of the Invention

[0006] The present invention provides a semiconductor layout pattern including high-voltage components, comprising a substrate on which a high-voltage component region and a MRAM (Magnetic Random Access Memory) region are adjacent to each other. The MRAM region at least includes a plurality of MRAM cells arranged in an array, wherein each MRAM cell includes two fin structures parallel to each other and arranged along an X direction, two gate structures parallel to each other and arranged along a Y direction, a drain metal layer located between the two gate structures, two source metal layers respectively located on the other sides of the two gate structures relative to the drain metal layer, and an MTJ (Magnetic Tunnel Junction) device electrically connected to the drain metal layer.

[0007] The present invention further provides a semiconductor structure including high-voltage components, comprising a substrate on which a high-voltage component region and a MRAM (Magnetic Random Access Memory) region are adjacent to each other. The MRAM region includes a plurality of fin structures, and at least one MTJ (Magnetic Tunnel Junction) device is located on the plurality of fin structures, and a shielding structure includes a horizontal portion and a vertical portion, and the vertical portion is located between the high-voltage component region and the MRAM.

[0008] The present invention provides a semiconductor layout pattern including high-voltage components. The present invention is characterized in that a high-voltage component area and an MRAM area are integrated on a chip. The MRAM in the MRAM area is suitable for replacing the display memory in the prior art and has the advantages of non-volatility, high read / write speed, low power consumption, etc., all of which can greatly improve the performance of display driver chips. In addition, in the MRAM area of the present invention, components are fabricated on a fin structure to form three-dimensional components, so that the component area can be further reduced and the component density can be increased. However, since the high-voltage component area and the MRAM area are integrated on a chip at the same time, in order to avoid the strong electromagnetic waves generated during the operation of the high-voltage components from affecting the operation performance of the components in the MRAM area, another embodiment of the present invention provides a shielding structure, in which the shielding structure has a special shape (the horizontal part is mesh-shaped and the vertical part is fence-shaped), and has the advantages of shielding electromagnetic waves and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To make the following text easier to understand, the accompanying drawings and their detailed textual descriptions can be referred to simultaneously when reading the present invention. Through the specific embodiments in this text and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the working principles of the specific embodiments of the present invention are elaborated. In addition, for clarity, the features in the drawings may not be drawn to actual scale, so the sizes of some features in certain drawings may be deliberately enlarged or reduced.

[0010] Figure 1 Schematic diagram of the connection relationship between components of a semiconductor structure including an MRAM structure;

[0011] Figure 2 Top view of the fin structure, gate structure, drain metal layer, source metal layer, contact structure and first metal layer in the semiconductor layout of the present invention;

[0012] Figure 3 Top view of the first metal layer and the first contact post in the semiconductor layout of the present invention;

[0013] Figure 4 Top view of the first contact post and the second metal layer in the semiconductor layout of the present invention;

[0014] Figure 5 Top view of the second metal layer and the MTJ element in the semiconductor layout of the present invention;

[0015] Figure 6 Top view of the MTJ element and the third metal layer in the semiconductor layout of the present invention;

[0016] Figure 7 Top view of the shielding structure in the semiconductor structure of the present invention;

[0017] Figure 8 Schematic perspective view of the shielding structure in the semiconductor structure of the present invention;

[0018] Figure 9 Schematic cross-sectional view of the shielding structure and the MRAM structure in the semiconductor structure of the present invention.

[0019] Symbol Explanation

[0020] 10: Substrate

[0021] 100: MRAM region

[0022] 200: High-voltage component region

[0023] 300: Shielding structure

[0024] 300A: Horizontal part

[0025] 300B: Vertical part

[0026] BL: Bit line

[0027] CT: Contact structure

[0028] CT1: Source contact pillar

[0029] CT2: Drain contact pillar

[0030] D: Drain

[0031] E1: Edge

[0032] E2: Edge

[0033] E3: Edge

[0034] E4: Edge

[0035] F: Fin structure

[0036] G: Gate

[0037] M1: First metal layer

[0038] M2: Second metal layer

[0039] M3: Third metal layer

[0040] MD: Metal layer

[0041] MD1: Source contact layer

[0042] MD2: Drain metal layer

[0043] MTJ: Magnetic tunneling junction element

[0044] R1: Region

[0045] R2: Region

[0046] S: Source electrode

[0047] SL: Select line

[0048] SP: Spacer wall

[0049] T: Transistor

[0050] V1: First contact post

[0051] V2: Second contact post

[0052] WL: Word line Detailed implementation manners

[0053] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the following specifically enumerate the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, elaborate on the composition and the intended effects of the present invention in detail.

[0054] For convenience of description, the drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up-and-down relationship of the relative elements in the drawings described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. This is hereby stated in advance.

[0055] Although the present invention uses terms such as first, second, third, etc. to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and they do not inherently imply or represent any previous ordinal number of the element, nor the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the following-described first element, component, region, layer, or section can also be referred to by the term of the second element, component, region, layer, or section.

[0056] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0057] As used herein, the terms "coupled", "coupling", and "electrically connected" include any direct and indirect means of electrical connection. For example, if it is described in the text that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0058] Although the present invention is described below by way of specific embodiments, the inventive concept of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and the omitted details are within the knowledge scope of those of ordinary skill in the art.

[0059] Please refer to Figure 1 , Figure 1 , which shows a schematic diagram of the connection relationship between the components of a semiconductor structure including an MRAM structure. First, a substrate 10 includes at least one transistor T, where the transistor T includes a gate structure G, a source S, and a drain D. The gate structure G is located on the surface of the substrate 10, and the source S and the drain D are formed in the substrate 10, for example, by ion doping or the like, and are located on both sides of the gate structure G. Spacer walls SP may be included on both sides of the gate structure G.

[0060] In this embodiment, the drain D of the transistor T is connected to a first metal layer M1, a first contact via V1, a second metal layer M2, and a magnetic tunneling junction element MTJ (subsequently abbreviated as MTJ element and denoted by the label MTJ in the figure) through a contact structure CT. The MTJ element can be subsequently connected to a bit line (BL). The source S of the transistor T is connected to a select line (SL) through the contact structure CT, the first contact via V1, and the second metal layer M2. The gate structure G of the transistor T can be connected to a word line (WL). It should be noted that the bit line BL and the word line WL may not directly contact the MTJ element and the gate structure G, but are indirectly electrically connected to the MTJ element and the gate structure G through metal layers or contact vias of other layers.

[0061] In this embodiment, the MTJ element includes a pin layer, an insulating layer, and a free layer. The magnetization direction of the free layer can freely rotate and point to one or two directions, and spin-torque transfer (STT) can be used for switching. For the pin layer, an antiferromagnetic layer can be used to fix the magnetization direction in a specific direction. An isolation layer is disposed between the free layer and the pin layer. As for the connecting elements such as the first metal layer M1, the second metal layer M2, the third metal layer M3, or the contact structure CT, the first contact post V1, etc., their materials are preferably metals such as copper, tungsten, etc., but the present invention is not limited thereto. The materials and manufacturing methods of the transistor T, the MTJ element, or each metal layer or contact structure belong to the prior art in this field and will not be elaborated here.

[0062] As mentioned in the prior art, current display memories have some drawbacks. For example, they are usually composed of volatile memories, so data will be lost if the power supply is interrupted. In addition, the display memory needs to have sufficient capacity to store the image data of the entire display screen. It also needs to have sufficient bandwidth and speed to be able to read and write a large amount of data quickly.

[0063] MRAM is a non-volatile memory, and the read and write speed of MRAM is faster than that of the elements currently used in display memories. Therefore, MRAM is an element suitable for replacing the current display memory. If MRAM is used to replace the display memory, due to the non-volatile and high-speed read and write capabilities of MRAM, better data protection and faster data access speed can be provided. In addition, MRAM can also provide higher density and lower power consumption. Therefore, MRAM can store more data in a smaller area while maintaining low power consumption.

[0064] With the progress of technology, various semiconductor elements are developing three-dimensionally. For example, a semiconductor structure originally fabricated on a plane is instead fabricated on a fin-like structure to increase the density of the elements. To meet the current technological development requirements, in the first embodiment of the present invention, a semiconductor layout pattern integrating MRAM with a fin-like structure is provided. The feature of the present invention is that on a chip including high-voltage elements, a high-voltage element region is integrated with an MRAM region. As mentioned above, the characteristics of MRAM are suitable for integration in high-voltage elements (such as display driver ICs), and the MRAM region includes fin-like structures, that is, each element is formed on the fin-like structure to achieve three-dimensionalization, so the area of the MRAM region can be further reduced. Details are as follows Figures 2 to 6 shown.

[0065] Figure 2 The top view of the fin-like structure, gate structure, drain metal layer, source metal layer, contact structure, and first metal layer in the semiconductor layout of the present invention is shown. AsFigure 2 As shown, first, a plurality of fin structures F and a plurality of gate structures G are included on the substrate 10. Each fin structure F is arranged in a first direction (e.g., the X direction), and each gate structure G is arranged in a second direction (e.g., the Y direction). The gate structure G straddles each fin structure F to form the above-mentioned transistor T (simultaneously refer to Figure 1 ). In addition, in this embodiment, the region R1 is defined first, where the region R1 is the region for subsequently forming a single semiconductor unit (which includes two transistors and one MTJ element), and details will be continued to be described in the subsequent paragraphs.

[0066] A metal layer MD is further included on the substrate 10. The metal layer MD further includes a source metal layer MD1 and a drain metal layer MD2. The drain metal layer MD2 described here is located in the central part of the region R1 and between two adjacent gate structures G. As for the source metal layer MD1, it is located outside the two gate structures G, that is, on the other side relative to the drain metal layer MD2. A part of the source metal layer MD1 overlaps with the boundary of the region R1 (represented by a dotted line), which means that two adjacent semiconductor units share a source metal layer MD1.

[0067] The source metal layer MD1 and the drain metal layer MD2 straddle the fin structure F to electrically connect the source / drain and other elements formed subsequently, such as selection lines or bit lines, etc. Then, a contact structure CT and a first metal layer M1 are formed on the source metal layer MD1 and the drain metal layer MD2. The contact structure CT described here is used to connect the source metal layer MD1 and the drain metal layer MD2 with the first metal layer M1, and can be referred to together with Figure 1 . For the convenience of distinction, the contact structure located on the source metal layer MD1 is defined as the source contact pillar CT1, and the contact structure located on the drain metal layer MD2 is defined as the drain contact pillar CT2.

[0068] In the present invention, the source metal layer MD1, the drain metal layer MD2, the contact structure CT, the first metal layer M1, and other metal layers or contact pillars mentioned subsequently are formed of a conductive material, such as being composed of metals such as tungsten, cobalt, copper, aluminum, gold, silver, etc., but the present invention is not limited thereto.

[0069] Please refer to Figure 3 Figure 3 which shows a top view of the first metal layer and the first contact pillar in the semiconductor layout of the present invention. Next, continue to form the first contact pillar V1 on the Figure 2 plane layout pattern shown. For the simplicity of the drawings, from Figure 3 to Figure 6, when a new pattern layer is formed to cover an old pattern layer, only the topmost layer of the old pattern layer is drawn, while the other underlying patterns are omitted. For example, Figure 3 only draws Figure 2 the topmost first metal layer M1 in Figure 3 , and other underlying layers such as the fin structure F, the gate structure G, the source metal layer MD1, and the drain metal layer MD2 where contact structures CT are formed are not shown in Figure 2 . However, their relative positions can be referred to

[0070] In this embodiment, it should be noted that there are three first contact posts V1 in the region R1. One of the first contact posts V1 is located above the drain metal layer MD2, and the other two first contact posts V1 are located above the source metal layer MD1 (please refer to Figure 2 at the same time). And preferably, the connection lines of these three first contact posts V1 form an isosceles triangle. Among them, the lengths of the two sides E1 and E2 of the isosceles triangle are equal. In addition, the two first contact posts V1 located above the source metal layer MD1 overlap with the boundary of the region R1. Such a configuration allows two adjacent semiconductor cells to share the first contact post V1. For example, Figure 3 draws another region R2 adjacent to the region R1 in the Y direction. There is another semiconductor cell in the region R2. After the MTJ is formed in the subsequent manufacturing process, the two semiconductor cells in the regions R1 and R2 can share the first contact post V1. In addition, if the four first contact posts V1 in the regions R1 and R2 are connected, a rhombus pattern can be obtained, as shown by the dotted line in Figure 3 . Among them, the lengths of the sides E1, E2, E3, and E4 of the rhombus are equal.

[0071] Please refer to Figure 4 , Figure 4 shows a top view of the first contact post and the second metal layer in the semiconductor layout of the present invention. Then, as shown in Figure 4 , the second metal layer M2 is continuously formed. It should be noted that since the first contact posts V1 on the source metal layer MD1 are aligned along the X direction, a part of the second metal layer M2 also extends along the X direction and connects each first contact post V1 on the source metal layer MD1. This second metal layer extending along the X direction can be connected to the select line SL in the future (refer to Figure 1 ). Therefore, with the arrangement of the first contact posts V1 of the present invention, only one second metal layer M2 extending along the X direction is needed to connect the sources of adjacent semiconductor cells to the select line SL, which has the advantage of simplifying the pattern.

[0072] Please refer to Figure 5 , Figure 5A top view of the second metal layer and the MTJ element in the semiconductor layout of the present invention is shown. As Figure 5 shown, the MTJ element is continuously formed on the second metal layer M2. Structures such as tungsten contact posts may be included between the MTJ element and the second metal layer M2, but are not shown here for the sake of simplicity of the drawings. Other characteristics of the MTJ element belong to the prior art in this field and will not be elaborated here.

[0073] Please refer to Figure 6 , Figure 6 A top view of the MTJ element and the third metal layer in the semiconductor layout of the present invention is shown. As Figure 6 shown, after the MTJ element is formed, the third metal layer M3 is then formed. The third metal layer M3 extends along the X direction, but the present invention is not limited thereto. Subsequently, other metal pillars or metal layers may continue to be formed to connect the MTJ element to the third metal layer M3 to the bit line.

[0074] The above Figures 2 to 6 The planar layout diagram shown illustrates an MRAM structure including fin structures. Taking the range within the region R1 as an example, each semiconductor cell includes two transistors and one MTJ element, and thus can also be called a 2T1MTJ element. In Figures 2 to 6 the configuration shown, the layout pattern of the semiconductor structure has the effects of pattern simplification, high area utilization rate, and integration of fin structures, so as to achieve three-dimensionalization.

[0075] The region where the above MRAM structure is formed can be defined as the MRAM region. It should be noted that, as mentioned above, there is not only the MRAM region on the chip, but also a high-voltage element region, and the driving voltage of the elements included in the high-voltage element region is usually relatively large (usually greater than 10V). In other words, in the structure shown in the present invention, the high-voltage element region and the MRAM region are located on the same chip. Although it can achieve the advantages of effective area utilization, improved chip operation speed, and increased product yield (because MRAM has characteristics such as fast operation speed and non-volatility), when the high-voltage elements in the high-voltage element region operate, relatively strong electromagnetic waves may be generated, affecting other surrounding elements, such as the elements in the above MRAM region. Therefore, in another embodiment of the present invention, a shielding structure is provided and arranged between the MRAM region and the high-voltage element region to shield electromagnetic waves and reduce the influence on the elements in the MRAM region.

[0076] More specifically, please refer to Figure 7 , Figure 8 and Figure 9 . Figure 7 A top view of the shielding structure in the semiconductor structure of the present invention is shown, Figure 8 A three-dimensional schematic diagram of the shielding structure in the semiconductor structure of the present invention is shown,Figure 9 The cross-sectional structural schematic diagram of the shielding structure and the MRAM structure in the semiconductor structure of the present invention is shown. As Figures 7 to 9 shown, Figure 6 The region where the MRAM structure formed in Figure 7 is defined as the MRAM region 100, and there is another high-voltage component region 200 beside the MRAM region 100, where the MRAM region 100 is adjacent to the high-voltage component region 200. The high-voltage component region 200 contains some high-voltage components, and their driving voltage is usually greater than 10 volts. Here, for the sake of simplicity of the drawings, the high-voltage components are not shown. In this embodiment, a shielding structure 300 is included between the MRAM region 100 and the high-voltage component region 200, where the shielding structure 300 has a horizontal portion 300A and a vertical portion 300B. From the top view ( Figure 8 ), the horizontal portion 300A of the shielding structure 300 has a mesh shape, and from the side view ( Figure 7 ), the vertical portion 300B of the shielding structure 300 has a fence shape, that is, it contains a plurality of vertically arranged columns adjacent to each other. It should be noted that from

[0077] view, although the horizontal portion 300A of the shielding structure 300 is formed above the third metal layer M3, it may be formed in a dielectric layer of multiple layers above the third metal layer M3. For example, it may be formed in the same dielectric layer as the seventh metal layer (usually referred to as M7 by those skilled in the art). In other words, between the horizontal portion 300A of the shielding structure 300 and the third metal layer M3, there may also be structures such as the fourth metal layer, the fifth metal layer, the sixth metal layer, and multiple vertical conductive columns. The fourth metal layer, the fifth metal layer, the sixth metal layer, and the seventh metal layer mentioned here are other metal layers above the third metal layer M3, and their constituent materials are similar to the aforementioned first metal layer M1, second metal layer M2, third metal layer M3, etc. Other related technologies belong to the prior art in this field and will not be elaborated here.

[0078] Based on the above description and drawings, the present invention provides a semiconductor layout pattern including high-voltage components, comprising a substrate 10, on which there are a high-voltage component region 200 and a MRAM (magnetic random access memory) region 100 adjacent to each other. At least multiple MRAM cells (semiconductor cells within region R1 are regarded as one semiconductor cell) in the MRAM region 100 are arranged in an array. Each MRAM cell includes two fin structures F parallel to each other and arranged along an X direction, two gate structures G parallel to each other and arranged along a Y direction, a drain metal layer MD2 located between the two gate structures G, two source metal layers MD1 respectively located on the other sides of the two gate structures G relative to the drain metal layer MD2, and a MTJ (magnetic tunneling junction) element (element MTJ) electrically connected to the drain metal layer MD2.

[0079] In some embodiments of the present invention, in each MRAM cell, there is also a drain contact post CT2 electrically connected to and directly contacting the drain metal layer MD2, and two source contact posts CT1 electrically connected to and directly contacting the source metal layer MD1.

[0080] In some embodiments of the present invention, two adjacent MRAM cells in the Y direction share the two source contact posts CT1.

[0081] In some embodiments of the present invention, when viewed from a top view, the two source contact posts CT1 shared by two adjacent MRAM cells in the Y direction, and the drain contact posts CT2 respectively included in the two MRAM cells surround a rhombus pattern (as Figure 2 shown in Figure 3 ).

[0082] In some embodiments of the present invention, the two source contact posts CT1 are aligned in the X direction.

[0083] In some embodiments of the present invention, when viewed from a top view, the drain contact post CT2 is located between two parallel fin structures F (as Figure 2 shown in

[0084] In some embodiments of the present invention, there is also a word line WL electrically connected to the two gate structures G.

[0085] In some embodiments of the present invention, there is also a select line SL electrically connected to the two source metal layers MD1.

[0086] In some embodiments of the present invention, there is also a bit line BL electrically connected to the drain metal layer.

[0087] In some embodiments of the present invention, from a cross-sectional view, the MTJ element is located above the drain metal layer MD2, and the MTJ element is located in a dielectric layer (i.e., the dielectric layer where the third metal layer M3 is located, not shown for simplicity of the drawings).

[0088] In some embodiments of the present invention, there is also a shielding structure 300. From a cross-sectional view, the shielding structure 300 includes a horizontal portion 300A and a vertical portion 300B. The horizontal portion 300A is located in another dielectric layer above the MTJ element (i.e., for example, the dielectric layer where the seventh metal layer is located, not shown for simplicity of the drawings).

[0089] In some embodiments of the present invention, from a top view, the horizontal portion 300A of the shielding structure 300 is mesh-shaped.

[0090] In some embodiments of the present invention, from a cross-sectional view, the vertical portion 300B of the shielding structure 300 extends downward, and a bottom surface of the vertical portion 300B is lower than a bottom surface of the MTJ element (as Figure 9 shown).

[0091] In some embodiments of the present invention, from a cross-sectional view, the vertical portion 300B of the shielding structure 300 is located between the high-voltage element region 200 and the MRAM region 100.

[0092] In some embodiments of the present invention, the vertical portion 300B of the shielding structure 300 is fence-shaped, including a plurality of vertically extending columnar structures arranged parallel to each other.

[0093] The present invention further provides a semiconductor structure including high-voltage elements, including a substrate 10. On the substrate 10, there are a high-voltage element region 200 and a MRAM (magnetic random access memory) region 100 adjacent to each other. The MRAM region 100 includes a plurality of fin structures F, and at least one MTJ (magnetic tunneling junction) element is located on the plurality of fin structures, and a shielding structure 300. The shielding structure 300 includes a horizontal portion 300A and a vertical portion 300B, and the vertical portion 300B is located between the high-voltage element region 200 and the MRAM region 100.

[0094] In some embodiments of the present invention, from a cross-sectional view, the horizontal portion 300A of the shielding structure 300 is located above the MTJ (magnetic tunneling junction) element, and the horizontal portion 300A and the vertical portion 300B are an integrally formed structure.

[0095] In summary, the present invention provides a semiconductor layout pattern including high-voltage components. The present invention is characterized in that a high-voltage component area and an MRAM area are integrated on a chip. The MRAM in the MRAM area is suitable for replacing the display memory in the prior art, and has the advantages of non-volatility, high-speed read / write rate, low power consumption, etc., which can greatly improve the performance of, for example, a display driver chip. In addition, in the MRAM area of the present invention, components are fabricated on a fin structure to form three-dimensional components, so that the component area can be further reduced and the component density can be increased. However, since the high-voltage component area and the MRAM area are integrated on a chip at the same time, in order to avoid the strong electromagnetic waves generated during the operation of the high-voltage components from affecting the operation performance of the components in the MRAM area, another embodiment of the present invention provides a shielding structure, wherein the shielding structure has a special shape (the horizontal part is reticular and the vertical part is fence-shaped), and has the advantages of shielding electromagnetic waves and improving the product yield.

[0096] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. A semiconductor layout pattern including high-voltage elements, comprising: A substrate, on which a high-voltage element region and a magnetic random access memory region are adjacent to each other; Wherein the magnetic random access memory region at least includes a plurality of magnetic random access memory cells arranged in an array, and each magnetic random access memory cell includes: Two fin structures parallel to each other and arranged along the X direction; Two gate structures parallel to each other and arranged along the Y direction; A drain metal layer located between the two gate structures; Two source metal layers respectively located on the other sides of the two gate structures relative to the drain metal layer; and A magnetic tunneling junction element electrically connected to the drain metal layer.

2. The semiconductor layout pattern including high-voltage elements according to claim 1, wherein in each magnetic random access memory cell, there is also a drain contact post electrically connected to and directly contacting the drain metal layer, and two source contact posts electrically connected to and directly contacting the source metal layers.

3. The semiconductor layout pattern including high-voltage elements according to claim 2, wherein two adjacent magnetic random access memory cells in the Y direction share the two source contact posts.

4. The semiconductor layout pattern including high-voltage elements according to claim 3, wherein when viewed from a top view, the two source contact posts shared by the two adjacent magnetic random access memory cells in the Y direction, and the drain contact posts respectively included in the two magnetic random access memory cells surround a rhombus pattern.

5. The semiconductor layout pattern including high-voltage elements according to claim 2, wherein the two source contact posts are aligned in the X direction.

6. The semiconductor layout pattern including high-voltage elements according to claim 2, wherein when viewed from a top view, the drain contact post is located between the two parallel fin structures.

7. The semiconductor layout pattern including high-voltage elements according to claim 1, which further includes a word line electrically connected to the two gate structures.

8. The semiconductor layout pattern including high-voltage elements according to claim 1, which further includes a select line electrically connected to the two source metal layers.

9. The semiconductor layout pattern including high-voltage elements according to claim 1, which further includes a bit line electrically connected to the drain metal layer.

10. The semiconductor layout pattern including high-voltage elements according to claim 1, wherein when viewed from a cross-sectional view, the magnetic tunneling junction element is located above the drain metal layer, and the magnetic tunneling junction element is located in a dielectric layer.

11. The semiconductor layout pattern including high-voltage elements according to claim 10, which further includes a shielding structure. When viewed from a cross-sectional view, the shielding structure includes a horizontal portion and a vertical portion, and the horizontal portion is located in another dielectric layer above the magnetic tunneling junction element.

12. The semiconductor layout pattern including high-voltage elements according to claim 11, wherein when viewed from a top view, the horizontal portion of the shielding structure is mesh-shaped.

13. The semiconductor layout pattern including a high-voltage element as claimed in claim 11, wherein, in a sectional view, the vertical portion of the shielding structure extends downward, and the bottom surface of the vertical portion is lower than the bottom surface of the magnetic tunneling junction element.

14. The semiconductor layout pattern including a high-voltage element as claimed in claim 11, wherein, in a sectional view, the vertical portion of the shielding structure is located between the high-voltage element region and the magnetic random access memory region.

15. The semiconductor layout pattern including a high-voltage element as claimed in claim 11, wherein the vertical portion of the shielding structure is in a fence shape, including a plurality of columnar structures extending vertically and arranged in parallel with each other.

16. A semiconductor structure including a high-voltage element, comprising: a substrate, on which a high-voltage element region and a magnetic random access memory region are adjacent to each other, wherein the magnetic random access memory region includes a plurality of fin structures, and at least one magnetic tunneling junction element is located on the plurality of fin structures; and a shielding structure, the shielding structure including a horizontal portion and a vertical portion, and the vertical portion being located between the high-voltage element region and the magnetic random access memory region.

17. The semiconductor structure including a high-voltage element as claimed in claim 16, wherein, in a top view, the horizontal portion of the shielding structure is in a mesh shape.

18. The semiconductor structure including a high-voltage element as claimed in claim 16, wherein, in a sectional view, the vertical portion of the shielding structure extends downward, and the bottom surface of the vertical structure is lower than the bottom surface of the magnetic tunneling junction element.

19. The semiconductor structure including a high-voltage element as claimed in claim 16, wherein, in a sectional view, the vertical portion of the shielding structure is in a fence shape, including a plurality of columnar structures extending vertically and arranged in parallel with each other.

20. The semiconductor structure including a high-voltage element as claimed in claim 16, wherein, in a sectional view, the horizontal portion of the shielding structure is located above the magnetic tunneling junction element, and the horizontal portion and the vertical portion are of an integrally formed structure.

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