Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device. The preparation method comprises the following steps: providing a substrate; mOS structures are formed in and on the substrate, an interconnection structure layer is formed on the MOS structures, and the interconnection structure layer is electrically connected with the MOS structures; the measurement threshold voltage of the MOS structure is obtained through measurement of the interconnection structure layer, and a target power value corresponding to a target threshold voltage is adjusted according to the difference value between the measurement threshold voltage and the target threshold voltage to obtain the power of the first ultraviolet irradiation process; forming a low-K dielectric layer to cover the interconnection structure layer; performing a first ultraviolet irradiation process on the dielectric layer at the power of the first ultraviolet irradiation process to reach a target threshold voltage; according to the invention, the threshold voltage of the semiconductor device is regulated to reach the target threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] In the manufacture of semiconductor devices, it is necessary to adjust the threshold voltage of the semiconductor device to meet the requirements of circuit design. Currently, generally, the doping concentration of the semiconductor device is changed by ion implantation to adjust the threshold voltage of the semiconductor device. However, when using ion implantation to adjust the threshold voltage of the semiconductor device, if the implantation energy or dose is too large, it will damage the existing patterns, resulting in device defects and affecting the device yield; and due to process fluctuations, the actual threshold voltage may also shift under the same ion implantation dose, which may seriously affect the device yield. When the threshold voltage parameter is measured during the subsequent wafer testing, it is no longer possible to adjust it. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for manufacturing a semiconductor device to achieve the adjustment of the threshold voltage of the semiconductor device to reach the target threshold voltage.

[0004] To achieve the above purpose, the present invention provides a method for manufacturing a semiconductor device, including:

[0005] Providing a substrate;

[0006] Forming a MOS structure in and on the substrate, and forming an interconnection structure layer on the MOS structure, the interconnection structure layer being electrically connected to the MOS structure;

[0007] Measuring and obtaining the measured threshold voltage of the MOS structure through the interconnection structure layer, and adjusting the target power value corresponding to the target threshold voltage according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of a first ultraviolet light irradiation process;

[0008] Forming a low-K dielectric layer to cover the interconnection structure layer; and,

[0009] Performing the first ultraviolet light irradiation process on the dielectric layer with the power of the first ultraviolet light irradiation process to reach the target threshold voltage.

[0010] Optionally, the target power value is obtained by simulating an ultraviolet light irradiation process simulation before manufacturing the semiconductor device.

[0011] Optionally, the power of the target power value is 30W to 100W.

[0012] Optionally, the step of obtaining the power of the first ultraviolet light irradiation process includes:

[0013] Obtain the difference between the measured threshold voltage and the target threshold voltage;

[0014] According to the difference between the measured threshold voltage and the target threshold voltage, obtain the power change amount corresponding to the difference between the measured threshold voltage and the target threshold voltage;

[0015] Adjust the target power value according to the power change amount to obtain the power of the first ultraviolet light irradiation process.

[0016] Optionally, the power of the first ultraviolet light irradiation process has a linear relationship with the target threshold voltage.

[0017] Optionally, the power of the first ultraviolet light irradiation process is 20W - 120W, and the time of the first ultraviolet light irradiation process is 60S - 120S.

[0018] Optionally, the MOS structure includes a gate oxide layer, form the gate oxide layer on the substrate, and perform a second ultraviolet light irradiation process after forming the gate oxide layer.

[0019] Optionally, the semiconductor device includes an NMOS device or a PMOS device. When the semiconductor device is an NMOS device, the power of the second ultraviolet light irradiation process is less than the target power value; when the semiconductor device is a PMOS device, the power of the second ultraviolet light irradiation process is greater than the target power value.

[0020] Optionally, the power of the second ultraviolet light irradiation process is 20W - 120W, and the time of the second ultraviolet light irradiation process is 60S - 120S.

[0021] Optionally, the MOS structure includes a gate oxide layer, a high-K dielectric layer, a metal gate and sidewalls located on the substrate, and a lightly doped region, a source region and a drain region located in the substrate. The interconnect structure layer includes an interconnect dielectric layer, an electrical connector and a metal layer. The interconnect dielectric layer covers the MOS structure, the electrical connector penetrates the interconnect dielectric layer and is electrically connected to the MOS structure, and the metal layer is electrically connected to the electrical connector.

[0022] In the method for manufacturing a semiconductor device provided by the present invention, a substrate is provided, a MOS structure is formed in and on the substrate, and an interconnection structure layer is formed on the MOS structure. The interconnection structure layer is electrically connected to the MOS structure. The measured threshold voltage of the MOS structure is obtained by measuring through the interconnection structure layer. The target power value corresponding to the target threshold voltage is adjusted according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of a first ultraviolet light irradiation process. A low-K dielectric layer is formed to cover the interconnection structure layer. The first ultraviolet light irradiation process is performed on the dielectric layer with the power of the first ultraviolet light irradiation process to reach the target threshold voltage. In the present invention, after the MOS structure and the interconnection structure layer are formed, the measured threshold voltage of the MOS structure is obtained. The target power value corresponding to the target threshold voltage is adjusted according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of the first ultraviolet light irradiation process. Then, the first ultraviolet light irradiation process is performed on the dielectric layer with the power of the first ultraviolet light irradiation process, which can compensate for the difference between the measured threshold voltage and the target threshold voltage to reach the target threshold voltage. Therefore, the threshold voltage of the semiconductor device is regulated to reach the target threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flowchart of the method for manufacturing a semiconductor device provided by the present invention;

[0024] Figures 2 to 8 is a cross-sectional schematic diagram of corresponding steps in the method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0025] Wherein, the reference numerals are:

[0026] 10 - Substrate; 20 - Gate oxide layer; 21 - High-K dielectric layer; 22 - Polysilicon layer; 23 - Sidewall; 24 - First opening; 25 - Second opening; 26 - Metal gate; 31 - Lightly doped region; 32 - Source region; 33 - Drain region; 41 - First interconnection dielectric layer; 42 - Second interconnection dielectric layer; 51 - First electrical connector; 52 - Second electrical connector; 53 - Third electrical connector; 61 - First metal pattern; 62 - Second metal pattern; 63 - Third metal pattern; 70 - Low-K dielectric layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the focus to be shown in each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] Figure 1 The flowchart of the method for manufacturing a semiconductor device provided by the present invention. Please refer to Figure 1 The present invention provides a method for manufacturing a semiconductor device, including:

[0030] Step S1: Provide a substrate with a gate oxide layer formed thereon;

[0031] Step S2: Form a MOS structure in and on the substrate, and form an interconnection structure layer on the MOS structure, the interconnection structure layer being electrically connected to the MOS structure;

[0032] Step S3: Measure the threshold voltage of the MOS structure through the interconnection structure layer, and adjust the target power value corresponding to the target threshold voltage according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of the first ultraviolet light irradiation process;

[0033] Step S4: Form a low-K dielectric layer to cover the interconnection structure layer;

[0034] Step S5: Perform the first ultraviolet light irradiation process on the dielectric layer with the power of the first ultraviolet light irradiation process to reach the target threshold voltage.

[0035] Figures 2 to 8 The cross-sectional schematic diagram of the corresponding steps in the method for manufacturing a semiconductor device provided in this embodiment. The following combines Figures 2 to 8 to describe in detail the method for manufacturing a semiconductor device provided in this embodiment.

[0036] Please refer to Figure 2 and perform Step S1: Provide a substrate 10, and the substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate.

[0037] Execute step S2: Form a MOS structure (device structure) in and on the substrate, and form an interconnect structure layer on the MOS structure. The interconnect structure layer is electrically connected to the MOS structure. The MOS structure includes a gate oxide layer, a high-K dielectric layer, a metal gate, and sidewalls located on the substrate, and a lightly doped region, a source region, and a drain region located in the substrate. The interconnect structure layer includes an interconnect dielectric layer (a first interconnect dielectric layer and a second interconnect dielectric layer), electrical connectors (second to third electrical connectors), and metal layers (second to third metal patterns). The interconnect dielectric layer covers the MOS structure. The electrical connectors penetrate the interconnect dielectric layer and are electrically connected to the MOS structure. The metal layers are electrically connected to the electrical connectors. Since the gate oxide layer has been formed first, this step completes the preparation of the MOS structure and the formation of the interconnect structure layer.

[0038] Specifically, please continue to refer to Figure 2 , form a gate oxide layer 20 on the substrate 10. A chemical vapor deposition process or a thermal oxidation process can be used. The gate oxide layer 20 can be a silicon oxide layer, and the thickness of the gate oxide layer 20 is determined according to the actual situation. Please refer to Figure 3 , form a high-K dielectric layer 21 and a polysilicon layer 22 on the gate oxide layer 20. The material of the high-K dielectric layer 21 can be hafnium oxide, hafnium oxide, or aluminum oxide. Please refer to Figure 4 , etch the polysilicon layer 22, the high-K dielectric layer 21, and the gate oxide layer 20 to form a first opening 24 exposing the substrate 10. Furthermore, form a lightly doped region 31 in the substrate 10 on both sides of the polysilicon layer 22, the high-K dielectric layer 21, and the gate oxide layer 20. Subsequently, form sidewalls 23 on both sides of the polysilicon layer 22, the high-K dielectric layer 21, and the gate oxide layer 20, and then form a source region 32 and a drain region 33 in the substrate 10 on both sides of the polysilicon layer 22, the high-K dielectric layer 21, and the gate oxide layer 20 respectively. The formed lightly doped region 31, source region 32, and drain region 33 mainly regulate the threshold voltage of the semiconductor device. Please refer to Figure 5 , form a first interconnect dielectric layer 41 to fill the first opening 24, and the first interconnect dielectric layer 41 exposes the polysilicon layer, and remove the polysilicon layer to form a second opening 25. Please refer to Figure 6 , fill the second opening with a metal material to form a metal gate 26. Please refer to Figure 7, a second interconnection dielectric layer 42 is formed to cover the first interconnection dielectric layer 41 and the metal gate 26; a first electrical connector 51 is formed to penetrate through the second interconnection dielectric layer 42 and be electrically connected to the metal gate 26, a second electrical connector 52 is formed to penetrate through the second interconnection dielectric layer 42 and the first interconnection dielectric layer 41 and be electrically connected to the source region 32, and a third electrical connector 53 is formed to penetrate through the second interconnection dielectric layer 42 and the first interconnection dielectric layer 41 and be electrically connected to the drain region 33; a metal layer is formed to cover the second interconnection dielectric layer 42, and the metal layer is patterned to form a first metal pattern 61, a second metal pattern 62, and a third metal pattern 63. The first metal pattern 61 is electrically connected to the first electrical connector 51, the second metal pattern 62 is electrically connected to the second electrical connector 52, and the third metal pattern 63 is electrically connected to the third electrical connector 53.

[0039] Since the semiconductor device has a corresponding target threshold voltage, in order to achieve the target threshold voltage, in addition to forming the necessary lightly doped regions, source regions, and drain regions (which mainly regulate the threshold voltage of the semiconductor device), ion implantation is also used as described in the background art to regulate the threshold voltage of the semiconductor device to achieve the target threshold voltage. For example, an additional doped region is formed at the top or bottom of the source region or drain region to regulate the threshold voltage of the semiconductor device. This method is likely to generate defects in the device structure, affecting the product yield, and is also easily affected by the manufacturing process during ion implantation. Therefore, in this embodiment, it is not necessary to form an additional doped region to regulate the threshold voltage of the device. In this embodiment, ultraviolet light irradiation is used at different process nodes to regulate the threshold voltage of the device to achieve the target threshold voltage, which can avoid generating defects in the device structure and affecting the product yield.

[0040] The principle of using ultraviolet light irradiation to regulate the threshold voltage of a device is as follows: Ultraviolet light irradiation causes electron-hole pairs to be generated at the interface between the gate oxide layer and the substrate. Since the Fermi level of the metal gate is relatively low, electrons escape from the metal gate. As the electrons in the substrate cannot neutralize the holes through tunneling, the holes migrate to the interface between the gate oxide layer and the substrate and accumulate, generating an additional pressure difference in the semiconductor device to regulate the threshold voltage of the semiconductor device to reach the target threshold voltage. The density of holes at the interface between the gate oxide layer and the substrate is related to the generated additional pressure difference and the power of ultraviolet light irradiation. The higher the power of ultraviolet light irradiation, the greater the density of holes at the interface between the gate oxide layer and the substrate, the greater the additional pressure difference generated in the semiconductor device, and the greater the change in the threshold voltage of the semiconductor device. That is, the power of ultraviolet light irradiation has a linear relationship with the threshold voltage of the semiconductor device. In this embodiment, the semiconductor device includes an NMOS device or a PMOS device. Due to the difference in device types, for the NMOS device, the higher the power of ultraviolet light irradiation, the greater the density of holes at the interface between the gate oxide layer and the substrate, which will cause the threshold voltage of the NMOS device to decrease. The power of ultraviolet light irradiation has a decreasing linear relationship with the threshold voltage of the NMOS device; for the PMOS device, the higher the power of ultraviolet light irradiation, the greater the density of holes at the interface between the gate oxide layer and the substrate, which will cause the threshold voltage of the PMOS device to increase. The power of ultraviolet light irradiation has an increasing linear relationship with the threshold voltage of the PMOS device.

[0041] Please continue to refer to Figure 7 , perform step S3: After the preparation in step S2, due to the influence of the preparation process (such as high-temperature annealing), the threshold voltage of the semiconductor device drifts, or there is a deviation between the threshold voltage of the semiconductor device after preparation and the target threshold voltage. Therefore, it is necessary to measure the measured threshold voltage of the MOS structure to facilitate subsequent regulation of the threshold voltage of the semiconductor device. The interconnect structure layer is electrically connected to the MOS structure, and the measured threshold voltage of the MOS structure is obtained by measuring through the interconnect structure layer. Specifically, a voltage is applied to the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 to measure the measured threshold voltage of the MOS structure.

[0042] Furthermore, adjust the target power value corresponding to the target threshold voltage according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of the first ultraviolet light irradiation process. Specifically, obtain the difference between the measured threshold voltage and the target threshold voltage of the semiconductor device; in this embodiment, the power of the first ultraviolet light irradiation process has a linear relationship with the target threshold voltage, and the target threshold voltage corresponds to a target power value. According to the difference between the measured threshold voltage and the target threshold voltage, obtain the power change amount corresponding to the difference between the measured threshold voltage and the target threshold voltage; adjust the target power value according to the power change amount to obtain the power of the first ultraviolet light irradiation process.

[0043] In this embodiment, the target power value is the power of the ultraviolet light irradiation process corresponding to the target threshold voltage. The target power value is obtained by simulating the ultraviolet light irradiation process before the semiconductor device is fabricated, generally by simulating semiconductor processes and device simulation tools (Technology Computer Aided Design, TCAD). In TCAD, the process parameters of the semiconductor device are set, and the process parameters include the target threshold voltage. The ultraviolet light irradiation process is simulated at the process node. The ultraviolet light irradiation process can be simulated after the interconnection structure layer is formed. The power of the simulated ultraviolet light irradiation process has a linear relationship with the threshold voltage of the semiconductor device. By changing the power of the simulated ultraviolet light irradiation process, the threshold voltage of the semiconductor device is adjusted to reach the target threshold voltage. The power of the simulated ultraviolet light irradiation process corresponding to the target threshold voltage is set as the target power value, that is, the target power value corresponding to the target threshold voltage is obtained by simulation. In this embodiment, the power of the target power value is 30W to 100W. For example, the target power value is 70W, and the process execution time can be 90S, but it is not limited thereto.

[0044] Please refer to Figure 8 , perform step S4: form a low-K dielectric layer 70 to cover the interconnection structure layer (covering the first metal pattern 61, the second metal pattern 62, the third metal pattern 63, and a part of the second interconnection dielectric layer 42); in this embodiment, the material of the low-K dielectric layer 70 can be an organic polymer, amorphous carbon chloride, ultra-small foam, silicon-based insulator containing an organic polymer, carbon-doped silicon oxide, and chlorine-doped silicon oxide. K represents the dielectric constant, and high and low are relative to the dielectric constant of silicon dioxide. The dielectric constant of silicon dioxide is usually 3.9, and the thickness of the low-K dielectric layer 70 is determined according to the actual situation.

[0045] Please continue to refer to Figure 8 , perform step S5: perform a first ultraviolet light irradiation process on the dielectric layer 70 with the power of the first ultraviolet light irradiation process ( Figure 8 the arrow direction in is the direction of ultraviolet light irradiation), and the ultraviolet light can penetrate the dielectric layer 70 and the interconnection structure layer to affect the interface between the gate oxide layer 20 and the substrate 10 to change the hole density at the interface between the gate oxide layer 20 and the substrate 10, so as to generate an additional pressure difference in the semiconductor device to adjust the threshold voltage of the semiconductor device to reach the target threshold voltage. In this embodiment, the wavelength of the first ultraviolet light irradiation process can be 185nm, the power of the first ultraviolet light irradiation process can be 20W to 120W, and the time of the first ultraviolet light irradiation process can be 60S to 600S, but it is not limited thereto.

[0046] In this embodiment, after the MOS structure and the interconnect structure layer are formed, the measured threshold voltage of the MOS structure is obtained. Due to the influence of the manufacturing process, the threshold voltage of the semiconductor device will drift, or there will be a deviation between the threshold voltage of the semiconductor device after manufacturing and the target threshold voltage (there will be a certain deviation in both cases. In the prior art, ion implantation is generally performed after the MOS structure is formed for adjustment). Then, according to the difference between the measured threshold voltage and a target threshold voltage, the target power value corresponding to the target threshold voltage is adjusted to obtain the power of the first ultraviolet light irradiation process. Then, the dielectric layer is subjected to the first ultraviolet light irradiation process with the power of the first ultraviolet light irradiation process (changing the hole density at the interface between the gate oxide layer and the substrate), which can compensate for the difference between the measured threshold voltage and the target threshold voltage to reach the target threshold voltage, without the need for ion implantation to adjust the threshold voltage, and can avoid generating defects in the MOS structure and affecting the product yield.

[0047] In other embodiments, please continue to refer to Figure 2 , after the gate oxide layer 20 is formed, the second ultraviolet light irradiation process is immediately performed on the gate oxide layer 20 ( Figure 2 the direction of the arrow in is the direction of ultraviolet light irradiation), and then the preparation of the MOS structure is completed; the wavelength of the second ultraviolet light irradiation process can be 185 nm, the power of the second ultraviolet light irradiation process can be 20 W to 120 W, and the time of the second ultraviolet light irradiation process can be 60 S to 600 S, which is not limited thereto. The target threshold voltage corresponds to a target power value, and similarly, the target power value is obtained by simulating the ultraviolet light irradiation process simulation before the semiconductor device is manufactured and is the same as the target power value in step S3. When the semiconductor device is an NMOS device, the power of the second ultraviolet light irradiation process is less than the target power value; when the semiconductor device is a PMOS device, the power of the second ultraviolet light irradiation process is greater than the target power value. Performing the second ultraviolet light irradiation process can first assist in regulating the threshold voltage of the semiconductor device to generate hole-electron pairs at the interface between the gate oxide layer and the substrate and generate an additional pressure difference in the semiconductor device.

[0048] In summary, in the method for manufacturing a semiconductor device provided by the present invention, a substrate is provided, a MOS structure is formed in and on the substrate, and an interconnect structure layer is formed on the MOS structure. The interconnect structure layer is electrically connected to the MOS structure; the measured threshold voltage of the MOS structure is obtained by measuring through the interconnect structure layer, and the target power value corresponding to the target threshold voltage is adjusted according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of the first ultraviolet light irradiation process; a low-K dielectric layer is formed to cover the interconnect structure layer; the first ultraviolet light irradiation process is performed on the dielectric layer with the power of the first ultraviolet light irradiation process to reach the target threshold voltage. In the present invention, after the MOS structure and the interconnect structure layer are formed, the measured threshold voltage of the MOS structure is obtained, the target power value corresponding to the target threshold voltage is adjusted according to the difference between the measured threshold voltage and a target threshold voltage to obtain the power of the first ultraviolet light irradiation process, and then the first ultraviolet light irradiation process is performed on the dielectric layer with the power of the first ultraviolet light irradiation process, which can compensate for the difference between the measured threshold voltage and the target threshold voltage to reach the target threshold voltage. Therefore, the threshold voltage of the semiconductor device is adjusted to reach the target threshold voltage.

[0049] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of not departing from the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate; Forming a MOS structure in and on the substrate, and forming an interconnection structure layer on the MOS structure, the interconnection structure layer being electrically connected to the MOS structure; Obtaining a measured threshold voltage of the MOS structure through measurement by the interconnection structure layer, and adjusting a target power value corresponding to the target threshold voltage according to a difference between the measured threshold voltage and a target threshold voltage to obtain a power of a first ultraviolet light irradiation process; Forming a low-K dielectric layer to cover the interconnection structure layer; And Performing the first ultraviolet light irradiation process on the dielectric layer with the power of the first ultraviolet light irradiation process to reach the target threshold voltage.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The target power value is obtained by simulating an ultraviolet light irradiation process simulation before semiconductor device fabrication.

3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, The power of the target power value is 30W to 100W.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The steps of obtaining the power of the first ultraviolet light irradiation process include: Obtaining a difference between the measured threshold voltage and the target threshold voltage; Obtaining a power change amount corresponding to the difference between the measured threshold voltage and the target threshold voltage according to the difference between the measured threshold voltage and the target threshold voltage; Adjusting the target power value according to the power change amount to obtain the power of the first ultraviolet light irradiation process.

5. The method for manufacturing a semiconductor device according to claim 4, wherein, The power of the first ultraviolet light irradiation process has a linear relationship with the target threshold voltage.

6. The method for preparing a semiconductor device according to claim 1 or 4, characterized in that, The power of the first ultraviolet light irradiation process is 20W to 120W, and the time of the first ultraviolet light irradiation process is 60S to 120S.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The MOS structure includes a gate oxide layer, the gate oxide layer is formed on the substrate, and a second ultraviolet light irradiation process is performed after the gate oxide layer is formed.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The semiconductor device includes an NMOS device or a PMOS device. When the semiconductor device is an NMOS device, the power of the second ultraviolet light irradiation process is less than the target power value; when the semiconductor device is a PMOS device, the power of the second ultraviolet light irradiation process is greater than the target power value.

9. The method for manufacturing a semiconductor device according to claim 1 or 8, characterized in that, The power of the second ultraviolet light irradiation process is 20W to 120W, and the time of the second ultraviolet light irradiation process is 60S to 120S.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The MOS structure includes a gate oxide layer, a high-K dielectric layer, a metal gate, and sidewalls located on the substrate, and a lightly doped region, a source region, and a drain region located in the substrate. The interconnection structure layer includes an interconnection dielectric layer, an electrical connector, and a metal layer. The interconnection dielectric layer covers the MOS structure. The electrical connector penetrates through the interconnection dielectric layer and is electrically connected to the MOS structure. The metal layer is electrically connected to the electrical connector.

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