Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a sacrificial feature in a substrate, forming a source / drain feature over the sacrificial feature, the source / drain feature protruding from the substrate, planarizing the substrate from a backside of the substrate to reduce a thickness of the substrate, performing a first etch process to selectively remove the substrate without substantially etching the sacrificial feature, and performing a second etch process to selectively remove the substrate from the backside of the substrate without substantially etching the sacrificial feature. The method includes forming a sacrificial feature, forming a dielectric layer adjacent to and under the sacrificial feature, performing a second etching process to form a trench in the dielectric layer to expose the sacrificial feature, performing a third etching process to selectively remove the sacrificial feature, and forming a conductive feature in the trench.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each having smaller and more complex circuits than the previous generation. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling generally provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology advances towards smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has an elevated channel (e.g., a gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate) that is wrapped by a gate on more than one side. A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed of nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives rise to alternative names for the GAA transistor, such as a nanosheet transistor or a nanowire transistor.

[0004] As the size of multi-gate devices shrinks, it becomes increasingly challenging to package all contact components on one side of the substrate. To reduce the packaging density, routing components can be moved to the backside of the substrate. Such routing components can include backside vias. Although existing backside via formation processes are generally sufficient for their intended purposes, they are not satisfactory in all aspects. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method of forming a semiconductor structure, including: receiving a structure including: a plurality of channel members disposed above a substrate; a gate structure wrapping each of the plurality of channel members; and source / drain components adjacent to the plurality of channel members, wherein the source / drain components are disposed above semiconductor components extending into the substrate; replacing the substrate with a dielectric layer; forming a mask having an opening exposing a portion of the dielectric layer; removing the portion of the dielectric layer to form a trench exposing the semiconductor components; selectively removing the semiconductor components to vertically extend the trench; and forming a via in the extended trench.

[0006] Another embodiment of the present disclosure provides a method of forming a semiconductor structure, including: forming a sacrificial component in a substrate; forming source / drain components above the sacrificial component, and the source / drain components protruding from the substrate; planarizing the substrate from a back side of the substrate to reduce a thickness of the substrate; performing a first etching process to selectively remove the substrate with substantially no etching of the sacrificial component; forming a dielectric layer adjacent to and below the sacrificial component; performing a second etching process to form a trench in the dielectric layer to expose the sacrificial component; performing a third etching process to selectively remove the sacrificial component; and forming a conductive component in the trench.

[0007] Yet another embodiment of the present disclosure provides a semiconductor structure, including: a plurality of nanostructures located above a dielectric layer; a gate structure wrapping each of the plurality of nanostructures and located above the dielectric layer; source / drain components coupled to at least one of the plurality of nanostructures; and vias extending through the dielectric layer to couple to the source / drain components, wherein, in a cross-sectional view, the vias have an asymmetric profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A flowchart of a method for forming a semiconductor structure having backside vias in accordance with one or more aspects of the present disclosure is shown.

[0010] Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A illustrate partial perspective views of a semiconductor structure during various manufacturing stages in a method of Figure 1 in accordance with one or more aspects of the present disclosure.

[0011] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18 illustrate partial cross-sectional views of a semiconductor structure during various manufacturing stages in a method of Figure 1 in accordance with one or more aspects of the present disclosure.

[0012] Figure 19 illustrates a flowchart of a first alternative method for forming a semiconductor structure having a backside via in accordance with one or more aspects of the present disclosure.

[0013] Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26A and Figure 26B illustrate partial cross-sectional views of a semiconductor structure during various manufacturing stages in a method of Figure 19 in accordance with one or more aspects of the present disclosure.

[0014] Figure 27 illustrates a flowchart of a second alternative method for forming a semiconductor structure having a backside via in accordance with one or more aspects of the present disclosure.

[0015] Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A , Figure 34A and Figure 35Ashows a partial perspective view of a semiconductor structure during various manufacturing stages in a method of Figure 27 The local perspective view of the semiconductor structure during each manufacturing stage in the method of

[0016] Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B , Figure 34B , Figure 35B and Figure 36 shows a partial cross - sectional view of a semiconductor structure during various manufacturing stages in a method of Figure 27 The local cross - sectional view of the semiconductor structure during each manufacturing stage in the method of DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the embodiments and / or configurations being discussed.

[0018] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0019] Additionally, when terms such as "about" or "approximate" are used to describe a numerical value or a range of numerical values, the term is intended to encompass values within a reasonable range, taking into account the inherent variations during manufacturing that are understood by those of ordinary skill in the art. For example, based on the known manufacturing tolerances associated with manufacturing a component having a property associated with that numerical value, the numerical value or range of numerical values encompasses a reasonable range including the recited numerical value, such as within + / - 10% of the recited numerical value. For example, a material layer having a thickness of "about 5 nm" can encompass a dimension range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with depositing the material layer are known to those of ordinary skill in the art to be + / - 15%. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the embodiments and / or configurations being discussed.

[0020] Source / drain contacts and gate contacts of a transistor on a substrate connect the source / drain components of the transistor to an interconnect structure above the front side of the substrate. As the size of IC devices shrinks, the close proximity between the source / drain contacts and the gate contacts can reduce the process window for forming these contacts and may increase the parasitic capacitance between them. A backside power rail (BPR) structure is a modern solution to alleviate the congestion of the contacts. In some scenarios, backside vias can be formed from the backside of the substrate and couple the source / drain components to the backside power rail. In some prior arts, forming non-self-aligned backside vias may involve performing lithography for patterning. However, the alignment coverage (e.g., overlay offset) associated with patterning may result in an electrical short between the backside vias and adjacent gate structures. Forming self-aligned backside vias can solve this problem. However, prior arts for forming self-aligned backside vias may involve forming deep trenches in the source / drain regions, which can be very challenging for forming semiconductor devices with reduced pitch.

[0021] The present disclosure provides methods for forming self-aligned backside source / drain vias without forming deep trenches in the source / drain regions. In an exemplary method, shallow trenches are formed in the source / drain regions. Sacrificial semiconductor components can be formed to fill the lower portions of the shallow trenches, and source / drain components can be formed to fill the upper portions of the shallow trenches. After forming a functional gate structure and interconnects above the front side of the substrate, the substrate is replaced with a dielectric layer, and then a first etching process is performed to form trenches exposing the sacrificial semiconductor components, followed by a second etching process to selectively remove the sacrificial semiconductor components to extend the trenches. Then, backside vias are formed under the source / drain components and in the extended trenches. Thus, self-aligned backside vias can be formed without forming deep trenches in the source / drain regions, and the coverage window for the lithography process for forming the trenches can be relaxed, which can facilitate the scaling down of the gate-to-gate pitch.

[0022] Aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flowchart showing a method 100 of forming a semiconductor structure 200 according to an embodiment of the present disclosure. The method 100 will be described below in conjunction with Figures 2A to 18 Describe method 100, Figures 2A to 18 is a partial perspective view or cross-sectional view of the semiconductor structure 200 at different manufacturing stages according to an embodiment of the method 100. Figure 19 is a flowchart showing a method 300 of forming a semiconductor structure 400 according to an embodiment of the present disclosure. The method 300 will be described below in conjunction with Figures 20 to 26B Describe method 300, Figures 20 to 26B is a partial cross-sectional view of the semiconductor structure 400 at different manufacturing stages according to an embodiment of the method 300. Figure 27 is a flowchart showing a method 500 of forming a semiconductor structure 600 according to an embodiment of the present disclosure. The method 500 will be described below in conjunction with Figures 28A to 36 Describe method 500, Figures 28A to 36 is a partial perspective view or cross-sectional view of the semiconductor structure 600 at different manufacturing stages according to an embodiment of the method 500. The methods 100, 300, 500 are merely examples and are not intended to limit the present disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and / or after the methods 100, 300, 500, and for additional embodiments of the method, some of the described steps may be replaced, eliminated, or rearranged. For simplicity, not all steps are described in detail here. To avoid doubt, Figures 2A to 36 The X, Y, and Z directions in

[0023] Refer to Figure 1 and Figures 2A to 2B, method 100 includes block 102, in which a semiconductor structure 200 is received. The semiconductor structure 200 includes a substrate 201. In some embodiments, the substrate 201 is a bulk silicon substrate (i.e., including bulk single-crystalline silicon). In various embodiments, the substrate 201 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof or other suitable materials. In some alternative embodiments, the substrate 201 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods. In the depicted embodiment, the substrate 201 is an SOI substrate and includes a carrier layer 202, an insulator layer 203 located on the carrier layer 202, and a semiconductor layer 204 located on the insulator layer 203. In some embodiments, the semiconductor layer 204 may be silicon, silicon-germanium, germanium, or other suitable materials, and may be undoped or unintentionally doped with a very low dose of dopants. In the depicted example, the carrier layer 202 includes silicon, the insulator layer 203 includes silicon oxide, and the semiconductor layer 204 includes silicon (i.e., single-crystalline silicon).

[0024] The semiconductor structure 200 further includes fin structures 205 located above the substrate 201. Each fin structure 205 extends longitudinally along the X direction and is divided into a channel region 205C overlapped by a pseudo-gate stack 210 and a source / drain region 205SD not covered by the pseudo-gate stack 210. Depending on the context, the source / drain region 205SD may refer to the source region or the drain region individually or jointly. Each channel region 205C is disposed between two source / drain regions 205SD along the X direction. The fin structures 205 may be formed from portions of a semiconductor layer 204 and a vertical stack of alternating semiconductor layers 206 and 208 using a combination of lithography and etching steps. Exemplary lithography processes include spin-coating a photoresist layer, soft baking the photoresist layer, mask alignment, exposure, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some cases, double patterning or multiple patterning processes may be used to perform the patterning of the fin structures 205 to create a pattern having a pitch smaller than the pitch obtainable using a single direct lithography process. The etching process may include dry etching, wet etching, and / or other suitable processes. In the depicted embodiment, the vertical stack of alternating semiconductor layers 206 and 208 may include a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. Each channel layer 208 may be formed of silicon (Si), and each sacrificial layer 206 may be formed of silicon germanium (SiGe). The channel layers 208 and the sacrificial layers 206 may be epitaxially deposited on the substrate 201 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), and / or other suitable epitaxial growth processes.

[0025] As Figure 2A shown, the semiconductor structure 200 further includes an isolation component 207 located around the fin structures 205 to isolate the fin structures 205 from adjacent fin structures 205. In some embodiments, the isolation component 207 is deposited in a trench that defines the fin structures 205. Such a trench may extend through the channel layer 208 and the sacrificial layer 206 and terminate at the substrate 201. The isolation component 207 may also be referred to as a shallow trench isolation (STI) component 207. In an exemplary process, a dielectric material for the isolation component is deposited above the semiconductor structure 200 using chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), flowable CVD (FCVD), physical vapor deposition (PVD), spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed until the fin structures 205 rise above the isolation component 207. The dielectric material for the isolation component 207 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0026] Still referring toFigures 2A to 2B The semiconductor structure 200 further includes a dummy gate stack 210 disposed over the channel region 205C of the fin structure 205. Figures 2A to 2B Two dummy gate stacks 210 are shown, but the semiconductor structure 200 may include more dummy gate stacks 210. In this embodiment, a gate replacement process (or post-gate process) is employed, where the dummy gate stack 210 serves as a placeholder for the functional gate structure 240. Other processes and configurations are possible. The dummy gate stack 210 includes a dummy dielectric layer 211, a dummy gate electrode layer 212 disposed over the dummy dielectric layer 211, and a gate top hard mask layer 215 disposed over the dummy gate electrode layer 212. The dummy dielectric layer 211 may include silicon oxide. The dummy gate electrode layer 212 may include polysilicon. The gate top hard mask layer 215 may be a multi-layer including a silicon oxide layer 213 and a silicon nitride layer 214 disposed on the silicon oxide layer 212. Suitable deposition processes, photolithography, and etching processes may be employed to form the dummy gate stack 210.

[0027] As Figures 2A to 2B shown, the semiconductor structure 200 further includes a gate spacer layer 216 disposed over the semiconductor structure 200. The gate spacer layer 216 may be a single-layer or multi-layer structure. In an embodiment, the gate spacer layer 216 includes a first spacer layer and a second spacer layer conformally deposited over the semiconductor structure 200 (including over the top surface and sidewalls of the dummy gate stack 210 and over the top surface of the fin structure 205). For the purpose of describing a layer having a substantially uniform thickness over various regions, the term "conformally" may be used herein. In some embodiments, the gate spacer layer 216 may include silicon oxide, silicon carbon oxide, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material, and may be deposited over the dummy gate stack 210 using a process such as CVD, SACVD, FCVD, atomic layer deposition (ALD), PVD, or other suitable processes.

[0028] Referring Figure 1 and Figures 3A to 3B , method 100 includes block 104, where the source / drain regions 205SD of the fin structure 205 are recessed to form source / drain openings 218. In an embodiment, an etching process is performed to etch back the gate spacer layer 216, thereby forming gate spacers 216a extending along the sidewall surfaces of the dummy gate stack 210. The etch back of the gate spacer layer 216 also forms fin sidewall spacers 216b extending along the lower portion of the fin structure 205 (as Figure 3Aas shown). The source / drain regions 205SD of the fin structure 205 not covered by the dummy gate stack 210 and the gate spacers 216a can be anisotropically etched by dry etching or a suitable etching process to form source / drain openings 218. Exemplary dry etching processes can employ oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasmas and / or combinations thereof. In Figures 3A to 3B the embodiment shown, the source / drain openings 218 extend through the vertical stack of the channel layer 208 and the sacrificial layer 206 and into the semiconductor layer 204 of the substrate 201. The lower portion of the source / drain openings 218 extending into the substrate 201 spans a width W1. In an embodiment, the width W1 ranges between about 8 nm and about 40 nm. In some embodiments, the etching process implemented to etch back the gate spacer layer 216 and / or form the source / drain openings 218 may slightly etch the isolation component 207. For example, as Figure 3A shown, the portion of the isolation component 207 not covered by the fin sidewall spacers 216b is slightly recessed. As Figures 3A to 3B shown, the sidewalls of the channel layer 208 and the sacrificial layer 206 are exposed in the source / drain openings 218.

[0029] Referring to Figure 1 and Figures 4A to 4B , method 100 includes block 106, where an internal spacer component 220 is formed. After forming the source / drain openings 218, the sacrificial layer 206 exposed to the source / drain openings 218 is selectively and partially recessed to form an internal spacer groove (not shown), while the exposed channel layer 208 is not significantly etched. In an embodiment where the channel layer 208 consists mainly of silicon (Si) and the sacrificial layer 206 consists mainly of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 can include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. After forming the internal spacer groove, an internal spacer material layer is deposited over the semiconductor structure 200 (including in the internal spacer groove). The internal spacer material layer can include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbonitride oxide, metal carbonitride, metal nitride, or a suitable dielectric material. Then, the deposited internal spacer material layer is etched back to remove the excess internal spacer material layer above the sidewalls of the channel layer 208, thereby forming the internal spacer component 220 as Figures 4A to 4B shown.

[0030] Reference Figure 1 and Figures 5A to 5B ,Method 100 includes block 108, in which a semiconductor component 228 is formed in the source / drain opening 218. The semiconductor component 228 can be selectively formed in the lower portion of the source / drain opening 218 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes. The composition of the semiconductor component 228 is different from that of the semiconductor layer 204, such that the semiconductor layer 204 can be selectively removed in a subsequent process. For example, when the semiconductor layer 204 is formed of silicon, the semiconductor component 228 can include SiGe, boron-doped SiGe (SiGe:B), or other suitable materials, such that the semiconductor layer 204 can be selectively removed with substantially no etching of the semiconductor component 228. In an embodiment, the semiconductor layer 204 is formed of silicon, and the semiconductor component 228 is formed of SiGe. The germanium concentration of the SiGe-based semiconductor component 228 can be in the range between about 10% and about 50%. If the germanium concentration is less than about 10%, the etching selectivity between the semiconductor component 228 and the semiconductor layer 204 may not be sufficient to provide satisfactory etching results; if the germanium concentration is greater than about 50%, the duration for removing the SiGe-based semiconductor component 228 may be extended, and it may also be difficult to epitaxially grow the source / drain component thereon.

[0031] The semiconductor component 228 has a height H1 along the Z direction. In some embodiments, the ratio of the height H1 of the semiconductor component 228 to the width (i.e., W1) of the semiconductor component 228 can be in the range between about 0.3 and about 3. If the ratio is greater than about 3, as described above, the size of the multi-gate device is reduced and the gate pitch is also reduced, and it will be challenging to form deep source / drain openings for devices with a reduced pitch; if the ratio is less than about 0.3, the portion of the backside via to be formed (e.g., Figure 17BThe portion 274a) shown in [reference] will be too close to the functional gate structure, undesirably resulting in an increase in parasitic capacitance. In an embodiment, the height H1 is in the range between about 2 nm and 30 nm. If the height H1 is greater than about 30 nm, as described above, the size of the multi-gate device is reduced and the gate pitch is also reduced, and it will be challenging to form deep source / drain openings. If the height H1 is less than about 2 nm, the portion of the backside vias to be formed will be too close to the functional gate structure, undesirably resulting in an increase in parasitic capacitance and an increase in the risk of electrical short circuits. In an embodiment, the top surface of the semiconductor component 228 has a recessed profile that has a concave shape and has a depth at its deepest part. In some embodiments, the depth is from about 1 nm to about 5 nm. Since one or more semiconductor components 228 can be removed during subsequent processes, the semiconductor component 228 can also be referred to as a sacrificial component 228 or a sacrificial semiconductor component 228.

[0032] Reference Figure 1 and Figures 6A to 6B, Method 100 includes block 110, where an isolation layer 230 is formed on semiconductor component 228 and in source / drain opening 218. The isolation layer 230 can be formed of any suitable dielectric material as long as its composition is different from that of channel layer 208, sacrificial layer 206, gate top hard mask layer 215, gate spacer 216a, and internal spacer component 220 to allow selective removal through an etching process. In some embodiments, the isolation layer 230 can include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide, hafnium oxide, or other suitable materials. In an embodiment, the isolation layer 230 is oxygen-free and includes silicon nitride. In some other embodiments, layer 230 can be a semiconductor layer, such as a silicon layer or a boron-doped silicon layer (Si:B). Although not shown, in some embodiments, the isolation layer 230 can also be formed on the top surface of the horizontal portion (along the Y direction) of the recessed isolation component 207. In the illustrated embodiment, the topmost surface of the isolation layer 230 is lower than the bottom surface of the bottommost channel layer 208 in the channel layer 208 or coplanar with the bottom surface of the bottommost channel layer 208 in the channel layer 208. In an embodiment, the isolation layer 230 is in direct contact with the bottommost internal spacer component 220 of the internal spacer component 220. In some other alternative embodiments, the top surface of the isolation layer 230 is lower than the topmost surface of the substrate 201. The thickness of the isolation layer 230 can range between about 2 nm and about 5 nm. If the thickness is less than 2 nm, potential current leakage between the source / drain component 232 and the semiconductor layer 204 may not be reduced or eliminated; if the thickness is greater than 5 nm, it may be too thick to be effectively removed by the subsequent etching process 268. It should be noted that the isolation layer 230 is optional. The semiconductor structure 200 may not include this isolation layer 230.

[0033] Reference Figure 1 and Figures 7A to 7B, Method 100 includes block 112, where source / drain components 232 are formed in source / drain openings 218. Depending on the context, source / drain components 232 may refer to the source or drain individually or collectively. By using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes, source / drain components 232 can be epitaxially and selectively formed from the exposed sidewalls of channel layer 208. Depending on the type of transistor, source / drain components 232 may include N-type source / drain components and / or P-type source / drain components. Exemplary N-type source / drain components may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing an N-type dopant (such as phosphorus, arsenic, or antimony) during the epitaxial process, or ex-situ doped using a junction implantation process. Exemplary P-type source / drain components may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped by introducing a P-type dopant (such as boron or gallium) during the epitaxial process, or ex-situ doped using a junction implantation process. The dopant concentration of N-type source / drain components or P-type source / drain components may be in the range between about 5E19 / cm 3 and about 5E21 / cm 3 . In some embodiments, each source / drain component 232 may include multiple semiconductor layers with different doping concentrations. For example, each source / drain component 232 may include a lightly doped semiconductor layer and a heavily doped semiconductor layer disposed above the lightly doped semiconductor layer.

[0034] Reference Figure 1 and Figures 8A to 8B , Method 100 includes block 114, where the dummy gate stack 210 and the sacrificial layer 206 are replaced by a gate structure 240. In this embodiment, a contact etch stop layer (CESL) 234 and an interlayer dielectric (ILD) layer 236 are deposited over semiconductor structure 200. CESL 234 may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by ALD, plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. As Figures 8A to 8BAs shown, the CESL 234 can be deposited on the top surface of the source / drain component 232 and the sidewalls of the gate spacer 216a. After depositing the CESL 234, an ILD layer 236 is deposited over the semiconductor structure 200 by a PECVD process or other suitable deposition technique. The ILD layer 236 can include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the ILD layer 236, the semiconductor structure 200 can be annealed to improve the integrity of the ILD layer 236. A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed on the semiconductor structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer 212 in the dummy gate stack 210.

[0035] With the exposure of the dummy gate electrode layer 212, the block 114 continues to remove the dummy gate stack 210. Removing the dummy gate stack 210 can include one or more etching processes that are selective to the materials in the dummy gate stack 210. For example, selective wet etching, selective dry etching, or a combination thereof can be used to perform the removal of the dummy gate stack 210. After removing the dummy gate stack 210, the sacrificial layer 206 is selectively removed to release the channel layer 208 as the channel member 208 in the channel region 205C. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., ammonium hydroxide - hydrogen peroxide - water mixture).

[0036] Then, a gate structure 240 is formed to wrap over the channel member 208. Each gate structure 240 includes a gate dielectric layer 242 and a gate electrode layer 244 located above the gate dielectric layer 242. In some embodiments, the gate dielectric layer 242 includes an interface layer disposed on the channel member 208 and a high-k dielectric layer located above the interface layer. Here, the high-k dielectric layer refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide (about 3.9). The low-k dielectric layer refers to a dielectric material having a dielectric constant not greater than the dielectric constant of silicon dioxide. In some embodiments, the interface layer includes silicon oxide. Then, the high-k dielectric layer is deposited above the interface layer using ALD, CVD, and / or other suitable methods. The high-k dielectric layer may include hafnium oxide. Optionally, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)TiO3 (BST), silicon nitride, silicon oxynitride, their combinations, or other suitable materials.

[0037] Then, the gate electrode layer 244 is deposited above the gate dielectric layer 242 using ALD, PVD, CVD, electron beam evaporation, or other suitable methods. The gate electrode layer 244 may include a single layer or an optional multi-layer structure, such as various combinations of metal layers (work function metal layers) having a selected work function to enhance device performance, buffer layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the gate electrode layer 244 may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, or other suitable metal materials, or their combinations. Additionally, in the case where the semiconductor structure 200 includes n-type transistors and p-type transistors, different gate electrode layers may be formed for the n-type transistors and the p-type transistors respectively, which may include different work function metal layers (e.g., for providing different n-type and p-type work function metal layers).

[0038] Reference Figure 1 and Figures 9A to 9B, method 100 includes block 116, where a first interconnect structure 252 is formed over the semiconductor structure 200. In an embodiment, after the gate structure 240 is formed, a dielectric structure 246 is formed over the ILD layer 236 and the gate structure 240. The dielectric structure 246 may include an etch stop layer and a dielectric layer deposited over the etch stop layer. The etch stop layer may be similar to the CESL 234, and the dielectric layer may be similar to the ILD layer 236 in terms of composition and formation process. The etch stop layer in the dielectric structure 246 may refer to an etch stop point for forming a gate via opening over the gate structure 240. After the dielectric structure 246 is formed, a silicide layer (not shown) and source / drain contacts 248 are formed over the source / drain components 232. The source / drain contacts 248 may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). Then, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove an excess portion of the deposited conductive layer used to form the source / drain contacts 248. In some embodiments, a dielectric barrier layer 250 may be formed to provide enhanced isolation between the gate structure 240 and its adjacent source / drain contacts 248. The gate via may be formed to extend through the dielectric structure 246 to couple to the gate structure 240.

[0039] After the gate via and the source / drain contacts 248 are formed, a first interconnect structure 252 is formed over the structure. The first interconnect structure 252 may include multiple inter-metal dielectric (IMD) layers and multiple metal lines or contact vias located in each IMD layer. In some cases, the IMD layers and the ILD layer 236 may share similar compositions. The metal lines and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layers and prevent electromigration. Since the first interconnect structure 252 is formed over the front side of the semiconductor structure 200, the first interconnect structure 252 may also be referred to as the front-side interconnect structure 252.

[0040] Reference Figure 1 and Figures 10A to 10B, Method 100 includes block 118, where the semiconductor structure 200 is flipped and flattened. After forming the first interconnect structure 252, a carrier substrate (not shown) is then bonded to the first interconnect structure 252 by fusion bonding, using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may include a semiconductor material (such as silicon), sapphire, glass, polymer material, or other suitable materials. In an embodiment using fusion bonding, the carrier substrate includes a bottom oxide layer, and the first interconnect structure 252 includes a top oxide layer. After processing the bottom oxide layer and the top oxide layer, they are placed in plush contact with each other for direct bonding at room temperature or an elevated temperature. Once the carrier substrate is bonded to the first interconnect structure 252, the semiconductor structure 200 is flipped. Then, the back side of the semiconductor structure 200 is flattened (e.g., by a flattening process such as a chemical mechanical polishing CMP process) to reduce the thickness of the substrate 201 from the back side. In an embodiment, as Figures 10A to 10B shown, the flattening process may stop until the bottom surface of the STI component 207 is exposed. In this embodiment, the carrier layer 202 and the insulator layer 203 of the substrate 201 are removed during the flattening process. It should be noted that the flattening process does not expose the semiconductor component 228. In some embodiments, the flattening process may also remove a portion of the STI component 207. For ease of description, as shown in the figure, the positional relationship will be described below based on the flipped structure 200.

[0041] Reference Figure 1 , Figures 11A to 11B and Figures 12A to 12B , Method 100 includes block 120, where the semiconductor layer 204 of the substrate 201 is replaced by a dielectric layer 258. Referring to Figures 11A to 11B , the semiconductor layer 204 is selectively and completely removed with respect to the semiconductor component 228, the STI component 207, and the gate structure 240. The removal of the semiconductor layer 204 forms an opening 254. The etching process for selectively removing the semiconductor layer 204 may be a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process may employ CF4, NF3, Cl2, HBr, other suitable gases, and / or plasmas, and / or a combination thereof.

[0042] Reference Figures 12A to 12B, and then a dielectric layer 258 is formed in the opening 254 and above the semiconductor structure 200. The dielectric layer 258 can be deposited above the back side of the semiconductor structure 200 by FCVD, CVD, PECVD, spin coating, or a suitable process. The dielectric layer 258 can include oxides, nitrides, or other suitable materials. For example, the dielectric layer 258 can include silicon oxide, silicon carbon oxide, silicon carbonitride oxide, silicon nitride, silicon carbonitride, zirconium nitride, tantalum carbonitride, aluminum oxynitride, hafnium oxide, zirconium oxide, zirconium aluminum oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, hafnium tantalum oxide, or hafnium titanium oxide. In some embodiments, the dielectric layer 258 can include silicon oxide or have a composition similar to that of the ILD layer 236. A planarization process can be performed to planarize the back side of the semiconductor structure 200 by removing an excess portion of the deposited dielectric layer 258 outside the opening 254.

[0043] Reference Figure 1 and Figures 13A to 13B , method 100 includes block 122, wherein a first etch process 262 is performed to form a trench 264 in the dielectric layer 258 to expose the semiconductor component 228. In an exemplary process, a dielectric structure 260 is formed above the back side of the semiconductor structure 200. To provide an end point for a subsequent planarization process, the dielectric structure 260 includes a first layer 260a and a second layer 260b having a different material composition from the first layer 260b. In an embodiment, the first layer 260a includes an oxide layer (e.g., silicon oxide), and the second layer 260b includes a nitride layer (e.g., silicon nitride). The thickness T1 of the patterned dielectric structure 260 can be in the range between about 5 nm and about 70 nm. If the thickness T1 is less than 5 nm, the dielectric structure 260 may be too thin to indicate the end point of a subsequent planarization process for forming a backside via; if the thickness T1 is greater than 70 nm, it will increase the manufacturing difficulty of forming a satisfactory backside via. For example, a thick dielectric structure may result in a longer etch duration for forming the trench 264, a deeper backside via opening, and thus increase the deposition difficulty of forming a layer in the deeper backside via opening. Reference Figures 13A to 13B , the dielectric structure 260 is patterned to form an opening 261. The opening 261 exposes a portion of the dielectric layer 258 directly above the semiconductor component 228. Although Figures 13A to 13B only one opening 261 is shown, the dielectric structure 260 can be patterned to form more openings 261.

[0044] After forming the patterned dielectric structure 260, while using the patterned dielectric structure 260 as an etch mask, a first etch process 262 is performed to form trenches 264 extending into the dielectric layer 258. In the illustrated embodiment, the width W2 of the trenches 264 is greater than the width W1 of the semiconductor component 228. That is, the trenches 264 expose not only the bottom surface of the semiconductor component 228 but also a portion of the dielectric layer 258 extending over the inner spacer component 220. In an embodiment, the width W2 can be in the range between about 10 nm and about 50 nm. In the illustrated embodiment, as Figure 13A shown, when viewed from the top, the trenches 264 further expose a portion of the STI component 207. Similarly, although Figures 13A to 13B only one trench 264 is shown, the dielectric layer 258 can be etched to form more trenches 264 to expose more semiconductor components 228. The first etch process 262 can be a dry etch process, and the dry etch process includes using argon (Ar), fluorine-containing etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8, and / or C2F6), oxygen-containing etchants, chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBr3), iodine-containing etchants, or a combination thereof. In some embodiments, the first etch process 262 can be an anisotropic etch.

[0045] Referring to Figure 1 and Figures 14A to 14B , method 100 includes block 124, where a second etch process 266 is performed to selectively remove the semiconductor component 228. After forming the trenches 264 to expose the semiconductor component 228, the second etch process 266 is performed to selectively remove the semiconductor component 228 exposed by the trenches 264 to vertically extend the trenches 264. The extended trenches 264 can be referred to as trenches 264'. The second etch process 266 is performed to selectively remove the semiconductor component 228 while substantially not etching the dielectric layer 258, the STI component 207, and the optional isolation layer 230. That is, the selective removal of the semiconductor component 228 is self-aligned, and the width of the extended portion of the trenches 264' is substantially equal to the width W1 of the semiconductor component 228. Even if there is alignment coverage during the formation of the trenches 264 (as Figure 13B shown), the self-aligned extended portion of the trenches 264' will not expose the gate structure 240. Therefore, the alignment requirements for forming the trenches 264 (as Figure 13BThe overlay window of the lithography process as shown). The second etching process 266 can be a selective wet etching process or a selective dry etching process. In some embodiments, the second etching process 266 is an isotropic etching process. In some other embodiments, the second etching process 266 is an anisotropic etching process. The second etching process 266 can employ an etchant solution to selectively remove the semiconductor component 228. The etchant solution includes a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O).

[0046] Referring Figure 1 and Figures 15A to 15B , method 100 includes block 126, where a third etching process 268 is performed to selectively remove the isolation layer 230. In embodiments where the semiconductor structure 200 includes the isolation layer 230, the third etching process 268 is performed to selectively remove the isolation layer 230 to expose the bottom surface of the source / drain component 232. In some embodiments, the etchant of the third etching process 268 can slightly etch the source / drain component 232 below the isolation layer 230. For example, after performing the third etching process 268, the source / drain component 232 can have an inwardly curved bottom surface. After removing the isolation layer 230, the trench 264’ can be referred to as the trench 264”. For embodiments where the semiconductor structure 200 does not include the isolation layer 230, the third etching process 268 will be omitted.

[0047] Referring Figure 1 , Figures 16A to 16B and Figures 17A to 17B , method 100 includes block 128, where a silicide layer 270 and a backside via 274 are formed in the trench 264”. After exposing the source / drain component 232, a silicide layer 270 is formed on the exposed surface of the source / drain component 232. To form the silicide layer 270, a metal layer (not explicitly shown) is deposited above the exposed surface of the source / drain component 232, and an annealing process is performed to produce a silicidation reaction between the metal layer and the source / drain component 232. Suitable metal layers can include titanium, tantalum, nickel, cobalt, or tungsten. In embodiments where the metal layer includes nickel and the source / drain component 232 includes silicon germanium, the silicide layer 270 includes nickel silicide, nickel germanide, and nickel silicogermanide. The silicide layer 270 generally follows the shape of the exposed source / drain component 232. In some embodiments, the silicide layer 270 can include TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, and / or YbSi. The excess portion of the metal layer that does not form the silicide layer 27 can be removed. In embodiments, the thickness of the silicide layer 270 can be in the range of about 1 nm to about 10 nm to effectively reduce the contact resistance without causing an electrical short circuit. As Figures 16A to 16BAs shown, a conductive layer 272 is then deposited over the back side of the semiconductor structure 200 (including in the trench 264” and on the silicide layer 270). The conductive layer 272 may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). In some embodiments, a barrier layer may be formed before depositing the conductive layer 272. The barrier layer may include titanium, tantalum, TiN, TaN, or other suitable materials. Refer to Figures 17A to 17B , and then a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove the excess material above the dielectric layer 258 to define the final structure of the backside via 274.

[0048] The backside via 274 has a flat bottom surface coplanar with the bottom surface of the dielectric layer 258 and a top surface in direct contact with the underlying silicide layer 270. In Figure 17B this illustrated embodiment, the backside via 274 has a first portion 274a spanning a width W2 and a second portion 274b spanning a width W1 that is less than W2. The width W2 may be in the range between about 10 nm and about 50 nm. If the width W2 is greater than 50 nm, the risk of electrical short circuit between the backside via and its adjacent conductive components may increase, and the device area may increase. If the width W2 is less than 10 nm, the parasitic resistance associated with the backside via may be too high, adversely affecting device performance. The width W1 may be in the range between about 8 nm and about 40 nm. If the width W1 is greater than 40 nm, the risk of electrical short circuit between the backside via and its adjacent conductive components may increase, and the device area may increase. If the width W1 is less than 8 nm, the parasitic resistance associated with the backside via may be too high, adversely affecting device performance.

[0049] In an embodiment, the backside via 274 has an asymmetric profile. More specifically, in a cross-sectional view, a first portion 274a overhangs a second portion 274b on one side and is aligned with the second portion 274b on an opposite side. That is, one sidewall surface of the backside via 274 has a stepped profile. In this embodiment, the first portion 274a of the backside via 274 vertically overlaps with the internal spacer member 220. The height of the backside via 274 is in a range between about 5 nm and about 70 nm. If the height is less than 5 nm, the parasitic capacitance between the power line and the gate structure in the backside interconnect structure may be too large, which may adversely affect device performance and reliability; if the height is greater than 70 nm, it will be challenging to form the deep trench 264 and perform a deposition process to form a satisfactory layer in the deep backside via opening, and the resulting backside via may have a large parasitic resistance. In some other embodiments, the CMP process in block 128 removes the first layer 260a of the patterned dielectric structure 260 without removing the second layer 260b, and the resulting backside via 274 will have a flat top surface coplanar with the top surface of the second layer 260b. As a result, along the Y direction, the backside via 274 can extend over a portion of the STI component 207 exposed in the trench 264".

[0050] Reference Figure 1 , method 100 includes block 130, where a further process is performed. Such a further process may include forming a second interconnect structure (not shown) over the backside of the semiconductor structure 200. The second interconnect structure may have a structure similar to that of the first interconnect structure 252. For example, the second interconnect structure may include multiple inter-metal dielectric (IMD) layers and multiple metal lines or contact vias located in each IMD layer. In some cases, the IMD layers and the ILD layer 236 may share similar components. The metal lines and contact vias in each IMD layer may be formed of a metal such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layers and prevent electromigration. Since the second interconnect structure is formed over the backside of the semiconductor structure 200, the second interconnect structure may also be referred to as a backside interconnect structure.

[0051] In reference Figures 17A to 17B described in the above embodiments, the backside via 274 has an asymmetric profile, and the first portion 274a of the backside via 274 overhangs the second portion 274b of the backside via 274 on one side and is aligned with the second portion 274b of the backside via 274 on the other side. In Figure 18In the alternative embodiment shown, the dorsal via 274 may have a symmetric profile. For example, a first portion 274a of the dorsal via 274 overhangs a second portion 274b of the dorsal via 274 on both sides. More specifically, in this alternative embodiment, the first portion 274a includes sidewalls 274S1 and a sidewall 274S2 opposite to the sidewall 274S1, and the second portion 274b includes sidewalls 274S3 and a sidewall 274S4 opposite to the sidewall 274S3. The sidewall 274S1 is offset from the sidewall 274S3, and the sidewall 274S2 is offset from the sidewall 274S4. In other words, each sidewall of the dorsal via 274 has a stepped profile. The first portion 274a may vertically overlap two internal spacer members 220 formed on opposite sides of the silicide layer 270. The distance between the sidewall 274S3 and the sidewall 274S1 is substantially equal to the distance between the sidewall 274S4 and the sidewall 274S2. In another alternative embodiment, the dorsal via 274 has an asymmetric profile, and the distance between the sidewall 274S3 and the sidewall 274S1 is different from the distance between the sidewall 274S4 and the sidewall 274S2.

[0052] In the above-described embodiments with reference Figures 1 to 18 During the manufacturing process in method 100, the semiconductor layer 204 is substantially completely removed. In some alternative embodiments, the semiconductor layer 204 may be partially removed so that the gate structure 240 is not damaged by the etchant of the etching process for etching the semiconductor layer 204. Figure 19 A flowchart of an alternative method 300 for forming a semiconductor structure 400 having a dorsal via in accordance with one or more aspects of the present disclosure is shown. The method 300 will be described below in conjunction with Figures 20 to 26B Describe method 300, Figures 20 to 26B is a partial cross-sectional view of the semiconductor structure 400 at different manufacturing stages in accordance with an embodiment of method 300.

[0053] With reference Figure 19 、 Figure 1 and Figures 2A to 10B Method 300 includes blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118 of method 100. For simplicity, repeated descriptions of the operations in blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118 are omitted. For ease of description, in this alternative embodiment, the semiconductor structure 200 represented by Figures 10A to 10B will be referred to as the semiconductor structure 400.

[0054] With reference Figure 19 and Figure 20, Method 300 includes block 302, in which the semiconductor layer 204 of the substrate 201 is selectively recessed. After flipping and planarizing the semiconductor structure 400 (as Figures 10A to 10B shown), refer to Figure 20 , an etching process is performed to selectively etch the semiconductor layer 204 relative to the semiconductor component 228, the STI component 207, and the gate structure 240. The etching process for selectively etching the semiconductor layer 204 can be a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process can employ CF4, NF3, Cl2, HBr, other suitable gases, and / or plasmas and / or combinations thereof. In this embodiment, the semiconductor layer 204 is partially removed to form an opening 254'. As Figure 20 shown, the opening 254' exposes the semiconductor component 228 and the semiconductor layer 204. In other words, a portion of the sidewall surface of the semiconductor component 228 is covered by the recessed semiconductor layer 204, and the opening 254' exposes another portion of the sidewall surface of the semiconductor component 228 that is not covered by the recessed semiconductor layer 204. The height of the semiconductor layer 204 can be adjusted by controlling the duration of the etching process performed in block 302. In the illustrated embodiment, after the etching process is performed in block 302, the height of the semiconductor layer 204 is less than the height of the semiconductor component 228.

[0055] Refer to Figure 19 and Figure 21 , Method 300 includes block 304, in which a dielectric layer 258 is formed over the recessed substrate (i.e., the recessed semiconductor layer 204). The formation and composition of the dielectric layer 258 have been described above with reference to Figures 12A to 12B , and for simplicity, the repeated description is omitted. The dielectric layer 258 is spaced apart from the gate structure 240 by the semiconductor layer 204.

[0056] Refer to Figure 19 and Figure 22 , Method 300 includes block 306, in which a first etching process 262 is performed to form a trench 264 in the dielectric layer 258 to expose the semiconductor component 228. The operation in block 306 is similar to the operation in block 122 described above with reference to Figure 1 and Figures 13A to 13B , and thus the repeated description is omitted for simplicity.

[0057] Refer to Figure 19 and Figure 23 , Method 300 includes block 308, in which a second etching process 266 is performed to selectively remove the semiconductor component 228. The operation in block 308 is similar to the operation in block 122 described above with reference to Figure 1 and Figures 14A to 14BThe operations in block 124 described above are thus omitted for simplicity of repetition. For embodiments in which the semiconductor structure 400 includes the optional isolation layer 230, a third etch process 268 is performed to selectively remove the isolation layer 230. Reference has been made to Figure 1 and Figures 15A to 15B for the description of the third etch process 268, and thus the repeated description is omitted for simplicity of repetition.

[0058] Reference Figure 19 and Figure 24 , the method 300 includes block 310, in which a dielectric barrier layer 402 is formed in the trench 264”. In an exemplary process, to form the dielectric barrier layer 402, a dielectric material layer is deposited over the back side of the semiconductor structure 400 (including in the trench 264’), and then a back-etch is performed to cover only the sidewalls of the trench 264” and expose the source / drain components 232. The dielectric barrier layer 402 may include silicon nitride or other suitable materials. The dielectric barrier layer 402 provides isolation between the recessed semiconductor layer 204 and the conductive components (e.g., the back-side vias 274 and the silicide layer 270) formed in the trench 264”.

[0059] Reference Figure 19 and Figure 25 , the method 300 includes block 312, in which a silicide layer 270 and back-side vias 274 are formed in the trench 264”. After forming the dielectric barrier layer 402, a silicide layer 270 and back-side vias 274 are formed in the trench 264”. The operations in block 312 are similar to the operations in block 128 described above with reference to Figure 1 , Figures 16A to 16B and Figures 17A to 17B , and thus the repeated description is omitted for simplicity of repetition. Figure 25 The semiconductor structure 400 shown is substantially similar to the conductor structure 200 shown in Figure 18 , and the main differences between the semiconductor structure 400 and the semiconductor structure 200 include that the semiconductor structure 200 includes a semiconductor layer 204 disposed between the dielectric layer 258 and the gate structure 240, and a dielectric barrier layer 402 disposed between the back-side vias 274 and the dielectric layer 258.

[0060] Figure 25 The back-side vias 274 shown have a symmetric profile similar to that described with reference to Figure 18 . In some alternative embodiments shown in Figure 26A and Figure 26B , the back-side vias 274 have an asymmetric profile. Reference Figure 26A , the back-side vias 274 have an asymmetric profile similar to that described with reference to Figure 17B . Reference Figure 26B, the backside through hole 274 has an asymmetric profile. For example, the portion of the backside through hole 274 closer to the silicide layer 270 is offset from the portion of the backside through hole 274 farther from the silicide layer 270. In the illustrated embodiment, the backside through hole 274 may have a uniform width or a non-uniform width from bottom to top. The dielectric barrier layer 402 extends along a vertical portion of the sidewall surface of the backside through hole 274. The dielectric barrier layer 402 provides isolation between the backside through hole 274 and the recessed semiconductor layer 204.

[0061] After forming the backside through hole 274, referring to Figure 19 , method 300 includes block 314, where further processes are performed. The operations in block 314 are similar to the operations in block 130 described above with reference to Figure 1 , and thus the repeated description is omitted for simplicity.

[0062] In the embodiment described above with reference to Figures 1 to 26B , the semiconductor layer 204 of the substrate 201 is completely or partially replaced by the dielectric layer 258, and the backside through hole 274 extends through the dielectric layer 258. In another alternative embodiment, the backside through hole 614 extends through the semiconductor layer 204 of the substrate 201. Figure 27 FIG. shows a flow chart of an alternative method 500 for forming a semiconductor structure 600 according to one or more aspects of the present disclosure, the semiconductor structure 600 having a backside through hole 614 extending through the semiconductor layer 204. Method 500 is described below in conjunction with Figures 28A to 36 , Figures 28A to 36 is a partial cross-sectional view of the semiconductor structure 600 at different manufacturing stages according to an embodiment of method 500.

[0063] Referring to Figure 27 , Figure 1 and Figures 2A to 10B , method 300 includes blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118 of method 100. For ease of description, in this alternative embodiment, the semiconductor structure 200 represented by Figures 10A to 10B will be referred to as the semiconductor structure 600.

[0064] Referring to Figure 27 , Figures 28A to 28B and Figures 29A to 29B , method 500 includes block 502, where a first etching process 602 is performed to form a trench 604 in the substrate 201 to expose the semiconductor component 228. Referring to Figures 28A to 28B , after flipping and planarizing the semiconductor structure 600 to remove the carrier layer 202 and the insulator layer 203 of the substrate 201 to expose the semiconductor layer 204, a patterned dielectric structure 260 is formed over the backside of the semiconductor structure 600. As has been referred to aboveFigures 13A to 13B The formation and components of the patterned dielectric structure 260 are described, and for simplicity, repeated descriptions are omitted. In the illustrated embodiment, the patterned dielectric structure 260 includes an opening 601 that exposes portions of the semiconductor layer 204 and portions of the STI component 207 (as Figure 28A shown).

[0065] Referring Figures 29A to 29B , while using the patterned dielectric structure 260 as an etch mask, a first etch process 602 is performed on the semiconductor structure 600 to form a trench 604 that extends into the semiconductor layer 204. The trench 604 exposes the semiconductor component 228 and has a width W2 that is greater than the width W1 of the semiconductor component 228. In the illustrated embodiment, the trench 604 also exposes a portion of the semiconductor layer 204 surrounding the semiconductor component 228. The first etch process 602 can be an anisotropic dry etch. In an embodiment, the first etch process 602 can employ an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasmas and / or combinations thereof.

[0066] Referring Figure 27 and Figures 30A to 30B , method 500 includes block 504 where a second etch process 606 is performed to selectively remove the semiconductor component 228 to vertically extend the trench 604. The extended trench 604 can be referred to as trench 604'. The second etch process 606 is performed to selectively remove the semiconductor component 228 while substantially not etching the semiconductor layer 204, the STI component 207, and the optional isolation layer 230. That is, the selective removal of the semiconductor component 228 is self-aligned, and the width of the extended portion of the trench 604' is substantially equal to the width W1 of the semiconductor component 228. In these embodiments, the second etch process 606 can be a selective wet etch process or a selective dry etch process. In an embodiment, the second etch process 606 can employ an etchant solution to selectively remove the semiconductor component 228, the etchant solution including a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O).

[0067] In embodiments where the semiconductor structure 600 includes an isolation layer 230 exposed by the trench 604', as Figures 31A to 31BAs shown, an additional etching process is performed to selectively remove the isolation layer 230 to expose the bottom surface of the source / drain component 232. In some embodiments, the etchant of the additional etching process may slightly etch the source / drain component 232 below the isolation layer 230. For example, after performing the additional etching process, the source / drain component 232 may have an inwardly curved bottom surface. After removing the isolation layer 230, the trench 604' may be referred to as trench 604". For embodiments in which the semiconductor structure 600 does not include the isolation layer 230, the additional etching process will be omitted.

[0068] Referring Figure 27 to Figures 32A to 32B and Figure 24 , method 500 includes block 506, in which a dielectric barrier layer 608 is formed in the trench 604". The formation and composition of the dielectric barrier layer 608 may be similar to those of the dielectric barrier layer 402 described in reference

[0069] Referring Figure 27 to Figures 33A to 33B and Figures 34A to 34B , method 500 includes block 508, in which a silicide layer 610 and a backside via 614 are formed in the trench 604". After the source / drain component 232 is exposed, the silicide layer 610 is formed on the exposed surface of the source / drain component 232. The formation and composition of the silicide layer 610 may be similar to the formation and composition of the silicide layer 270 described in reference Figures 16A to 16B , and thus the repeated description is omitted for simplicity. As Figures 33A to 33B shown, a conductive layer 612 is then deposited over the backside of the semiconductor structure 600 (including in the trench 604" and on the silicide layer 610). The formation and composition of the conductive layer 612 may be similar to the formation and composition of the conductive layer 272 described in reference Figures 16A to 16B , and thus the repeated description is omitted for simplicity. Similarly, in some embodiments, a barrier layer may be formed before depositing the conductive layer 612. The barrier layer may include titanium, tantalum, TiN, TaN, or other suitable materials. Along the Y direction, the conductive layer 612 extends over the portion of the STI component 207 exposed in the trench 604".

[0070] Referring Figures 34A to 34B to Figures 34A to 34BIn the illustrated embodiment, the backside via 614 has a first portion spanning a width W2 and a second portion spanning a width W1 that is less than W2. In an embodiment, the backside via 614 has a symmetric profile. More specifically, the first portion of the backside via 614 overhangs the second portion of the backside via 612 on both sides. That is, each of the two sidewall surfaces of the backside via 274 has a stepped profile. In another embodiment, the backside via 614 has an asymmetric profile, where the first portion of the backside via 614 overhangs the second portion of the backside via 614 by different amounts on both sides.

[0071] Reference Figure 27 , method 500 includes block 510, where a further process is performed. The operations in block 510 are similar to the operations in block 130 described above with reference to Figure 1 and thus the repeated description is omitted for simplicity.

[0072] In the above-described embodiment with reference to Figure 35B the backside via 614 has a first portion and a second portion with different widths. In Figures 35A to 35B another alternative embodiment shown, the backside via 614 may have a substantially uniform width (e.g., W1) from bottom to top and substantially vertical sidewalls. In Figure 36 another alternative embodiment shown, the backside via 614 may have an asymmetric profile. For example, the portion of the backside via 614 closer to the silicide layer 610 is offset from the portion of the backside via 614 farther from the silicide layer 610. In the illustrated embodiment, the backside via 614 may have a uniform width or a non-uniform width from bottom to top.

[0073] Embodiments of the present disclosure provide advantages. The method of the present disclosure forms self-aligned backside vias without forming deep trenches in the source / drain regions. Thus, the overlay window for the lithography process used to form the trenches can be relaxed to facilitate the scaling of the gate-to-gate pitch.

[0074] The present disclosure provides many different embodiments. A semiconductor structure and a method of manufacturing the same are disclosed herein. In one exemplary aspect, the present disclosure relates to a method. The method includes receiving a structure that includes a plurality of channel members disposed above a substrate, a gate structure wrapping each of the plurality of channel members, and source / drain components adjacent to the plurality of channel members, where the source / drain components are disposed above semiconductor components extending into the substrate. The method further includes disposing source / drain components above the semiconductor components extending into the substrate, replacing the substrate with a dielectric layer, forming a mask having an opening that exposes a portion of the dielectric layer, removing a portion of the dielectric layer to form a trench that exposes the semiconductor components, selectively removing the semiconductor components to vertically extend the trench, and forming a via in the extended trench.

[0075] In some embodiments, the via has a first portion spanning a first width and a second portion spanning a second width that is greater than the first width. In some embodiments, one sidewall surface of the first portion of the via is offset from one sidewall surface of the second portion of the via. In some embodiments, the structure may further include an isolation layer disposed between the source / drain component and the semiconductor component, and the method may further include selectively removing the isolation layer after selectively removing the semiconductor component. In some embodiments, the width spanned by the trench is greater than the width of the semiconductor component. In some embodiments, the structure may further include an isolation component disposed between a plurality of channel members and another plurality of channel members, and the method may further include reducing the thickness of the substrate from the back side of the substrate to expose the isolation component before replacing the substrate with a dielectric layer. In some embodiments, the trench may further expose a portion of the isolation component, and the via may vertically overlap the isolation component. In some embodiments, the source / drain component is a first source / drain component and the semiconductor component is a first semiconductor component, the structure may further include a second source / drain component located above the second semiconductor component, and the height of the via is greater than the height of the second semiconductor component. In some embodiments, the composition of the semiconductor component may be different from the composition of the substrate.

[0076] In another exemplary aspect, the present disclosure relates to a method. The method includes forming a sacrificial component in a substrate, forming a source / drain component above the sacrificial component, the source / drain component protruding from the substrate, planarizing the substrate from the back side of the substrate to reduce the thickness of the substrate, performing a first etching process to selectively remove the substrate with substantially no etching of the sacrificial component, forming a dielectric layer adjacent to and below the sacrificial component, performing a second etching process to form a trench in the dielectric layer to expose the sacrificial component, performing a third etching process to selectively remove the sacrificial component, and forming a conductive component in the trench.

[0077] In some embodiments, the width spanned by the trench is greater than the width of the sacrificial component. In some embodiments, the sacrificial component is a semiconductor layer having a composition different from that of the substrate. In some embodiments, the method may further include forming an isolation layer on the sacrificial component before forming the source / drain component, and performing a fourth etching process to selectively remove the sacrificial component after performing the third etching process. In some embodiments, forming the conductive component in the trench may include forming a silicide layer that is located below the source / drain component and coupled to the source / drain component, depositing a conductive layer to fill the trench, and planarizing the conductive layer to expose the dielectric layer. In some embodiments, in a cross-sectional view, the conductive component may have an asymmetric profile. In some embodiments, the method may further include forming a source / source contact above the source / drain component.

[0078] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a plurality of nanostructures located above a dielectric layer, a gate structure that wraps each of the plurality of nanostructures and is located above the dielectric layer, a source / drain component coupled to at least one of the plurality of nanostructures, and a via that extends through the dielectric layer to couple to the source / drain component, wherein, in a cross-sectional view, the via has an asymmetric profile.

[0079] In some embodiments, the semiconductor structure may further include another source / drain component coupled to at least one of the plurality of nanostructures, and a semiconductor component located below the source / drain component and embedded in the dielectric layer, wherein the height of the via is greater than the height of the semiconductor component. In some embodiments, the via has a first portion and a second portion located below the first portion, and the width of the first portion is substantially equal to the width of the semiconductor component and less than the width of the second portion. In some embodiments, the semiconductor structure may further include an isolation layer disposed between the semiconductor component and the another source / drain component.

[0080] Some embodiments of the present application provide a method, including: receiving a structure, the structure including: a plurality of channel members disposed above a substrate; a gate structure that wraps each of the plurality of channel members; and a source / drain component adjacent to the plurality of channel members, wherein the source / drain component is disposed above a semiconductor component extending into the substrate; replacing the substrate with a dielectric layer; forming a mask having an opening that exposes a portion of the dielectric layer; removing the portion of the dielectric layer to form a trench that exposes the semiconductor component; selectively removing the semiconductor component to vertically extend the trench; and forming a via in the extended trench.

[0081] In some embodiments, the through hole has a first portion spanning a first width and a second portion spanning a second width, and the second width is greater than the first width. In some embodiments, one sidewall surface of the first portion of the through hole is offset from one sidewall surface of the second portion of the through hole. In some embodiments, the structure further includes an isolation layer disposed between the source / drain component and the semiconductor component, and the method further includes: selectively removing the isolation layer after selectively removing the semiconductor component. In some embodiments, the width spanned by the trench is greater than the width of the semiconductor component. In some embodiments, the structure further includes an isolation component disposed between the plurality of channel members and another plurality of channel members, and the method further includes: reducing the thickness of the substrate from the back side of the substrate to expose the isolation component before replacing the substrate with the dielectric layer. In some embodiments, the trench also exposes a portion of the isolation component, and the through hole vertically overlaps with the isolation component. In some embodiments, the source / drain component is a first source / drain component, and the semiconductor component is a first semiconductor component, the structure further includes a second source / drain component located above a second semiconductor component, and wherein the height of the through hole is greater than the height of the second semiconductor component. In some embodiments, the composition of the semiconductor component is different from the composition of the substrate.

[0082] Some other embodiments of the present application provide a method, including: forming a sacrificial component in a substrate; forming a source / drain component above the sacrificial component, and the source / drain component protrudes from the substrate; planarizing the substrate from the back side of the substrate to reduce the thickness of the substrate; performing a first etching process to selectively remove the substrate with substantially no etching of the sacrificial component; forming a dielectric layer adjacent to and below the sacrificial component; performing a second etching process to form a trench in the dielectric layer to expose the sacrificial component; performing a third etching process to selectively remove the sacrificial component; and forming a conductive component in the trench.

[0083] In some embodiments, the width spanned by the trench is greater than the width of the sacrificial component. In some embodiments, the sacrificial component is a semiconductor layer having a composition different from that of the substrate. In some embodiments, the method further includes: forming an isolation layer on the sacrificial component before forming the source / drain component; and after performing the third etching process, performing a fourth etching process to selectively remove the sacrificial component. In some embodiments, forming the conductive component in the trench includes: forming a silicide layer that is located under the source / drain component and coupled to the source / drain component; depositing a conductive layer to fill the trench; and planarizing the conductive layer to expose the dielectric layer. In some embodiments, in a cross-sectional view, the conductive component has an asymmetric profile. In some embodiments, the method further includes: forming a source / source contact above the source / drain component.

[0084] Some other embodiments of the present application provide a semiconductor structure, including: a plurality of nanostructures located above a dielectric layer; a gate structure that wraps each of the plurality of nanostructures and is located above the dielectric layer; a source / drain component coupled to at least one of the plurality of nanostructures; and a via hole that extends through the dielectric layer to be coupled to the source / drain component, wherein, in a cross-sectional view, the via hole has an asymmetric profile.

[0085] In some embodiments, the semiconductor structure further includes: another source / drain component coupled to at least one of the plurality of nanostructures; and a semiconductor component located under the source / drain component and embedded in the dielectric layer, wherein the height of the via hole is greater than the height of the semiconductor component. In some embodiments, the via hole has a first portion and a second portion located under the first portion, and the width of the first portion is substantially equal to the width of the semiconductor component and less than the width of the second portion. In some embodiments, the semiconductor structure further includes: an isolation layer disposed between the semiconductor component and the another source / drain component.

[0086] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Receiving a structure, the structure comprising: A plurality of channel members disposed above a substrate; A gate structure wrapping each of the plurality of channel members; and Source / drain components adjacent to the plurality of channel members, wherein the source / drain components are disposed above semiconductor components extending into the substrate; Replacing the substrate with a dielectric layer; Forming a mask having an opening exposing a portion of the dielectric layer; Removing the portion of the dielectric layer to form a trench exposing the semiconductor components; Selectively removing the semiconductor components to vertically extend the trench; and Forming a via in the extended trench.

2. The method according to claim 1, wherein The via has a first portion spanning a first width and a second portion spanning a second width, the second width being greater than the first width.

3. The method according to claim 2, wherein One sidewall surface of the first portion of the via is offset from one sidewall surface of the second portion of the via.

4. The method according to claim 1, wherein The structure further comprises an isolation layer disposed between the source / drain components and the semiconductor components, and the method further comprises: After selectively removing the semiconductor components, selectively removing the isolation layer.

5. The method according to claim 1, wherein The width spanned by the trench is greater than the width of the semiconductor components.

6. The method according to claim 1, wherein, The structure further comprises an isolation component disposed between the plurality of channel members and another plurality of channel members, and the method further comprises: Before replacing the substrate with the dielectric layer, reducing the thickness of the substrate from the backside of the substrate to expose the isolation component.

7. The method according to claim 6, wherein The trench also exposes a portion of the isolation component, and the via vertically overlaps with the isolation component.

8. The method according to claim 1, wherein The source / drain components are first source / drain components, and the semiconductor components are first semiconductor components. The structure further comprises second source / drain components located above second semiconductor components, and wherein the height of the via is greater than the height of the second semiconductor components.

9. A method of forming a semiconductor structure, comprising: Forming a sacrificial component in a substrate; Forming source / drain components above the sacrificial component, and the source / drain components protruding from the substrate; Planarizing the substrate from the backside of the substrate to reduce the thickness of the substrate; Performing a first etching process to selectively remove the substrate with substantially no etching of the sacrificial component; Forming a dielectric layer adjacent to and below the sacrificial component; Performing a second etching process to form a trench in the dielectric layer to expose the sacrificial component; Performing a third etching process to selectively remove the sacrificial component; And Forming a conductive component in the trench.

10. A semiconductor structure, comprising: A plurality of nanostructures located above a dielectric layer; A gate structure wrapping each of the plurality of nanostructures and located above the dielectric layer; Source / drain components coupled to at least one of the plurality of nanostructures; And A via extending through the dielectric layer to be coupled to the source / drain components, wherein in a cross-sectional view, the via has an asymmetric profile.

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