Preparation method of semiconductor device and semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the following steps: providing a substrate; sequentially forming a channel layer and a barrier layer on one side of the substrate; forming a first protection layer on one side, far away from the substrate, of the barrier layer; forming a second protection layer on one side, far away from the substrate, of the first protection layer; the thickness of the second protection layer is a first preset thickness; etching the first protection layer and the second protection layer to form a first ohmic contact hole and a second ohmic contact hole; metal layers are formed in the first ohmic contact hole, the second ohmic contact hole and the side, away from the substrate, of the second protection layer; forming a photoresist layer on one side, far away from the substrate, of the metal layer; removing the photoresist layer and the metal layer on one side, far away from the substrate, of the second protection layer; a source electrode is formed in the first ohmic contact hole, and a drain electrode is formed in the second ohmic contact hole. According to the invention, the preparation process flow of the GaN HEMT device is simplified.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] For existing gallium nitride (GaN) high electron mobility transistor (HEMT) devices, when fabricating ohmic contact electrodes, that is, when fabricating the source and drain electrodes, it is necessary to deposit a metal layer in the ohmic contact holes and on the device surface, then spin-coat a layer of photoresist on the surface of the metal layer, perform patterning on the photoresist through processes such as exposure and development, and finally remove the metal layer outside the area covered by the photoresist to form the source and drain electrodes. The existing process flow for fabricating the source and drain electrodes of GaN HEMT devices is complex, requiring patterning of both the photoresist and the metal layer, and the manufacturing cost is relatively high. Summary of the Invention

[0003] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problems that the existing process flow for fabricating the source and drain electrodes of GaN HEMT devices is complex and the manufacturing cost is relatively high.

[0004] In a first aspect, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method including:

[0005] Providing a substrate;

[0006] Successively forming a channel layer and a barrier layer on one side of the substrate;

[0007] Forming a first protective layer on the side of the barrier layer away from the substrate;

[0008] Forming a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness;

[0009] Etching the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole;

[0010] Forming a metal layer in the first ohmic contact hole, the second ohmic contact hole, and on the side of the second protective layer away from the substrate;

[0011] Forming a photoresist layer on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate;

[0012] Removing the photoresist layer and the metal layer on the side of the second protective layer away from the substrate; so as to form a source electrode in the first ohmic contact hole and a drain electrode in the second ohmic contact hole.

[0013] Optionally, forming a second protective layer on the side of the first protective layer away from the substrate includes:

[0014] On one side of the first protective layer away from the substrate, a second protective layer with a thickness of is formed.

[0015] Optionally, after forming the second protective layer on one side of the first protective layer away from the substrate, it further includes:

[0016] Forming a barrier layer on one side of the second protective layer away from the substrate;

[0017] Etching the barrier layer to form a third ohmic contact hole and a fourth ohmic contact hole, where the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate;

[0018] After etching the first protective layer and the second protective layer to form the first ohmic contact hole and the second ohmic contact hole, it further includes:

[0019] Etching the second protective layer on both sides of the first ohmic contact hole to form a fifth ohmic contact hole on both sides of the first ohmic contact hole; the fifth ohmic contact hole communicates with the first ohmic contact hole;

[0020] Etching the second protective layer on both sides of the second ohmic contact hole to form a sixth ohmic contact hole on both sides of the second ohmic contact hole; the sixth ohmic contact hole communicates with the second ohmic contact hole;

[0021] Forming a metal layer in the first ohmic contact hole, the second ohmic contact hole, and on one side of the second protective layer away from the substrate, including:

[0022] Forming a metal layer in the first ohmic contact hole, the fifth ohmic contact hole, the second ohmic contact hole, the sixth ohmic contact hole, and on one side of the barrier layer away from the substrate;

[0023] Removing the photoresist layer and the metal layer on one side of the second protective layer away from the substrate, including:

[0024] Removing the photoresist layer, the metal layer on one side of the barrier layer away from the substrate, and the barrier layer.

[0025] Optionally, before forming the first protective layer on one side of the barrier layer away from the substrate, it further includes:

[0026] Forming a doped group III-V semiconductor layer in the middle region on one side of the barrier layer away from the substrate;

[0027] Forming a Schottky contact layer on one side of the doped group III-V semiconductor layer away from the substrate;

[0028] Forming the first protective layer on one side of the barrier layer away from the substrate, including:

[0029] A first protective layer is formed on the side of the barrier layer away from the substrate, on the side of the doped group III-V semiconductor layer away from the substrate, and on the side of the Schottky contact layer away from the substrate.

[0030] Optionally, after removing the photoresist layer and the metal layer on the side of the second protective layer away from the substrate, the following steps are further included:

[0031] Etch the first protective layer and the second protective layer in the corresponding area of the Schottky contact layer to expose the Schottky contact layer.

[0032] Optionally, forming the first protective layer on the side of the barrier layer away from the substrate includes:

[0033] Form a silicon nitride protective layer on the side of the barrier layer away from the substrate;

[0034] Forming the second protective layer on the side of the first protective layer away from the substrate includes:

[0035] Form a silicon dioxide protective layer on the side of the first protective layer away from the substrate.

[0036] In a second aspect, the present invention provides a semiconductor device, which includes:

[0037] A substrate;

[0038] A channel layer and a barrier layer located on one side of the substrate;

[0039] A first protective layer located on the side of the barrier layer away from the substrate; the first protective layer is provided with a first sub-ohmic contact hole and a second sub-ohmic contact hole;

[0040] A second protective layer located on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness; the second protective layer is provided with a third sub-ohmic contact hole and a fourth sub-ohmic contact hole; the first sub-ohmic contact hole and the third sub-ohmic contact hole are combined into a first ohmic contact hole, and the second sub-ohmic contact hole and the fourth sub-ohmic contact hole are combined into a second ohmic contact hole;

[0041] A source electrode located in the first ohmic contact hole;

[0042] A drain electrode located in the second ohmic contact hole.

[0043] Optionally, the first preset thickness is

[0044] Optionally, the second protective layer further includes a fifth ohmic contact hole and a sixth ohmic contact hole;

[0045] The fifth ohmic contact hole is located on both sides of the third sub-ohmic contact hole and is connected to the third sub-ohmic contact hole; the sixth ohmic contact hole is located on both sides of the fourth sub-ohmic contact hole and is connected to the fourth sub-ohmic contact hole;

[0046] The source electrode is located within the first ohmic contact hole and the fifth ohmic contact hole; the drain electrode is located within the second ohmic contact hole and the sixth ohmic contact hole.

[0047] Optionally, the semiconductor device further includes: a doped group III-V semiconductor layer and a Schottky contact layer; the doped group III-V semiconductor layer and the Schottky contact layer are located between the barrier layer and the first protective layer; the first ohmic contact hole and the second ohmic contact hole are located on both sides of the doped group III-V semiconductor layer and the Schottky contact layer;

[0048] The doped group III-V semiconductor layer is located in the middle region on the side of the barrier layer away from the substrate;

[0049] The Schottky contact layer is located on the side of the doped group III-V semiconductor layer away from the substrate.

[0050] Optionally, the first protective layer includes a silicon nitride protective layer, and the second protective layer includes a silicon dioxide protective layer.

[0051] In the technical solution of the embodiment of the present invention, after a photoresist layer is formed on the side of the metal layer away from the substrate, it is not necessary to perform photolithography processes such as exposure and development on the photoresist layer for patterning. Instead, the photoresist layer and the metal layer on the side of the second protective layer away from the substrate can be effectively removed directly through an etching process, and the metal layer within the first ohmic contact hole is retained as the source electrode, and the metal layer within the second ohmic contact hole is retained as the drain electrode. The present invention simplifies the preparation process flow of the source electrode and the drain electrode of the GaN HEMT device. At the same time, since it is not necessary to perform photolithography processes such as exposure and development on the photoresist layer for patterning, the number of mask plates and the number of photolithography processes are saved, effectively reducing the preparation cost.

[0052] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0054] Figure 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0055] Figures 2 - 8 is a schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0056] Figure 9 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0057] Figure 10 is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0058] Figures 11 - 16 is a schematic structural diagram corresponding to some steps in yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 17 is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0060] Figure 18 is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0061] Figure 19 is a schematic structural diagram corresponding to some steps in yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0062] Figure 20 is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0063] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0064] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0065] Figure 1It is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figures 2 - 8 It is a schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 1 shown, the manufacturing method includes:

[0066] S100: Provide a substrate.

[0067] Specifically, as Figure 2 shown, first provide a substrate 1. The substrate 1 can be a Si substrate, a sapphire substrate, or a GaN substrate.

[0068] S110: Form a channel layer and a barrier layer in sequence on one side of the substrate.

[0069] Specifically, as Figure 2 shown, first form a channel layer 2 on one side of the substrate 1, and form a barrier layer 3 on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can use intrinsic GaN as the channel layer, and the barrier layer 3 can use an AlGaN material.

[0070] S120: Form a first protective layer on the side of the barrier layer away from the substrate.

[0071] Specifically, as Figure 3 described, form a first protective layer 4 on the side of the barrier layer 3 away from the substrate 1.

[0072] S130: Form a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness.

[0073] Specifically, as Figure 4 shown, form a second protective layer 5 on the side of the first protective layer 4 away from the substrate 1. The thickness of the second protective layer 5 should meet the requirement of the first preset thickness to ensure that the thickness of the second protective layer 5 is thick enough. Exemplarily, the thickness of the second protective layer 5 can be

[0074] S140: Etch the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole.

[0075] Specifically, as Figure 5 shown, the second protective layer 5 and the first protective layer 4 can be etched through a dry etching process to form a first ohmic contact hole 51 and a second ohmic contact hole 52. The first ohmic contact hole 51 and the second ohmic contact hole 52 are located on both sides of the device.

[0076] S150: Form a metal layer in the first ohmic contact hole, in the second ohmic contact hole, and on the side of the second protective layer away from the substrate.

[0077] Specifically, asFigure 6 As shown, a metal layer 6 is formed inside the first ohmic contact hole 51, inside the second ohmic contact hole 52, and on the side of the second protective layer 5 away from the substrate 1. The metal layer 6 can be an alloy metal layer.

[0078] S160: A photoresist layer is formed on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0079] Specifically, as Figure 7 shown, a photoresist layer 7 is formed on the side of the metal layer 6 away from the substrate 1. The vertical projection of the photoresist layer 7 on the substrate 1 can coincide with the vertical projection of the metal layer 6 on the substrate 1.

[0080] S170: Remove the photoresist layer and the metal layer on the side of the second protective layer away from the substrate; to form a source electrode in the first ohmic contact hole and a drain electrode in the second ohmic contact hole.

[0081] Specifically, as Figure 8 shown, the photoresist layer and the metal layer 6 on the side of the second protective layer 5 away from the substrate 1 can be removed by an etching process, and the metal layer 6 inside the first ohmic contact hole 51 is retained as the source electrode 61, and the metal layer 6 inside the second ohmic contact hole 52 is retained as the drain electrode 62. At this time, a part of the metal layer 6 at the edges of the first ohmic contact hole 51 and the second ohmic contact hole 52 may be etched.

[0082] During the process of fabricating the GaN HEMT device, the thickness of the second protective layer 5 should meet the requirement of the first preset thickness, ensuring that the thickness of the second protective layer 5 is thick enough so that the depths of the first ohmic contact hole 51 and the second ohmic contact hole 52 are deep enough. When the metal layer 6 is formed inside the first ohmic contact hole 51, inside the second ohmic contact hole 52, and on the side of the second protective layer 5 away from the substrate 1, the thickness of the metal layer in the middle region inside the first ohmic contact hole 51 and the second ohmic contact hole 52 is basically the same as the thickness of the metal layer 6 on the side of the second protective layer 5 away from the substrate 1, making the surface of the metal layer in the middle region inside the first ohmic contact hole 51 and the second ohmic contact hole 52 far from the surface on the side of the second protective layer 5 away from the substrate 1. When removing the photoresist layer and the excess metal layer 6 by an etching process, by controlling the etching depth, it can effectively remove the photoresist layer and the metal layer 6 on the side of the second protective layer 5 away from the substrate 1, and retain the metal layer 6 inside the first ohmic contact hole 51 as the source electrode 61 and the metal layer 6 inside the second ohmic contact hole 52 as the drain electrode 62.

[0083] Exemplarily, as Figure 7 and Figure 8As shown, after forming a photoresist layer 7 on the side of the metal layer 6 away from the substrate 1, through a dry etching process, such as introducing an etching gas, the etching gas can react chemically with both the photoresist layer 7 and the metal layer 6. First, the etching gas reacts with the entire photoresist layer 7. When the reaction reaches the side of the metal layer 6 away from the substrate 1 outside the regions corresponding to the first ohmic contact hole 51 and the second ohmic contact hole 52, the etching gas reacts with the contacted metal layer 6, and at the same time, continues to react with the photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52. Since the material of the photoresist layer 7 is an organic material, the reaction rate of the etching gas with the photoresist layer 7 is greater than the reaction rate of the etching gas with the metal layer 6. Etching stops after the metal layer 6 outside the regions corresponding to the first ohmic contact hole 51 and the second ohmic contact hole 52 completely reacts with the etching gas, and the etching depth is precisely controlled by controlling the etching time. Then, a professional cleaning solution is used to remove the reaction products generated by the reaction of the etching gas with the photoresist layer 7, and the reaction products generated by the reaction of the etching gas with the metal layer 6. After completing the above etching steps, there may still be some remaining photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52. Finally, the remaining photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52 is removed through a photoresist stripping process. During the photoresist stripping process, the second protective layer 5 is not affected, and the metal layer 6 in the first ohmic contact hole 51 and the second ohmic contact hole 52 is also not affected.

[0084] In the technical solution of the embodiment of the present invention, after forming a photoresist layer 7 on the side of the metal layer 6 away from the substrate 1, it is not necessary to perform patterning on the photoresist layer 7 through processes such as exposure and development. The metal layer 6 on the side of the photoresist layer 7 and the second protective layer 5 away from the substrate 1 can be effectively removed directly through the etching process, and the metal layer 6 in the first ohmic contact hole 51 is retained as the source electrode 61, and the metal layer 6 in the second ohmic contact hole 52 is retained as the drain electrode 62. The present invention simplifies the preparation process flow of the source electrode and the drain electrode of the GaN HEMT device. At the same time, since it is not necessary to perform patterning on the photoresist layer 7 through processes such as exposure and development, the number of mask plates and the number of photolithography processes are saved, and the preparation cost is effectively reduced.

[0085] Optionally, on the basis of the above embodiments, Figure 9 is a flowchart of another method for preparing a semiconductor device provided by an embodiment of the present invention. As Figure 9 shown, the preparation method includes:

[0086] S200: Provide a substrate.

[0087] S210: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0088] S220: Form a first protective layer on the side of the barrier layer away from the substrate.

[0089] S230: Form a second protective layer with a thickness of on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness.

[0090] Specifically, as Figure 4 shown, form a second protective layer 5 on the side of the first protective layer 4 away from the substrate 1. The thickness of the second protective layer 5 should meet the requirements of the first preset thickness to ensure that the thickness of the second protective layer 5 is thick enough. Exemplarily, the thickness of the second protective layer 5 can be

[0091] S240: Etch the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole.

[0092] S250: Form a metal layer in the first ohmic contact hole, the second ohmic contact hole, and on the side of the second protective layer away from the substrate.

[0093] S260: Form a photoresist layer on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0094] S270: Remove the photoresist layer and the metal layer on the side of the second protective layer away from the substrate; to form a source electrode in the first ohmic contact hole and a drain electrode in the second ohmic contact hole.

[0095] Optionally, on the basis of the above embodiments, Figure 10 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 11 - 16 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 10 shown, the manufacturing method includes:

[0096] S300: Provide a substrate.

[0097] S310: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0098] S320: Form a first protective layer on the side of the barrier layer away from the substrate.

[0099] S330: Form a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness.

[0100] S340: Form a barrier layer on the side of the second protective layer away from the substrate.

[0101] Specifically, as Figure 11As shown, a barrier layer 8 is formed on the side of the second protective layer 5 away from the substrate 1. Exemplarily, the barrier layer 8 may include a titanium nitride (TiN) barrier layer.

[0102] S350: Etch the barrier layer to form a third ohmic contact hole and a fourth ohmic contact hole.

[0103] Specifically, as Figure 12 shown, the barrier layer 8 can be etched by a dry etching process to form a third ohmic contact hole 81 and a fourth ohmic contact hole 82. The third ohmic contact hole 81 and the fourth ohmic contact hole 82 are located on both sides of the device.

[0104] S360: Etch the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole; the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate.

[0105] Specifically, as Figure 12 shown, continue to etch the second protective layer 5 and the first protective layer 4 in the area corresponding to the third ohmic contact hole 81 to form a first ohmic contact hole 51. The first ohmic contact hole 51 and the third ohmic contact hole 81 can be completed in the same dry etching process step. Continue to etch the second protective layer 5 and the first protective layer 4 in the area corresponding to the fourth ohmic contact hole 82 to form a second ohmic contact hole 52. The second ohmic contact hole 52 and the fourth ohmic contact hole 82 can be completed in the same dry etching process step.

[0106] S370: Etch the second protective layer on both sides of the first ohmic contact hole to form a fifth ohmic contact hole on both sides of the first ohmic contact hole; the fifth ohmic contact hole is in communication with the first ohmic contact hole.

[0107] Specifically, as Figure 13 shown, continue to etch the second protective layer 5 on both sides of the first ohmic contact hole 51 by a wet etching process to form a fifth ohmic contact hole 53. The second protective layer 5 is recessed inward relative to the barrier layer 8 and the first protective layer 4.

[0108] S380: Etch the second protective layer on both sides of the second ohmic contact hole to form a sixth ohmic contact hole on both sides of the second ohmic contact hole; the sixth ohmic contact hole is in communication with the second ohmic contact hole.

[0109] Specifically, as Figure 13 shown, continue to etch the second protective layer 5 on both sides of the second ohmic contact hole 52 by a wet etching process to form a sixth ohmic contact hole 54. The second protective layer 5 is recessed inward relative to the barrier layer 8 and the first protective layer 4.

[0110] S390: A metal layer is formed inside the first ohmic contact hole, inside the fifth ohmic contact hole, inside the second ohmic contact hole, inside the sixth ohmic contact hole, and on the side of the barrier layer away from the substrate.

[0111] Specifically, as Figure 14 shown, a metal layer 6 is formed inside the first ohmic contact hole 51, inside the fifth ohmic contact hole 53, inside the second ohmic contact hole 52, inside the sixth ohmic contact hole 54, and on the side of the barrier layer 8 away from the substrate 1. During the formation of the metal layer 6, the barrier layer 8 in the corresponding area of the fifth ohmic contact hole 53 can disconnect the metal layer 6 inside the fifth ohmic contact hole 53 from the metal layer 6 on the side of the barrier layer 8 away from the substrate 1, and the barrier layer 8 in the corresponding area of the sixth ohmic contact hole 54 can disconnect the metal layer 6 inside the sixth ohmic contact hole 54 from the metal layer 6 on the side of the barrier layer 8 away from the substrate 1.

[0112] S391: A photoresist layer is formed on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0113] Specifically, as Figure 15 shown, a photoresist layer 7 is formed on the side of the metal layer 6 away from the substrate 1.

[0114] S392: Remove the photoresist layer, the metal layer on the side of the barrier layer away from the substrate, and the barrier layer.

[0115] Specifically, as Figure 16 shown, the photoresist layer, the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer can be removed through an etching process, and the metal layer 6 inside the first ohmic contact hole 51 is retained as the source electrode 61, and the metal layer 6 inside the second ohmic contact hole 52 is retained as the drain electrode 62.

[0116] In the process of fabricating a GaN HEMT device, the thickness of the second protective layer 5 should meet the requirement of the first preset thickness, ensuring that the thickness of the second protective layer 5 is thick enough so that the depths of the first ohmic contact hole 51, the second ohmic contact hole 52, the fifth ohmic contact hole 53, and the sixth ohmic contact hole 54 are deep enough. When forming a metal layer 6 in the first ohmic contact hole 51, the second ohmic contact hole 52, the fifth ohmic contact hole 53, and the sixth ohmic contact hole 54 and on the side of the barrier layer away from the substrate 1, the thickness of the metal layer in the middle region of the first ohmic contact hole 51 and the second ohmic contact hole 52 is basically the same as the thickness of the metal layer 6 on the side of the second protective layer 5 away from the substrate 1, such that the surface of the metal layer in the middle region of the first ohmic contact hole 51 and the second ohmic contact hole 52 is at a relatively far distance from the surface of the barrier layer on the side away from the substrate 1. Also, the barrier layer in the region corresponding to the fifth ohmic contact hole 53 disconnects the metal layer 6 in the fifth ohmic contact hole 53 from the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer in the region corresponding to the sixth ohmic contact hole 54 disconnects the metal layer 6 in the sixth ohmic contact hole 54 from the metal layer 6 on the side of the barrier layer away from the substrate 1. When removing the photoresist layer, the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer through an etching process, by controlling the etching depth, the photoresist layer, the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer can be effectively removed, and the metal layer 6 in the first ohmic contact hole 51 is retained as the source electrode 61, and the metal layer 6 in the second ohmic contact hole 52 is retained as the drain electrode 62.

[0117] Exemplarily, such as Figure 15 and Figure 16As shown, after a photoresist layer 7 is formed on the side of the metal layer 6 away from the substrate 1, through a dry etching process, such as introducing an etching gas, the etching gas can react chemically with both the photoresist layer 7 and the metal layer 6 and the barrier layer 8. First, the etching gas reacts with the entire photoresist layer 7. When the reaction reaches the side of the metal layer 6 away from the substrate 1 outside the regions corresponding to the first ohmic contact hole 51 and the second ohmic contact hole 52, the etching gas reacts with the metal layer 6 on the side of the barrier layer 8 away from the substrate 1, and at the same time continues to react with the photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52. Since the material of the photoresist layer 7 is an organic material, the reaction rate of the etching gas with the photoresist layer 7 is greater than the reaction rate of the etching gas with the metal layer 6. When the reaction reaches the side of the barrier layer 8 away from the substrate 1, the etching gas reacts with the barrier layer 8, and at the same time continues to react with the photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52. The reaction rate of the etching gas with the photoresist layer 7 is greater than the reaction rate of the etching gas with the barrier layer 8. The etching is stopped after the barrier layer 8 has completely reacted with the etching gas, and the etching depth is precisely controlled by controlling the etching time. Then, a professional cleaning solution is used to remove the reaction products generated by the reaction of the etching gas with the photoresist layer 7, the reaction products generated by the reaction of the etching gas with the metal layer 6, and the reaction products generated by the reaction of the barrier layer 8 with the etching gas. After the above etching steps are completed, there may still be some remaining photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52. Finally, the remaining photoresist layer 7 in the first ohmic contact hole 51 and the second ohmic contact hole 52 is removed through a photoresist stripping process. During the photoresist stripping process, the second protective layer 5 is not affected, and the metal layer 6 in the first ohmic contact hole 51 and the second ohmic contact hole 52 is also not affected.

[0118] As Figure 15 and Figure 16 shown, the metal layer 6 is an alloy metal layer, and along the thickness direction of the substrate 1, the metal layer 6 is composed of different material layers. The barrier layer 8 in the regions corresponding to the fifth ohmic contact hole 53 and the sixth ohmic contact hole 54 can disconnect the metal layer 6 in the fifth ohmic contact hole 53 and the sixth ohmic contact hole 54 from the metal layer 6 on the side of the barrier layer 8 away from the substrate 1. When removing the photoresist layer 7, the metal layer 6 on the side of the barrier layer 8 away from the substrate 1, and the barrier layer 8, the metal layer 6 in the fifth ohmic contact hole 53 and the sixth ohmic contact hole 54 will not be etched, avoiding the situation where the material of the intermediate layer may be etched first when the metal layer 6 in the fifth ohmic contact hole 53 and the sixth ohmic contact hole 54 is etched, which may cause the material layer above the metal layer 6 in the fifth ohmic contact hole 53 and the sixth ohmic contact hole 54 to break and fall into other regions of the device, affecting the performance of the device.

[0119] Optionally, based on the above embodiments,Figure 17 It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 17 shown, the manufacturing method includes:

[0120] S400: Provide a substrate.

[0121] S410: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0122] S420: Form a doped group III-V semiconductor layer in the middle region on the side of the barrier layer away from the substrate.

[0123] Specifically, as Figure 2 shown, a doped group III-V semiconductor layer 9 is formed in the middle region on the side of the barrier layer 3 away from the substrate 1. Exemplarily, the doped group III-V semiconductor layer 9 may include a P-GaN layer.

[0124] S430: Form a Schottky contact layer on the side of the doped group III-V semiconductor layer away from the substrate.

[0125] Specifically, as Figure 2 shown, a Schottky contact layer 10 is formed on the side of the doped group III-V semiconductor layer 9 away from the substrate 1. Exemplarily, the Schottky contact layer 10 may include a titanium nitride layer.

[0126] S440: Form a first protective layer on the side of the barrier layer away from the substrate, on the side of the doped group III-V semiconductor layer away from the substrate, and on the side of the Schottky contact layer away from the substrate.

[0127] Specifically, as Figure 3 shown, a first protective layer 4 is formed on the side of the barrier layer 3 away from the substrate 1, on the side of the doped group III-V semiconductor layer 9 away from the substrate 1, and on the side of the Schottky contact layer 10 away from the substrate 1.

[0128] S450: Form a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness.

[0129] S460: Form a barrier layer on the side of the second protective layer away from the substrate.

[0130] S470: Etch the barrier layer to form a third ohmic contact hole and a fourth ohmic contact hole.

[0131] S480: Etch the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole; the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate.

[0132] S490: Etch the second protective layer on both sides of the first ohmic contact hole to form fifth ohmic contact holes on both sides of the first ohmic contact hole; the fifth ohmic contact holes communicate with the first ohmic contact hole.

[0133] S491: Etch the second protective layer on both sides of the second ohmic contact hole to form sixth ohmic contact holes on both sides of the second ohmic contact hole; the sixth ohmic contact holes communicate with the second ohmic contact hole.

[0134] S492: Form a metal layer inside the first ohmic contact hole, inside the fifth ohmic contact hole, inside the second ohmic contact hole, inside the sixth ohmic contact hole, and on the side of the barrier layer away from the substrate.

[0135] S493: Form a photoresist layer on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0136] S494: Remove the photoresist layer, the metal layer on the side of the barrier layer away from the substrate, and the barrier layer.

[0137] Optionally, based on the above embodiments, Figure 18 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figure 19 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 18 shown, the manufacturing method includes:

[0138] S500: Provide a substrate.

[0139] S510: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0140] S520: Form a doped group III-V semiconductor layer in the middle region on the side of the barrier layer away from the substrate.

[0141] S530: Form a Schottky contact layer on the side of the doped group III-V semiconductor layer away from the substrate.

[0142] S540: Form a first protective layer on the side of the barrier layer away from the substrate, on the side of the doped group III-V semiconductor layer away from the substrate, and on the side of the Schottky contact layer away from the substrate.

[0143] S550: Form a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness.

[0144] S560: Form a barrier layer on the side of the second protective layer away from the substrate.

[0145] S570: Etch the barrier layer to form third ohmic contact holes and fourth ohmic contact holes.

[0146] S580: Etch the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole; the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate.

[0147] S590: Etch the second protective layer on both sides of the first ohmic contact hole to form a fifth ohmic contact hole on both sides of the first ohmic contact hole; the fifth ohmic contact hole communicates with the first ohmic contact hole.

[0148] S591: Etch the second protective layer on both sides of the second ohmic contact hole to form a sixth ohmic contact hole on both sides of the second ohmic contact hole; the sixth ohmic contact hole communicates with the second ohmic contact hole.

[0149] S592: Form a metal layer inside the first ohmic contact hole, inside the fifth ohmic contact hole, inside the second ohmic contact hole, inside the sixth ohmic contact hole, and on the side of the barrier layer away from the substrate.

[0150] S593: Form a photoresist layer on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0151] S594: Remove the photoresist layer, the metal layer on the side of the barrier layer away from the substrate, and the barrier layer.

[0152] S595: Etch the first protective layer and the second protective layer in the corresponding area of the Schottky contact layer to expose the Schottky contact layer.

[0153] Specifically, as Figure 19 shown, etch the first protective layer 4 and the second protective layer 5 in the corresponding area of the Schottky contact layer 10 to form a first through hole 55 to expose the Schottky contact layer 10. The doped III-V semiconductor layer 9 and the Schottky contact layer 10 can be used as a gate structure, and the exposed Schottky contact layer 10 can be connected to the metal layer in subsequent processes.

[0154] Optionally, on the basis of the above embodiments, Figure 20 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 20 shown, the manufacturing method includes:

[0155] S600: Provide a substrate.

[0156] S610: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0157] S620: Form a doped III-V semiconductor layer in the middle area on the side of the barrier layer away from the substrate.

[0158] S630: A Schottky contact layer is formed on the side of the doped group III-V semiconductor layer away from the substrate.

[0159] S640: A silicon nitride protective layer is formed on the side of the barrier layer away from the substrate, on the side of the doped group III-V semiconductor layer away from the substrate, and on the side of the Schottky contact layer away from the substrate.

[0160] Specifically, as Figure 3 shown, a first protective layer 4 is formed on the side of the barrier layer 3 away from the substrate 1, on the side of the doped group III-V semiconductor layer 9 away from the substrate 1, and on the side of the Schottky contact layer 10 away from the substrate 1. Exemplarily, the first protective layer 4 can be a silicon nitride protective layer.

[0161] S650: A silicon dioxide protective layer is formed on the side of the silicon nitride protective layer away from the substrate; the thickness of the silicon dioxide protective layer is a first preset thickness.

[0162] Specifically, as Figure 4 shown, a second protective layer 5 is formed on the side of the first protective layer 4 away from the substrate 1. Exemplarily, the second protective layer 5 can be a silicon dioxide protective layer. The thickness of the silicon dioxide protective layer should meet the requirement of the first preset thickness to ensure that the thickness of the silicon dioxide protective layer is thick enough. Exemplarily, the thickness of the silicon dioxide protective layer can be

[0163] S660: A barrier layer is formed on the side of the silicon dioxide protective layer away from the substrate.

[0164] S670: The barrier layer is etched to form a third ohmic contact hole and a fourth ohmic contact hole.

[0165] S680: The first protective layer and the second protective layer are etched to form a first ohmic contact hole and a second ohmic contact hole; the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate.

[0166] S690: The second protective layer on both sides of the first ohmic contact hole is etched to form a fifth ohmic contact hole on both sides of the first ohmic contact hole; the fifth ohmic contact hole communicates with the first ohmic contact hole.

[0167] S691: The second protective layer on both sides of the second ohmic contact hole is etched to form a sixth ohmic contact hole on both sides of the second ohmic contact hole; the sixth ohmic contact hole communicates with the second ohmic contact hole.

[0168] S692: A metal layer is formed inside the first ohmic contact hole, inside the fifth ohmic contact hole, inside the second ohmic contact hole, inside the sixth ohmic contact hole, and on the side of the barrier layer away from the substrate.

[0169] S693: A photoresist layer is formed on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate.

[0170] S694: Remove the photoresist layer, the metal layer on the side of the barrier layer away from the substrate, and the barrier layer.

[0171] Figure 19 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. As Figure 19 shown, the semiconductor device includes: a substrate 1, a channel layer 2 and a barrier layer 3 located on one side of the substrate 1. A first protective layer 4 is located on the side of the barrier layer 3 away from the substrate 1. The first protective layer 4 is provided with a first sub-ohmic contact hole and a second sub-ohmic contact hole. A second protective layer 5 is located on the side of the first protective layer 4 away from the substrate 1. The thickness of the second protective layer 5 is a first preset thickness. The second protective layer 5 is provided with a third sub-ohmic contact hole and a fourth sub-ohmic contact hole. The first sub-ohmic contact hole and the third sub-ohmic contact hole are combined to form a first ohmic contact hole 51, and the second sub-ohmic contact hole and the fourth sub-ohmic contact hole are combined to form a second ohmic contact hole 52. A source electrode 61 is located inside the first ohmic contact hole 51. A drain electrode 62 is located inside the second ohmic contact hole 52. Preferably, the first preset thickness is

[0172] Specifically, Figure 19 shows the structure of a GaN HEMT semiconductor device. The GaN HEMT semiconductor device includes a substrate 1, a channel layer 2 and a barrier layer 3 stacked. The substrate 1 can be a Si substrate, a sapphire substrate or a GaN substrate. The channel layer 2 can use intrinsic GaN as the channel layer, and the barrier layer 3 can use an AlGaN material.

[0173] The first protective layer 4 and the second protective layer 5 can be jointly provided with a first ohmic contact hole 53 formed by the first sub-ohmic contact hole and the third sub-ohmic contact hole, and a second ohmic contact hole 54 formed by the second sub-ohmic contact hole and the fourth sub-ohmic contact hole. The second protective layer 5 can also be provided with a fifth ohmic contact hole 53 and a sixth ohmic contact hole 54. The fifth ohmic contact hole 53 is located on both sides of the third sub-ohmic contact hole and is connected to the third sub-ohmic contact hole. The sixth ohmic contact hole 54 is located on both sides of the fourth sub-ohmic contact hole and is connected to the fourth sub-ohmic contact hole. The thickness of the second protective layer 5 should meet the requirement of the first preset thickness to ensure that the thickness of the second protective layer 5 is thick enough. Exemplarily, the thickness of the second protective layer 5 can be

[0174] In the process of fabricating a GaN HEMT device, a blocking layer can be formed on the side of the second protective layer 5 away from the substrate 1. The blocking layer can include a third ohmic contact hole and a fourth ohmic contact hole. The vertical projection of the third ohmic contact hole on the substrate 1 coincides with the vertical projection of the first ohmic contact hole 51 on the substrate 1, and the vertical projection of the fourth ohmic contact hole on the substrate 1 coincides with the vertical projection of the second ohmic contact hole 52 on the substrate 1. Then, a metal layer 6 is formed inside the first ohmic contact hole 51, inside the fifth ohmic contact hole 53, inside the second ohmic contact hole 52, inside the sixth ohmic contact hole 54, and on the side of the blocking layer away from the substrate 1. During the formation of the metal layer 6, the blocking layer in the region corresponding to the fifth ohmic contact hole 53 can disconnect the metal layer 6 inside the fifth ohmic contact hole 53 from the metal layer 6 on the side of the blocking layer away from the substrate 1, and the blocking layer in the region corresponding to the sixth ohmic contact hole 54 can disconnect the metal layer 6 inside the sixth ohmic contact hole 54 from the metal layer 6 on the side of the blocking layer away from the substrate 1.

[0175] A photoresist layer is formed on the side of the metal layer 6 away from the substrate 1. The vertical projection of the photoresist layer on the substrate 1 can coincide with the vertical projection of the metal layer 6 on the substrate 1. Finally, the photoresist layer, the metal layer 6 on the side of the blocking layer away from the substrate 1, and the blocking layer can be removed through an etching process, and the metal layer 6 inside the first ohmic contact hole 51 and inside the fifth ohmic contact hole 53 is retained as the source electrode 61, and the metal layer 6 inside the second ohmic contact hole 52 and inside the sixth ohmic contact hole 54 is retained as the drain electrode 62.

[0176] In the process of fabricating a GaN HEMT device, the thickness of the second protective layer 5 should meet the requirement of a first preset thickness, ensuring that the thickness of the second protective layer 5 is thick enough so that the depths of the first ohmic contact hole 51, the second ohmic contact hole 52, the fifth ohmic contact hole 53, and the sixth ohmic contact hole 54 are deep enough. When forming a metal layer 6 in the first ohmic contact hole 51, the second ohmic contact hole 52, the fifth ohmic contact hole 53, and the sixth ohmic contact hole 54 and on the side of the barrier layer away from the substrate 1, the thickness of the metal layer in the middle regions of the first ohmic contact hole 51 and the second ohmic contact hole 52 is basically the same as the thickness of the metal layer 6 on the side of the barrier layer away from the substrate 1, such that the surface of the metal layer in the middle regions of the first ohmic contact hole 51 and the second ohmic contact hole 52 is far from the surface of the side of the barrier layer away from the substrate 1. Moreover, the barrier layer in the region corresponding to the fifth ohmic contact hole 53 disconnects the metal layer 6 in the fifth ohmic contact hole 53 from the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer in the region corresponding to the sixth ohmic contact hole 54 disconnects the metal layer 6 in the sixth ohmic contact hole 54 from the metal layer 6 on the side of the barrier layer away from the substrate 1. When removing the photoresist layer, the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer through an etching process, by controlling the etching depth, the photoresist layer, the metal layer 6 on the side of the barrier layer away from the substrate 1, and the barrier layer can be effectively removed, and the metal layer 6 in the first ohmic contact hole 51 and the metal layer 6 in the fifth ohmic contact hole 53 are retained as the source electrode 61, and the metal layer 6 in the second ohmic contact hole 52 and the metal layer 6 in the sixth ohmic contact hole 54 are retained as the drain electrode 62.

[0177] In the embodiment of the present invention, the thickness of the second protective layer 5 should meet the requirement of the first preset thickness, ensuring that the thickness of the second protective layer 5 is thick enough. Compared with the existing GaN HEMT devices, after the source electrode 61 and the drain electrode 62 are fabricated, there is no need to further form protective layers such as silicon nitride and silicon dioxide on the side of the second protective layer 5 away from the substrate 1, further simplifying the fabrication process of the GaN HEMT device and reducing the fabrication cost.

[0178] Optionally, on the basis of the above embodiments, with continued reference to Figure 19 , the semiconductor device further includes: a doped III-V semiconductor layer 9 and a Schottky contact layer 10. The doped III-V semiconductor layer 9 and the Schottky contact layer 10 are located between the barrier layer 3 and the first protective layer 4. The first ohmic contact hole 51 and the second ohmic contact hole 52 are located on both sides of the doped III-V semiconductor layer 9 and the Schottky contact layer 10. The doped III-V semiconductor layer 9 is located in the middle region on the side of the barrier layer 3 away from the substrate 1. The Schottky contact layer 10 is located on the side of the doped III-V semiconductor layer 9 away from the substrate 1.

[0179] Specifically, the doped group III-V semiconductor layer 9 may include a P-GaN layer, and the Schottky contact layer 10 may include a titanium nitride layer. The first protective layer 4 may be located on the side of the barrier layer 3 away from the substrate 1, on the side of the doped group III-V semiconductor layer 9 away from the substrate 1, and on the side of the Schottky contact layer 10 away from the substrate 1.

[0180] The first protective layer 4 and the second protective layer 5 may also be jointly provided with a first through hole 55 to expose the Schottky contact layer 10. The doped group III-V semiconductor layer 9 and the Schottky contact layer 10 may serve as a gate structure, and the exposed Schottky contact layer 10 may be connected to a metal layer in subsequent processes.

[0181] Optionally, on the basis of the above embodiments, continue to refer to Figure 19 , the first protective layer 4 includes a silicon nitride protective layer, and the second protective layer 5 includes a silicon dioxide protective layer.

[0182] Specifically, the first protective layer 4 may be a silicon nitride protective layer, and the second protective layer 5 may be a silicon dioxide protective layer. The thickness of the silicon dioxide protective layer should meet the requirements of the first preset thickness to ensure that the thickness of the silicon dioxide protective layer is thick enough. Exemplarily, the thickness of the silicon dioxide protective layer may be

[0184] The semiconductor device provided in any of the above embodiments of the present invention is manufactured by using the manufacturing method of the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the manufacturing method of the semiconductor device provided in any of the above embodiments of the present invention.

[0185] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0186] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate; Successively forming a channel layer and a barrier layer on one side of the substrate; Forming a first protective layer on the side of the barrier layer away from the substrate; Forming a second protective layer on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness; Etching the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole; Forming a metal layer in the first ohmic contact hole, in the second ohmic contact hole, and on the side of the second protective layer away from the substrate; Forming a photoresist layer on the side of the metal layer away from the substrate; the vertical projection of the photoresist layer on the substrate coincides with the vertical projection of the metal layer on the substrate; Removing the photoresist layer and the metal layer on the side of the second protective layer away from the substrate; To form a source electrode in the first ohmic contact hole and a drain electrode in the second ohmic contact hole.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Forming a second protective layer on the side of the first protective layer away from the substrate, including: On a side of the first protective layer away from the substrate, a second protective layer with a thickness of is formed.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, After forming a second protective layer on the side of the first protective layer away from the substrate, further including: Forming a barrier layer on the side of the second protective layer away from the substrate; Etching the barrier layer to form a third ohmic contact hole and a fourth ohmic contact hole, the vertical projection of the third ohmic contact hole on the substrate coincides with the vertical projection of the first ohmic contact hole on the substrate; the vertical projection of the fourth ohmic contact hole on the substrate coincides with the vertical projection of the second ohmic contact hole on the substrate; After etching the first protective layer and the second protective layer to form a first ohmic contact hole and a second ohmic contact hole, further including: Etching the second protective layer on both sides of the first ohmic contact hole to form a fifth ohmic contact hole on both sides of the first ohmic contact hole; the fifth ohmic contact hole communicates with the first ohmic contact hole; Etching the second protective layer on both sides of the second ohmic contact hole to form a sixth ohmic contact hole on both sides of the second ohmic contact hole; the sixth ohmic contact hole communicates with the second ohmic contact hole; Forming a metal layer in the first ohmic contact hole, in the second ohmic contact hole, and on the side of the second protective layer away from the substrate, including: Forming a metal layer in the first ohmic contact hole, in the fifth ohmic contact hole, in the second ohmic contact hole, in the sixth ohmic contact hole, and on the side of the barrier layer away from the substrate; Removing the photoresist layer and the metal layer on the side of the second protective layer away from the substrate, including: Removing the photoresist layer, the metal layer on the side of the barrier layer away from the substrate, and the barrier layer.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Before forming a first protective layer on the side of the barrier layer away from the substrate, further including: Forming a doped III-V semiconductor layer in the middle region on the side of the barrier layer away from the substrate; Forming a Schottky contact layer on the side of the doped III-V semiconductor layer away from the substrate; Forming a first protective layer on the side of the barrier layer away from the substrate, including: A first protective layer is formed on the side of the barrier layer away from the substrate, on the side of the doped group III-V semiconductor layer away from the substrate, and on the side of the Schottky contact layer away from the substrate.

5. The manufacturing method of the semiconductor device according to claim 4, characterized in that, After removing the photoresist layer and the metal layer on the side of the second protective layer away from the substrate, it further includes: Etching the first protective layer and the second protective layer in the corresponding area of the Schottky contact layer to expose the Schottky contact layer.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Forming the first protective layer on the side of the barrier layer away from the substrate includes: Forming a silicon nitride protective layer on the side of the barrier layer away from the substrate; Forming the second protective layer on the side of the first protective layer away from the substrate includes: Forming a silicon dioxide protective layer on the side of the first protective layer away from the substrate.

7. A semiconductor device, characterized in that, It includes: A substrate; A channel layer and a barrier layer located on one side of the substrate; A first protective layer located on the side of the barrier layer away from the substrate; the first protective layer is provided with a first sub-ohmic contact hole and a second sub-ohmic contact hole; A second protective layer located on the side of the first protective layer away from the substrate; the thickness of the second protective layer is a first preset thickness; the second protective layer is provided with a third sub-ohmic contact hole and a fourth sub-ohmic contact hole; the first sub-ohmic contact hole and the third sub-ohmic contact hole are combined into a first ohmic contact hole, and the second sub-ohmic contact hole and the fourth sub-ohmic contact hole are combined into a second ohmic contact hole; A source electrode located in the first ohmic contact hole; A drain electrode located in the second ohmic contact hole.

8. The semiconductor device according to claim 7, wherein The first preset thickness is 9. The semiconductor device according to claim 7, wherein The second protective layer further includes a fifth ohmic contact hole and a sixth ohmic contact hole; The fifth ohmic contact hole is located on both sides of the third sub-ohmic contact hole and is communicated with the third sub-ohmic contact hole; the sixth ohmic contact hole is located on both sides of the fourth sub-ohmic contact hole and is communicated with the fourth sub-ohmic contact hole; The source electrode is located in the first ohmic contact hole and the fifth ohmic contact hole; the drain electrode is located in the second ohmic contact hole and the sixth ohmic contact hole.

10. The semiconductor device according to claim 7, characterized in that, It further includes: A doped group III-V semiconductor layer and a Schottky contact layer; the doped group III-V semiconductor layer and the Schottky contact layer are located between the barrier layer and the first protective layer; The first ohmic contact hole and the second ohmic contact hole are located on both sides of the doped group III-V semiconductor layer and the Schottky contact layer; The doped group III-V semiconductor layer is located in the middle area on the side of the barrier layer away from the substrate; The Schottky contact layer is located on the side of the doped group III-V semiconductor layer away from the substrate.

11. The semiconductor device according to claim 7, wherein, The first protective layer includes a silicon nitride protective layer, and the second protective layer includes a silicon dioxide protective layer.

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