A low-drive-voltage trench-gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides a low-drive voltage trench-gate silicon carbide VDMOS and a preparation method thereof, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a masking layer, a P-type well region, a P-type base region, a P-type source region, and an N-type source region; reforming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the N-type source region, and depositing metal to form a source metal layer; reforming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the masking layer, and depositing to form an insulating dielectric layer; reforming the barrier layer, etching the barrier layer to form a through hole, and etching the insulating dielectric layer to form a trench, depositing metal to form a gate metal layer, removing the barrier layer, and completing the preparation, thereby reducing the device driving voltage and device driving loss, thereby improving device reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a low-driving-voltage trench-gate silicon carbide (VDMOS) and a preparation method thereof. Background Art

[0002] Due to their wide bandgap characteristics, silicon carbide VDMOS devices naturally have the characteristics of low gate charge and high switching speed compared to Si VDMOS devices. However, due to the relationship between their bandgap width and the bandgap of the insulating dielectric silicon dioxide, silicon carbide VDMOS devices generally can only achieve full conduction and the lowest on-resistance when the gate drive voltage reaches 15V. However, due to the poor quality of the insulating dielectric silicon dioxide, the gate voltage withstand capability of the device is low, and high drive voltages can easily lead to gate reliability issues of the device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a low-drive voltage trench-gate silicon carbide VDMOS and its preparation method, which can achieve full device conduction at a gate drive voltage of 12V, reduce device drive voltage, reduce device drive losses, and improve device reliability.

[0004] In a first aspect, the present invention provides a method for preparing a low drive voltage trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a masking layer;

[0007] Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region;

[0008] Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type base region;

[0009] Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type source region;

[0010] Step 6: remove the barrier layer in step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0011] Step 7: remove the barrier layer in step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the N-type source region, deposit metal to form a source metal layer;

[0012] Step 8: removing the barrier layer in step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the mask layer, and depositing to form an insulating dielectric layer;

[0013] Step 9: remove the barrier layer of step 8, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a groove, deposit metal to form a gate metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention provides a low driving voltage trench gate silicon carbide VDMOS, which is prepared by the method for preparing a low driving voltage trench gate silicon carbide VDMOS according to the first aspect.

[0015] The advantages of the present invention are:

[0016] First, the present invention constructs a P-type base region and a P-type well region with a gradually decreasing concentration gradient. The highly doped P-type base region vertically ensures that the N-type source region and the space charge region formed therewith do not affect the diffusion of the lateral space charge region to the device gate, thereby ensuring the gate-controlled turn-off characteristics of the device. The P-type base region shields the space charge region of the N-type source region. The space charge region formed by the low-doped P-type well region at the bottom of the P-type base region ensures the gate turn-off characteristics of the device. When the device withstands reverse voltage, the two-layer P-type doping structure can form a structure with a gradually increasing electric field near the N-type source region of the device, thereby improving the withstand voltage capability of the source region of the device.

[0017] Second, the N-type source region, P-type base region, and P-type well region are not directly connected to the insulating dielectric layer. A drift layer is placed in between. A space charge region is formed by the P-type well region, the P-type base region, and the drift layer to achieve shutdown during reverse withstand voltage. The gap structure can reduce the inversion driving voltage, thereby reducing the driving voltage of the device.

[0018] 3. In order to ensure the gate reliability of the device, a masking layer with the same width as the insulating dielectric is constructed directly below the insulating dielectric layer of the device to avoid the impact on the device gate structure during the reverse withstand voltage test. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0020] Figure 1 This is a schematic diagram of a low-drive voltage trench-gate silicon carbide VDMOS according to the present invention.

[0021] Figure 2 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0022] Figure 3This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0023] Figure 4 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0024] Figure 5 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0025] Figure 6 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0026] Figure 7 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0027] Figure 8 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0028] Figure 9 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0029] Figure 10 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0030] Figure 11 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0031] Figure 12 This is a cross-sectional view of the process of a low driving voltage trench gate silicon carbide VDMOS of the present invention Figure 10 one. DETAILED DESCRIPTION

[0032] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0035] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0036] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a low driving voltage trench gate silicon carbide VDMOS, comprising the following steps:

[0038] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111; and perform epitaxial growth on the side of the silicon carbide substrate 101 to form a drift layer 102;

[0039] Step 2: forming a barrier layer 100 on the drift layer 102, etching the barrier layer 100 to form a through hole, and performing ion implantation to form a masking layer 107;

[0040] Step 3: removing the barrier layer 100 in step 2, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type well region 103;

[0041] Step 4: removing the barrier layer 100 in step 3, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type base region 104;

[0042] Step 5: removing the barrier layer 100 of step 4, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type source region 105;

[0043] Step 6: removing the barrier layer 100 in step 5, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form an N-type source region 106;

[0044] Step 7: remove the barrier layer 100 in step 6, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the N-type source region 106, and deposit metal to form a source metal layer 110;

[0045] Step 8: remove the barrier layer 100 in step 7, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the mask layer 107, and deposit to form an insulating dielectric layer 108;

[0046] Step 9, remove the barrier layer 100 of step 8, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the insulating dielectric layer 108 to form a groove 1081, deposit metal to form a gate metal layer 109, remove the barrier layer 100, and complete the preparation.

[0047] In this embodiment, preferably, the distance between the inner side of the P-type well region 103 and the outer side of the insulating dielectric layer 108 is greater than the distance between the inner side of the P-type base region 104 and the outer side of the insulating dielectric layer 108 .

[0048] In this embodiment, preferably, the lower side surface of the gate metal layer 109 and the lower side surface of the P-type well region 103 are located in the same plane.

[0049] In this embodiment, preferably, the doping concentration of the P-type base region 104 is greater than the doping concentration of the P-type well region 103 .

[0050] In this embodiment, preferably, the doping concentration of the P-type well region 103 is greater than the doping concentration of the drift layer 102 .

[0051] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the N-type source region 106 .

[0052] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0053] silicon carbide substrate 101,

[0054] a drift layer 102 , wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101 ; a protrusion 1021 is provided on the drift layer 102 , and a groove (not shown) is provided in the protrusion 1021 ;

[0055] A P-type well region 103 , wherein the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102 , and the inner side of the P-type well region 103 is connected to the outer side of the protrusion 1021 ;

[0056] A P-type base region 104 , wherein the lower side of the P-type base region 104 is connected to the upper side of the P-type well region 103 , and the inner side of the P-type base region 104 is connected to the outer side of the protrusion 1021 ;

[0057] A P-type source region 105 , wherein the lower side of the P-type source region 105 is connected to the upper side of the P-type base region 104 ;

[0058] An N-type source region 106, wherein the lower side of the N-type source region 106 is connected to the upper side of the P-type base region 104, the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 105, and the inner side of the N-type source region 106 is connected to the outer side of the protrusion 1021;

[0059] a masking layer 107, wherein the masking layer 107 is disposed in the groove;

[0060] an insulating dielectric layer 108 , the insulating dielectric layer 108 being disposed in the groove, and the lower side of the insulating dielectric layer 108 being connected to the upper side of the masking layer 107 ; the insulating dielectric layer 108 protruding from the groove, and having a groove 1081 therein;

[0061] a gate metal layer 109 , wherein the gate metal layer 109 is disposed in the trench 1081 ;

[0062] a source metal layer 110 , the source metal layer 110 being connected to the upper side of the protrusion 1021 , the upper side of the P-type source region 105 , and the upper side of the N-type source region 106 ;

[0063] and a drain metal layer 111 , wherein the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101 .

[0064] In another embodiment of the present invention, the silicon carbide substrate 101 and the drift layer 102 are N-type, and the masking layer 107 is P-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the drift layer 102 is 6-10e15cm -3 , the doping concentration of the masking layer 107 is 1-5e16cm -3 The doping concentration of the P-type well region 103 is 1-5e17cm -3 The doping concentration of the P-type base region 104 is 1-5e18cm -3 , the doping concentration of the P-type source region 105 is 1-5e19cm -3 , the doping concentration of the N-type source region 106 is 2-8e18cm -3 , the material of the insulating dielectric layer 108 may be silicon dioxide;

[0065] The doping concentration of the silicon carbide substrate 101 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 111, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the masking layer 107 is to improve the reliability of the bottom of the insulating dielectric layer 108 of the device, ensure that the leakage current of the device is small enough when the reverse withstand voltage is low, shield the capacitance from the gate to the drain of the device, and reduce the Maitreya capacitance of the device; the doping concentration of the P-type well region 103 is designed to protect the source of the device and ensure the low driving voltage characteristics of the gate control area of ​​the device; the doping concentration of the P-type base region 104 is to reduce the downward extension of the space charge region formed by the N-type source region 106 of the device and ensure the turn-off characteristics of the device; the doping concentration of the P-type source region 105 is designed to reduce the loss of the parasitic pn junction diode of the device; the doping concentrations of the N-type source region 106 and the P-type source region 105 are designed to reduce the contact resistance of the device, thereby reducing the on-resistance of the device;

[0066] The thickness of the silicon carbide substrate 101 of the device is 1 μm, which is to ensure the support during the device preparation process. The thickness of the drift layer 102 is 50-100 μm, which is adjusted within the above range according to the different requirements for the device's withstand voltage characteristics. The thickness of the device source metal layer 110 is 300 nm, the thickness of the P-type well region 103 is 500 nm, and the width is 1.12 μm. The thickness of the P-type base region 104 is 300 nm and the width is 1.15 μm. The thickness of the P-type source region 105 is 200 nm and the width is 600 nm. The thickness of the N-type source region 106 is 200 nm and the width is 550 nm. The width of the device insulating dielectric layer 108 is 1.2 μm, the width of the gate metal layer 109 is 1.1 μm, the thickness of the gate metal layer 109 is 1.4 μm, and the thickness of the insulating dielectric at the bottom of the gate metal layer 109 is 1. The width of the insulating dielectric on the left and right sides of the gate metal layer 109 is 50nm, the width of the masking layer 107 is 1.2μm, and the thickness is 200nm. The top of the N-type source region 106 and the P-type source region 105 are in direct contact with the source metal layer 110, the top of the P-type base region 104 is in direct contact with the N-type source region 106 and the P-type source region 105, the top of the P-type well region 103 is in direct contact with the top of the P-type base region 104, the P-type source region 105, the P-type base region 104, and the P-type well region 103 are aligned away from the side of the device gate, and the device masking layer 107 is in direct contact with the bottom of the device insulating dielectric layer 108. The width, thickness and relative relationship of the above structure are to construct a low driving voltage structure of the device. Its cooperation with the doping concentration can achieve a low driving voltage of the device under low reverse leakage conditions, thereby improving device performance and reliability.

[0067] The present invention constructs a P-type base region 104 and a P-type well region 103 with a gradually decreasing concentration gradient. The highly doped P-type base region 104 vertically ensures that the space charge region formed with the N-type source region 106 does not affect the diffusion of the lateral space charge region to the device gate, thereby ensuring the device's gate-controlled turn-off characteristics. The P-type base region 104 shields the space charge region of the N-type source region 106. The space charge region formed at the bottom of the low-doped P-type well region 103 ensures the device's gate turn-off characteristics. The P-type base region 104 and the P-type well region 103 with a gradually decreasing concentration gradient can form a structure with a gradually increasing electric field near the N-type source region 106 of the device during reverse withstand voltage, thereby improving the withstand voltage capability of the source region of the device.

[0068] On the left and right sides of the device, an N-type source region 106 and a P-type base region 104 are formed, with a distance of 50nm from the insulating dielectric layer 108. This portion is the drift layer 102. The P-type well region 103 below the P-type base region 104 is 80nm away from the insulating dielectric layer 108, forming a trapezoidal structure with an increased gap. This structure forms a space charge region through the P-type well region 103 and the P-type base region 104 and the drift layer 102 in the gap, achieving shutdown during reverse withstand voltage. The gap structure can reduce the inversion driving voltage, thereby reducing the driving voltage of the device. This structure is intended to reduce the driving charge in the part away from the N-type source region 106 and reduce switching losses.

[0069] In order to ensure the gate reliability of the device, a 200 nm thick masking layer 107 with the same width as the insulating dielectric layer 108 is constructed directly below the insulating dielectric layer 108 of the device to avoid the influence on the gate structure of the device during the reverse withstand voltage of the device.

[0070] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A low drive voltage trench gate silicon carbide VDMOS, characterized by: include Silicon carbide substrate, a drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a protrusion is provided on the drift layer, and a groove is provided in the protrusion; A P-type well region, wherein a lower side surface of the P-type well region is connected to an upper side surface of the drift layer, and an inner side surface of the P-type well region is connected to an outer side surface of the protrusion; A P-type base region, wherein the lower side of the P-type base region is connected to the upper side of the P-type well region, and the inner side of the P-type base region is connected to the outer side of the protrusion; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the P-type base region; An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the P-type base region, the outer side of the N-type source region is connected to the inner side of the P-type source region, and the inner side of the N-type source region is connected to the outer side of the protrusion; a masking layer, the masking layer being disposed in the groove; an insulating dielectric layer, the insulating dielectric layer being disposed in the groove, and the lower side of the insulating dielectric layer being connected to the upper side of the masking layer; the insulating dielectric layer protruding from the groove, and having a groove therein; a gate metal layer, the gate metal layer being disposed in the trench; a source metal layer, the source metal layer being respectively connected to the upper side surface of the protrusion, the upper side surface of the P-type source region, and the upper side surface of the N-type source region; and a drain metal layer connected to the lower side of the silicon carbide substrate; The N-type source region, the highly doped P-type base region and the low-doped P-type well region are not directly connected to the insulating dielectric layer, and a drift layer is interposed in between.

2. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 1, wherein: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a masking layer; Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region; Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type base region; Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type source region; Step 6: remove the barrier layer in step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region; Step 7: remove the barrier layer in step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the N-type source region, deposit metal to form a source metal layer; Step 8: removing the barrier layer in step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the mask layer, and depositing to form an insulating dielectric layer; Step 9: remove the barrier layer of step 8, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a groove, deposit metal to form a gate metal layer, remove the barrier layer, and complete the preparation.

3. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 2, wherein: The distance between the inner side of the P-type well region and the outer side of the insulating dielectric layer is greater than the distance between the inner side of the P-type base region and the outer side of the insulating dielectric layer.

4. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 2, wherein: The lower side surface of the gate metal layer and the lower side surface of the P-type well region are located in the same plane.

5. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 2, wherein: The doping concentration of the P-type base region is greater than the doping concentration of the P-type well region.

6. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 2, wherein: The doping concentration of the P-type well region is greater than the doping concentration of the drift layer.

7. The method for preparing a low driving voltage trench gate silicon carbide VDMOS according to claim 2, wherein: The doping concentration of the P-type source region is greater than the doping concentration of the N-type source region.

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