Radiation-proof gallium nitride transistor and preparation method thereof

Abstract

The invention discloses an anti-radiation gallium nitride transistor and a preparation method, the gallium nitride transistor comprises a substrate, a buffer layer, an intrinsic gallium nitride layer and an intrinsic aluminum gallium nitride layer which are sequentially arranged from bottom to top, and an aluminum oxide tunneling layer, a source electrode and a drain electrode are arranged on the intrinsic aluminum gallium nitride layer in parallel; a ferroelectric material layer, an aluminum oxide insulating layer and a grid electrode are sequentially grown on the aluminum oxide tunneling layer, a silicon nitride insulating layer is deposited on the intrinsic aluminum gallium nitride layer, and the source electrode and the drain electrode respectively penetrate through the silicon nitride insulating layer to form ohmic contact with the intrinsic aluminum gallium nitride layer; each of the source electrode, the drain electrode and the grid electrode comprises a plurality of fingers, the plurality of fingers of the source electrode and the plurality of fingers of the drain electrode are mutually crossed, the plurality of fingers of the grid electrode extend to the source electrode and the drain electrode to form an interdigital structure, and each finger of the grid electrode is positioned between the source electrode and the drain electrode. According to the gallium nitride transistor, the interdigital structure active region is introduced, and the aluminum oxide tunneling layer, the ferroelectric material layer, the aluminum oxide insulating layer and the grid electrode sequentially extend out of the intrinsic aluminum gallium nitride layer, so that the gallium nitride transistor with excellent radiation resistance is formed.

Description

Technical Field

[0001] The present invention relates to an anti - radiation gallium nitride transistor and a preparation method thereof, belonging to the technical field of integrated circuit devices. Background Art

[0002] With the increasing tasks and plans of space exploration, the performance and reliability of space - borne electronic devices have become key factors to ensure the successful implementation of space missions. In the complex space environment, high - energy particle radiation is one of the main risks threatening the normal operation of satellite electronic devices. When high - energy particles penetrate semiconductor devices, they interact with atoms in the semiconductor material, generating electron - hole pairs. These additional charge carriers accumulate inside the semiconductor, which may trigger transient current pulses, leading to the single - event upset (SEU) effect in semiconductor devices, and further causing anomalies or failures in the functions of satellite systems. Historically, satellite failure events caused by the single - event upset effect have been frequent, posing significant challenges to space exploration missions.

[0003] Gallium nitride (GaN) - based high - electron - mobility transistors (HEMTs) have shown great application potential in fields such as microwave power amplification, high - speed communication, and space power management due to their excellent high - speed, high - power - density, and high - efficiency characteristics. Especially in space applications, GaN HEMT devices have gradually become an ideal choice to replace traditional silicon - based devices because of their excellent performance. However, with the wide application of GaN HEMTs in the space field, their anti - radiation ability has become an urgent problem to be solved. Due to the complexity of the space radiation environment, traditional GaN HEMT devices are still likely to experience the single - event upset effect when facing high - energy particle radiation, thus affecting the stability and reliability of the entire satellite system.

[0004] To address this challenge, researchers have been continuously exploring new methods to improve the anti - radiation ability of GaN HEMTs. Traditional anti - radiation strategies, such as increasing the physical thickness of the device or using special packaging materials, can improve the anti - radiation performance of the device to a certain extent, but often at the cost of sacrificing the device's performance or increasing the manufacturing cost. Therefore, it is particularly important to develop a new technology that can both maintain the excellent performance of GaN HEMTs and effectively improve their anti - radiation ability. Summary of the Invention

[0005] To solve the above problems, the present invention provides an anti-radiation gallium nitride transistor and a preparation method thereof, aiming to fundamentally improve its ability to resist single-particle radiation by optimizing the device structure. Based on the gallium nitride-based high electron mobility transistor, the present invention introduces an interdigital structure active region, and sequentially epitaxially grows an aluminum oxide tunneling layer, a ferroelectric material layer, an aluminum oxide insulating layer, and a gate on the intrinsic aluminum gallium nitride layer, finally forming a gallium nitride transistor with excellent anti-radiation performance. This innovative design not only maintains the high-speed, high-power, and high-efficiency characteristics of the gallium nitride HEMT, but also significantly improves its ability to resist space radiation, providing a more reliable choice for future space electronic devices.

[0006] In a first aspect, the present invention provides an anti-radiation gallium nitride transistor, including a substrate, a buffer layer, an intrinsic gallium nitride layer, and an intrinsic aluminum gallium nitride layer sequentially arranged from bottom to top. An aluminum oxide tunneling layer, a source electrode, and a drain electrode are arranged in parallel on the intrinsic aluminum gallium nitride layer. A ferroelectric material layer, an aluminum oxide insulating layer, and a gate are sequentially grown on the aluminum oxide tunneling layer. A silicon nitride insulating layer is deposited on the intrinsic aluminum gallium nitride layer. The source electrode and the drain electrode respectively pass through the silicon nitride insulating layer to form an ohmic contact with the intrinsic aluminum gallium nitride layer. The source electrode, the drain electrode, and the gate all include a plurality of fingers. The plurality of fingers of the source electrode intersect with the plurality of fingers of the drain electrode. The plurality of fingers of the gate extend towards the source electrode and the drain electrode to form an interdigital structure. Each finger of the gate is located between the source electrode and the drain electrode.

[0007] In an embodiment of the present invention, the two-dimensional electron gas generated by the GaN / AlGaN heterojunction is used as the electron source stored in the ferroelectric material layer.

[0008] In an embodiment of the present invention, the thickness of the buffer layer is 2 - 4 μm; the thickness of the intrinsic gallium nitride layer is 1 - 50 μm; the thickness of the intrinsic aluminum gallium nitride layer is 5 - 30 nm; the thickness of the silicon nitride insulating layer is 10 - 800 nm.

[0009] In an embodiment of the present invention, the thickness of the aluminum oxide tunneling layer is 0.8 nm - 3.5 nm; the thickness of the ferroelectric material layer is 1 - 50 nm; the thickness of the aluminum oxide insulating layer is 2 - 50 nm.

[0010] In an embodiment of the present invention, the material of the ferroelectric material layer includes at least one of HfO2-based materials, BFO, BTO, and MoS2.

[0011] In an embodiment of the present invention, the material of the substrate is any one of Si, SiC, and sapphire; the material of the buffer layer is one or a combination of AlN, GaN, AlGaN, and InGaN.

[0012] In one embodiment of the present invention, the source electrode, drain electrode, and gate electrode are at least one of Ti, Al, Ni, and Au.

[0013] Second, the present invention provides a method for preparing an anti-irradiation gallium nitride transistor, comprising the following steps:

[0014] S101. Using metal-organic chemical vapor deposition, grow a buffer layer, an intrinsic gallium nitride layer, and an intrinsic aluminum gallium nitride layer on a substrate;

[0015] S102. Using magnetron sputtering, prepare a source electrode and a drain electrode on the intrinsic aluminum gallium nitride layer;

[0016] S103. Using atomic layer deposition, sequentially epitaxially grow an aluminum oxide tunneling layer, a ferroelectric material layer, and an aluminum oxide insulating layer on the intrinsic aluminum gallium nitride layer;

[0017] S104. Using dry etching or wet etching, remove the aluminum oxide and ferroelectric material below the gate electrode;

[0018] S105. Using magnetron sputtering, prepare a gate electrode on the aluminum oxide insulating layer;

[0019] S106. Using plasma enhanced chemical vapor deposition, deposit a silicon nitride insulating layer on the intrinsic aluminum gallium nitride layer;

[0020] S107. Using dry etching or wet etching, remove part of the silicon oxide above the gate electrode, source electrode, and drain electrode;

[0021] S108. Using magnetron sputtering, prepare metal PADs for the gate electrode, source electrode, and drain electrode.

[0022] In one embodiment of the present invention, in step S101, a buffer layer with a thickness of 2 - 4 μm, an intrinsic gallium nitride layer with a thickness of 5 μm, and an intrinsic aluminum gallium nitride layer with a thickness of 20 nm are grown on the substrate; wherein, the flow rate of trimethylgallium is 20 - 25 μmol / min, the flow rate of ammonia gas is 3.5 slm, the temperature is 1050 °C - 1070 °C, and the pressure is 100 Mbar; the flow rate of trimethylaluminum is 3 - 4 μmol / min; the material of the substrate is aluminum nitride grown in a magnetron sputtering device;

[0023] In step S102, the drain electrode and the source electrode form an ohmic contact with the intrinsic aluminum gallium nitride layer;

[0024] In step S104 and step S107, dry etching is performed using Cl2 or BCl3 and doped with O2 or SF6;

[0025] Steps S102, S103, and S105 further include annealing the device at a temperature of 800 - 900 °C.

[0026] In a third aspect, the present invention provides a method for a radiation - resistant gallium nitride transistor to resist single - event effects, including the following steps:

[0027] S601. When a positive voltage is applied to the gate, electrons flow from the source to the drain and are attracted by the positive voltage to pass through the aluminum oxide tunneling layer under the gate and be stored in the ferroelectric material layer.

[0028] S602. Due to the thin aluminum oxide tunneling layer, electrons are easily tunneled into the intrinsic aluminum gallium nitride layer.

[0029] S603. When high - energy particles pass through the crystal, a large number of electron - hole pairs are generated inside the transistor. The electrons are drawn out from the drain under the influence of the electric field, and part of the remaining holes are drawn out from the source, and part are accumulated under the gate.

[0030] S604. The hole pairs accumulated under the gate recombine with the tunneling electrons, avoiding damage to the device function caused by excess charge carriers and improving the radiation - resistant performance of the device.

[0031] The beneficial effects of the present invention are as follows:

[0032] 1. A radiation - resistant gallium nitride transistor provided by the present invention is based on a gallium nitride - based high - electron - mobility transistor. An aluminum oxide tunneling layer, a ferroelectric material layer, an aluminum oxide insulating layer, and a gate are epitaxially grown on the intrinsic aluminum gallium nitride layer in sequence to form a radiation - resistant gallium nitride transistor, and an active region with an interdigital structure is adopted, having the advantage of high electron mobility.

[0033] 2. A preparation method of a radiation - resistant gallium nitride transistor provided by the present invention uses metal - organic chemical vapor deposition (MOCVD) to grow an intrinsic aluminum gallium nitride layer and an intrinsic gallium nitride layer. The aluminum component in the intrinsic aluminum gallium nitride layer can be adjusted by adjusting the ratio of trimethyl gallium, trimethyl aluminum, and ammonia, thereby adjusting the concentration of the two - dimensional electron gas. At the same time, the MOCVD - prepared abrupt heterojunction has a good interface steepness, and the prepared transistor has high stability and is more suitable for extreme environments such as space.

[0034] 3. A method for a radiation - resistant gallium nitride transistor provided by the present invention to resist single - event effects can improve the phenomenon that electron - hole pairs are generated due to single - event upsets, thereby causing device performance degradation, and can significantly improve the radiation - resistant ability of gallium nitride transistors. Description of the Drawings

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of the device after the end of step S101 in Embodiment 2.

[0037] Figure 2 It is a schematic structural diagram of the device after the end of step S102 in Embodiment 2.

[0038] Figure 3 It is a schematic structural diagram of the device after the end of step S105 in Embodiment 2.

[0039] Figure 4 It is a schematic structural diagram of an anti-irradiation gallium nitride transistor provided by the present invention.

[0040] Figure 5 It is a comparison diagram of the transfer characteristics of devices with different tunneling layer thicknesses before and after irradiation.

[0041] In the figure: 1. Substrate; 2. Intrinsic gallium nitride layer; 3. Intrinsic aluminum gallium nitride layer; 4. Aluminum oxide tunneling layer; 5. Source electrode; 6. Drain electrode; 7. Ferroelectric material layer; 8. Aluminum oxide insulating layer; 9. Gate electrode; 10. Silicon nitride insulating layer; 11. Buffer layer. Specific Embodiments

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe the embodiments of the present invention in detail with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0043] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0045] Embodiment 1

[0046] This embodiment provides an anti-radiation gallium nitride transistor, which includes a substrate 1, a buffer layer 11, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 arranged in sequence from bottom to top. An alumina tunneling layer 4, a source electrode 5, and a drain electrode 6 are arranged in parallel on the intrinsic aluminum gallium nitride layer 3. A ferroelectric material layer 7, an alumina insulating layer 8, and a gate electrode 9 are grown in sequence on the alumina tunneling layer 4. A silicon nitride insulating layer 10 is deposited on the intrinsic aluminum gallium nitride layer 3. The source electrode 5 and the drain electrode 6 respectively pass through the silicon nitride insulating layer 10 to form ohmic contacts with the intrinsic aluminum gallium nitride layer 3; the source electrode 5, the drain electrode 6, and the gate electrode 9 all include a plurality of fingers. The plurality of fingers of the source electrode 5 intersect with the plurality of fingers of the drain electrode 6. The plurality of fingers of the gate electrode 9 extend towards the source electrode 5 and the drain electrode 6 to form an interdigital structure. Each finger of the gate electrode 9 is located between the source electrode 5 and the drain electrode 6.

[0047] In this embodiment, the active region adopts an interdigital structure, and the two-dimensional electron gas generated by the GaN / AlGaN heterojunction is used as the electron source stored in the ferroelectric material layer 7.

[0048] Optionally, the thickness of the buffer layer 11 is 2 - 4 μm; the thickness of the intrinsic aluminum gallium nitride layer 3 is 5 - 30 nm; the thickness of the silicon nitride insulating layer 10 is 10 - 800 nm.

[0049] Optionally, the thickness of the alumina tunneling layer 4 is 0.8 nm - 3.5 nm; the thickness of the ferroelectric material layer 7 is 1 - 50 nm; the thickness of the alumina insulating layer 8 is 2 - 50 nm.

[0050] Optionally, the material of the ferroelectric material layer 7 includes at least one of HfO2-based materials, BFO (bismuth ferrite), BTO (blue tungsten oxide), and MoS2 (molybdenum disulfide).

[0051] Optionally, the material of the substrate 1 is any one of Si, SiC, and sapphire.

[0052] Optionally, the material of the buffer layer 11 is one or a combination of AlN, GaN, AlGaN, and InGaN.

[0053] Optionally, the source electrode 5, the drain electrode 6, and the gate electrode 9 are at least one of Ti, Al, Ni, and Au.

[0054] Embodiment 2

[0055] This embodiment provides a method for preparing the anti-radiation gallium nitride transistor described in Embodiment 1, including the following steps:

[0056] S101. Using metal organic chemical vapor deposition, grow a buffer layer 11, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 on the substrate 1;

[0057] S102. Using magnetron sputtering, prepare the source electrode 5 and the drain electrode 6 on the intrinsic aluminum gallium nitride layer 3;

[0058] S103. Using atomic layer deposition, sequentially epitaxially grow an aluminum oxide tunneling layer 4, a ferroelectric material layer 7, and an aluminum oxide insulating layer 8 on the intrinsic aluminum gallium nitride layer 3;

[0059] S104. Using dry etching or wet etching, remove the aluminum oxide and ferroelectric material other than under the gate electrode;

[0060] S105. Using magnetron sputtering, prepare the gate electrode 9 on the aluminum oxide insulating layer 8;

[0061] S106. Using plasma enhanced chemical vapor deposition, deposit a silicon nitride insulating layer 10 on the intrinsic aluminum gallium nitride layer 3;

[0062] S107. Using dry etching or wet etching, remove part of the silicon nitride above the gate electrode 9, the source electrode 5, and the drain electrode 6;

[0063] S108. Using magnetron sputtering, prepare metal PADs (pin pads) for the gate electrode 9, the source electrode 5, and the drain electrode 6.

[0064] Optionally, in step S101, grow a buffer layer with a thickness of 2 - 4 μm, an intrinsic gallium nitride layer 2 with a thickness of 5 μm, and an intrinsic aluminum gallium nitride layer 3 with a thickness of 20 nm on the substrate 1; wherein, in the growth of aluminum gallium nitride, the flow rate of trimethyl gallium is 20 - 25 μmol / min, the flow rate of ammonia gas is 3.5 slm, the temperature is 1050 °C - 1070 °C, and the pressure is 100 Mbar; the flow rate of trimethyl aluminum is 3 - 4 μmol / min.

[0065] In this embodiment, the metalorganic chemical vapor deposition (MOCVD) method is used to grow the intrinsic gallium nitride layer 2 and the intrinsic aluminum gallium nitride layer 3. The aluminum component in the intrinsic aluminum gallium nitride layer 3 can be adjusted by adjusting the ratios of trimethyl gallium, trimethyl aluminum, and ammonia, thereby adjusting the concentration of the two-dimensional electron gas. At the same time, the abrupt heterojunction prepared by MOCVD has a good interface steepness, and the prepared transistor has high stability and is more suitable for extreme environments such as space.

[0066] Optionally, in step S104 and step S107, dry etching is performed using Cl2 or BCl3, and O2 or SF6 is incorporated.

[0067] Optionally, in step S102 and step S103, the temperature for annealing the device is 850 °C.

[0068] Embodiment 3

[0069] This embodiment provides a method for preparing the radiation-resistant gallium nitride transistor described in Embodiment 1, including the following steps:

[0070] S201. Using the metalorganic chemical vapor deposition method, a buffer layer 11, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 are grown on a substrate 1;

[0071] Among them, the material of the substrate 1 is aluminum nitride grown in a magnetron sputtering device; the growth temperature of the intrinsic gallium nitride layer 2 is 900 °C, and the thickness is 2 μm; the growth temperature of the intrinsic aluminum gallium nitride layer 3 is 950 °C, and the thickness is 25 nm;

[0072] S202. Using the magnetron sputtering method, a source electrode 5 and a drain electrode 6 are deposited on the intrinsic aluminum gallium nitride layer 3, and the device is subjected to high-temperature annealing, and the drain electrode 6 and the source electrode 5 form an ohmic contact with the intrinsic aluminum gallium nitride layer 3;

[0073] In this embodiment, Ti / Al / Ni / Au (20 nm / 160 nm / 55 nm / 90 nm) is deposited in the corresponding area on the intrinsic aluminum gallium nitride layer 3, and rapid annealing is performed at 850 °C in nitrogen for 1 min to form an ohmic contact, obtaining the source electrode 5 and the drain electrode 6;

[0074] S203. Using the atomic deposition method, an aluminum oxide tunneling layer 4 (0.5 nm), a ferroelectric material layer 7 (30 nm), and an aluminum oxide insulating layer 8 (30 nm) are sequentially epitaxially grown on the intrinsic aluminum gallium nitride layer 3, and the device is annealed;

[0075] In this embodiment, the heating system of the atomic deposition equipment heats the substrate to 300 °C, and the device is rapidly annealed at 850 °C in nitrogen for 1 min;

[0076] S204. Using the dry etching method, the aluminum oxide and the ferroelectric material under non-gate regions are removed;

[0077] In this embodiment, dry etching is performed using Cl2 doped with SF6.

[0078] S205. Prepare a gate 9 on the alumina insulating layer 8 by magnetron sputtering, and perform high-temperature annealing on the device.

[0079] In this embodiment, Ni / Au (55 nm / 45 nm) is deposited in the correspondingly etched area to obtain the gate 9.

[0080] S206. Deposit a silicon nitride insulating layer 10 on the intrinsic aluminum gallium nitride layer 3 by plasma-enhanced chemical vapor deposition.

[0081] In this embodiment, the heating system of the plasma-enhanced chemical vapor deposition equipment heats the substrate to 300 °C.

[0082] S207. Use dry etching to remove the silicon oxide above part of the gate 9, source electrode 5, and drain electrode 6.

[0083] In this embodiment, dry etching is performed using Cl2 doped with SF6.

[0084] S208. Prepare metal PADs (pin pads) for the gate 9, source electrode 5, and drain electrode 6 by magnetron sputtering.

[0085] In this embodiment, Ni / Au (50 nm / 100 nm) is deposited in the correspondingly etched area to obtain the metal PADs for the gate 9, source electrode 5, and drain electrode 6.

[0086] Example 4

[0087] This embodiment provides a method for preparing the radiation-resistant gallium nitride transistor described in Example 1, including the following steps:

[0088] S301. Use organic chemical vapor deposition to grow a buffer layer 11, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 on a substrate 1.

[0089] Among them, the material of the substrate 1 is aluminum nitride grown in a magnetron sputtering device; the growth temperature of the intrinsic gallium nitride layer 2 is 900 °C, and the thickness is 2 μm; the growth temperature of the intrinsic aluminum gallium nitride layer 3 is 950 °C, and the thickness is 25 nm.

[0090] S302. Use magnetron sputtering to deposit a source electrode 5 and a drain electrode 6 on the intrinsic aluminum gallium nitride layer 3, and perform high-temperature annealing on the device. The drain electrode 6 and the source electrode 5 form an ohmic contact with the intrinsic aluminum gallium nitride layer 3.

[0091] In this embodiment, Ti / Al / Ni / Au (20 nm / 160 nm / 55 nm / 90 nm) is deposited on the corresponding region of the intrinsic aluminum gallium nitride layer 3, and rapid annealing is performed at 850 °C for 1 minute in nitrogen to form an ohmic contact, obtaining the source electrode 5 and the drain electrode 6;

[0092] S303. Use atomic deposition method to epitaxially grow an aluminum oxide tunneling layer 4 (2 nm), a ferroelectric material layer 7 (30 nm), and an aluminum oxide insulating layer 8 (30 nm) on the intrinsic aluminum gallium nitride layer 3 in sequence, and anneal the device;

[0093] In this embodiment, the heating system of the atomic deposition equipment heats the substrate to 300 °C, and rapid annealing is performed on the device at 850 °C for 1 minute in nitrogen;

[0094] S304. Use dry etching method to remove the aluminum oxide and ferroelectric material below the non-gate;

[0095] In this embodiment, Cl2 doped with SF6 is used for dry etching.

[0096] S305. Use magnetron sputtering method to prepare the gate 9 on the aluminum oxide insulating layer 8, and perform high-temperature annealing on the device;

[0097] In this embodiment, Ni / Au (55 nm / 45 nm) is deposited in the corresponding etched region to obtain the gate 9;

[0098] S306. Use plasma-enhanced chemical vapor deposition method to deposit a silicon nitride insulating layer 10 on the intrinsic aluminum gallium nitride layer 3;

[0099] In this embodiment, the heating system of the plasma-enhanced chemical vapor deposition equipment heats the substrate to 300 °C.

[0100] S307. Use dry etching method to remove part of the silicon oxide above the gate 9, the source electrode 5, and the drain electrode 6;

[0101] In this embodiment, Cl2 doped with SF6 is used for dry etching.

[0102] S308. Use magnetron sputtering method to prepare the metal PAD (pin pad) of the gate 9, the source electrode 5, and the drain electrode 6.

[0103] In this embodiment, Ni / Au (50 nm / 100 nm) is deposited in the corresponding etched region to obtain the metal PAD of the gate 9, the source electrode 5, and the drain electrode 6.

[0104] Embodiment 5

[0105] This embodiment provides a preparation method of the radiation-resistant gallium nitride transistor described in Embodiment 1, including the following steps:

[0106] S401. Use the organic chemical vapor deposition method to grow a buffer layer 11, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 on the substrate 1;

[0107] Among them, the material of the substrate 1 is aluminum nitride grown in a magnetron sputtering device; the growth temperature of the intrinsic gallium nitride layer 2 is 900 °C, and the thickness is 2 μm; the growth temperature of the intrinsic aluminum gallium nitride layer 3 is 950 °C, and the thickness is 25 nm;

[0108] S402. Use the magnetron sputtering method to deposit a source electrode 5 and a drain electrode 6 on the intrinsic aluminum gallium nitride layer 3, and perform high-temperature annealing on the device. The drain electrode 6 and the source electrode 5 form an ohmic contact with the intrinsic aluminum gallium nitride layer 3;

[0109] In this embodiment, Ti / Al / Ni / Au (20 nm / 160 nm / 55 nm / 90 nm) is deposited in the corresponding area on the intrinsic aluminum gallium nitride layer 3, and rapid annealing is performed at 850 °C in nitrogen for 1 min to form an ohmic contact, obtaining the source electrode 5 and the drain electrode 6;

[0110] S403. Use the atomic deposition method to epitaxially grow an aluminum oxide tunneling layer 4 (8 nm), a ferroelectric material layer 7 (30 nm), and an aluminum oxide insulating layer 8 (30 nm) on the intrinsic aluminum gallium nitride layer 3 in sequence, and perform annealing on the device;

[0111] In this embodiment, the heating system of the atomic deposition equipment heats the substrate to 300 °C, and performs rapid annealing on the device at 850 °C in nitrogen for 1 min;

[0112] S404. Use the dry etching method to remove the aluminum oxide and ferroelectric material under non-gate areas;

[0113] In this embodiment, Cl2 doped with SF6 is used for dry etching.

[0114] S405. Use the magnetron sputtering method to prepare a gate 9 on the aluminum oxide insulating layer 8, and perform high-temperature annealing on the device;

[0115] In this embodiment, Ni / Au (55 nm / 45 nm) is deposited in the corresponding etched area to obtain the gate 9;

[0116] S406. Use the plasma-enhanced chemical vapor deposition method to deposit a silicon nitride insulating layer 10 on the intrinsic aluminum gallium nitride layer 3;

[0117] In this embodiment, the heating system of the plasma-enhanced chemical vapor deposition equipment heats the substrate to 300 °C.

[0118] S407. Use the dry etching method to remove part of the silicon oxide above the gate 9, the source electrode 5, and the drain electrode 6;

[0119] In this embodiment, dry etching is performed by incorporating Cl2 into SF6.

[0120] S408. Prepare the metal PADs (pin pads) of the gate 9, source 5, and drain 6 by magnetron sputtering.

[0121] In this embodiment, Ni / Au (50 nm / 100 nm) is deposited in the corresponding etched area to obtain the metal PADs of the gate 9, source 5, and drain 6.

[0122] Irradiation tests are performed on the devices fabricated in the above Embodiment 3, Embodiment 4, and Embodiment 5. The test results before and after irradiation are as Figure 5 . The results show that irradiation will cause a negative shift in the threshold voltage of the device, an increase in the off-state current, and the thickness of the aluminum oxide tunneling layer 4 has an impact on the radiation resistance performance of the device. Therefore, the thickness of the aluminum oxide tunneling layer 4 should be appropriate. Too thick will make it difficult for electrons to tunnel, and too thin will make it difficult for electrons to be stored. Select an appropriate thickness of the aluminum oxide tunneling layer 4 according to different device processes to optimize the radiation resistance performance of the device. According to the experimental results, the thickness of the aluminum oxide tunneling layer 4 can reach the optimum at 0.8 nm - 3.5 nm.

[0123] Embodiment 6

[0124] This embodiment provides a method for the anti-radiation gallium nitride transistor described in Embodiment 1 to resist single-event effects, including the following steps:

[0125] S601. When a positive voltage is applied to the gate 9, electrons flow from the source 5 to the drain 6 and are attracted by the positive voltage to pass through the aluminum oxide tunneling layer 4 under the gate 9 and be stored in the ferroelectric material layer 7.

[0126] In this embodiment, the source 5 is grounded and the voltage of the drain 6 is set to 5V.

[0127] S602. Due to the thin aluminum oxide tunneling layer 4, electrons are easy to tunnel into the intrinsic aluminum gallium nitride layer 3.

[0128] S603. When high-energy particles pass through the crystal, a large number of electron-hole pairs are generated inside the transistor. The electrons are drawn out from the drain 6 under the influence of the electric field, and part of the remaining holes are drawn out from the source 5 and part are gathered under the gate 9.

[0129] S604. The hole pairs gathered under the gate 9 recombine with the tunneling electrons to avoid damage to the device function caused by excess charge carriers, thereby improving the radiation resistance performance of the device.

[0130] In summary, the present invention provides an anti-irradiation gallium nitride transistor and a preparation method thereof. By optimizing the device structure, the ability to resist single-particle radiation is fundamentally improved. The present invention is based on a gallium nitride-based high electron mobility transistor. By introducing an interdigital structure active region and epitaxially growing an aluminum oxide tunneling layer, a ferroelectric material layer, an aluminum oxide insulating layer, and a gate on the intrinsic aluminum gallium nitride layer in sequence, a gallium nitride transistor with excellent anti-irradiation performance is finally formed, which can improve the phenomenon that electron-hole pairs are generated due to single-particle flipping, thereby causing device performance degradation, and can significantly improve the anti-irradiation ability of the gallium nitride transistor.

[0131] Specific embodiments are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Therefore, the protection scope of this invention patent shall be subject to the appended claims.

Claims

1. An anti-radiation gallium nitride transistor, characterized in that, It includes a substrate (1), a buffer layer (11), an intrinsic gallium nitride layer (2), and an intrinsic aluminum gallium nitride layer (3) arranged successively from bottom to top. An alumina tunneling layer (4), a source electrode (5), and a drain electrode (6) are arranged in parallel on the intrinsic aluminum gallium nitride layer (3). A ferroelectric material layer (7), an alumina insulating layer (8), and a gate electrode (9) are successively grown on the alumina tunneling layer (4). A silicon nitride insulating layer (10) is deposited on the intrinsic aluminum gallium nitride layer (3). The source electrode (5) and the drain electrode (6) respectively form ohmic contacts with the intrinsic aluminum gallium nitride layer (3) through the silicon nitride insulating layer (10). The source electrode (5), the drain electrode (6), and the gate electrode (9) all include a plurality of fingers. The plurality of fingers of the source electrode (5) and the plurality of fingers of the drain electrode (6) cross each other. The plurality of fingers of the gate electrode (9) extend towards the source electrode (5) and the drain electrode (6) to form an interdigital structure, and each finger of the gate electrode (9) is located between the source electrode (5) and the drain electrode (6).

2. The anti-radiation gallium nitride transistor according to claim 1, wherein The two-dimensional electron gas generated by the GaN / AlGaN heterojunction is used as the electron source stored in the ferroelectric material layer (7).

3. The anti-radiation gallium nitride transistor according to claim 1, wherein The thickness of the buffer layer (11) is 2 - 4 μm; the thickness of the intrinsic gallium nitride layer (2) is 1 - 50 μm; the thickness of the intrinsic aluminum gallium nitride layer (3) is 5 - 30 nm; the thickness of the silicon nitride insulating layer (10) is 10 - 800 nm.

4. The anti-radiation gallium nitride transistor according to claim 1, characterized in that The thickness of the alumina tunneling layer (4) is 0.8 nm - 3.5 nm; the thickness of the ferroelectric material layer (7) is 1 - 50 nm; the thickness of the alumina insulating layer (8) is 2 - 50 nm.

5. The anti-radiation gallium nitride transistor according to claim 1, characterized in that, The material of the ferroelectric material layer (7) includes at least one of HfO2 - based materials, BFO, BTO, and MoS2.

6. The anti-radiation gallium nitride transistor according to claim 1, wherein The material of the substrate (1) is any one of Si, SiC, and sapphire; the material of the buffer layer (11) is one or a combination of AlN, GaN, AlGaN, and InGaN.

7. The anti-radiation gallium nitride transistor according to claim 1, wherein The source electrode (5), the drain electrode (6), and the gate electrode (9) are made of at least one of Ti, Al, Ni, and Au.

8. A method for preparing an anti-radiation gallium nitride transistor according to any one of claims 1-7, characterized in that, It includes the following steps: S101: Using metal - organic chemical vapor deposition, grow the buffer layer (11), the intrinsic gallium nitride layer (2), and the intrinsic aluminum gallium nitride layer (3) on the substrate (1). S102: Using magnetron sputtering, prepare the source electrode (5) and the drain electrode (6) on the intrinsic aluminum gallium nitride layer (3). S103: Using atomic layer deposition, epitaxially grow the alumina tunneling layer (4), the ferroelectric material layer (7), and the alumina insulating layer (8) on the intrinsic aluminum gallium nitride layer (3) in sequence. S104: Using dry etching or wet etching methods, remove the alumina and ferroelectric material below the non - gate area. S105: Using magnetron sputtering, prepare the gate electrode (9) on the alumina insulating layer (8). S106: Using plasma - enhanced chemical vapor deposition, deposit the silicon nitride insulating layer (10) on the intrinsic aluminum gallium nitride layer (3). S107: Using dry etching or wet etching methods, remove the silicon oxide above part of the gate electrode (9), the source electrode (5), and the drain electrode (6). S108. Prepare the metal PADs of the gate (9), source (5), and drain (6) by magnetron sputtering method.

9. The preparation method of an anti-irradiation gallium nitride transistor according to claim 8, characterized in that in the step S101, a buffer layer (11) with a thickness of 2 - 4 μm, an intrinsic gallium nitride layer (2) with a thickness of 5 μm, and an intrinsic aluminum gallium nitride layer (3) with a thickness of 20 nm are grown on the substrate (1); wherein, the flow rate of trimethylgallium is 20 - 25 μmol / min, the flow rate of ammonia is 3.5 slm, the temperature is 1050 °C - 1070 °C, and the pressure is 100 Mbar; the flow rate of trimethylaluminum is 3 - 4 μmol / min; the material of the substrate (1) is aluminum nitride grown in a magnetron sputtering device; in the step S102, the drain (6) and the source (5) form an ohmic contact with the intrinsic aluminum gallium nitride layer (3); in the steps S104 and S107, dry etching is performed using Cl2 or BCl3, and O2 or SF6 is incorporated; the steps S102, S103, and S105 further include annealing the device, and the annealing temperature of the device is 800 - 900 °C.

10. A method for resisting single event effects of an anti-irradiation gallium nitride transistor according to any one of claims 1-7, characterized in that, Comprising the following steps: S601. When a positive voltage is applied to the gate (9), electrons flow from the source (5) to the drain (6), and are attracted by the positive voltage to pass through the aluminum oxide tunneling layer (4) under the gate (9) and are stored in the ferroelectric material layer (7); S602. Due to the thinness of the aluminum oxide tunneling layer (4), electrons are easily tunneled into the intrinsic aluminum gallium nitride layer (3); S603. When high-energy particles pass through the crystal, a large number of electron-hole pairs are generated inside the transistor. The electrons are drawn out from the drain (6) under the influence of the electric field, and part of the remaining holes are drawn out from the source (5), and part of them are accumulated under the gate (9); S604. The hole pairs accumulated under the gate (9) recombine with the tunneling electrons, avoiding damage to the device function caused by excessive charge carriers and improving the anti-irradiation performance of the device.

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