Semiconductor device, electronic equipment and preparation method of semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, electronic equipment and a preparation method of the semiconductor device, and relates to the technical field of semiconductors. The semiconductor device comprises a substrate, a fin structure and a grid electrode. Wherein the fin structure is arranged on the substrate, the fin structure comprises conductive parts and channel parts, the conductive parts and the channel parts are alternately arranged in the first direction, and each channel part comprises multiple channel layers which are stacked in the direction away from the substrate and are arranged at intervals. The grid electrode is arranged on the surface of each channel layer in the multiple channel layers in a surrounding mode. Wherein the sizes of at least two channel layers in the multiple channel layers are different in the first direction; the first direction is parallel to the substrate. According to the semiconductor device, the purpose of electrical uniformity at different positions of the fin structure can be achieved through simple structure arrangement, and the reliability of the semiconductor device is effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device. Background Art

[0002] In advanced process technologies, fin field-effect transistors (FinFETs) are mostly used for the transistors of integrated circuits. However, as the process precision reaches below 5 nm, fin field-effect transistors will also face problems such as increased electrostatic coupling and parasitic capacitance, and increased off-state leakage.

[0003] Currently, a new transistor architecture, namely the gate all-around field-effect transistor (GAA FET), has been introduced in the field. The GAA FET is a non-planar transistor. Compared with a planar transistor of the same area, it has a larger effective width (Weff), a higher channel density and performance, and a larger drive-switching current per unit area of the transistor. Moreover, the gate of the GAA FET is arranged to surround its multi-layer channel layers (such as nanowires / nanosheets), which can strengthen the control of the current in the channel layer, is conducive to the depletion of majority carriers in the channel layer, reduces the short-channel effect, and thus improves the response speed of the transistor.

[0004] However, due to reasons such as process errors, there are differences between different channel layers. For example, the doping concentrations may be different, which leads to the problem of non-uniform electrical properties at different positions of the GAA FET, greatly reducing the reliability of the device. Summary of the Invention

[0005] Embodiments of this application provide a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device, aiming to achieve the purpose of uniform electrical properties at different positions of the GAA FET through a simple structural design, and effectively improve the reliability of the semiconductor device.

[0006] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a fin structure, and a gate.

[0008] Among them, the fin structure is disposed on the substrate. The fin structure includes a conductive portion and a channel portion alternately arranged in a first direction. The channel portion includes multiple channel layers, and the multiple channel layers are stacked and spaced apart in a direction away from the substrate. The gate is disposed around the surface of each channel layer in the multiple channel layers. Among them, at least two of the multiple channel layers have different dimensions in the first direction; the first direction is parallel to the substrate.

[0009] In the semiconductor device provided by the embodiment of the present application, by setting that at least two of the multiple channel layers have different dimensions (i.e., lengths) in the first direction, the electrical properties corresponding to the multiple channel layers are relatively uniform. That is, by controlling the length of the channel layer, the regulation of the electrical properties of the channel layer is realized. For example, the length of the channel layer corresponding to a smaller saturation current in the multiple channel layers is set to be smaller, so that the saturation currents corresponding to the multiple channel layers approach consistency, thereby optimizing the uniformity of the electrical properties of the semiconductor device and improving the reliability of the semiconductor device, which is beneficial to the continuous development of the technology node.

[0010] Compared with the technical means of regulating electrical properties by doping concentration in the related art, the regulation of electrical properties by the length of the channel layer in the embodiment of the present application is relatively simple. The change in the length of the channel layer can be realized only by controlling the etching position, and the degree of refinement is relatively high, the error is small, and the effect of realizing the uniformity of the electrical properties of the semiconductor device is good.

[0011] The embodiment of the present application adds a regulation means (i.e., length regulation) for the regulation of the electrical properties of the semiconductor device. The means of regulating the electrical properties of the device by the length of the channel layer can be combined with the means of regulating the electrical properties of the device by the doping concentration of the channel layer, so that the uniformity of the electrical properties of the semiconductor device can be regulated from multiple dimensions, further optimizing the regulation effect of the uniformity of the electrical properties of the semiconductor device, and further improving the reliability of the semiconductor device.

[0012] In addition, in the embodiment of the present application, by designing the lengths of the channel layers differently, the stress received by the entire multiple channel layers can be dispersed, avoiding the situation that the channel layer bends under the action of stress due to the relatively concentrated stress when the lengths of the multiple channel layers are exactly the same, and improving the structural stability of the semiconductor device.

[0013] In a possible implementation manner of the first aspect, the saturation currents corresponding to two channel layers with different dimensions in the first direction are the same. Thereby ensuring that the electrical properties of the semiconductor device at different positions where the channel layers are located are approximately the same, thereby improving the reliability of the semiconductor device.

[0014] In a possible implementation of the first aspect, among the multiple channel layers, the channel layer with a lower doping concentration has a smaller size in the first direction. That is, the length of the channel layer can be set according to the magnitude of the doping concentration of the channel layer. For example, after detecting the variation law of the doping concentration of the channel layer, the length of the channel layer can be adaptively and regularly set to compensate for the electrical difference caused by the doping concentration difference.

[0015] In a possible implementation of the first aspect, the aspect ratios of two channel layers with different sizes in the first direction are the same; the aspect ratio is the ratio of the size of the channel layer in the second direction to the size in the first direction; the second direction is parallel to the substrate and perpendicular to the first direction. That is, by controlling the size of the length of the channel layer, the aspect ratios of different channel layers can be made the same, so that the saturation currents corresponding to different channel layers are the same, improving the electrical performance uniformity of the semiconductor device at different positions, and thus optimizing the reliability of the semiconductor device.

[0016] In a possible implementation of the first aspect, among the multiple channel layers, the channel layer with a smaller size in the second direction also has a smaller size in the first direction. Thereby, the multiple channel layers can maintain a substantially the same aspect ratio, making the saturation currents corresponding to different channel layers the same, improving the electrical performance uniformity of the semiconductor device at different positions, and thus optimizing the reliability of the semiconductor device.

[0017] In a possible implementation of the first aspect, along the direction away from the substrate, both the size of the multiple channel layers in the second direction and the size in the first direction gradually decrease. It is possible to avoid the problem of difficult etching of the fin structure due to a high aspect ratio while meeting the electrical performance uniformity of the semiconductor device, reducing the manufacturing difficulty of the semiconductor device.

[0018] In a possible implementation of the first aspect, the two opposite side surfaces of the channel portion in the first direction are inclined, and in the same side, the side surfaces of different channel layers are located in the same plane. Thus, during the etching preparation process, it is possible to achieve the purpose of gradually reducing the length of the multiple channel layers along the direction away from the substrate by only performing one etching cut with an inclined angle.

[0019] In a possible implementation of the first aspect, the two opposite side surfaces of the channel portion in the first direction are arranged in a stepped manner.

[0020] In a possible implementation of the first aspect, along the direction away from the substrate, the size of the conductive portion in the first direction gradually increases.

[0021] By setting the length of the conductive portion to gradually increase in the direction away from the substrate, on the one hand, the conductive portion can adapt to the trend that the length of the multi-layer channel layer gradually decreases, so that it is convenient for the conductive portion (source and / or drain) to always be in contact with the channel layer, ensuring the smooth opening and closing of the semiconductor device. On the other hand, the length of the end portion of the conductive portion away from the substrate is relatively large, resulting in a relatively large area at its top. Therefore, when a contact structure is provided on the top of the conductive portion, the process window is relatively large, thereby reducing the preparation difficulty of the contact structure and improving the electrical connection performance between the conductive portion and the contact structure.

[0022] In a possible implementation manner of the first aspect, the sizes of at least two portions of the gate in the first direction are different, and the larger the size of the channel layer in the first direction, the larger the size of the corresponding portion of the gate surrounding the channel layer in the first direction.

[0023] That is, the size of the gate in the first direction changes with the change of the size of the channel layer it surrounds in the first direction, so that the gate can completely surround the channel layer, ensuring the control of the channel in the channel layer while avoiding the problems that the preparation difficulty of the conductive portion increases due to the too large size of the gate in the first direction, or the channel transmission efficiency decreases due to the too large distance between the conductive portion and the channel layer.

[0024] In a possible implementation manner of the first aspect, along the direction away from the substrate, the size of the multi-layer channel layer in the first direction gradually decreases, and the two opposite side surfaces of the multi-layer channel layer in the first direction are arranged in a stepped manner. The two opposite side surfaces of the gate in the first direction are arranged in a stepped manner, and the stepped side surfaces of the gate match the shape of the stepped side surfaces of the multi-layer channel layer.

[0025] In a possible implementation manner of the first aspect, the semiconductor device further includes a sidewall layer, and the sidewall layer is disposed on the two opposite side surfaces of the gate in the first direction. Among them, when the two opposite side surfaces of the gate in the first direction are arranged in a stepped manner, the surface of the sidewall layer is arranged in a stepped manner, and the stepped surface of the sidewall layer matches the shape of the stepped side surfaces of the gate.

[0026] In the second aspect, a method for manufacturing a semiconductor device is provided, and the manufacturing method includes:

[0027] A fin structure is formed on a substrate; the fin structure includes a sacrificial layer and a channel layer alternately stacked in a direction away from the substrate. A dummy gate is formed; the dummy gate straddles the fin structure, and at least two portions of the dummy gate arranged in a direction away from the substrate have different dimensions in a first direction; the first direction is parallel to the substrate; the portion of the fin structure covered by the dummy gate is a channel portion, and the channel portion includes multiple layers of channel layers, and the channel layer is a portion of the semiconductor layer covered by the dummy gate; among the multiple layers of channel layers, at least two layers of channel layers have different dimensions in the first direction. The portion of the fin structure not covered by the dummy gate is removed and replaced with a conductive portion; the conductive portion and the channel portion are alternately arranged in the first direction. The dummy gate and the sacrificial layer are removed and replaced with a gate; the gate surrounds the surface of each channel layer in the multiple layers of channel layers.

[0028] The manufacturing method provided by the embodiments of the present application can manufacture a semiconductor device with at least two channel layers having different lengths, that is, the manufacturing method provided by the embodiments of the present application can effectively regulate the electrical properties corresponding to multiple channel layers in the semiconductor device by varying the channel layer length, so that the electrical properties corresponding to multiple channel layers are relatively uniform, thereby improving the reliability of the semiconductor device.

[0029] In addition, in a semiconductor device with a relatively high aspect ratio, compared with the case where the lengths of multiple channel layers are exactly the same, the design of different lengths of multiple channel layers in the embodiments of the present application is beneficial for material filling at a relatively deep position. For example, it is beneficial for the gate to fill the surface of the channel layer closest to the substrate, avoiding the formation of voids or uneven filling at this position and preventing the impact on the DC performance of the semiconductor device.

[0030] In a third aspect, an integrated circuit is provided, and the integrated circuit includes an electronic device and the semiconductor device provided by any one of the embodiments in the first aspect. Among them, the electronic device is electrically connected to the semiconductor device.

[0031] In a fourth aspect, an electronic device is provided, and the electronic device includes a circuit board and the integrated circuit provided by the embodiment in the third aspect. Among them, the integrated circuit is disposed on the circuit board and is electrically connected to the circuit board.

[0032] For the technical effects brought by the integrated circuit in the third aspect and the electronic device in the fourth aspect, reference can be made to the technical effects brought by the design method of the semiconductor device in the first aspect, which will not be elaborated here. Description of the Drawings

[0033] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0034] Figure 2 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0035] Figure 3 is a sectional view along the sectional line A-A' in Figure 2 ;

[0036] Figure 4 is a sectional view along the sectional line B-B' in Figure 2 ;

[0037] Figure 5 is another sectional view along the sectional line B-B' in Figure 2 ;

[0038] Figure 6 is another sectional view along the sectional line B-B' in Figure 2 ;

[0039] Figure 7 is another sectional view along the sectional line B-B' in Figure 2 ;

[0040] Figure 8 is another sectional view of the semiconductor device provided by the embodiment of the present application;

[0041] Figure 9 is a side view along the C direction in Figure 2 ;

[0042] Figure 10 is a flowchart of the preparation of the semiconductor device provided by the embodiment of the present application;

[0043] Figures 11 to 18 is a schematic structural diagram corresponding to each preparation step of the semiconductor device. Detailed implementation manners

[0044] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present application belong to the scope of protection of the present application.

[0045] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0048] When describing some embodiments, the expressions "coupled", "connected" and their derivatives may be used. The terms "coupled", "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integral one; it may be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0049] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0051] As used herein, "parallel", "perpendicular", and "equal" include the stated cases and cases similar to the stated cases, where the similar cases are within an acceptable deviation range, which is determined by a person of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one of them.

[0052] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary figures. In the figures, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the figures due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0053] In addition, the scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. As can be known to a person of ordinary skill in the art, with the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0054] The embodiments of the present application provide an electronic device, which can be, for example, a mobile phone, a tablet computer (Pad), a personal digital assistant (PDA), a television, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (such as a soymilk machine, a floor sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. The embodiments of the present application do not impose special restrictions on the specific form of the electronic device.

[0055] Figure 1The following is a schematic structural diagram of an electronic device provided exemplarily for an embodiment of the present application. As Figure 1 shown, the electronic device 1000 includes an integrated circuit 100 and a circuit board 200, and the integrated circuit 100 can be disposed on the circuit board 200.

[0056] Exemplarily, the circuit board 200 can be a printed circuit board (PCB).

[0057] It can be understood that Figure 1 the structure of the electronic device 1000 shown in Figure 1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 can include more or fewer components than those shown in Figure 1 , or can combine some of the components shown in Figure 1 , or can be arranged differently from the components shown in

[0058] An embodiment of the present application also provides an integrated circuit 100.

[0059] Exemplarily, as Figure 1 shown, the integrated circuit 100 can include a logic circuit 101, an analog circuit 102, a storage circuit 103, an input / output circuit 104, etc.

[0060] It should be understood that the integrated circuit 100 includes but is not limited to the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104. For example, in addition to the foregoing four circuits, the integrated circuit 100 can also include other types or functions of circuits, or discrete devices.

[0061] In addition, the integrated circuit 100 can include one or more of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104.

[0062] On this basis, the number of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 can include one or more logic circuits 101. The integrated circuit 100 can also include one or more analog circuits 102. The integrated circuit 100 can also include one or more storage circuits 103. The integrated circuit 100 can also include one or more input / output circuits 104.

[0063] As Figure 1 shown, the integrated circuit 100 can include a semiconductor device 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the semiconductor device 10.

[0064] Exemplarily, referring to Figure 1 , the semiconductor device 10 and the electronic device 20 can be integrated in the logic circuit 101. The semiconductor device 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to implement functions such as "AND", "OR", and "NOT" in the logic circuit 101.

[0065] Exemplarily, the electronic device 20 can be an electronic device such as a resistor or a capacitor.

[0066] Exemplarily, the semiconductor device 10 and the electronic device 20 can also be arranged in other circuits. For example, they can be arranged in the storage circuit 103. The present application does not make specific limitations on this.

[0067] The embodiment of the present application also provides a semiconductor device 10. Figure 2 is a schematic structural diagram of the semiconductor device 10 provided by the embodiment of the present application. Figure 3 is a cross-sectional view along the Figure 2 section line A-A' in Figure 4 is a cross-sectional view along the Figure 2 section line B-B' in

[0068] In some embodiments, as shown in Figure 2 , Figure 3 and Figure 4 , the semiconductor device 10 includes a substrate 1, a fin structure 2, and a gate 3.

[0069] Among them, exemplarily, the material of the substrate 1 can be a semiconductor material. For example, it can be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI). The embodiment of the present application does not limit the material of the substrate 1.

[0070] Exemplarily, at least part or all of the substrate 1 can be doped. For example, it can be P-type doping or N-type doping.

[0071] Referring to Figure 2 , Figure 3 and Figure 4 , the fin structure 2 is arranged on the substrate 1.

[0072] Exemplarily, referring to Figure 2 , Figure 3 and Figure 4 , the fin structure 2 extends along the first direction X. That is, the length extension direction of the fin structure 2 is the first direction X.

[0073] Among them, the first direction X is parallel to the substrate 1.

[0074] Referring toFigure 4 , the fin structure 2 includes a conductive portion 22 and a channel portion 21A alternately arranged along a first direction X.

[0075] Among them, referring to Figure 3 and Figure 4 , the channel portion 21A includes a plurality of channel layers 21, and the plurality of channel layers 21 are stacked and spaced along a direction away from the substrate 1.

[0076] The material of the plurality of channel layers 21 includes a semiconductor material to form a metal oxide semiconductor field effect transistor. For example, a gate-all-around-effect transistor (GAA FET) is formed. Among them, the channel layer 21 is a region of the transistor for forming a channel.

[0077] For example, the channel layer 21 can be a nanowire (NW) or a nanosheet (NS).

[0078] It can be understood that the semiconductor device 10 can include a plurality of fin structures 2 arranged along a second direction Y. A plurality of transistors can be formed on one fin structure 2, and each transistor includes a channel portion 21A (i.e., a plurality of channel layers 21). Figure 2 , Figure 3 and Figure 4 Only one fin structure 2 included in the semiconductor device 10 and one fin structure 2 corresponding to form one transistor are taken as an example for illustration, and it does not limit the number of fin structures 2 in the semiconductor device 10 and the number of formed transistors.

[0079] Referring to Figure 2 and Figure 4 , the fin structure 2 can include a plurality of conductive portions 22.

[0080] Exemplarily, referring to Figure 4 , one conductive portion 22 can be respectively provided on both sides of a channel portion 21A (i.e., a plurality of channel layers 21) arranged oppositely along the first direction X. For example, referring to Figure 2 and Figure 4 , two conductive portions 22 can be included in one transistor, and one conductive portion 22 is respectively provided on both sides of the channel portion 21A (i.e., a plurality of channel layers 21) arranged oppositely along the first direction X. It can be understood that one transistor can also include a plurality of channel portions 21A and a plurality of conductive portions 22, and the embodiments of the present application do not limit the number of channel portions 21A and conductive portions 22 in the transistor.

[0081] Among them, the conductive portion 22 is used to form the source and drain of the transistor in the semiconductor device 10. For example, referring to Figure 4The two conductive portions 22 disposed along the first direction X on both sides of the channel portion 21A (ie, the multi-layer channel layer 21 ) serve as the source and drain of the transistor in the semiconductor device 10 , respectively.

[0082] The multi-layer channel layer 21 in the channel portion 21A is used as a channel region of a transistor in the semiconductor device 10. Figure 4 In the multilayer channel layer 21, two side surfaces of each channel layer 21 that are opposite to each other along the first direction X are in contact with the conductive portion 22, so that after a channel is formed in the multilayer channel layer 21 under the control of the gate 3, conduction between the two conductive portions 22 on both sides of the channel layer 21 (i.e., between the source and the drain) can be achieved.

[0083] Exemplarily, the doping type of the conductive portion 22 is different from the doping type of the channel layer 21 .

[0084] Exemplarily, the doping concentration of the conductive portion 22 is greater than the doping concentration of the channel layer 21 .

[0085] Exemplarily, the conductive portion 22 may be formed by using an epitaxial growth method and an etching process.

[0086] For example, the conductive portion 22 may be P-type doped or N-type doped by selecting the epitaxial material and the type of doped atoms.

[0087] Exemplarily, the material of the conductive part 22 may be, for example, a germanium-silicon mixture.

[0088] Exemplarily, the conductive portion 22 is doped with a high concentration, thereby improving the conductivity of the conductive portion 22 (ie, the source and the drain).

[0089] For example, the shape of the conductive portion 22 can be made as needed. For example, the shape of the conductive portion 22 can be a quadrangular pyramid. Figure 2 The conductive portion 22 may be in the shape of a cuboid. Alternatively, for example, the conductive portion 22 may be in an irregular shape, which is not limited herein.

[0090] For example, see Figure 4 The size of the conductive portion 22 in the thickness direction of the substrate 1 (ie, the third direction Z) may be smaller than the size of the fin structure 2 in the thickness direction of the substrate 1 .

[0091] For example, see Figure 2 , Figure 3 and Figure 4 The fin structure 2 may further include a well structure 23. Figure 3 and Figure 4As shown, at least a part of the well structure 23 is located between the substrate 1 and the conductive portion 22, and the sum of the dimensions of the conductive portion 22 and the well structure 23 in the thickness direction of the substrate 1 (i.e., the third direction Z) is approximately equal to the dimension of the fin structure 2 in the thickness direction of the substrate 1.

[0092] Exemplarily, the doping concentration of the well structure 23 is different from that of the conductive portion 22. For example, the doping concentration of the well structure 23 is less than that of the conductive portion 22.

[0093] Exemplarily, refer to Figure 4 , at least a part of the well structure 23 is also located between the substrate 1 and the channel layer 21.

[0094] Exemplarily, the well structure 23 can be integrally formed with the channel layer 21, that is, the doping concentration and doping type of the well structure 23 and the channel layer 21 can be the same.

[0095] Exemplarily, the well structure 23 can also be integrally formed with the substrate 1.

[0096] Refer to Figure 2 , Figure 3 and Figure 4 , the gate 3 in the semiconductor device 10 straddles the fin structure 2 and surrounds the surface of each channel layer 21 in the multi-layer channel layer 21.

[0097] For example, refer to Figure 3 , at least a part of the gate 3 is stacked with the channel layer 21 in the third direction Z, so that at least a part of the gate 3 is disposed above and below the channel layer 21 (taking the orientation in Figure 3 as an example), and refer to Figure 3 , partial gates 3 are also provided on two opposite side surfaces of the channel layer 21 along the second direction Y.

[0098] It can be understood that, refer to Figure 4 , the two opposite side surfaces of the channel layer 21 along the first direction X are used to contact the conductive portion 22, so no gate 3 is provided thereon.

[0099] The gate 3 is used to control the formation of a channel in the channel layer 21, thereby controlling the conduction between the two conductive portions 22 on both sides of the channel layer 21, or controlling that no channel is formed in the channel layer 21, so that the two conductive portions 22 on both sides of the channel layer 21 are disconnected. That is, the gate 3 is used to control the opening and closing of the transistor in the semiconductor device 10.

[0100] By surrounding the gate 3 around the surface of each channel layer 21 in the multi-layer channel layer 21, the control ability of the gate 3 over the channel in the channel layer 21 can be effectively improved, thereby enhancing the electrical performance of the semiconductor device 10.

[0101] Exemplarily, referring to Figure 2 , Figure 3 and Figure 4 , the semiconductor device 10 further includes a gate oxide layer 5 disposed between the gate 3 and the channel layer 21 to achieve electrical insulation between the gate 3 and the channel layer 21, thereby facilitating the control of the gate 3 over the channel in the channel layer 21.

[0102] Exemplarily, referring to Figure 2 and Figure 3 as shown, the semiconductor device 10 may further include a shallow trench isolation layer 4. The shallow trench isolation layer 4 is disposed on the substrate 1 and on two opposite sides of the fin structure 2 along the second direction Y. The surface of the shallow trench isolation layer 4 away from the substrate 1 is closer to the substrate 1 than the surface of the fin structure 2 away from the substrate 1.

[0103] That is, referring to Figure 2 , the shallow trench isolation layer 4 is only disposed around the portion of the fin structure 2 close to the substrate 1. For example, referring to Figure 2 , the shallow trench isolation layer 4 is disposed on two opposite side surfaces of the well structure 23 along the second direction Y, thereby facilitating the isolation between two adjacent fin structures 2 (not shown in the figure).

[0104] Exemplarily, the material of the shallow trench isolation layer 4 is an insulating material. For example, the material of the shallow trench isolation layer 4 may include binary or multi-component compounds composed of elements such as silicon (Si), carbon (C), nitrogen (N), oxygen (O), etc.

[0105] Referring to Figure 4 , in the semiconductor device 10, the dimensions d1 of at least two of the multiple channel layers 21 in the first direction X are different, that is, among the multiple channel layers 21 stacked in the direction away from the substrate 1 in the same transistor, the lengths of at least two channel layers 21 are different.

[0106] Exemplarily, the lengths of the multiple channel layers 21 are all different, or some of the channel layers 21 in the multiple channel layers 21 may have the same length, while the remaining channel layers 21 have longer lengths, or the remaining channel layers 21 have shorter lengths, or at least one of the remaining channel layers 21 has a longer length and at least one of the remaining channel layers 21 has a shorter length.

[0107] With the rapid development of semiconductor technology, the integration degree of GAA FETs (such as the aforementioned semiconductor device 10) is getting higher and higher, and the refinement degree of each internal structure is gradually increasing, which poses great challenges to the performance of GAA FETs. For example, in devices with a relatively high integration degree, limited by the high aspect ratio, the process difficulty of etching or doping the device is relatively large, which easily leads to large performance differences between structures (such as the channel layer 21) at different depth positions, affecting the uniformity of the entire device. For example, when doping the multi-layer channel layer 21, the doping concentration of the channel layer 21 at a deeper position (closer to the substrate 1) may be different from that of the channel layer 21 at a shallower position, resulting in poor electrical uniformity at different depths of the semiconductor device 10 and affecting the reliability of the semiconductor device 10.

[0108] In order to ensure the continuous progress of Moore's Law, it is inevitable to improve the performance of GAA FETs, such as the improvement of electrical performance uniformity. In related technologies, in order to ensure that the electrical performance (such as the conductivity of the channel) corresponding to each layer of the channel layer approaches consistency, efforts are usually made to improve the refinement degree of the doping process so as to ensure that the channel layers of different layers in the multi-layer channel layer have the same doping concentration as much as possible. However, limited by the high integration degree of the device, the refinement degree of the doping process cannot be infinitely improved. At present, there are still process errors in GAA FETs, resulting in different doping concentrations of different channel layers, affecting the uniformity of the electrical performance of GAA FETs. In addition, there are other factors besides the doping concentration that will also cause different electrical performances of different channel layers, which also affect the uniformity of the electrical performance of GAA FETs.

[0109] In the semiconductor device 10 provided in the embodiment of the present application, by setting that at least two of the multi-layer channel layers 21 have different sizes d1 (i.e., lengths) in the first direction X, the electrical performances corresponding to the multi-layer channel layers 21 can be made relatively uniform. That is, by controlling the length of the channel layer 21, the electrical performance of the channel layer 21 can be adjusted. For example, by setting the length of the channel layer 21 with a relatively small saturation current in the multi-layer channel layer 21 to be relatively small, the saturation currents corresponding to the multi-layer channel layers 21 are made to approach consistency, thereby optimizing the uniformity of the electrical performance of the semiconductor device 10 and improving the reliability of the semiconductor device 10, which is beneficial to the continuous development of technology nodes.

[0110] Compared with the technical means of adjusting the electrical performance by doping concentration in related technologies, the adjustment of the electrical performance by the length of the channel layer 21 in the embodiment of the present application is relatively simple. The length change of the channel layer 21 can be achieved only by controlling the etching position, and the refinement degree is relatively high, the error is relatively small, and the implementation effect on the uniformity of the electrical performance of the semiconductor device 10 is good.

[0111] The embodiment of the present application adds a control means (i.e., length control) for regulating the electrical performance of the semiconductor device 10. The means of regulating the electrical performance of the device through the length of the channel layer 21 can be combined with other control means, such as the means of regulating the electrical performance of the device through the doping concentration of the channel layer 21, so as to regulate the uniformity of the electrical performance of the semiconductor device 10 from multiple dimensions, further optimize the regulation effect of the electrical performance uniformity of the semiconductor device 10, and further improve the reliability of the semiconductor device 10.

[0112] In addition, in the embodiment of the present application, by designing the length of the channel layer 21 differently, the stress received by the overall multi-layer channel layer 21 can be dispersed, avoiding the situation that the channel layer 21 bends under the action of stress due to the more concentrated stress when the lengths of the multi-layer channel layer 21 are exactly the same, and improving the structural stability of the semiconductor device 10.

[0113] In some embodiments, the saturation currents corresponding to the multi-layer channel layers 21 are the same. For example, for two channel layers 21 with different sizes d1 in the first direction X, the corresponding saturation currents are also the same, so as to ensure that the electrical performance of the semiconductor device 10 at the positions where different channel layers 21 are located is roughly the same, thereby improving the reliability of the semiconductor device 10.

[0114] Under specific conditions, the current in the circuit reaches the maximum value and no longer increases with the increase of the voltage. Among them, the current reaching the maximum value is the saturation current. This saturation current is an important index of the semiconductor device 10. In a transistor, the magnitude of the saturation current is directly related to the electrical performance and working state of the semiconductor device 10.

[0115] In the I D -V DS (I D is the saturation current, V DS is the source-drain voltage difference) curve saturation region, the relationship between the ideal saturation current and the length of the channel layer 21 (i.e., the size d1 in the first direction X) is:

[0116]

[0117] Among them, W is the width of the channel layer 21 (i.e., the size d2 of the channel layer 21 in the second direction Y), L is the length of the channel layer 21 (i.e., the size d1 of the channel layer 21 in the first direction X), μ n is the carrier mobility, C ox is the capacitance between the gate 3 and the channel layer 21, V GS is the working voltage applied by the gate 3, and V T is the threshold voltage.

[0118] According to this formula, it can be seen that the greater the length of the channel layer 21, the smaller the corresponding saturation current. When the electrical properties corresponding to different channel layers 21 of the semiconductor device 10 are non-uniform, by controlling the change in the length of the channel layer 21, the magnitude of the saturation current can be effectively adjusted, so that the electrical properties corresponding to the multiple channel layers 21 approach consistency, improving the electrical uniformity and reliability of the semiconductor device 10.

[0119] In some embodiments, among the multiple channel layers 21, the channel layer 21 with a smaller doping concentration has a smaller size d1 (i.e., length) in the first direction X. That is, the length of the channel layer 21 can be set according to the magnitude of the doping concentration of the channel layer 21. For example, after obtaining the variation law of the doping concentration of the channel layer 21, the length of the channel layer 21 can be adaptively and regularly set to make up for the electrical differences caused by the doping concentration differences.

[0120] For example, channel layers 21 with different depths are set to correspond to different doping concentrations to ensure that each channel layer 21 can reach an accurate doping state. Then, among the multiple channel layers 21, the channel layer 21 with a smaller doping concentration is set to have a smaller corresponding length. Thus, through the regulation means combining the doping concentration and the length, the electrical properties of the multiple channel layers 21 approach uniformity, improving the reliability of the semiconductor device 10.

[0121] The doping concentration of the channel layer 21 is closely related to the resistance of the channel layer 21. It can be understood that the greater the doping concentration, the greater the concentration of carriers that can be formed in the channel layer 21, that is, the smaller the resistance of the channel layer 21.

[0122] The relationship between the resistance of the channel layer 21 and the length is as follows:

[0123]

[0124] Wherein, R is the resistance, ρ is the resistivity, L is the length (i.e., the size d1 of the channel layer 21 in the first direction X), CD is the width (i.e., the size of the channel layer 21 in the second direction Y), s is the thickness (i.e., the size of the channel layer 21 in the third direction Z), and CD×s is the cross-sectional area of the channel layer 21 parallel to the second direction Y.

[0125] According to this resistance formula, when the resistivity ρ and the cross-sectional area CD×s of the channel layer 21 are constant, the greater the length L of the channel layer 21, the greater the corresponding resistance R.

[0126] In summary, in the multi-layer channel layer 21, if the doping concentration of one of the channel layers 21 is relatively low, its corresponding resistance is relatively high, resulting in a relatively small current flowing through this channel layer 21. To keep the current flowing through the multi-layer channel layer 21 approximately the same, it is necessary to reduce the resistance of the channel layer 21 with a relatively low doping concentration. According to the above formula for resistance R, the length of the channel layer 21 is proportional to the resistance. Therefore, the resistance of the channel layer 21 can be reduced by shortening the length of the channel layer 21. That is, to keep the electrical properties of the multi-layer channel layer 21 approximately the same, the length corresponding to the channel layer 21 with a relatively low doping concentration can be reduced.

[0127] The following can also use the threshold voltage V T to characterize the mutual variation law between the doping concentration and the length of the channel layer 21.

[0128] In the formula for the aforementioned saturation current I D , the threshold voltage V T is determined by material properties and process parameters and is closely related to the doping concentration of the channel layer 21. The threshold voltage V T can be expressed by the following formula:

[0129]

[0130] where Q SD (max) is the maximum value of the space charge density per unit area of the depletion layer, Q’ SS is the charge number per unit area, Φ ms is the metal-semiconductor work function difference, and Φ f is the barrier height.

[0131] Among them, the barrier height Φ f can be:

[0132]

[0133] The maximum value of the space charge density Q SD per unit area of the channel layer 21 can be:

[0134] Q SD (max) = eN a x dT ;

[0135] Among them, x dT can be:

[0136]

[0137] In the aforementioned multiple formulas, Na is the doping concentration of the channel layer 21. From the aforementioned multiple formulas, it can be seen that the doping concentration Na is related to the barrier height Φ fis directly proportional. The doping concentration Na is directly proportional to the maximum value Q of the space charge density per unit area. SD (max).

[0138] By substituting the aforementioned multiple formulas into the formula for the saturation current I D , the lengths (L1 and L2) of the channel layer 21 and the barrier height Φ f and the maximum value Q of the space charge density per unit area SD (max) have the following relationship:

[0139]

[0140] From the above formula, it can be seen that the length L (including L1 and L2) of the channel layer 21 and the barrier height Φ f (including Φ f,1 and Φ f,2 ) are directly proportional, and the length L of the channel layer 21 and the maximum value Q of the space charge density per unit area SD (max) are directly proportional.

[0141] In summary, when the saturation current I D is the same, the smaller the doping concentration Na of the channel layer 21, the smaller the barrier height Φ f , the smaller the maximum value Q of the space charge density per unit area SD (max), and the smaller the corresponding length L of the channel layer 21. That is, the doping concentration Na of the channel layer 21 is directly proportional to the length L of the channel layer 21.

[0142] That is, by setting the lengths of the channel layers 21 with smaller doping concentrations to be smaller in the multi-layer channel layer 21, the saturation current of the multi-layer channel layer 21 can be ensured to be approximately the same. That is, when there are differences in the doping concentrations corresponding to different channel layers 21 of the semiconductor device 10 resulting in different electrical properties, the length of the channel layer 21 can be adjusted accordingly according to the variation law of the doping concentration of the channel layer 21, so as to effectively control the electrical properties corresponding to the multi-layer channel layer 21 to be approximately the same, and improve the electrical uniformity and reliability of the semiconductor device 10.

[0143] In some embodiments, the aspect ratios of the multi-layer channel layer 21 are the same.

[0144] Among them, the aspect ratio of the channel layer 21 is the ratio of the dimension d2 of the channel layer 21 in the second direction Y to the dimension d1 of the channel layer 21 in the first direction X.

[0145] For example, two channel layers 21 with different dimensions d1 in the first direction X have the same width-to-length ratio. That is, by controlling the length of the channel layer 21, the width-to-length ratios of different channel layers 21 can be made the same, so that the saturation currents corresponding to different channel layers 21 are the same, improving the electrical performance uniformity of the semiconductor device 10 at different positions, and thus optimizing the reliability of the semiconductor device 10.

[0146] Exemplarily, the smaller the dimension d2 (i.e., the width) of the channel layer 21 in the second direction Y, the smaller the dimension d1 (i.e., the length) in the first direction X, so that different channel layers 21 can have approximately the same width-to-length ratio.

[0147] As the integration degree of the semiconductor device 10 gradually increases, the aspect ratio of the fin structure 2 in the semiconductor device 10 (the ratio of the dimension of the fin structure 2 in the third direction Z to the dimension d2 of the fin structure 2 in the second direction Y) gradually increases. In the etching process, the closer to the substrate 1 (i.e., the deeper the position), the lighter the etching degree of the fin structure 2, resulting in the dimension d2 (i.e., the width) of the fin structure 2 being approximately wider at the bottom and narrower at the top (taking the orientation in Figure 3 as an example), that is, along the direction away from the substrate 1, the width of the channel layer 21 can gradually decrease (as shown in Figure 3 ).

[0148] In some embodiments, as shown in Figure 3 , it is set that along the direction away from the substrate 1, the lengths of the multiple channel layers 21 (i.e., the dimensions d1 in the first direction X) also gradually decrease, so that the multiple channel layers 21 can maintain approximately the same width-to-length ratio, so that the saturation currents corresponding to different channel layers 21 are the same, improving the electrical performance uniformity of the semiconductor device 10 at different positions, and thus optimizing the reliability of the semiconductor device 10.

[0149] In addition, by setting the lengths of the multiple channel layers 21 to gradually decrease along the direction away from the substrate 1, the problem of large etching difficulty caused by a high aspect ratio can also be avoided, reducing the manufacturing difficulty of the semiconductor device 10.

[0150] In some embodiments, as shown in Figure 4 , the two opposite side surfaces of the channel portion 21A in the first direction X (such as the left side surface and the right side surface in Figure 4 ) are inclined, that is, the two opposite side surfaces of the multiple channel layers 21 in the first direction X (such as in Figure 4The left and right sides (in the figure) are inclined, and on the same side (for example, both on the left side or both on the right side), the sides of different channel layers 21 are approximately located on the same plane. Thus, during the etching preparation process, only one etching cut with an inclined angle is required to achieve the purpose that the lengths of the multiple channel layers 21 gradually decrease in the direction away from the substrate 1.

[0151] It can be understood that referring to Figure 4 , the two opposite sides of the multiple channel layers 21 in the first direction X gradually approach in the direction away from the substrate 1, that is, these two sides are inclined towards the direction of approaching each other, so that the dimension d1 of the multiple channel layers 21 in the first direction X gradually decreases in the direction away from the substrate 1.

[0152] In some embodiments, as Figure 5 shown, the two opposite sides of the channel portion 21A in the first direction X (such as Figure 5 the left and right sides in the figure) are arranged in a stepped manner, that is, the two opposite sides of the multiple channel layers 21 in the first direction X (such as Figure 5 the left and right sides in the figure) are arranged in a stepped manner, and the purpose that the lengths of the multiple channel layers 21 gradually decrease in the direction away from the substrate 1 can also be achieved.

[0153] Exemplarily, referring to Figure 5 , the steps formed by the sides of the multiple channel layers 21 gradually rise in the direction away from the substrate 1, so that the dimension of the multiple channel layers 21 in the first direction X gradually decreases in the direction away from the substrate 1.

[0154] Exemplarily, the dimension d1 of the multiple channel layers 21 in the first direction X can change continuously. For example, referring to Figure 5 , in the direction away from the substrate 1, the dimension d1 of the multiple channel layers 21 in the first direction X decreases in sequence.

[0155] Or exemplarily, the dimension d1 of the multiple channel layers 21 in the first direction X can also change in stages. For example, referring to Figure 6 , in the direction away from the substrate 1, the length of the channel layer 21 can decrease once for each layer of the channel layer 21, or the length of the channel layer 21 can also decrease once for every two layers of the channel layer 21. The change rule of the length of the channel layer 21 can depend on factors such as the doping concentration or width of the channel layer 21, and the application embodiments do not limit this.

[0156] In some embodiments, referring to Figure 7 , it is also possible to change the length of one of the channel layers 21 in the channel layer 21, so as to achieve precise regulation of the channel layer 221. For example, referring to Figure 7, in the multi-layer channel layer 21, the length of only one of the channel layers 21 can be set to be relatively small. For example, the length of one or more channel layers 21 with a relatively small doping concentration can be set to be small. That is, the length of the target channel layer 21 (such as the channel layer 21 with a relatively large doping concentration error) can be specifically set, so as to correct the channel layer 21 with relatively large electrical performance defects and improve the overall electrical performance uniformity of the semiconductor device 10.

[0157] It can be understood that the foregoing multiple embodiments can be combined with each other. For example, in some embodiments, multiple factors affecting the saturation current of the channel layer 21, such as the width, doping concentration, and length of the channel layer 21, can be comprehensively considered to regulate the electrical performance of the channel layer 21, so that the electrical performance of the multi-layer channel layer 21 approaches consistency and the reliability of the semiconductor device 10 is improved.

[0158] Figure 8 It is a cross-sectional view when the semiconductor device 10 includes multiple transistors T.

[0159] In some embodiments, as Figure 4 and Figure 8 shown, along the direction away from the substrate 1, the size d3 of the conductive portion 22 in the first direction X gradually increases, that is, the length of the conductive portion 22 gradually increases. For example, referring to Figure 4 , the length of the conductive portion 22 is generally narrow at the bottom and wide at the top (taking the orientation in Figure 4 as an example).

[0160] By setting the length of the conductive portion 22 to gradually increase in the direction away from the substrate 1, on the one hand, the conductive portion 22 can adapt to the trend that the length (i.e., the size d1 in the first direction X) of the multi-layer channel layer 21 gradually decreases, so as to facilitate the conductive portion 22 (source electrode and / or drain electrode) to always be in contact with the channel layer 21, ensuring the smooth opening and closing of the semiconductor device 10. On the other hand, the length of the end portion of the conductive portion 22 away from the substrate 1 is relatively large, so that the area of its top is relatively large, so that when the contact structure 6 is provided on the top of the conductive portion 22 (refer to Figure 8 ), the process window is relatively large, thereby reducing the preparation difficulty of the contact structure 6 and improving the electrical connection performance between the conductive portion 22 and the contact structure 6.

[0161] Exemplarily, referring to Figure 8 , the semiconductor device 10 may further include a contact structure 6. The contact structure 6 is provided on the fin structure 2 and at least covers the upper surface of the conductive portion 22, so as to realize the external connection of the conductive portion 22 and facilitate the transmission of electrical signals to the conductive portion 22.

[0162] It can be understood that the two opposite side surfaces of the conductive portion 22 in the first direction X can also be inclined or stepped (refer toFigure 8 ), so that the conductive portion 22 matches the structure of the plurality of channel layers 21 arranged obliquely or in a stepped manner.

[0163] Figure 9 For the semiconductor device 10 in Figure 2 is a side view in the C direction.

[0164] In some embodiments, as Figure 9 shown, the dimensions d4 of at least two portions of the gate 3 in the first direction X are different, and the dimension d1 of the channel layer 21 in the first direction X (refer to Figure 4 ) is larger, and the dimension d4 of the corresponding portion of the gate 3 surrounding the channel layer 21 in the first direction X is larger.

[0165] That is, the dimension d4 of the gate 3 in the first direction X changes with the change of the dimension d1 of the channel layer 21 it surrounds in the first direction X, so that the gate 3 can completely surround the channel layer 21, ensuring the control of the channel in the channel layer 21, while avoiding the problem that the too large dimension of the gate 3 in the first direction X increases the manufacturing difficulty of the conductive portion 22, or the too large distance between the conductive portion 22 and the channel layer 21 leads to a decrease in the channel transmission efficiency.

[0166] Exemplarily, the shapes of the two opposite sides of the gate 3 in the first direction X are similar to the shapes of the two opposite sides of the multi-layer channel layer 21 in the first direction X. For example, when the two opposite sides of the multi-layer channel layer 21 in the first direction X are arranged obliquely, the two opposite sides of the gate 3 in the first direction X are also arranged obliquely. Or, for example, refer to Figure 9 , when the two opposite sides of the multi-layer channel layer 21 in the first direction X are arranged in a stepped manner, the two opposite sides of the gate 3 in the first direction X are also arranged in a stepped manner.

[0167] Exemplarily, the variation law of the dimension d4 of the gate 3 in the first direction X corresponds to the variation law of the dimension d1 of the channel layer 21 it surrounds in the first direction X.

[0168] For example, refer to Figure 9 , the two opposite sides of the gate 3 in the first direction X are arranged in a stepped manner, and the stepped sides of the gate 3 match the stepped sides of the multi-layer channel layer 21. For example, along the direction away from the substrate 1, the steps of the stepped sides of the gate 3 gradually increase, corresponding to the design that the length (dimension d1 in the first direction X) of the multi-layer channel layer 21 gradually decreases along the direction away from the substrate 1.

[0169] In some embodiments, as Figure 9As shown, the semiconductor device 10 may further include a sidewall layer 7.

[0170] The sidewall layer 7 extends along the second direction Y, and referring to Figure 9 , the sidewall layer 7 is disposed on two opposite sides of the gate 3 along the first direction X, and the sidewall layer 7 can protect the gate 3 from external damage.

[0171] Exemplarily, it can be understood that the surface of the sidewall layer 7 (the surface extending along the second direction Y) can also be inclined or stepped, and the stepped surface of the sidewall layer 7 matches the shape of the stepped side surface of the gate 3. The specific setting manner of the sidewall layer 7 is the same as that of the two opposite sides of the gate 3 along the first direction X, and will not be elaborated here.

[0172] In some embodiments, it can be understood that an inclined or stepped shape can be formed only on one of the two opposite sides of the multi-layer channel layer 21 along the first direction X, that is, the length change of the channel layer 21 can be performed only on one side (for example, Figure 4 the left side or the right side in ), or the length change can also be performed on both sides. The drawings provided in the embodiments of the present application only take the length change on both sides as an example for illustration, and do not form a limitation thereto.

[0173] The uniformity of the electrical performance of the semiconductor device 10 obtained in the above embodiments will be analyzed below:

[0174] In the related art, in a semiconductor device having three-layer channel layers, the variance of the resistance of the three-layer channel layers can reach 22.3%, and the variance of the electric power of the three-layer channel layers can reach 20.1%, indicating that the difference in electrical performance between the three-layer channel layers is relatively large.

[0175] In the embodiments of the present application, by adjusting the lengths of the three-layer channel layers 21, the difference in electrical performance between the three-layer channel layers can be effectively reduced. Specifically, refer to Tables 1, 2, and 3.

[0176] Table 1

[0177] Resistance Resistivity Length Width Thickness Electric power First channel layer 0.60 0.70 0.85 1.00 1.00 1.68 Second channel layer 0.51 0.70 0.77 1.05 1.00 1.95 Third channel layer 0.54 0.70 0.85 1.10 1.00 1.85 Standard deviation 7.6％ 7.4％

[0178] Referring to Table 1, in the embodiments of the present application, by setting L1 = L3 > L2 (that is, the lengths of the first channel layer and the third channel layer are the same and greater than the length of the second channel layer), the resistance variance of the three-layer channel layers 21 can be effectively reduced to 7.6%, and the electric power variance can be reduced to 7.4%. Compared with the related art, the difference in electrical performance between the three-layer channel layers 21 is effectively reduced.

[0179] Table 2

[0180] Resistance Resistivity Length Width Thickness Electric power First channel layer 0.54 0.70 0.77 1.00 1.00 1.86 Second channel layer 0.57 0.70 0.85 1.05 1.00 1.76 Third channel layer 0.54 0.70 0.85 1.10 1.00 1.85 Standard deviation 2.8％ 2.8％

[0181] Referring to Table 2, in the embodiment of the present application, by setting L1 < L2 = L3, the resistance variance and the electric power variance of the three-layer channel layer 21 are both reduced to 2.8%. Compared with the related art, the difference in electrical properties between the three-layer channel layers 21 is further reduced.

[0182] Table 3

[0183] Resistance Resistivity Length Width Thickness Electric power First channel layer 0.54 0.70 0.77 1.00 1.00 1.86 Second channel layer 0.53 0.70 0.80 1.05 1.00 1.88 Third channel layer 0.54 0.70 0.85 1.10 1.00 1.85 Standard deviation 0.7％ 0.7％

[0184] Referring to Table 3, in the embodiment of the present application, by setting L1 < L2 < L3 (that is, along the direction away from the substrate 1, the lengths of the multi-layer channel layers 21 gradually decrease), the resistance variance and the electric power variance of the three-layer channel layer 21 are both reduced to 0.7%. That is, there is almost no difference in electrical properties between the three-layer channel layers 21, and the improvement effect on the reliability of the semiconductor device 10 is obvious.

[0185] Similarly, in the related art, in a semiconductor device with five-layer channel layers, the variance of the resistance of the five-layer channel layers can reach 20.8%, and the variance of the electric power of the three-layer channel layers can reach 16.5%, indicating that the difference in electrical properties between the five-layer channel layers is also relatively large.

[0186] Table 4 is an embodiment provided by the present application for adjusting the length of the five-layer channel layer 21.

[0187] Table 4

[0188] Resistance Resistivity Length Width Thickness Electric power First channel layer 0.54 0.70 0.77 1.00 1.00 1.86 Second channel layer 0.51 0.70 0.77 1.05 1.00 1.88 Third channel layer 0.54 0.70 0.85 1.10 1.00 1.85 Fourth channel layer 0.51 0.70 0.85 1.16 1.00 1.95 Fifth channel layer 0.49 0.70 0.85 1.22 1.00 2.04 Standard deviation 4.0％ 4.1％

[0189] Referring to Table 4, in the embodiment of the present application, by setting L1 = L2 < L3 = L4 = L5, the resistance variance of the three-layer channel layer 21 can be reduced to 4.0%, and the electric power variance can be reduced to 4.1%, reducing the difference in electrical properties between the five-layer channel layers 21. That is, in a semiconductor device 10 having more than three-layer channel layers 21, the electrical property uniformity of the multi-layer channel layers 21 can still be regulated by changing the length of the channel layer 21.

[0190] It can be understood that in the embodiments corresponding to the foregoing multiple tables of the present application, except for the length difference, other parameters are exactly the same as those in the related art. For example, the resistivity, width, thickness, etc. are all the same, so as to highlight the influence of the length change on the electrical properties.

[0191] The embodiment of the present application also provides a method for manufacturing a semiconductor device 10. Figure 10 It is a manufacturing flow chart corresponding to this manufacturing method, Figures 11 to 18Schematic diagrams corresponding to each step in the manufacturing process of semiconductor device 10.

[0192] In some embodiments, such as Figure 10 shown, the manufacturing method includes the following manufacturing steps S1 to S4:

[0193] S1: As Figure 11 shown, a fin structure 2 is formed on a substrate 1.

[0194] Exemplarily, this step S1 may include: sequentially and alternately stacking a sacrificial layer 2A and a semiconductor layer 2B on the substrate 1. Cutting the sacrificial layer 2A and the semiconductor layer 2B to form a plurality of fin structures 2 spaced apart from each other. The plurality of fin structures 2 are arranged along a second direction Y, and each fin structure 2 extends along a first direction X.

[0195] It can be understood that the fin structure 2 formed in step S1 includes a sacrificial layer 2A and a semiconductor layer 2B alternately stacked along a direction away from the substrate 1.

[0196] That is, the fin structure 2 includes a plurality of stacked and spaced semiconductor layers 2B, and adjacent semiconductor layers 2B are spaced apart by a sacrificial layer 2A.

[0197] Exemplarily, as Figure 11 shown, this step S1 may further include: forming a shallow trench isolation layer 4 on the substrate 1.

[0198] Exemplarily, a shallow trench isolation material that completely wraps the fin structure 2 may be deposited first, and then the shallow trench isolation material is etched back in the direction towards the substrate 1 to form the shallow trench isolation layer 4 so as to expose at least a part of the fin structure 2. The unexposed part of the fin structure 2 (i.e., the part surrounded by the shallow trench isolation layer 4) serves as a well structure 23. By controlling the etching-back time, the height of the exposed part of the fin structure 2 can be controlled.

[0199] S2: As Figure 12 shown, a dummy gate 3A is formed.

[0200] Referring to Figure 12 , the dummy gate 3A straddles the fin structure 2. For example, the dummy gate 3A straddles the part of the fin structure 2 on the side away from the substrate 1 of the shallow trench isolation layer 4.

[0201] Figure 13 is a side view along the D direction in Figure 12 .

[0202] Referring to Figure 13, at least two portions of the dummy gate 3A arranged in a direction away from the substrate 1 have different dimensions d5 in the first direction X. For example, the portions of the dummy gate 3A covering different semiconductor layers 2B have different dimensions d5 in the first direction X, facilitating the cutting of at least two semiconductor layers 2B in the multi-layer semiconductor layer 2B into different lengths in subsequent process steps, that is, forming channel layers 21 with different lengths.

[0203] For example, referring to Figure 13 , in a direction away from the substrate 1, the dimension d5 of the dummy gate 3A in the first direction X gradually decreases, facilitating the lengths (dimensions d1 in the first direction X) of the multi-layer channel layers 21 formed in subsequent process steps to gradually decrease in a direction away from the substrate 1.

[0204] Exemplarily, during the formation of the dummy gate 3A, the dummy gate 3A can be etched at a certain inclination angle, so that the two opposite side surfaces of the dummy gate 3A in the first direction X are inclined.

[0205] Or exemplarily, during the formation of the dummy gate 3A, by controlling the etching time at different positions of the dummy gate 3A, the two opposite side surfaces of the dummy gate 3A in the first direction X can be made to be stepped. For example, along the direction away from each other of the two side surfaces, the etching duration gradually increases and the etching degree gradually deepens, so that the two side surfaces form steps that gradually rise in a direction away from the substrate 1.

[0206] Referring to Figure 13 , the portion of the fin structure 2 covered by the dummy gate 3A is the channel portion 21A, that is, the portion of the fin structure 2 covered by the dummy gate 3A can be used as the channel portion 21A.

[0207] Referring to Figure 13 , the channel portion 21A includes multi-layer channel layers 21, and the channel layer 21 is the portion of the semiconductor layer 2B covered by the dummy gate 3A. That is, the portion of the semiconductor layer 2B covered by the dummy gate 3A serves as the channel layer 21 in the channel portion 21A. The portion of the semiconductor layer 2B not covered by the dummy gate 3A will be removed in subsequent process steps.

[0208] Referring to the subsequent Figure 16 , among the multi-layer channel layers 21 of one channel portion 21A, at least two channel layers 21 have different dimensions d1 in the first direction X.

[0209] Exemplarily, as Figure 14 shown, after the formation of the dummy gate 3A, the manufacturing method may further include:

[0210] S21: Referring to Figure 14, a sidewall layer 7 is formed. The sidewall layer 7 is disposed on two opposite side surfaces of the dummy gate 3A along the first direction X.

[0211] It can be understood that the shape of the surface (the surface extending along the second direction Y) of the sidewall layer 7 depends on the shapes of the two opposite side surfaces of the dummy gate 3A along the first direction X. For example, referring to Figure 14 , when the two opposite side surfaces of the dummy gate 3A along the first direction X are stepped, the surface of the sidewall layer 7 is also stepped.

[0212] S3: Refer to Figure 15 and Figure 16 , remove the portions of the fin structure 2 that are not covered by the dummy gate 3A (refer to Figure 15 , remove the portions of the fin structure 2 located on the left and right sides of the dummy gate 3A), and replace them with the conductive portions 22 (refer to Figure 16 ).

[0213] Exemplarily, an in-situ multi-step etching process can be used to remove the portions of the fin structure 2 located on both sides of the dummy gate 3A, so as to be compatible with the existing manufacturing process of the GAA FET, and there is no need to specifically design the corresponding manufacturing process.

[0214] Exemplarily, referring to Figure 15 , the portions of the fin structure 2 located on both sides of the dummy gate 3A can be removed with the surface of the sidewall layer 7 as the boundary, so that in the portion of the fin structure 2 covered by the dummy gate 3A and the sidewall layer 7, the dimension d1 of the multi-layer channel layer 21 in the first direction X can be the same as the change in the surface of the sidewall layer 7.

[0215] For example, referring to Figure 16 , after step S3, in the multi-layer channel layer 21 covered by the dummy gate 3A, at least two channel layers 21 have different dimensions d1 in the first direction X. For example, referring to Figure 16 , the dimension d1 of the multi-layer channel layer 21 in the first direction X gradually decreases along the direction away from the substrate 1.

[0216] Exemplarily, referring to Figure 16 , the dimension d3 of the formed conductive portion 22 in the first direction X gradually increases along the direction away from the substrate 1, so as to match the length change of the multi-layer channel layer 21.

[0217] S4: Refer to Figure 17 and Figure 18 , remove the dummy gate 3A and the sacrificial layer 2A (refer to Figure 17 ), and replace them with the gate 3.

[0218] Refer to Figure 18 , the formed gate 3 is disposed to surround the surface of each channel layer 21 in the multi-layer channel layer 21.

[0219] Exemplarily, it can be understood that after removing the dummy gate 3A and the sacrificial layer 2A and before filling the gate material to form the gate 3, the manufacturing method may further include: depositing a gate oxide layer 5 on the sidewalls of the sidewall layer 7 and the surface of the channel layer 21, so as to electrically insulate the subsequently formed gate 3 from the channel layer 21 and electrically insulate the gate 3 from the conductive portion 22.

[0220] Exemplarily, referring to Figure 18 , since the gate 3 replaces the positions of the dummy gate 3A and the sacrificial layer 2A, the shapes of the two opposite sides of the gate 3 along the first direction X depend on the shapes of the two opposite sides of the dummy gate 3A along the first direction X. For example, referring to Figure 18 , the two opposite sides of the gate 3 along the first direction X may be stepped, so as to match the length of the channel layer 21 surrounded by the gate 3.

[0221] The manufacturing method provided by the embodiment of the present application can manufacture a semiconductor device 10 in which the lengths (dimensions d1 in the first direction X) of at least two channel layers 21 are different. That is, the manufacturing method provided by the embodiment of the present application can effectively regulate the electrical properties corresponding to the multiple channel layers 21 in the semiconductor device 10 by changing the lengths of the channel layers 21, so that the electrical properties corresponding to the multiple channel layers 21 are relatively uniform, thereby improving the reliability of the semiconductor device 10.

[0222] In addition, in a semiconductor device 10 with a relatively high aspect ratio, compared with the case where the lengths of the multiple channel layers 21 are exactly the same, the design of different lengths of the multiple channel layers 21 in the embodiment of the present application is beneficial to material filling at a relatively deep position. For example, it is beneficial for the gate 3 to be filled on the surface of the channel layer 21 closest to the substrate 1, avoiding the formation of voids or uneven filling at this position and avoiding affecting the DC performance of the semiconductor device 10.

[0223] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure who thinks of changes or substitutions should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A fin structure disposed on the substrate, the fin structure including conductive portions and channel portions alternately arranged in a first direction; the channel portions include multiple channel layers, and the multiple channel layers are stacked and spaced apart in a direction away from the substrate; A gate surrounding the surface of each channel layer in the multiple channel layers; Wherein, at least two of the multiple channel layers have different dimensions in the first direction; the first direction is parallel to the substrate.

2. The semiconductor device according to claim 1, wherein Two channel layers with different dimensions in the first direction have the same saturation current.

3. The semiconductor device according to claim 1 or 2, characterized in that, Among the multiple channel layers, the channel layer with a smaller doping concentration also has a smaller dimension in the first direction.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, Two channel layers with different dimensions in the first direction have the same width-to-length ratio; the width-to-length ratio is the ratio of the dimension of the channel layer in a second direction to the dimension in the first direction; The second direction is parallel to the substrate and perpendicular to the first direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, Among the multiple channel layers, the channel layer with a smaller dimension in the second direction also has a smaller dimension in the first direction.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, Along the direction away from the substrate, both the dimension of the multiple channel layers in the second direction and the dimension in the first direction gradually decrease.

7. The semiconductor device according to claim 6, wherein, Two opposite side surfaces of the channel portion in the first direction are inclined, and among the same side, the side surfaces of different channel layers are located in the same plane.

8. The semiconductor device according to claim 6, wherein, Two opposite side surfaces of the channel portion in the first direction are arranged in a stepped manner.

9. The semiconductor device according to any one of claims 6 to 8, characterized in that, Along the direction away from the substrate, the dimension of the conductive portion in the first direction gradually increases.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, At least two portions of the gate have different dimensions in the first direction, and the larger the dimension of the channel layer in the first direction, the larger the dimension of the corresponding portion of the gate surrounding the channel layer in the first direction.

11. The semiconductor device according to claim 10, wherein, Along the direction away from the substrate, the dimension of the multiple channel layers in the first direction gradually decreases, and two opposite side surfaces of the multiple channel layers in the first direction are arranged in a stepped manner; Two opposite side surfaces of the gate are arranged in a stepped manner, and the stepped side surfaces of the gate match the shape of the stepped side surfaces of the multiple channel layers.

12. The semiconductor device according to claim 11, wherein, Further comprising: A sidewall layer disposed on two opposite side surfaces of the gate in the first direction, the surface of the sidewall layer is arranged in a stepped manner, and the stepped surface of the sidewall layer matches the shape of the stepped side surfaces of the gate.

13. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a fin structure on a substrate; the fin structure includes a sacrificial layer and a semiconductor layer alternately stacked in a direction away from the substrate; Forming a dummy gate; The dummy gate straddles the fin structure, and at least two portions of the dummy gate arranged in a direction away from the substrate have different dimensions in a first direction; the first direction is parallel to the substrate; the portion of the fin structure covered by the dummy gate is a channel portion, and the channel portion includes multiple channel layers, and the channel layer is a portion of the semiconductor layer covered by the dummy gate; among the multiple channel layers, at least two channel layers have different dimensions in the first direction; Remove the portion of the fin structure not covered by the dummy gate and replace it with a conductive portion; the conductive portion and the channel portion are alternately arranged in the first direction; Remove the dummy gate and the sacrificial layer and replace them with a gate; the gate is disposed around the surface of each channel layer in the multiple channel layers.

14. An integrated circuit, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 12; An electronic device electrically connected to the semiconductor device.

15. An electronic device, characterized in that, Comprising: The integrated circuit according to claim 14; A circuit board, on which the integrated circuit is disposed.

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