Nitride-based UMOSFET device and preparation method thereof

Abstract

The invention provides a nitride-based UMOSFET (Universal Metal Oxide Semiconductor Field Effect Transistor) device and a preparation method thereof. The nitride-based UMOSFET device comprises a semiconductor structure, a groove gate structure, a source electrode and a drain electrode, wherein the groove gate structure, the source electrode and the drain electrode are matched with the semiconductor structure. The semiconductor structure comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially arranged in a stacked mode in the first direction, and materials of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer comprise n-type nitride, p-type nitride and unintentionally-doped nitride. The groove gate structure comprises a groove which extends from the surface of the semiconductor structure to the bottom end face of the second semiconductor layer or the interior of the third semiconductor layer along the first direction; the grid electrode is at least partially arranged in the groove; the bottom filling layer is arranged at the bottom of the groove; the passivation layer is arranged on the second semiconductor layer on the inner side wall of the groove; and the dielectric layer is at least arranged between the grid electrode and the inner wall of the groove and covers the bottom filling layer. The bottom filling layer is arranged at the bottom of the groove gate structure of the vertical device, so that the voltage withstanding effect of the device is improved, and the breakdown field strength is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a nitride-based UMOSFET device and a preparation method thereof. Background Art

[0002] The core advantage of vertical nitride-based (such as GaN-based) power devices lies in their unique structural design, which concentrates the peak electric field inside the device, effectively improving reliability and reducing the leakage risk. By increasing the thickness of the longitudinal epitaxial layer, the breakdown voltage can be directly increased while maintaining high current density and high reliability, forming a synergistic performance advantage. Its natural enhancement-mode operation avoids the safety hazards of traditional normally-on devices and is suitable for high-voltage and high-current scenario requirements. Compared with other structures, the vertical trench-gate MOSFET (hereinafter referred to as UMOSFET) uses a single-step epitaxial process to construct a three-dimensional conductive channel without a secondary epitaxial step, simplifying the process and reducing costs. Its longitudinal electric field distribution characteristics further expand the theoretical upper limit of the breakdown voltage. In recent years, technological breakthroughs have focused on optimizing the trench-gate structure to improve dynamic performance and stability, promoting the development of devices in high-voltage power electronic systems and high-current density applications.

[0003] Existing methods for treating the sidewalls of the nitride-based UMOSFET trench gates mainly include TMAH wet etching, nitrogen plasma treatment, etc. Among them, although TMAH wet etching can remove dry etching damage, it may not be able to completely eliminate deep or microscopic defects. Wet etching may introduce surface roughness, affecting electrical performance, and the process parameters (time, temperature) need to be strictly controlled, increasing manufacturing complexity. Nitrogen plasma treatment only targets nitrogen vacancy defects and is ineffective for other defects (such as metal contamination, lattice dislocations, etc.). Moreover, it may change the surface chemical state or introduce new defects, resulting in an increase in the interface state density. In addition, due to the presence of the UMOSFET trench gate, the electric field is concentrated inside the device. For the trench gate, the electric field will be concentrated at the right angle at the bottom of the trench, resulting in premature breakdown of the gate oxide layer and the breakdown field strength of the device being less than the theoretical value. Summary of the Invention

[0004] To solve all or part of the above technical problems, the present invention provides the following technical solutions: One object of the present invention is to provide a nitride-based UMOSFET device, including a semiconductor structure and a trench-gate structure, a source electrode, and a drain electrode cooperating with the semiconductor structure; the semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked along a first direction, the material of the first semiconductor layer includes n-type nitride, the material of the second semiconductor layer includes p-type nitride, and the material of the third semiconductor layer includes unintentionally doped nitride; The trench-gate structure includes: A groove that extends from the surface of the semiconductor structure in the first direction into the interior of the third semiconductor layer; A gate, at least a part of which is disposed in the groove; A bottom fill layer disposed at the bottom of the groove; A passivation layer covering the second semiconductor layer on the inner sidewall of the groove; A dielectric layer disposed at least between the gate and the inner wall of the groove and covering the bottom fill layer.

[0005] Due to the characteristics of the trench gate structure, the electric field of the device often concentrates at the right angle at the bottom of the trench gate, causing the dielectric layer to bear too high a voltage at the right angle and resulting in premature breakdown of the device. In the present invention, a bottom fill layer with a preset thickness is disposed at the bottom of the device to protect the dielectric layer from the peak electric field, thereby improving the breakdown field strength.

[0006] The groove extends into the interior of the third semiconductor layer, that is, the bottom of the groove is lower than the bottom end surface of the second semiconductor layer, ensuring normal turn-on of the device, while realizing passivation of the second semiconductor layer on the inner wall of the groove and filling the bottom fill layer at its bottom.

[0007] In some embodiments, the top end surface of the bottom fill layer is flush with or lower than the bottom end surface of the second semiconductor layer, preferably lower than the bottom end surface of the second semiconductor layer, to ensure the forward conduction characteristics of the device.

[0008] In some embodiments, the material of the bottom fill layer is different from the material of the dielectric layer. In this case, the improvement effect on the breakdown voltage and breakdown field strength of the device is better; if the bottom fill layer and the dielectric layer are the same medium, the gate dielectric may be too thick, resulting in poor conduction performance of the device or even insulation.

[0009] In some embodiments, the material of the bottom fill layer includes SiN x , silicon oxide, or a combination of one or more of curable insulating polymers.

[0010] Further, the curable insulating polymer includes at least one of polyimide (PI glue) and ethylene-octene copolymer (EOC).

[0011] In some embodiments, the thickness of the bottom fill layer is 100 nm - 600 nm. The bottom fill layer with this thickness can protect the dielectric layer from the peak electric field, thereby improving the breakdown field strength.

[0012] In some embodiments, the material of the dielectric layer includes any one or a combination of Al2O3, Si3N4, silicon oxide, AlN, or HfO2, but is not limited thereto.

[0013] In some embodiments, the thickness of the dielectric layer is 10 nm - 80 nm.

[0014] In some embodiments, the dielectric layer is further disposed on at least a partial top surface of the semiconductor structure, for example, on at least a partial top surface of the first semiconductor layer.

[0015] In some embodiments, the passivation layer is formed by in-situ conversion of a portion of the second semiconductor layer adjacent to the inner sidewall of the groove. The method of in-situ conversion includes performing plasma treatment (H-plasma) and annealing treatment in sequence. The plasma treatment includes at least one of hydrogen plasma treatment or nitrogen plasma treatment.

[0016] In the embodiment using hydrogen plasma treatment, after H-Plasma treatment, H exists on the surface of the second semiconductor layer on the sidewall of the groove gate. Further diffusion of H is achieved through annealing, and a neutral complex is formed with acceptor impurities in the second semiconductor layer, thereby forming a passivation layer. Since H-plasma is gaseous, it can fully contact the sidewall of the groove. Therefore, the in-situ formed passivation layer can completely cover the second semiconductor layer on the sidewall of the groove, or in other words, convert the portion of the second semiconductor layer originally exposed inside the groove into a passivation layer. And due to the nature of H-plasma itself, it only acts on the second semiconductor layer on the sidewall of the groove, and the formed passivation layer is located on the surface of the second semiconductor layer on the inner sidewall of the groove. The formation of the passivation layer can effectively reduce the leakage current of the groove gate sidewall, improve the field-effect mobility, and the drain current density.

[0017] In the embodiment using nitrogen plasma treatment, the nitrogen plasma can fill the nitrogen vacancies caused by etching.

[0018] The nitride-based UMOSFET device provided by the present invention is simultaneously provided with a passivation layer covering the second semiconductor layer on the inner wall of the groove and a bottom filling layer filled at the bottom of the groove. By such a setting, not only can the electric field concentration at the bottom of the groove gate be improved, but also the overall trend of the electric field distribution in the drift region can be avoided from being changed, without affecting the forward conduction of the device, significantly enhancing the breakdown characteristics of the device, and also improving the current density of the device, so that the comprehensive performance of the device is synergistically enhanced.

[0019] In some embodiments, the material of the passivation layer includes a neutral complex, and the neutral complex is formed by the semiconductor material of the second semiconductor layer located on the sidewall of the groove contacting with hydrogen plasma and nitrogen plasma and undergoing annealing treatment.

[0020] Further, the neutral complex includes (H-Mg)0. For example, the acceptor impurity in the p-type nitride of the second semiconductor layer includes Mg, which is in-situ converted to (H-Mg)0 during the H-plasma process.

[0021] In some embodiments, the shape of the groove of the grooved gate structure may be a U-shaped groove.

[0022] In some embodiments, the thickness of the first semiconductor layer is 190-210 nm.

[0023] In some embodiments, the material of the first semiconductor layer includes n-type GaN.

[0024] In some embodiments, the thickness of the second semiconductor layer is 490-510 nm.

[0025] In some embodiments, the material of the second semiconductor layer includes p-type GaN.

[0026] In some embodiments, the acceptor impurity in the p-type nitride of the second semiconductor layer includes Mg.

[0027] In some embodiments, the thickness of the third semiconductor layer is 3900-4100 nm.

[0028] In some embodiments, the material of the third semiconductor layer includes unintentionally doped GaN, typically n - -GaN.

[0029] In some embodiments, the source electrode is in ohmic contact with the first semiconductor layer.

[0030] In some embodiments, the semiconductor structure further includes a fourth semiconductor layer. The fourth semiconductor layer is disposed on a side of the third semiconductor layer away from the second semiconductor layer. The material of the fourth semiconductor layer includes n-type nitride, and the drain electrode is in ohmic contact with the fourth semiconductor layer.

[0031] Further, the thickness of the fourth semiconductor layer is 900-1100 nm.

[0032] In the present invention, the materials of the source electrode, the drain electrode, and the gate electrode can be any materials known in the art, and the present invention does not make special limitations thereon. For example, it includes one or more of Au, Ti, Ni, and Al.

[0033] In some embodiments, the semiconductor structure further includes a substrate. The first direction is perpendicular to the surface of the substrate and towards the substrate. In some embodiments, the semiconductor structure includes a substrate and a fourth semiconductor layer, a third semiconductor layer, a second semiconductor layer, and a first semiconductor layer sequentially disposed on the substrate.

[0034] The material of the substrate used in the present invention can be any material known in the art, which can be a homogeneous substrate or a heterogeneous substrate, including but not limited to GaN, sapphire, Si, SiC, etc.

[0035] The second object of the present invention is to provide a method for manufacturing a nitride-based UMOSFET device, including: Providing a semiconductor structure, the semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked along a first direction, the material of the first semiconductor layer includes n-type nitride, the material of the second semiconductor layer includes p-type nitride, and the material of the third semiconductor layer includes unintentionally doped nitride; Processing a groove on the semiconductor structure, and making the groove extend from the surface of the semiconductor structure to the inside of the third semiconductor layer along the first direction; Forming a bottom filling layer at the bottom of the groove; Making a part of the second semiconductor layer adjacent to the inner sidewall of the groove undergo in-situ transformation to form a passivation layer; Forming a dielectric layer at least on the inner sidewall of the groove and the bottom filling layer; Covering a gate material at least on the dielectric layer of the groove to form a gate at least partially located in the groove, and fabricating a source electrode and a gate electrode cooperating with it on the semiconductor structure.

[0036] Among them, the order of forming the bottom filling layer and the passivation layer is not limited. In some embodiments, the bottom filling layer can be formed first, and then the passivation layer is formed; in other embodiments, the passivation layer can be formed first, and then the bottom filling layer is formed.

[0037] The method of processing a groove on the semiconductor structure can adopt any known method in the art, such as etching with a Cl-based gas or the like. When etching, it can be etched from the top surface of the semiconductor structure, and the etching depth should reach at least the bottom end surface of the second GaN layer. The shape of the groove can be a U-shaped groove.

[0038] In some embodiments, it further includes a step of annealing the semiconductor structure with a groove. Annealing can activate acceptor impurities such as Mg in the second semiconductor layer. The specific process conditions of annealing can be processes known in the art, which should be obvious to those of ordinary skill in the art after reading the present invention and will not be elaborated herein.

[0039] In some embodiments, it further includes a step of wet etching the semiconductor structure with grooves after dry etching to repair the damage generated inside the grooves due to dry etching and obtain an ideal groove gate morphology. The specific process conditions of the wet etching can be processes known in the art, which should be obvious to those of ordinary skill in the art after reading the present invention and will not be elaborated herein.

[0040] In some embodiments, the preparation method specifically includes: performing plasma treatment on the inner sidewalls of the grooves, where the plasma treatment includes at least one of hydrogen plasma treatment and nitrogen plasma treatment; then annealing the structure obtained after the plasma treatment to in-situ transform a part of the second semiconductor layer adjacent to the inner sidewalls of the grooves to form the passivation layer. The hydrogen plasma treatment can also reduce defect states and / or dangling bonds, and the nitrogen plasma can fill the nitrogen vacancies caused by etching.

[0041] Furthermore, the power of the plasma treatment is 2 - 5 W and the time is 5 - 8 min.

[0042] Furthermore, the annealing treatment specifically includes: annealing for 5 - 6 min under the temperature condition of 350 - 355 °C in a protective atmosphere. To ensure the stability of nitrides such as GaN and avoid material decomposition or introduction of other impurities, the annealing is carried out in a protective atmosphere such as a nitrogen atmosphere.

[0043] Under the above process conditions of hydrogen plasma and annealing treatment, a passivation layer with a suitable thickness (about 5 nm) can be formed. On the basis of achieving a certain degree of isolation leakage, repairing etching damage, and improving the current density, it can prevent the H passivation effect from being too deep and reducing the effective area of the device.

[0044] In some embodiments, the material of the passivation layer includes a neutral complex.

[0045] Furthermore, the neutral complex includes (H - Mg)0.

[0046] In some embodiments, the top surface of the bottom filling layer is flush with or lower than the bottom end surface of the second semiconductor layer.

[0047] In some embodiments, the material of the bottom filling layer includes SiN x , silicon oxide, or a combination of one or more of curable insulating polymers, and the material of the bottom filling layer is different from the material of the dielectric layer.

[0048] Furthermore, the curable insulating polymer includes at least one of polyimide (PI glue) and ethylene - octene copolymer (EOC), but is not limited thereto.

[0049] In some embodiments, the thickness of the bottom-fill layer is 100 nm - 600 nm.

[0050] In embodiments where the material of the bottom-fill layer includes SiN x , silicon oxide, methods for forming a bottom-fill layer at the bottom of the groove include atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD). After deposition, the bottom-fill layer material at non-ideal positions can be removed, such as removing the material that is not deposited at the bottom within the groove gate and the material covering the top surface of the semiconductor structure, so that the bottom-fill layer is only formed at the bottom of the groove. The specific process conditions of ALD and PECVD can be processes known in the art, which should be obvious to those of ordinary skill in the art after reading the present invention, and will not be elaborated herein. In embodiments where the bottom-fill layer is a curable insulating polymer, the method for forming a fill layer at the bottom of the groove includes: coating the curable insulating polymer in the groove, and then performing high-temperature curing and etching to fill it at the bottom of the groove.

[0051] Further, specifically, it includes: filling the interior of the groove with the curable insulating polymer at least, curing at a temperature of 200 °C to 230 °C, and then etching with O2-Plasma to form a bottom-fill layer with a preset thickness at the bottom of the groove.

[0052] In some embodiments, it further includes forming a dielectric layer on at least a part of the top surface of the first semiconductor layer.

[0053] In some embodiments, the material of the dielectric layer includes any one or a combination of more of Al2O3, Si3N4, silicon oxide, AlN, or HfO2.

[0054] In some embodiments, the thickness of the dielectric layer is 10 nm - 80 nm.

[0055] The method for forming the dielectric layer can be a method known in the art, such as ALD, etc. The deposition process should be obvious to those of ordinary skill in the art after reading the present invention, and will not be elaborated herein.

[0056] In some embodiments, the material of the first semiconductor layer includes n-type GaN.

[0057] In some embodiments, the thickness of the first semiconductor layer is 190 - 210 nm.

[0058] In some embodiments, the material of the second semiconductor layer includes p-type GaN.

[0059] In some embodiments, the acceptor impurities in the p-type nitride of the second semiconductor layer include Mg.

[0060] In some embodiments, the thickness of the second semiconductor layer is 490 - 510 nm.

[0061] In some embodiments, the material of the third semiconductor layer includes unintentionally doped GaN.

[0062] In some embodiments, the thickness of the third semiconductor layer is 3900 - 4100 nm.

[0063] In some embodiments, the semiconductor structure further includes a fourth semiconductor layer disposed on a side of the third semiconductor layer away from the second semiconductor layer. The material of the fourth semiconductor layer includes n-type nitride; a source electrode in ohmic contact with the first semiconductor layer is fabricated on the first semiconductor layer, and a drain electrode in ohmic contact with the fourth semiconductor layer is fabricated on the fourth semiconductor layer.

[0064] Further, the thickness of the fourth semiconductor layer is 900 - 1100 nm.

[0065] In some embodiments, the manufacturing method of the semiconductor structure may include: sequentially depositing the fourth semiconductor layer, the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer on a substrate. The material of the substrate used may be any material known in the art, and may be a homo-substrate or a hetero-substrate, including but not limited to GaN, sapphire, Si, and SiC, etc.

[0066] Compared with the prior art, the present invention has at least the following beneficial effects: By filling a bottom filling layer at the bottom of the groove gate structure of the nitride-based UMOSFET device, the present invention can improve the electric field concentration at the bottom of the groove gate, protect the dielectric layer from the peak electric field, enhance the breakdown field strength, and at the same time avoid changing the overall trend of the electric field distribution in the drift region and not affect the forward conduction of the device.

[0067] The nitride-based UMOSFET device provided by the present invention is simultaneously provided with a passivation layer covering the inner wall of the groove of the second semiconductor layer and a bottom filling layer filled at the bottom of the groove, which can simultaneously improve the current density and breakdown voltage of the device and synergistically enhance the comprehensive performance of the device.

[0068] The present invention applies the H-plasma passivation technology to the passivation treatment of the sidewalls of the UMOSFET groove gate. By in-situ forming a neutral complex on the sidewall structure of the groove gate, not only the passivation process is more stable, avoiding adverse effects such as incomplete passivation layer coating caused by processes such as photoresist stripping, but also the heat dissipation is better and the integration space is more saved. Finally, the current density of the UMOSFET device can be effectively improved and the sidewall interface states can be reduced. Brief Description of the Drawings

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0070] Figure 1 is a schematic structural diagram of a vertical UMOSFET device in Embodiment 1 of the present invention; Figure 2 is a process schematic diagram of H-plasma passivation of the groove gate sidewall of the vertical UMOSFET device in Embodiment 1 of the present invention; 1 - First GaN layer, 2 - Second GaN layer, 3 - Third GaN layer, 4 - Substrate, 5 - Source electrode, 6 - Gate electrode, 7 - Drain electrode, 8 - Dielectric layer, 9 - Bottom filling layer, 10 - Fourth GaN layer, 11 - Groove, 12 - Passivation layer. Detailed Description of the Specific Embodiments

[0071] The following will detail the technical solutions of the present invention in combination with specific embodiments, so that those skilled in the art can better understand and implement the technical solutions of the present invention. The specific functional details disclosed herein should not be construed as restrictive, but only as the basis of the claims and as a representative basis for teaching those skilled in the art to adopt the present invention in any appropriate detailed embodiment in different ways.

[0072] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0073] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including the recited number, and above, below, within, etc. are understood as including the recited number. If the first and second are described only for the purpose of distinguishing technical features, they should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0074] In the description of the present invention, unless otherwise clearly defined, terms such as "arrangement", "installation", and "connection" should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution. The technical solution of the present invention will be further described below in conjunction with the drawings and embodiments.

[0075] In addition, unless otherwise specified, various raw materials used in the following embodiments can be obtained from the market or other channels, and various production and testing equipment used are also equipment known in the art, and the testing methods used are also methods known in the art.

[0076] Embodiment 1 This embodiment provides a structure of a nitride-based vertical device and a preparation method thereof, specifically as follows: Figure 1 is a schematic structural diagram of the nitride-based vertical device in this embodiment, as Figure 1 shown, which includes a semiconductor structure and a grooved gate structure, a source electrode, and a drain electrode that cooperate with the semiconductor structure, wherein the grooved gate structure is a grooved gate structure with a bottom filling.

[0077] The semiconductor structure includes a substrate 4 and a fourth GaN layer 10, a third GaN layer 3, a second GaN layer 2, and a first GaN layer 1 that are sequentially arranged thereon in a direction away from the substrate 4; wherein the materials of the fourth GaN layer 10 and the first GaN layer 1 are heavily doped n-type GaN, the material of the second GaN layer 2 is p-type GaN, and the material of the third semiconductor layer 3 is unintentionally doped GaN.

[0078] The semiconductor structure is provided with a groove 11, and the groove 11 extends from the surface of the first GaN layer 1 to the inside of the third GaN layer 3.

[0079] A bottom filling layer 9 is provided on the bottom of the groove 11, and the top surface of the bottom filling layer 9 is lower than the bottom surface of the second GaN layer 2. In this embodiment, the material of the bottom filling layer 9 is silicon oxide and the thickness is 500 nm.

[0080] A passivation layer 12 is formed on the second GaN layer 2 on the inner sidewall of the groove 11, and the passivation layer 12 is formed in situ by the conversion of the part of the second GaN layer 2 adjacent to the inner sidewall of the groove 11 during the hydrogen plasma treatment and annealing process. In this embodiment, the material of the second GaN layer 2 is Mg-doped p-type GaN, and during the hydrogen plasma and annealing treatment, it is converted into (H-Mg)0 neutral complexes, that is, the material of the passivation layer 12 includes (H-Mg)0.

[0081] A part of the gate 6 is disposed in the groove 11, and a continuously disposed dielectric layer 8 is provided between the gate 6 and the inner wall of the groove 11, forming a MOS structure with the gate 6. Specifically, the dielectric layer 8 continuously covers the inner sidewall of the groove 11 and the bottom filling layer 9 of the groove 11, and is also formed on the surface of the first GaN layer 1. The material of the dielectric layer 8 in this embodiment is aluminum oxide, and the thickness is 50 nm.

[0082] The source electrode 5 and the drain electrode 7 respectively form ohmic contacts with the first GaN layer and the fourth GaN layer.

[0083] Figure 2 It is a schematic flow chart of the manufacturing process of the above nitride-based vertical device. The manufacturing method of the device is as follows: (1) Use metalorganic chemical vapor deposition (MOCVD) to sequentially grow a fourth GaN layer 10, a third GaN layer 3, a second GaN layer 2, and a first GaN layer 1 on the GaN substrate 4 to form a semiconductor structure. Among them, the material of the first GaN layer 1 is Si-doped n-type GaN, and the doping concentration is 5E18 cm -3 , and the thickness is 200 nm; the material of the second GaN layer 2 is Mg-doped p-type GaN, and the doping concentration is 3E17 cm -3 , and the thickness is 500 nm; the third GaN layer 3 is unintentionally doped GaN, and the thickness is 4000 nm; the material of the fourth GaN layer 10 is Si-doped n-type GaN, and the thickness is 1000 nm.

[0084] (2) Use Cl-based gas to etch the semiconductor structure to form a groove 11, and the etching depth is such that the groove 11 extends from the top surface of the first GaN layer 1 to the inside of the third GaN layer 3, as shown in Figure 2 2a in.

[0085] (3) Anneal the semiconductor structure with the groove 11 obtained by the above etching under a protective atmosphere at a temperature of 850 °C for 30 min to deactivate the Mg acceptor impurities in the second GaN layer 2; then perform wet etching treatment to repair the damage generated inside the groove gate due to dry etching.

[0086] (4) Deposit silicon oxide in the groove 11 by PECVD method and remove the silicon oxide material at non-ideal positions, so as to form a bottom filling layer 9 with a thickness of 500 nm only at the bottom of the groove, which is used to improve the electric field distribution at the bottom of the groove gate, thereby improving the breakdown voltage effect of the device and increasing the breakdown field strength, as shown in Figure 2 2b and 2c in.

[0087] (5) The inner sidewalls of the groove 11 are processed using H-plasma to ensure full contact between the H-plasma and the inner walls of the groove 11. The power of the H-plasma is 2 W, and the processing time is 5 min, so that H exists on the surface of the second semiconductor layer on the sidewalls of the groove gate. After the H-plasma treatment, annealing is performed in a protective gas atmosphere at 350 °C for 5 min to promote further diffusion of H and react with Mg in the second GaN layer 2 to form (H-Mg)0, thereby forming the passivation layer 12, as shown in Figure 2 2d in

[0088] (6) The atomic layer deposition (ALD) method is used to deposit a continuously covering dielectric layer 8 with a thickness of 50 nm and a material of aluminum oxide on the upper surface of the first GaN layer 1, the inner sidewalls of the groove 11, and the bottom filling layer 9, as shown in Figure 2 2e in

[0089] (7) The dielectric layer 11 on the surface of the first GaN layer 1 is windowed by dry etching in the source region as the window for depositing the source electrode. Ti / Al / Ni / Au is used as the source electrode and deposited on the first GaN layer 1 to form an ohmic contact; the drain electrode metal Ti / Al / Ni / Au is deposited on the fourth GaN layer 10 to form an ohmic contact, as shown in Figure 2 2f in

[0090] (8) The gate metal is deposited on the dielectric layer 11 in the groove 11 to fabricate a Ti / Au gate partially disposed in the groove 11, as shown in Figure 2 2g in

[0091] Example 2 Example 2 is basically the same as Example 1, except that in Example 2, the material of the bottom filling layer 9 is ethylene-octene copolymer (EOC).

[0092] The manufacturing process specifically includes: spin-coating EOC in the groove to fill the inside of the groove gate, heating it to 230 °C to cure it, and then etching it with O2-Plasma to form an EOC filling layer with a thickness of 500 nm at the bottom of the groove. The rest is the same as in Example 1 and will not be elaborated here.

[0093] Example 3 Example 3 is basically the same as Example 1, except that in Example 2, the material of the bottom filling layer 9 is polyimide (PI glue).

[0094] The manufacturing process is specifically as follows: Spin-coat PI glue in the groove to fill the inside of the groove grid, heat it to 200 °C for curing, and then etch it through O2-Plasma to form a PI glue filling layer with a thickness of 100 nm at the bottom of the groove. The rest is implemented in the same way as in Example 1 and will not be elaborated here.

[0095] Example 4 Example 4 is basically the same as Example 1, except that the material of the bottom filling layer 9 in Example 4 is SiN x , with a thickness of 600 nm. The rest is implemented in the same way as in Example 1 and will not be elaborated here.

[0096] Example 5 Example 5 is basically the same as Example 1, except that step (4) of Example 5 is as follows: Use H-plasma to treat the inner sidewall of the groove 11 to make H-plasma fully contact with the inner wall of the groove 11. The power of H-plasma is 5 W and the treatment time is 8 min, so that H exists on the surface of the second semiconductor layer on the sidewall of the groove grid; after H-plasma treatment, in a protective gas atmosphere, anneal at 355 °C for 6 min to promote the further diffusion of H and react with Mg in the second GaN layer 2 to form (H-Mg)0, thereby forming a passivation layer 12. The rest is implemented in the same way as in Example 1 and will not be elaborated here.

[0097] Comparative Example 1 The difference between the device of Comparative Example 1 and Example 1 is that it does not have a passivation layer 12, that is, the step of treating the sidewall of the groove with H-Plasma is not carried out during the preparation process.

[0098] By comparing Example 1 and Comparative Example 1, it is found that the current density of the device treated with H-Plasma is doubled, the threshold voltage is slightly reduced, and the switching current ratio is reduced by one order of magnitude.

[0099] Comparative Example 2 The difference between the device of Comparative Example 2 and Example 1 is that it does not have a bottom filling layer 9. At this time, the dielectric layer 8 continuously covers the sidewall and bottom of the groove 11.

[0100] By comparing Example 1 and Comparative Example 2, it is found that the breakdown voltage of the device with a bottom filling layer 9 is increased by 1.5 times and the gate leakage is slightly reduced.

[0101] Comparative Example 3 The difference between the device of Comparative Example 3 and Example 1 is that it does not have a passivation layer 12 and a bottom filling layer 9.

[0102] Comparing Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3, it is found that using H-Plasma for passivation and simultaneously filling the bottom of the groove grid can effectively improve the current density and breakdown voltage, while reducing the switching current ratio.

[0103] The nitride-based UMOSFET device provided by the present invention is simultaneously provided with a passivation layer covering the inner wall of the groove of the second semiconductor layer and a bottom filling layer filled at the bottom of the groove. By such a setting, the electric field concentration at the bottom of the groove grid can be improved, while avoiding changing the overall trend of the electric field distribution in the drift region, without affecting the forward conduction of the device, and greatly enhancing the breakdown characteristics of the device.

[0104] All aspects, embodiments, features, and examples of the present invention should be considered illustrative in all respects and are not intended to limit the present invention. The scope of the present invention is only defined by the claims. Without departing from the spirit and scope of the claimed invention, those skilled in the art will understand other embodiments, modifications, and uses.

[0105] In addition, the inventors of this case also referred to the foregoing embodiments and conducted tests with other raw materials, process operations, and process conditions described in this specification, and all obtained relatively ideal results.

[0106] Although the present invention has been described with reference to illustrative embodiments, those skilled in the art will understand that various other changes, omissions, and / or additions can be made without departing from the spirit and scope of the present invention, and elements of the embodiments can be replaced with substantial equivalents. In addition, many modifications can be made without departing from the scope of the present invention to adapt a particular situation or material to the teachings of the present invention. Therefore, the present invention is not intended to be limited to the specific embodiments disclosed for carrying out the present invention, but is intended to include all embodiments within the scope of the appended claims. In addition, unless specifically stated, any use of the terms first, second, etc. does not indicate any order or importance, but the terms first, second, etc. are used to distinguish one element from another element.

Claims

1. A nitride-based UMOSFET device, characterized in that: It includes a semiconductor structure, a grooved gate structure, a source electrode, and a drain electrode that cooperate with the semiconductor structure; the semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer that are sequentially stacked along a first direction, the material of the first semiconductor layer includes an n-type nitride, the material of the second semiconductor layer includes a p-type nitride, and the material of the third semiconductor layer includes an unintentionally doped nitride; The grooved gate structure includes: A groove that extends from the surface of the semiconductor structure into the interior of the third semiconductor layer along the first direction; A gate electrode, at least a part of which is disposed in the groove; A bottom filling layer disposed at the bottom of the groove; A passivation layer that covers the second semiconductor layer on the inner sidewall of the groove; A dielectric layer that is at least disposed between the gate electrode and the inner wall of the groove and covers the bottom filling layer.

2. The nitride-based UMOSFET device according to claim 1, wherein: The top end surface of the bottom filling layer is flush with or lower than the bottom end surface of the second semiconductor layer; And / or, the material of the underfill layer includes SiN x , one or a combination of silica or curable insulating polymers, and the material of the underfill layer is different from that of the dielectric layer. Preferably, the curable insulating polymer includes at least one of polyimide and ethylene-octene copolymer; And / or, the material of the dielectric layer includes any one or a combination of more than one of Al2O3, Si3N4, silicon oxide, AlN, or HfO2; And / or, the thickness of the bottom filling layer is 100 nm - 600 nm; And / or, the thickness of the dielectric layer is 10 nm - 80 nm.

3. The nitride-based UMOSFET device according to claim 1, wherein: The passivation layer is formed by in-situ conversion of a part of the second semiconductor layer adjacent to the inner sidewall of the groove, and the method of in-situ conversion includes sequentially performing plasma treatment and annealing treatment, and the plasma treatment includes at least one of hydrogen plasma treatment or nitrogen plasma treatment; And / or, the material of the passivation layer includes a neutral complex, preferably, the neutral complex includes (H - Mg)0.

4. The bottom-fill groove gate structure according to claim 1, wherein: The material of the first semiconductor layer includes n-type GaN; And / or, the material of the second semiconductor layer includes p-type GaN; And / or, the acceptor impurity in the p-type nitride of the second semiconductor layer includes Mg; And / or, the material of the third semiconductor layer includes unintentionally doped GaN.

5. The nitride-based UMOSFET device according to claim 1, characterized in that: The source electrode is in ohmic contact with the first semiconductor layer; And / or, the semiconductor structure further includes a fourth semiconductor layer, the fourth semiconductor layer is disposed on a side of the third semiconductor layer away from the second semiconductor layer, the material of the fourth semiconductor layer includes an n-type nitride, and the drain electrode is in ohmic contact with the fourth semiconductor layer.

6. A method for fabricating a nitride-based UMOSFET device, characterized in that, It includes: Providing a semiconductor structure, the semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer that are sequentially stacked along a first direction, the material of the first semiconductor layer includes an n-type nitride, the material of the second semiconductor layer includes a p-type nitride, and the material of the third semiconductor layer includes an unintentionally doped nitride; Processing a groove on the semiconductor structure and making the groove extend from the surface of the semiconductor structure into the interior of the third semiconductor layer along the first direction; Forming a bottom filling layer at the bottom of the groove; Subjecting a part of the second semiconductor layer adjacent to the inner sidewall of the groove to in-situ conversion to form a passivation layer; Form a dielectric layer on at least the inner sidewall of the groove and the bottom filling layer; Cover a gate material on at least the dielectric layer of the groove to form a gate at least partially located in the groove, and fabricate a source electrode and a gate electrode that cooperate with it on the semiconductor structure.

7. The preparation method according to claim 6, characterized in that, Make the top surface of the bottom filling layer flush with or lower than the bottom surface of the second semiconductor layer; And / or, the material of the underfill layer includes SiN x , one or a combination of silica or curable insulating polymers, and the material of the underfill layer is different from the material of the dielectric layer. Preferably, the curable insulating polymer includes at least one of polyimide and ethylene-octene copolymer; And / or, the dielectric layer is made of any one or a combination of more than one of Al2O3, Si3N4, silicon oxide, AlN or HfO2; And / or, the thickness of the bottom filling layer is 100 nm - 600 nm; And / or, the thickness of the dielectric layer is 10 nm - 80 nm; And / or, the passivation layer is made of a neutral complex, preferably including (H-Mg)0; And / or, the first semiconductor layer is made of n-type GaN; And / or, the second semiconductor layer is made of p-type GaN; And / or, the acceptor impurity in the p-type nitride of the second semiconductor layer includes Mg; And / or, the third semiconductor layer is made of unintentionally doped GaN.

8. The preparation method according to claim 6, characterized in that, Specifically include: Perform plasma treatment on the inner sidewall of the groove. The plasma treatment includes at least one of hydrogen plasma treatment and nitrogen plasma treatment; then perform annealing treatment on the structure obtained by the plasma treatment to in-situ transform the part of the second semiconductor layer adjacent to the inner sidewall of the groove to form the passivation layer.

9. The preparation method according to claim 8, characterized in that: The power of the plasma treatment is 2 - 5 W, and the treatment time is 5 - 8 min; And / or, the annealing treatment specifically includes: annealing for 5 - 6 min under the temperature condition of 350 - 355 °C in a protective atmosphere.

10. The preparation method according to claim 6, characterized in that: The semiconductor structure further includes a fourth semiconductor layer. The fourth semiconductor layer is disposed on a side of the third semiconductor layer away from the second semiconductor layer. The fourth semiconductor layer is made of an n-type nitride; fabricate a source electrode in ohmic contact with the first semiconductor layer and a drain electrode in ohmic contact with the fourth semiconductor layer on the fourth semiconductor layer.

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