Semiconductor device

Abstract

A semiconductor device includes a substrate having a first conductivity type; the epitaxial layer is arranged on the substrate, and the epitaxial layer has a second conduction type different from the first conduction type; the buried layer structure is arranged in the substrate, and the buried layer structure has a second conduction type; and the first high-voltage well is arranged in the epitaxial layer, and the first high-voltage well has the first conduction type. The semiconductor device further includes a well disposed in the first high-voltage well, where the well has a second conductivity type; the source electrode region is arranged in the well, and the source electrode region has the first conduction type; and the second high-voltage well is arranged in the epitaxial layer, and the second high-voltage well has a second conduction type. The second high-voltage well directly contacts the buried layer structure and the well at the same time.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to the configuration of buried layers and high-voltage wells. Background Art

[0002] The technology of high-voltage semiconductor devices is applicable to microwave / radio frequency power amplifiers. Conventional high-voltage semiconductor devices, such as vertically diffused metal-oxide semiconductor (VDMOS) transistors and laterally diffused metal-oxide semiconductor (LDMOS) transistors, are mainly used in device application fields above 12V. The advantages of high-voltage semiconductor devices are cost-effectiveness and easy compatibility with other processes, and they have been widely used in display driver integrated circuit devices, power supplies, power management, communications, automotive electronics, or industrial control and other fields.

[0003] Although existing high-voltage semiconductor devices generally meet their original uses, they are not satisfactory in all aspects. For example, breakdown voltage, vertical punch-through voltage, and on-state resistance need to be further improved. Therefore, there are still some problems to be overcome regarding high-voltage semiconductor devices and manufacturing technologies. Summary of the Invention

[0004] A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer structure disposed in the substrate, wherein the buried layer structure has the second conductivity type; and a first high-voltage well disposed in the epitaxial layer, wherein the first high-voltage well has the first conductivity type. The semiconductor device further includes: a well disposed in the first high-voltage well, wherein the well has the second conductivity type; a source region disposed in the well, wherein the source region has the first conductivity type; and a second high-voltage well disposed in the epitaxial layer, wherein the second high-voltage well has the second conductivity type. The second high-voltage well directly contacts both the buried layer structure and the well at the same time.

[0005] The present invention can provide a high-voltage well at the source end, which can cooperate with the buried layer structure of the prior art to strengthen the electrical grounding at the source end, effectively isolate the current flowing from the drain end, and balance the charge flowing from the drain end. Such a configuration can replace the substrate end of traditional semiconductor devices and the required circuit space, thereby meeting the market's continuous requirement for device size miniaturization. Description of the Drawings

[0006] The following will detail various aspects of the embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, the sizes of the various devices can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0007] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to some comparative examples.

[0008] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to other comparative examples.

[0009] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0010] Figure 4 is a drain current-voltage curve graph of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 5 is an electric field-position curve graph of a semiconductor device according to some embodiments of the present invention.

[0012] Symbol Description

[0013] 10: Semiconductor device

[0014] 20: Semiconductor device

[0015] 30: Semiconductor device

[0016] 40: Drain current-voltage curve graph

[0017] 50: Electric field-position curve graph

[0018] 100: Substrate

[0019] 102: Epitaxial layer

[0020] 104: Buried layer structure

[0021] 106: First buried layer

[0022] 106-1: First buried layer

[0023] 106-2: First buried layer

[0024] 108-1: Second buried layer

[0025] 108-2: Second buried layer

[0026] 108-3: Second buried layer

[0027] 110: First high-voltage well

[0028] 112: Second high-voltage well

[0029] 114: Well

[0030] 116-1: Drift region

[0031] 116-2: Drift region

[0032] 122: Heavily doped region

[0033] 124-1: Source region

[0034] 124-2: Source region

[0035] 126-1: Drain region

[0036] 126-2: Drain region

[0037] 132-1: Isolation structure

[0038] 132-2: Isolation structure

[0039] 134-1: Isolation structure

[0040] 134-2: Isolation structure

[0041] 136-1: Gate structure

[0042] 136-2: Gate structure

[0043] 140: Interlayer dielectric layer

[0044] 142: Via hole

[0045] 144-1: Via hole

[0046] 144-2: Via hole

[0047] 152: Source electrode

[0048] 154-1: Drain electrode

[0049] 154-2: Drain electrode Detailed implementation manners

[0050] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description that the first component is formed on the second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present invention may repeat device symbols and / or letters in various examples. Such repetition is for the purpose of simplification and clarity and does not itself dictate the relationship between the various embodiments and / or configurations being discussed.

[0051] In addition, in some embodiments of the present invention, terms related to joining and connecting, such as "connect", "interconnect", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between these two structures.

[0052] Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship between a device or component and other devices or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientation shown in the figures. When the device is rotated to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein may be interpreted accordingly in the rotated orientation.

[0053] The terms "about", "approximately", "substantially" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or ±3%, or ±2%, or ±1%, or 0.5%. The given value is an approximate value, that is, even without specifically stating "about", "approximately", "substantially", the given value may still implicitly imply the meaning of "about", "approximately", "substantially".

[0054] Some embodiments of the present invention are described below, in which additional steps may be provided before, during, and / or after the described multiple stages. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the steps discussed in the embodiments are performed in a specific order, these steps may still be performed in another logical order.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is understood that such terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with the context of the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in an embodiment of this invention.

[0056] The semiconductor device of the present invention illustrates an embodiment of a high-voltage integrated circuit, particularly an embodiment of a laterally diffused metal-oxide semiconductor (LDMOS) transistor. In the prior art, generally, by adjusting the doping concentration and structural profile of each semiconductor region of the laterally diffused metal-oxide semiconductor transistor in the process, the laterally diffused metal-oxide semiconductor transistor can generate a sufficiently high breakdown voltage and vertical punch-through voltage, as well as a sufficiently low on-state resistance, to further optimize the overall performance. However, in an actual process, such as in a bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) process, adjusting the doping concentration or structural profile of the semiconductor region may require the use of additional mask plates, resulting in an increase in the overall manufacturing cost. In addition, in order to achieve effective isolation and electrical grounding, a large area is generally consumed to form one or more wells. In this way, although the semiconductor device can ensure acceptable performance, it cannot meet the market's continuous requirement for device size miniaturization.

[0057] To improve the breakdown voltage, vertical punchthrough voltage, and on-resistance of a laterally diffused metal oxide semiconductor transistor, prior art has added a dual-diffused buried layer structure with a stepped profile in the diffused metal oxide semiconductor transistor. The buried layer structure not only traverses the source and drain regions of the transistor but also includes components extending downward to different junction depths. In other words, the buried layer structure can increase both the vertically assisted depletion layer (VADL) and the laterally assisted depletion layer (LADL), thereby improving the breakdown voltage, vertical punchthrough voltage, and on-resistance of the overall device. A laterally diffused metal oxide semiconductor transistor with a high breakdown voltage, vertical punchthrough voltage, and low on-resistance can also be widely applied in fields such as lighting, flat panel displays, audio, switched-mode power supplies, and power control.

[0058] Generally speaking, a laterally diffused metal oxide semiconductor transistor has electrical grounding at two ends: the source end and the substrate end. The source end can serve as the electrical grounding for the active components on the surface of the epitaxial layer, while the substrate end can establish an electrical grounding that penetrates the epitaxial layer and reaches the substrate. The electrical grounding at both ends enables the device to achieve good isolation during operation and can maintain the balance of the charges flowing through the drain end, thereby exhibiting excellent and stable breakdown voltage performance. To achieve good isolation, the substrate end needs to be separated from the source end by a sufficient distance, thus occupying a large amount of circuit space.

[0059] Since the buried layer structure of the prior art can significantly improve the breakdown voltage, vertical punchthrough voltage, and on-resistance of the overall device, embodiments of the present invention further omit the substrate end and the required circuit space for miniaturization purposes. It can be imagined that removing the substrate end and the required circuit space will impact the breakdown voltage, vertical punchthrough voltage, and on-resistance of the overall device. To cope with the lost performance, the inventors found that an additional high-voltage well can be configured between the source end in the epitaxial layer and the buried layer structure on the lower surface of the epitaxial layer as compensation for the good isolation lost due to the omission of the substrate end. In addition, to further demonstrate a more efficient use of circuit space, embodiments of the present invention configure two transistors connected in series with each other to present an array-type structure, and the two transistors share the same source end. The active components with two transistors are also referred to as laterally "double"-diffused metal oxide semiconductor transistors. Furthermore, before entering the embodiments of the present invention, two comparative examples will be discussed in this case to more specifically illustrate the advantages and necessity of configuring the additional high-voltage well.

[0060] Figure 1FIG. 0 is a cross-sectional schematic view of a semiconductor device 10 according to some comparative examples. In some embodiments, the semiconductor device may include any number of active components and passive components. The active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, lateral-diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, planar transistors, fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), other similar devices, or combinations thereof. The passive components include metal traces, capacitors, inductors, resistors, diodes, bond pads, or other similar structures. For simplicity, Figure 1 only an exemplary lateral double-diffused metal-oxide semiconductor transistor is depicted.

[0061] Referring Figure 1 , the semiconductor device 10 may include a substrate 100, an epitaxial layer 102, a buried layer structure 104, isolation structures 132-1, isolation structures 132-2, isolation structures 134-1, isolation structures 134-2, gate structures 136-1, gate structures 136-2, an interlayer dielectric (ILD) 140, via holes 142, via holes 144-1, via holes 144-2, a source electrode 152, a drain electrode 154-1, and a drain electrode 154-2. In some embodiments, the epitaxial layer 102 may include a first high-voltage well 110. The first high-voltage well 110 may include a well 114, drift regions 116-1, and drift regions 116-2. The well 114 may include a heavily doped region 122, source regions 124-1, and source regions 124-2. The drift regions 116-1 and the drift regions 116-2 may include drain regions 126-1 and drain regions 126-2, respectively. Furthermore, the buried layer structure 104 may include a first buried layer 106, second buried layers 108-1, and second buried layers 108-2.

[0062] ReferringFigure 1 , the substrate 100 may be, for example, a wafer or a die, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. Additionally, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

[0063] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide (BOX) layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. In addition, the substrate 100 may be of a first conductivity type or a second conductivity type different from the first conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be doped with appropriate dopants (or impurities) individually. P-type dopants may include boron (B), indium (In), aluminum (Al), or gallium (Ga), while N-type dopants may include phosphorus (P) or arsenic (As). In a specific embodiment of the present invention, the substrate 100 may be of the first conductivity type (P-type), and its doping concentration is between 1×10 19 cm -3 and 3×10 19 cm -3 between.

[0064] In other embodiments, the substrate 100 may include isolation structures (not shown) to define active regions and electrically isolate active region components within or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structures may include deep trench isolation (DTI) structures, shallow trench isolation (STI) structures, or local oxidation of silicon (LOCOS) structures. In some embodiments, forming the isolation structures may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form trenches extending from the top surface of the substrate 100 to a position within the substrate 100, where the trenches are located between adjacent active regions. Then, forming the isolation structures may include growing a liner rich in nitrogen (such as silicon oxynitride (SiON) or other similar materials) along the trenches, and then filling the trenches with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. After that, an annealing process is performed on the insulating material in the trenches, and a planarization process (such as chemical mechanical polish (CMP)) is performed on the substrate 100 to remove the excess insulating material, so that the insulating material in the trenches is flush with the top surface of the substrate 100.

[0065] Continue to refer to Figure 1 , an epitaxial layer 102 is formed on the substrate 100. According to some embodiments of the present invention, the epitaxial layer 102 has a second conductivity type (N-type), and its doping concentration is between 1.13×10 15 cm -3 and 2.30×10 15 cm -3 . In a specific embodiment of the present invention, the substrate 100 and the epitaxial layer 102 may have different conductivity types, and the doping concentration of the substrate 100 is greater than that of the epitaxial layer 102. The material of the epitaxial layer 102 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 102 may be between 3 μm and 7 μm. The epitaxial layer 102 can be formed by an epitaxial process, which may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

[0066] Refer to Figure 1 , the semiconductor device 10 includes a buried layer structure 104 disposed in the substrate 100 and the epitaxial layer 102, which includes a first buried layer 106, a second buried layer 108-1, and a second buried layer 108-2. Since the second buried layer 108-1 / second buried layer 108-2 and the subsequently formed drift regions 116-1 / drift regions 116-2 can be formed by the same mask, even though the buried layer structure 104 has two different components, the number of masks required for the entire semiconductor device 10 will not increase, so the manufacturing cost or cycle will not increase significantly. In some embodiments, the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 have a second conductivity type (N-type). According to some embodiments of the present invention, the first buried layer 106 is laterally adjacent to the second buried layer 108-1 and the second buried layer 108-2, and the bottom surfaces of the second buried layer 108-1 and the second buried layer 108-2 are lower than the bottom surface of the first buried layer 106. In some alternative embodiments, the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 may be laterally separated, depending on application and design requirements.

[0067] The formation method of the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 may include ion implanting an N-type dopant (such as phosphorus or arsenic) into the substrate 100 before forming the epitaxial layer 102, performing a heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 102 on the substrate 100. In some embodiments, since the epitaxial layer 102 is formed under high-temperature conditions, the implanted ions will diffuse into the epitaxial layer 102. As Figure 1 shown, the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 are located near the interface between the substrate 100 and the epitaxial layer 102, and have a part in the substrate 100 and another part in the epitaxial layer 102. In other words, the buried layer structure 104 can extend upward from the interface between the substrate 100 and the epitaxial layer 102. Since the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 undergo diffusion in the same epitaxial process, the overall top of the buried layer structure 104 can have a planarized surface.

[0068] The function of the first buried layer 106 is to provide relatively complete isolation under the source region, which helps prevent leakage current and further improve the breakdown voltage of the overall device. The position of the first buried layer 106 can be regarded as the high-side region of the semiconductor device 10. In some embodiments, the doping concentration of the first buried layer 106 can be between 1×10 15 cm -3 and 5×10 15 cm -3 . According to some embodiments of the present invention, the doping concentration of the first buried layer 106 is higher than that of the second buried layer 108-1 and the second buried layer 108-2. By design, in addition to having a relatively high doping concentration, the dopant distribution of the first buried layer 106 is relatively dense. Therefore, the vertical dimension of the first buried layer 106 is smaller than the vertical dimensions of the second buried layer 108-1 and the second buried layer 108-2. The vertical dimension of the first buried layer 106 is between 4 μm and 5 μm. The lateral dimension of the first buried layer 106 can cross the well 114 formed in the first high-voltage well 110 subsequent to the epitaxial layer 102. The degree of lateral extension depends on the requirements of depletion region isolation. According to some embodiments, a complete depletion region can reduce leakage current and improve the breakdown voltage, vertical punch-through voltage, and on-resistance of the overall device.

[0069] The functions of the second buried layers 108-1 and 108-2 are to provide a relatively large junction depth below the drift region, enabling the depletion region to expand in the vertical direction to increase the vertical punch-through voltage. The positions of the second buried layers 108-1 and 108-2 can be regarded as the low-side regions of the semiconductor device 10. Furthermore, the junction depth can be the junction region between the epitaxial layer 102 and the substrate 100, which is defined by the buried layer structure 104. In some embodiments, the doping concentrations of the second buried layers 108-1 and 108-2 can be between 1.5×10 15 cm -3 and 4.5×10 15 cm -3 . As described above, the doping concentration of the first buried layer 106 is higher than that of the second buried layers 108-1 and 108-2. By design, in addition to having a relatively low doping concentration, the dopant distribution of the second buried layers 108-1 and 108-2 is relatively dispersed. Therefore, the vertical dimensions of the second buried layers 108-1 and 108-2 are approximately twice as large as the vertical dimensions of the first buried layer 106, that is, they have a wider junction, which can more effectively prevent leakage current between the drift region and the underlying substrate. It should be noted that since the first high-voltage well 110 formed subsequently on the second buried layers 108-1 and 108-2 has a very high doping concentration, the dopants of the second buried layers 108-1 and 108-2 do not diffuse upward but diffuse into the substrate 100 with a lower doping concentration below. That is to say, the top surfaces of the first buried layer 106 and the second buried layers 108-1 and 108-2 can be maintained substantially coplanar with each other.

[0070] According to some embodiments of the present invention, the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2 of the buried layer structure 104 have a stepped profile at the bottom due to different dopant distributions. The buried layer structure 104 can simultaneously possess the characteristics of a continuous structure and double diffusion. The junction depths of the second buried layer 108-1 and the second buried layer 108-2 are greater than the junction depth of the first buried layer 106, such that the portions of the depletion regions located below the drift regions 116-1 and 116-2 can further extend downward. In some embodiments, the drift regions 116-1 and 116-2 can be regarded as the regions between the gate extreme and the drain extreme, and thus have a crucial impact on the overall device performance. When the depletion regions below the drift regions 116-1 and 116-2 extend downward, the regions between the drift regions 116-1 and 116-2 and the depletion regions below them become larger, thereby creating a larger electric field. The reduced surface field (RESURF) effect on the epitaxial layer 102 can also be enhanced. The buried layer structure 104 can achieve a continuous structure, a gradual change in doping concentration, and an extension of the depletion region. When the doping concentration and the electric field can be more balancedly controlled, the depletion region can be more completely "depleted", which helps to optimize the characteristics of the overall device.

[0071] Continuing to refer to Figure 1 , a first high-voltage well 110 can be formed within the epitaxial layer 102. The first high-voltage well 110 vertically extends from the top surface of the epitaxial layer 102 to the interface between the epitaxial layer 102 and the substrate 100 or the interface between the epitaxial layer 102 and the buried layer structure 104. According to some embodiments of the present invention, the first high-voltage well 110 can be of the first conductive type (P-type). The first high-voltage well 110 can be formed by, for example, ion implantation and / or diffusion process. In alternative embodiments, instead of using ion implantation and / or diffusion process, the first high-voltage well 110 can be doped in situ during the growth of the epitaxial layer 102. In other embodiments, in-situ and implant doping can be used together.

[0072] The first high-voltage well 110 can completely cover the first buried layer 106, the second buried layer 108-1, and the second buried layer 108-2. In some embodiments, the doping concentration of the first high-voltage well 110 can be between 7×10 15 cm -3 and 9×10 15 cm -3Therebetween. The first high-voltage well 110 may include a subsequently formed well 114, a drift region 116-1, and a drift region 116-2, which further include a source region 124-1 and a source region 124-2, a drain region 126-1, and a drain region 126-2, respectively. Furthermore, subsequently formed gate structures 136-1 and 136-2 are also disposed on the surface of the first high-voltage well 110 of the epitaxial layer 102. The gate structure 136-1 may be laterally located between the source region 124-1 and the drain region 126-1, and the gate structure 136-2 may be laterally located between the source region 124-2 and the drain region 126-2.

[0073] Referring to Figure 1 , the well 114, the drift region 116-1, and the drift region 116-2 may be formed within the first high-voltage well 110, which may extend downward from the top surface of the first high-voltage well 110. According to some embodiments of the present invention, the well 114 may be of a second conductive type (N-type), and the drift regions 116-1 and 116-2 may be of a first conductive type (P-type). The well 114, the drift region 116-1, and the drift region 116-2 may be laterally separated. The formation method of the well 114, the drift region 116-1, and the drift region 116-2 may be similar to the formation method of the first high-voltage well 110, and the details thereof will not be repeated herein.

[0074] The well 114 may be located above the first buried layer 106. In some embodiments, the doping concentration of the well 114 may be between 1×10 16 cm -3 and 2×10 16 cm -3 Therebetween. The well 114 may include a subsequently formed heavily doped region 122, a source region 124-1, and a source region 124-2. The thickness of the well 114 may be between 2.0 μm and 2.5 μm. Since the well 114 is located at the source end that needs to be electrically grounded, it is necessary to ensure that the well 114 is not "depleted" during operation to avoid electrical short circuits caused by leakage current flowing from the drain end.

[0075] The drift regions 116-1 and 116-2 can be respectively located above the second buried layers 108-1 and 108-2. As previously mentioned, the drift regions 116-1 and 116-2 can respectively have the same lateral dimensions as the second buried layers 108-1 and 108-2. Therefore, the same mask can be used during the manufacturing process to further reduce the manufacturing cost. The drift regions 116-1 and 116-2 can enable the semiconductor device 10 to generate a long depletion region under high-voltage operation, thereby reducing the phenomenon of excessive electric field concentration and improving the breakdown voltage. In addition, the doping of the drift regions 116-1 and 116-2 also determines the on-resistance of the semiconductor device 10. In some embodiments, the doping concentrations of the drift regions 116-1 and 116-2 can be between 7×10 15 cm -3 and 8×10 15 cm -3 . The drift regions 116-1 and 116-2 can respectively include the subsequently formed drain regions 126-1 and 126-2. The thicknesses of the drift regions 116-1 and 116-2 can be between 2 μm and 4 μm.

[0076] Continuing to refer to Figure 1 , a heavily doped region 122, a source region 124-1, and a source region 124-2 can be formed in the well 114, which can extend downward from the top surface of the well 114. According to some embodiments of the present invention, the heavily doped region 122 can be of the second conduction type (N-type), while the source regions 124-1 and 124-2 can be of the first conduction type (P-type). The heavily doped region 122, the source region 124-1, and the source region 124-2 can be laterally adjacent to each other, and the heavily doped region 122 can be laterally located between the source region 124-1 and the source region 124-2. The formation methods of the heavily doped region 122, the source region 124-1, and the source region 124-2 can be similar to the formation method of the first high-voltage well 110, and the details will not be repeated here.

[0077] In some embodiments, the doping concentration of the heavily doped region 122 can be between 1.0×10 19 cm -3 and 1.5×10 19 cm -3Therebetween. The heavily doped region 122 can be simultaneously coupled to the subsequently formed source electrode 152 together with the source region 124-1 or the source region 124-2. The thickness of the heavily doped region 122 can be between 0.2 μm and 0.5 μm. The heavily doped region 122 having the second conductivity type can achieve charge balance with the source regions 124-1 and 124-2 having the first conductivity type, and provide an ohmic contact of the second conductivity type for the source electrode 152. In addition, since the well 114 and the heavily doped region 122 have the same conductivity type, the heavily doped region 122 can serve as the source end body connecting the source regions 124-1 and 124-2, and play a key role in the electrical grounding of the source end.

[0078] In some embodiments, the doping concentrations of the source regions 124-1 and 124-2 can be between 2×10 18 cm -3 and 2×10 19 cm -3 Therebetween. The thicknesses of the source regions 124-1 and 124-2 can be between 0.2 μm and 0.5 μm. Forming the source regions 124-1 and 124-2 of the first conductivity type within the well 114 of the second conductivity type can form a bipolar junction, which can further improve the state of charge balance, and the expected depletion region will be "depleted" more completely.

[0079] Referring to Figure 1 , drain regions 126-1 and 126-2 can be respectively formed within the drift regions 116-1 and 116-2, which can extend downward from the top surfaces of the drift regions 116-1 and 116-2. According to some embodiments of the present invention, the drain regions 126-1 and 126-2 can be of the first conductivity type (P-type). In some embodiments, the doping concentrations of the drain regions 126-1 and 126-2 can be between 2×10 18 cm -3 and 2×10 19 cm -3 Therebetween. The thicknesses of the drain regions 126-1 and 126-2 can be between 0.3 μm and 0.6 μm. The drain regions 126-1 and 126-2 can be respectively coupled to the subsequently formed drain electrodes 154-1 and 154-2. The forming methods of the drain regions 126-1 and 126-2 can be similar to the forming method of the first high-voltage well 110, and the details will not be repeated here.

[0080] Continuing to refer to Figure 1, isolation structures 132-1, 132-2, 134-1, and 134-2 can be formed on the epitaxial layer 102. Specifically, since their manufacturing process involves high-temperature treatment, isolation structures 132-1, 132-2, 134-1, and 134-2 are partially embedded in the epitaxial layer 102. According to some embodiments of the present invention, isolation structures 132-1, 132-2, 134-1, and 134-2 can be drift oxides (DOX) used to isolate various conductive components to avoid electrical short circuits during the operation of the semiconductor device 10.

[0081] As Figure 1 shown, the well 114 of the first high-voltage well 110, and the subsequently formed gate structures 136-1 and 136-2 can be located laterally between the isolation structure 132-1 and the isolation structure 132-2. It should be noted that the gate structure 136-1 can extend on a partial surface of the isolation structure 132-1, and the gate structure 136-2 can extend on a partial surface of the isolation structure 132-2. The isolation structure 132-1 can laterally isolate the source region 124-1 and the drain region 126-1. The isolation structure 132-2 can laterally isolate the source region 124-2 and the drain region 126-2. The drain region 126-1 of the drift region 116-1 can be located laterally between the isolation structure 132-1 and the isolation structure 134-1. The drain region 126-2 of the drift region 116-2 can be located laterally between the isolation structure 132-2 and the isolation structure 134-2.

[0082] In some embodiments, isolation structures 132-1, 132-2, 134-1, and 134-2 can be formed of silicon oxide (SiO), which can be local oxidation of silicon isolation structures formed by thermal oxidation. In other embodiments, isolation structures 132-1, 132-2, 134-1, and 134-2 can be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

[0083] Referring to Figure 1, after the isolation structures 132-1, 132-2, 134-1, and 134-2 are formed, the gate structures 136-1 and 136-2 can be formed on the epitaxial layer 102. The gate structure 136-1 can extend horizontally from the well 114 over the first high-voltage well 110 and reach the drift region 116-1. The gate structure 136-2 can extend horizontally from the well 114 over the first high-voltage well 110 and reach the drift region 116-2. The portion of the epitaxial layer 102 or the portion of the well 114 contacted by the gate structures 136-1 and 136-2 can be regarded as the channel region of the semiconductor device 10, and the gate structures 136-1 and 136-2 can serve as the gate terminals of the active components. According to some embodiments of the present invention, the source region 124-1, the drain region 126-1, and the gate structure 136-1 form a transistor of the first conductivity type (P-type) (hereinafter referred to as the first transistor), and the source region 124-2, the drain region 126-2, and the gate structure 136-2 form another transistor of the first conductivity type (P-type) (hereinafter referred to as the second transistor). The first transistor and the second transistor can together constitute, for example, a lateral double-diffused metal oxide semiconductor transistor and have a channel region of the second conductivity type (N-type). The thickness of the gate structures 136-1 and 136-2 can be between 0.25 μm and 0.30 μm. In some embodiments, the gate structures 136-1 and 136-2 can include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. In other embodiments, the semiconductor device 10 can have a transistor of the second conductivity type (N-type) and a channel region of the first conductivity type (P-type), and be paired with a buried layer structure of the first conductivity type (P-type), but such a configuration is less common in the industry.

[0084] The material of the gate dielectric layer may include a high dielectric constant (high-k) dielectric material (e.g., a material having a K value greater than 7), which may include hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (Al2O3), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO2), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride, or other suitable high dielectric constant materials. The gate dielectric layers of gate structure 136-1 and gate structure 136-2 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), other similar methods, or a combination thereof.

[0085] The material of the gate electrode may include amorphous silicon, polysilicon, poly - SiGe, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metals may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, their combinations, or their multi - layer films. The gate electrodes of gate structure 136 - 1 and gate structure 136 - 2 can be formed by physical vapor deposition (PVD), atomic layer deposition, plating, other suitable processes, or their combinations.

[0086] Continuing to refer to Figure 1 , an inter - layer dielectric layer 140 can be formed on the epitaxial layer 102. In some embodiments, the inter - layer dielectric layer 140 can cover the isolation structures 132 - 1, isolation structures 132 - 2, isolation structures 134 - 1, isolation structures 134 - 2, gate structure 136 - 1, and gate structure 136 - 2. The inter - layer dielectric layer 140 can not only provide mechanical protection and insulation for the underlying components, but also isolate different levels of conductive materials. The material of the inter - layer dielectric layer 140 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO x N y C 1-x - y, where x and y range from 0 to 1), tetraethyl orthosilicate (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials.

[0087] The thickness of the interlayer dielectric layer 140 can be between and . The interlayer dielectric layer 140 can be formed by spin-on coating, chemical vapor deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Then, a planarization process (such as chemical mechanical polishing) can be performed on the interlayer dielectric layer 400 to make the interlayer dielectric layer 400 have a flat top surface.

[0088] Refer to Figure 1, via holes 142, via holes 144-1, and via holes 144-2 can be formed to penetrate through the interlayer dielectric layer 140. The via holes 142, via holes 144-1, and via holes 144-2 can physically contact the heavily doped region 122 and the source regions 124-1 / source regions 124-2, the drain region 126-1, and the drain region 126-2 respectively. In addition, a source electrode 152, a drain electrode 154-1, and a drain electrode 154-2 can be formed on the interlayer dielectric layer 140. In some embodiments, the source electrode 152 is electrically coupled to the heavily doped region 122 and the source regions 124-1 / source regions 124-2 through the via hole 142, the drain electrode 154-1 is electrically coupled to the drain region 126-1 through the via hole 144-1, and the drain electrode 154-2 is electrically coupled to the drain region 126-2 through the via hole 144-2. The source electrode 152 and the drain electrode 154-1 can serve as the source terminal and the drain terminal of the first transistor respectively, while the source electrode 152 and the drain electrode 154-2 can serve as the source terminal and the drain terminal of the second transistor respectively. The first transistor and the second transistor are connected in series with each other to present an array-type structure, and the first transistor and the second transistor share the same source electrode 152.

[0089] The via holes 142, via holes 144-1, via holes 144-2, source electrode 152, drain electrode 154-1, and drain electrode 154-2 can be integrally formed and thus include the same material, which can be similar to the material of the gate electrodes of the gate structures 136-1 and 136-2, the details of which will not be repeated here. First, a plurality of openings can be formed in the interlayer dielectric layer 140, corresponding to the heavily doped region 122 and the source regions 124-1 / source regions 124-2, the drain region 126-1, and the drain region 126-2 respectively. Then, the above-mentioned material can be deposited blanketly on the interlayer dielectric layer 140 through a suitable deposition process. The above-mentioned material is not only formed on the surface of the interlayer dielectric layer 140 but also filled into all the openings to form the via holes 142, via holes 144-1, and via holes 144-2. The deposited film layer can be patterned by a photolithography process followed by an etching process to form the source electrode 152, the drain electrode 154-1, and the drain electrode 154-2. The photolithography process can include coating photoresist, soft baking, exposure, post-exposure baking, development, other similar techniques, or a combination thereof. The etching process can include dry etching, wet etching, other similar methods, or a combination thereof. Based on the integrally formed process, the source electrode 152, the drain electrode 154-1, and the drain electrode 154-2 can have substantially the same thickness, which can be between and between.

[0090] Figure 2A cross-sectional schematic view of the semiconductor device 20 in accordance with other comparative examples. Compared with Figure 1 , the buried layer structure 104 of the semiconductor device 20 includes another second buried layer 108-3 below the well 114. The substrate 100, epitaxial layer 102, buried layer structure 104, first high-voltage well 110, well 114, drift regions 116-1, drift regions 116-2, heavily doped region 122, source regions 124-1, source regions 124-2, drain regions 126-1, drain regions 126-2, isolation structures 132-1, isolation structures 132-2, isolation structures 134-1, isolation structures 134-2, gate structures 136-1, gate structures 136-2, interlayer dielectric layer 140, via holes 142, via holes 144-1, via holes 144-2, source electrodes 152, drain electrodes 154-1, and drain electrodes 154-2 are similar to those Figure 1 shown, and the details thereof will not be repeated here.

[0091] Referring to Figure 2 , the buried layer structure 104 includes a first buried layer 106-1, a first buried layer 106-2, a second buried layer 108-1, a second buried layer 108-2, and a second buried layer 108-3. The second buried layer 108-3 can be regarded as separating Figure 1 the first buried layer 106 into a first buried layer 106-1 and a first buried layer 106-2. Since the junction depth of the second buried layer 108-3 is greater than the junction depths of the first buried layer 106-1 and the first buried layer 106-2, it can cause the part of the depletion region below the well 114 (including the heavily doped region 122, the source regions 124-1, and the source regions 124-2) to further extend downward. Such a configuration can enhance the vertical diffusion of the depletion region near the source end. As previously described, the drift regions 116-1 and the drift regions 116-2 can have the same lateral dimensions as the second buried layer 108-1 and the second buried layer 108-2 respectively, so the same mask can be used in the manufacturing process to further reduce the manufacturing cost. In some embodiments, the second buried layer 108-3 can have the same lateral dimension as the heavily doped region 122, so the same mask can be used in the manufacturing process to further reduce the manufacturing cost.

[0092] Figure 3 A cross-sectional schematic view of the semiconductor device 30 in accordance with some embodiments of the present invention. Compared with Figure 1, the epitaxial layer 102 of the semiconductor device 30 further includes a second high-voltage well 112. The substrate 100, epitaxial layer 102, buried layer structure 104, first high-voltage well 110, well 114, drift regions 116-1, drift regions 116-2, heavily doped regions 122, source regions 124-1, source regions 124-2, drain regions 126-1, drain regions 126-2, isolation structures 132-1, isolation structures 132-2, isolation structures 134-1, isolation structures 134-2, gate structures 136-1, gate structures 136-2, interlayer dielectric layer 140, via holes 142, via holes 144-1, via holes 144-2, source electrodes 152, drain electrodes 154-1, and drain electrodes 154-2 are similar to those Figure 1 shown, and their details will not be repeated here.

[0093] Referring to Figure 3 , the second high-voltage well 112 can be disposed in the epitaxial layer 102. The second high-voltage well 112 can be laterally surrounded by the first high-voltage well 110. In addition, the second high-voltage well 112 is vertically located between the buried layer structure 104 and the well 114. In some embodiments, the second high-voltage well 112 directly contacts the first buried layer 106 of the buried layer structure 104 and the well 114 at the same time. The first buried layer 106 can laterally extend beyond both sides of the second high-voltage well 112. According to some embodiments of the present invention, the second high-voltage well 112 can be of the second conductive type (N-type). Since the second high-voltage well 112 and the well 114 are located at the source end that needs to be electrically grounded, it is necessary to ensure that the second high-voltage well 112 and the well 114 are not "depleted" during operation to avoid an electrical short circuit caused by the leakage current flowing from the drain end. In addition, the well 114, the second high-voltage well 112, and the buried layer structure 104 (such as the first buried layer 106) span the entire thickness of the epitaxial layer 102 in the vertical direction and all have the second conductive type (N-type). Such a configuration can strengthen the electrical grounding to the substrate 100 for the source end and isolate the current flowing from the drain end more effectively, which can be used as compensation for the loss of good isolation due to the omission of the substrate end of the conventional structure.

[0094] Continuing to refer to Figure 3 , the second high-voltage well 112 vertically extends from the lower surface of the well 114 to the upper surface of the buried layer structure 104 (such as the first buried layer 106). In some embodiments, the doping concentration of the second high-voltage well 112 can be between 6.9×10 15 cm -3 and 1.3×10 16 cm -3Between. The thickness of the second high-voltage well 112 can be between 2.5 μm and 2.8 μm. In the absence of the second high-voltage well 112, since the doping concentration of the well 114 is relatively low, its diffusion is not likely to reach the buried layer structure 104 (such as the first buried layer 106) below, and good isolation cannot be formed at the source extreme during operation. On the other hand, the vertical diffusion of the buried layer structure 104 may reach the well 114 above, but the leakage current on the surface of the epitaxial layer 102 cannot be avoided due to insufficient doping concentration.

[0095] According to some embodiments of the present invention, the implantation of the second high-voltage well 112 can increase the doping concentration near the surface of the epitaxial layer 102. When the second high-voltage well 112 is combined with the buried layer structure 104, relatively complete isolation can be provided for the semiconductor device 30, which helps to prevent leakage current in the off state. In other words, the source extreme of the semiconductor device 30 can have both the buried layer structure 104 diffusing upward and the second high-voltage well 112 diffusing downward. The second high-voltage well 112 can be formed by, for example, ion implantation and / or diffusion processes. In an alternative embodiment, instead of using ion implantation and / or diffusion processes, the second high-voltage well 112 can be doped in-situ during the growth of the epitaxial layer 102. In other embodiments, in-situ and implantation doping can be used together.

[0096] In this case, the semiconductor devices 10, 20, and 30 are compared. The design features are listed and the electrical parameters are measured. The relevant data are summarized in Table 1.

[0097] Table 1

[0098]

[0099] In Table 1, the design features and electrical parameters of the conventional semiconductor device are listed for reference. In the conventional semiconductor device, the lateral dimension of the well 114 (including the heavily doped region 122, the source region 124-1, and the source region 124-2) is 6.65 μm. Since the conventional semiconductor device has only a single transistor, there is only one measured breakdown voltage value. In contrast, since the semiconductor devices 10, 20, and 30 all include a first transistor and a second transistor, the breakdown voltage 1 and the breakdown voltage 2 in Table 1 correspond to the first transistor and the second transistor respectively.

[0100] As previously mentioned, to meet the market's ever - increasing demand for device size miniaturization, in addition to omitting the substrate bottom end and its required circuit space, the sizes of other components may also need to be appropriately adjusted. The inventor takes the lateral dimension of the well 114 as an example and measures and collects electrical parameters at three experimental sizes. According to some embodiments of the present invention, the space from the left edge of the source region 124 - 1 to the left edge of the well 114 can be used as the channel region of the first transistor, and the space from the right edge of the source region 124 - 2 to the right edge of the well 114 can be used as the channel region of the second transistor. Regardless of how much the lateral dimension of the well 114 is miniaturized, the size of the channel region cannot be changed, otherwise, the short channel effect will occur, which will in turn affect the performance of the semiconductor device. When the size of the well 114 is set to 3μm (which is the minimum allowable value of the current manufacturing technology and the most severe operating condition), the sizes of the heavily doped region 122, the source region 124 - 1, and the source region 124 - 2 are all 0.5μm, and the channel regions of the first transistor and the second transistor are both 0.75μm (which are fixed size values).

[0101] In some embodiments, the semiconductor device 10 can be regarded as a structure in which a conventional semiconductor device with a buried layer structure 104 directly omits the substrate bottom end and its required circuit space (and another transistor is connected in series). In addition, the semiconductor device 20 can be regarded as a structure in which the semiconductor device 10 is added with a second buried layer 108 - 3 at the source end. Furthermore, the semiconductor device 30 can be regarded as a structure in which the semiconductor device 10 is added with a second high - voltage well 112 at the source end. It should be understood that both the semiconductor device 20 and the semiconductor device 30 are upgraded versions of the semiconductor device 10. Since the semiconductor device 10 has shown good performance when the size of the well 114 is 7μm, the inventor omits the electrical measurement of the semiconductor device 20 and the semiconductor device 30 when the size of the well 114 is 7μm. In other words, under the same size conditions, if the semiconductor device 10 has shown good performance, the upgraded semiconductor devices 20 and 30 should also be able to show good performance.

[0102] In some embodiments, when the size of well 114 is scaled down to 5 μm, semiconductor devices 10, 20, and 30 still exhibit acceptable performance. However, when the size of well 114 is scaled down to 3 μm, the performance of semiconductor devices 10 and 20 is significantly impacted. Since the size scaling of well 114 may directly compress the depletable space and the regions to be isolated within epitaxial layer 102, semiconductor device 10 cannot achieve complete depletion under the condition that the size of well 114 is 3 μm. Although the second buried layer 108-3 of semiconductor device 20 can improve the diffusion of the depletion region, the impact ionization between electrons and holes cannot be concentrated at the drain end, resulting in leakage current. The second high-voltage well 112 of semiconductor device 30 can avoid the leakage current in the off state near the surface of epitaxial layer 102 at the source end, and the buried layer structure 104 can electrically ground the source end to substrate 100, thereby effectively compensating for the loss of good isolation due to the omission of the substrate end of the conventional structure. Therefore, the performance of semiconductor device 30 still exhibits the same level as that of the conventional semiconductor device when the size of well 114 is 3 μm.

[0103] It should be understood that the lateral double-diffused metal-oxide semiconductor transistor according to the embodiments of the present invention needs to operate at 120V. With an additional 10% buffer range, the lateral double-diffused metal-oxide semiconductor transistor should have a breakdown voltage of at least 132V. According to other embodiments of the present invention, the lateral dimensions of isolation structures 132-1 and 132-2 can also respectively affect the breakdown voltages of the first transistor and the second transistor. When the lateral dimensions of isolation structures 132-1 and 132-2 are 10 μm, the breakdown voltages of the first transistor and the second transistor of semiconductor device 30 can both exceed -150V. In other words, each 1 μm of isolation structure 132-1 or 132-2 can contribute a breakdown voltage of more than -15V. If it is necessary to reduce the on-resistance of semiconductor device 30, the pitch of the first transistor and the second transistor can be reduced by shrinking the lateral dimensions of isolation structures 132-1 and 132-2 to reduce the on-resistance. Since the breakdown voltage exhibited by semiconductor device 30 has a considerable margin compared to the minimum standard of 132V, reducing the isolation structure 132-1 and / or isolation structure 132-2 by 1 μm to 2 μm can still maintain an acceptable breakdown voltage. Therefore, the lateral dimensions of isolation structure 132-1 and / or isolation structure 132-2 can be appropriately adjusted to optimize the on-resistance. In other words, depending on the application and design requirements, an appropriate trade-off can be made between the breakdown voltage and the on-resistance.

[0104] Figure 4According to some embodiments of the present invention, the drain current-voltage curve of the semiconductor device is shown in FIG. 40. According to some embodiments of the present invention, the drain current-voltage curve in FIG. 40 compares the performance of semiconductor device 10, semiconductor device 20, and semiconductor device 30. Semiconductor device 10 only omits the substrate end and its required circuit space in the structure of the conventional semiconductor device, so its transistors experience early breakdown during operation. Although semiconductor device 20 solves the problem of early breakdown, it still has an excessive leakage current. The semiconductor device 30 of the embodiments of the present invention can exhibit excellent breakdown voltage and leakage current in the off state. Since the well 114, the second high-voltage well 112, and the buried layer structure 104 achieve electrical grounding extending from the epitaxial layer 102 to the substrate 100 at the source end, the semiconductor device 30 can have a breakdown voltage close to -160V.

[0105] Figure 5 According to some embodiments of the present invention, the electric field-position curve of the semiconductor device is shown in FIG. 50. According to some embodiments of the present invention, the electric field-position curve in FIG. 50 compares the performance of semiconductor device 10, semiconductor device 20, and semiconductor device 30. It should be noted that the breakdown voltages of the first transistor and the second transistor depend on the integral value of the overall electric field curve. In some embodiments, the peak value of the electric field spike should not exceed 3.0×10 5 V / cm, otherwise it is easy to cause device damage. When the spike of the electric field is too high, it is necessary to optimize the overall electric field to obtain a better balanced distribution. Due to early breakdown, semiconductor device 10 only has a relatively low spike at the source end. The electric field distribution of semiconductor device 20 is relatively normal, but it is inferior to the electric field performance of semiconductor device 30. The semiconductor device 30 exhibits spikes with a peak value of approximately 2.6×10 5 V / cm in the drift region 116-1, the drift region 116-2, the drain region 126-1, and the drain region 126-2, and thus has good reliability. Therefore, the semiconductor device 30 has good isolation and enhanced electrical grounding, thereby improving the breakdown voltage and leakage current.

[0106] The present invention can set a high-voltage well at the source extreme, which can be combined with the buried layer structure of the prior art to strengthen the electrical grounding of the source extreme, effectively isolate the current flowing from the drain extreme, and maintain the balance of the charge flowing from the drain extreme. Such a configuration can replace the substrate end of the traditional semiconductor device and the required circuit space, thereby meeting the continuous market demand for device size miniaturization. The source extreme can include a well, a high-voltage well, and a buried layer structure, vertically spanning the entire thickness of the epitaxial layer. Since the well, the high-voltage well, and the buried layer structure all have the same conduction type, the electrical grounding of the source extreme can extend from the epitaxial layer to the substrate. The high doping concentration of the high-voltage well can effectively suppress the leakage current on the upper surface of the epitaxial layer. When configuring an array type structure in which two transistors are connected in series with each other, the high-voltage well of the present invention can still keep the source extreme well isolated to optimize the characteristics of the overall device.

[0107] The above outlines the features of several embodiments so that those skilled in the art can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate having a first conductivity type; An epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; A buried layer structure disposed within the substrate, wherein the buried layer structure has the second conductivity type; A first high-voltage well disposed in the epitaxial layer, wherein the first high-voltage well has the first conductivity type; A well disposed in the first high-voltage well, wherein the well has the second conductivity type; A source region disposed in the well, wherein the source region has the first conductivity type; and A second high-voltage well disposed in the epitaxial layer, wherein the second high-voltage well has the second conductivity type, and the second high-voltage well is in direct contact with both the buried layer structure and the well simultaneously.

2. The semiconductor device according to claim 1, wherein The well extends downward from the upper surface of the epitaxial layer, while the buried layer structure extends upward from the interface between the substrate and the epitaxial layer.

3. The semiconductor device according to claim 2, wherein, The second high-voltage well is vertically located between the buried layer structure and the well.

4. The semiconductor device according to claim 1, wherein The buried layer structure further comprises: A first buried layer located below the well; and A second buried layer laterally adjacent to the first buried layer.

5. The semiconductor device according to claim 4, wherein The bottom surface of the second buried layer is lower than the bottom surface of the first buried layer.

6. The semiconductor device according to claim 5, wherein, The bottom of the buried layer structure has a stepped shape.

7. The semiconductor device according to claim 4, characterized in that, The top of the buried layer structure has a planarized surface.

8. The semiconductor device according to claim 4, wherein, The doping concentration of the first buried layer is higher than that of the second buried layer.

9. The semiconductor device according to claim 4, wherein, The second high-voltage well is in direct contact with the first buried layer of the buried layer structure.

10. The semiconductor device according to claim 4, wherein Further comprising a drift region disposed in the first high-voltage well, wherein the drift region has the first conductivity type, and the second buried layer is located below the drift region.

11. The semiconductor device according to claim 10, wherein, The lateral dimension of the second buried layer is equal to the lateral dimension of the drift region.

12. The semiconductor device according to claim 10, wherein, Further comprising a drain region disposed in the drift region, wherein the drain region has the first conductivity type.

13. The semiconductor device according to claim 12, wherein, Further comprising a gate structure disposed on the epitaxial layer and laterally located between the source region and the drain region.

14. The semiconductor device according to claim 13, characterized in that, The gate structure extends laterally from above the well to above the drift region.

15. The semiconductor device according to claim 13, wherein, Further comprising an isolation structure disposed on the drift region and laterally located between the drain region and the gate structure.

16. The semiconductor device according to claim 13, wherein, The source region, the drain region, and the gate structure constitute a transistor of the first conductivity type.

17. The semiconductor device according to claim 13, wherein, Further comprising a heavily doped region disposed in the well, wherein the heavily doped region has the second conductivity type and is laterally adjacent to the source region.

18. The semiconductor device according to claim 17, wherein, Further comprising an interlayer dielectric layer covering the epitaxial layer.

19. The semiconductor device according to claim 18, wherein, Further comprising: A first via hole disposed through the interlayer dielectric layer and physically contacting the heavily doped region and the source region; and A second via hole disposed through the interlayer dielectric layer and physically contacting the drain region.

20. The semiconductor device according to claim 19, wherein, Further comprising: A source electrode electrically coupled to the heavily doped region and the source region through the first via hole; And A drain electrode electrically coupled to the drain region through the second via hole.

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