Power device with drain electrode led out from front side and manufacturing method thereof

Abstract

The invention discloses a power device with a drain electrode led out from the front side and a manufacturing method thereof, the power device comprises a substrate, an epitaxial layer and an isolation layer, and the power device is divided into a gate contact region, an active region, a terminal region and a terminal peripheral region along the horizontal direction; gate metal is arranged on the isolation layer of the gate contact region and is connected with the gate interconnection structure; source electrode metal is arranged on the isolation layer of the active region and is connected with the source region; the terminal region is provided with a voltage-withstanding ring and a cut-off ring structure, the isolation layer of the terminal peripheral region is provided with drain electrode metal, and the drain electrode metal is connected with the first injection region of the terminal peripheral region. According to the invention, the drain electrode metal of the power device is changed into the terminal peripheral area arranged on the front surface of the power device, so that the source electrode metal, the drain electrode metal and the grid electrode metal of the power device are all located on the same plane, the demand of clip materials can be effectively reduced, the performance of the power device can be improved, and the parasitic effect can be reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor power devices, and particularly relates to a power device with a front-side drain lead-out and a manufacturing method thereof. Background Art

[0002] In the high-frequency application field, it is necessary to integrate the upper and lower bridge power transistors and the control IC into a DrMOS (Driver and MOSFET; a power module that integrates a driver and a metal-oxide-semiconductor field-effect transistor, generally realized through system-level packaging). Since the source metal and the drain metal of the MOSFET in the prior art are generally vertically distributed (i.e., the source metal is on the front side of the device and the drain metal is on the back side of the device), multiple Clip (copper clip) frames are required to connect the upper bridge power transistor and the lower bridge power transistor. Considering cost control from the product level, there is a need to reduce the material usage of the Clip, which requires making the source / drain / gate three terminals on one plane. In the prior art, generally through packaging processes such as flip, etc., to meet the requirement that the back-side drain of a certain device in the co-packaged device faces upward, but it is impossible to meet the requirement that the three electrodes of the device are on one plane. Summary of the Invention

[0003] Aiming at the deficiencies of the above prior art, the technical problem to be solved by the present invention is: to provide a power device with a front-side drain lead-out and a manufacturing method thereof.

[0004] To solve the above technical problem, the present invention provides the following technical solutions:

[0005] A power device with a front-side drain lead-out includes a substrate, an epitaxial layer disposed on the substrate, and an isolation layer disposed on the epitaxial layer. The power device is horizontally divided into a gate contact region, an active region, a termination region, and a termination peripheral region; a first implantation region is disposed on the upper part of the epitaxial layer, and the first implantation regions in the gate contact region and the active region form a body region; a gate interconnection structure is disposed in the epitaxial layer of the gate contact region, a gate metal is disposed on the isolation layer of the gate contact region, and the gate metal is connected to the gate interconnection structure; a plurality of trench gates are disposed in the epitaxial layer of the active region, a second implantation region is disposed on one side of each trench gate, the second implantation region forms a source region, a source metal is disposed on the isolation layer of the active region, and the source metal is connected to the source region; the termination region is provided with a breakdown voltage ring and a cut-off ring structure, and a drain metal is disposed on the isolation layer of the termination peripheral region, and the drain metal is connected to the first implantation region of the termination peripheral region.

[0006] Further, a first isolation passivation layer is formed between the gate metal and the source metal, and a second isolation passivation layer is formed at the upper end and both sides of the cut-off ring metal.

[0007] Further, a gate interconnection trench is formed in the gate contact region. The depth of the gate interconnection trench is greater than the depth of the body region. A gate interconnection structure is formed in the gate interconnection trench by depositing polysilicon.

[0008] A gate trench is formed in the active region. The depth of the gate trench is greater than the depth of the body region. A trench gate is formed in the gate trench by depositing polysilicon.

[0009] A plurality of breakdown voltage ring trenches and at least one cut-off ring trench are formed in the terminal region. The cut-off ring trench is located on the side of the terminal region far from the active region. The depths of the breakdown voltage ring trenches and the cut-off ring trench are both greater than the depth of the body region. A breakdown voltage ring is formed in the breakdown voltage ring trench by depositing polysilicon, and a cut-off ring is formed in the cut-off ring trench by depositing polysilicon.

[0010] Further, a gate interconnection contact hole penetrating the isolation layer and extending into the gate interconnection structure is formed on the isolation layer in the gate contact region. A gate interconnection contact is formed in the gate interconnection contact hole. The gate metal is connected to the gate interconnection structure through the gate interconnection contact.

[0011] A first active region contact hole penetrating the isolation layer and extending into the source region, and a second active region contact hole penetrating the isolation layer and extending into the body region between the trench gate and the breakdown voltage ring are formed on the isolation layer in the active region. A first source region contact is formed in the first active region contact hole, and a second source region contact is formed in the second active region contact hole. The source metal is connected to the source region through the first source region contact and connected to the body region between the gate trench and the breakdown voltage ring trench through the second source region contact.

[0012] Further, a first cut-off ring contact hole penetrating the isolation layer and extending into the cut-off ring, and a second cut-off ring contact hole penetrating the isolation layer and extending into the first implantation region on the side of the cut-off ring adjacent to the terminal peripheral region are formed on the isolation layer in the terminal region. A first cut-off ring contact is formed in the first cut-off ring contact hole, and a second cut-off ring contact is formed in the second cut-off ring contact hole. A cut-off ring metal is further formed on the isolation layer in the terminal region. The cut-off ring metal covers the upper ends of the first cut-off ring contact hole and the second cut-off ring contact hole. The cut-off ring metal is connected to the cut-off ring through the first cut-off ring contact and connected to the first implantation region through the second cut-off ring contact, thereby forming a cut-off ring structure.

[0013] Further, a drain pad contact hole penetrating the isolation layer and extending into the first implantation region is formed on the isolation layer in the terminal peripheral region. A drain contact is formed in the drain pad contact hole. The drain metal is connected to the first implantation region in the terminal peripheral region through the drain contact.

[0014] A method for manufacturing a power device with a drain front lead, comprising the following steps:

[0015] S100, growing an epitaxial layer on a substrate;

[0016] S200, dividing the gate contact region, the active region, the terminal region and the terminal peripheral region in the horizontal direction, forming a gate interconnection structure in the gate contact region, forming a trench gate in the active region, and forming a plurality of voltage-resistant rings and a cut-off ring in the terminal region;

[0017] S300, forming a first implantation region on the upper part of the epitaxial layer by ion implantation, wherein the thickness of the first implantation region is less than the depth of the cut-off ring, and the first implantation region of the gate contact region and the active region forms a body region;

[0018] S400, forming a source region on one side of the trench gate by ion implantation;

[0019] S500, depositing an isolation layer on the epitaxial layer, and making a gate interconnection contact, a source region contact, a stop ring contact and a drain contact penetrating the isolation layer; the gate interconnection contact is connected to the gate interconnection structure, the source region contact is connected to the source region, the stop ring contact is connected to the stop ring, and the drain contact is connected to the first injection region in the peripheral region of the terminal;

[0020] S600, performing metallization deposition on the isolation layer, and forming mutually isolated gate metal, source metal, stop ring metal and drain metal through photolithography and etching; the gate metal is contact-connected with the gate interconnection, the source metal is contact-connected with the source region, the stop ring metal is contact-connected with the stop ring, and the drain metal is contact-connected with the drain.

[0021] Furthermore, the step S200 includes the following sub-steps:

[0022] S210, dividing the epitaxial layer into a gate contact region, an active region, a terminal region and a terminal peripheral region along a horizontal direction;

[0023] S220, forming a gate interconnection trench in the gate contact region, forming a gate trench in the active region, and forming a plurality of voltage-resistant ring trenches and at least one cut-off ring trench in the terminal region;

[0024] S230, forming a trench gate in the gate trench, forming a gate interconnection structure in the gate interconnection trench, forming a voltage-resistant ring in the voltage-resistant ring trench, and forming a stop ring in the stop ring trench.

[0025] Furthermore, the step S500 includes the following sub-steps:

[0026] S510, depositing silicon dioxide on the epitaxial layer to form an isolation layer;

[0027] S520. Form a gate interconnection contact hole that penetrates the isolation layer on the isolation layer in the gate contact region and extends into the gate interconnection structure, form a first active region contact hole that penetrates the isolation layer on the isolation layer in the active region and extends into the source region, and a second active region contact hole that penetrates the isolation layer on the isolation layer in the body region between the gate trench and the breakdown voltage ring trench, form a first breakdown voltage ring contact hole that penetrates the isolation layer on the isolation layer in the terminal region and extends into the breakdown voltage ring, and a second breakdown voltage ring contact hole that penetrates the isolation layer on the isolation layer in the first implantation region adjacent to the periphery of the terminal on the side of the breakdown voltage ring, form a drain pad contact hole that penetrates the isolation layer on the isolation layer in the terminal peripheral region and extends into the first implantation region;

[0028] S530. Form a gate interconnection contact in the gate interconnection contact hole, a first source region contact in the first active region contact hole, a second source region contact in the second active region contact hole, a first breakdown voltage ring contact in the first breakdown voltage ring contact hole, a second breakdown voltage ring contact in the second breakdown voltage ring contact hole, and a drain contact in the drain pad contact hole by depositing metal.

[0029] Further, after the step S600, the following steps are also executed:

[0030] S700. Deposit silicon dioxide and / or silicon nitride to form a passivation layer, and perform photolithography and etching on the passivation layer to form a first isolation passivation layer between the gate metal and the source metal, and a second isolation passivation layer on the upper end and both sides of the breakdown voltage ring metal.

[0031] In the present invention, considering cost control from the perspective of product level, through simulation experiments on the device, it is found that the potential of the front surface of the power device in the terminal peripheral region is basically the same as the potential of the back substrate. Therefore, the drain metal on the back surface of the power device is changed to be disposed in the terminal peripheral region on the front surface of the power device, so that the source metal, drain metal, and gate metal of the power device are all located on the same plane, which can effectively reduce the demand for clip materials, improve the performance of the power device, and reduce parasitic effects. Description of the Drawings

[0032] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0033] Figure 1 It is a schematic structural diagram of a power device with the drain led out from the front surface of the present invention.

[0034] Figure 2 It is a potential simulation diagram of the P_UMOS product and N_UMOS product of this embodiment.

[0035] Figure 3The flowchart is a method for manufacturing a power device with a front-side drain lead according to an embodiment of the present invention.

[0036] Figure 4 Schematic diagram of the structure after growing the epitaxial layer.

[0037] Figure 5 Schematic diagram of the structure after etching the groove.

[0038] Figure 6 It is a schematic diagram of the structure after the first injection region is formed.

[0039] Figure 7 Schematic diagram of the structure after the source region is formed.

[0040] Figure 8 Schematic diagram of the structure after the isolation layer is formed.

[0041] Figure 9 Schematic diagram of the structure after contact holes are made.

[0042] Figure 10 It is a schematic diagram of the structure after the gate metal, source metal, cut-off ring metal and drain metal are formed.

[0043] The accompanying drawings in the specification are as follows:

[0044] Substrate-100; epitaxial layer-110; first implantation region-120; body region-121; source region-130; isolation layer-140; first isolation passivation layer-151; second isolation passivation layer-152;

[0045] Gate contact region-200; gate interconnection trench-210; gate interconnection structure-211; gate interconnection contact hole-230; gate interconnection contact-231; gate metal-250;

[0046] Active area-300; gate trench-310; trench gate-311; first active area contact hole-330; first source area contact-331; second active area contact hole-340; second source area contact-341; source metal-350;

[0047] Terminal region-400; pressure-resistant ring groove-410; pressure-resistant ring-411; stop ring groove-420; stop ring-421; first stop ring contact hole-430; first stop ring contact-431; second stop ring contact hole-440; second stop ring contact-441; stop ring metal-450;

[0048] Terminal peripheral region-500; drain pad contact hole-530; drain contact-531; drain metal-550. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples. The diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0050] Please refer to Figure 1 , Figure 1 , which is a schematic structural diagram of a power device with a front drain lead-out of the present invention. The power device with a front drain lead-out of this embodiment includes a substrate 100, an epitaxial layer 110 disposed on the substrate 100, and an isolation layer 140 disposed on the epitaxial layer 110. The lower end of the substrate 100 is the back surface, and the other surface opposite to the back surface is the front surface. The power device is horizontally divided into a gate contact region 200, an active region 300, a termination region 400, and a termination peripheral region 500. A first implantation region 120 is disposed on the upper portion of the epitaxial layer 110, and the first implantation region 120 in the gate contact region 200 and the active region 300 forms a body region 121.

[0051] A gate interconnection structure 211 is disposed in the epitaxial layer 110 of the gate contact region 200, and a gate metal 250 is disposed on the isolation layer 140 of the gate contact region 200. The gate metal 250 is connected to the gate interconnection structure 211. In this embodiment, a gate interconnection trench 210 is formed in the gate contact region 200. The depth of the gate interconnection trench 210 is greater than the depth of the body region 121. The gate interconnection structure 211 is formed by depositing polysilicon in the gate interconnection trench 210. A gate interconnection contact hole 230 penetrating the isolation layer 140 and extending into the gate interconnection structure 211 is formed on the isolation layer 140 of the gate contact region 200. A gate interconnection contact 231 is formed in the gate interconnection contact hole 230. The gate metal 250 is connected to the gate interconnection structure 211 through the gate interconnection contact 231.

[0052] A plurality of trench gates 311 are provided in the epitaxial layer 110 of the active region 300. A second implantation region is respectively provided on one side of each trench gate 311, and the second implantation region forms a source region 130. A source metal 350 is provided on the isolation layer 140 of the active region 300, and the source metal 350 is connected to the source region 130. In this embodiment, a gate trench 310 is formed in the active region 300, and the depth of the gate trench 310 is greater than the depth of the body region 121. A trench gate 311 is formed by depositing polysilicon in the gate trench 310. A first active region contact hole 330 penetrating the isolation layer 140 and extending into the source region 130, and a second active region contact hole 340 penetrating the isolation layer 140 and extending into the body region 121 between the trench gate 311 and the breakdown voltage ring 411 are formed on the isolation layer 140 of the active region 300. A first source region contact 331 is formed in the first active region contact hole 330, and a second source region contact 341 is formed in the second active region contact hole 340; the source metal 350 is connected to the source region 130 through the first source region contact 331, and is connected to the body region 121 between the gate trench 310 and the breakdown voltage trench 410 through the second source region contact 341.

[0053] The terminal region 400 is provided with a breakdown voltage ring 411 and a cut-off ring structure. In this embodiment, a plurality of breakdown voltage trenches 410 and at least one cut-off ring trench 420 are formed in the terminal region 400, and the cut-off ring trench 420 is located on the side of the terminal region 400 away from the active region 300; the depths of the breakdown voltage trenches 410 and the cut-off ring trenches 420 are both greater than the depth of the body region 121. A breakdown voltage ring 411 is formed by depositing polysilicon in the breakdown voltage trench 410, and a cut-off ring 421 is formed by depositing polysilicon in the cut-off ring trench 420. A first cut-off ring contact hole 430 penetrating the isolation layer 140 and extending into the cut-off ring 421, and a second cut-off ring contact hole 440 penetrating the isolation layer 140 and extending into the first implantation region 120 on the side of the cut-off ring 421 adjacent to the terminal peripheral region 500 are formed on the isolation layer 140 of the terminal region 400. A first cut-off ring contact 431 is formed in the first cut-off ring contact hole 430, and a second cut-off ring contact 441 is formed in the second cut-off ring contact hole 440. A cut-off ring metal 450 is further formed on the isolation layer 140 of the terminal region 400, and the cut-off ring metal 450 covers the upper ends of the first cut-off ring contact hole 430 and the second cut-off ring contact hole 440. The cut-off ring metal 450 is connected to the cut-off ring 421 through the first cut-off ring contact 431, and is connected to the first implantation region 120 through the second cut-off ring contact 441, thereby forming a cut-off ring structure.

[0054] A drain metal 550 is disposed on the isolation layer 140 in the terminal peripheral region 500, and the drain metal 550 is connected to the first implantation region 120 in the terminal peripheral region 500. In this embodiment, a drain pad contact hole 530 that penetrates the isolation layer 140 and extends into the first implantation region 120 is formed in the isolation layer 140 in the terminal peripheral region 500. A drain contact 531 is formed in the drain pad contact hole 530, and the drain metal 550 is connected to the first implantation region 120 in the terminal peripheral region 500 through the drain contact 531.

[0055] A first isolation passivation layer 151 is formed between the gate metal 250 and the source metal 350. The first isolation passivation layer 151 extends to the upper ends of the gate metal 250 and the source metal 350 respectively on both sides. Isolation between the gate metal 250 and the source metal 350 can be achieved through the first isolation passivation layer 151. A second isolation passivation layer 152 is formed at the upper end and on both sides of the cutoff ring metal 450. The second isolation passivation layer 152 extends to the upper ends of the source metal 350 and the drain metal 550 respectively on both sides. Isolation between the cutoff ring structure and the gate metal 250, and isolation between the cutoff ring structure and the source metal 350 can be achieved through the second isolation passivation layer 152.

[0056] Please refer to Figure 2 , in which, Figure 2 the upper figure is the metal wiring diagram of the product, Figure 2 the middle figure and the lower figure are the potential simulation diagrams of the P_UMOS product and the N_UMOS product in this embodiment respectively. It can be seen from Figure 2 that due to the isolation effect of the cutoff ring structure, the potential of the front surface in the terminal peripheral region 500 of the above two power devices adopting the structure of this embodiment is basically the same as the potential of the back substrate 100. Therefore, disposing the drain metal 550 in the terminal peripheral region 500 on the front surface of the power device will not affect the performance of the device.

[0057] In this embodiment, from the perspective of product-level cost control, through simulation experiments on the device, it is found that the potential of the front surface in the terminal peripheral region 500 of the power device is basically the same as the potential of the back substrate 100. Thus, the drain metal 550 on the back surface of the power device is changed to be disposed in the terminal peripheral region 500 on the front surface of the power device, so that the source metal 350, the drain metal 550, and the gate metal 250 of the power device are all located on the same plane (i.e., the front surface of the power device), which can effectively reduce the demand for clip materials and can improve the performance of the power device and reduce parasitic effects.

[0058] Please refer to Figure 3 , Figure 3The flowchart of an embodiment of the manufacturing method of a power device with a front drain lead of the present invention. The manufacturing method of the power device with a front drain lead of this embodiment includes the following steps:

[0059] S100, Refer to Figure 4 , and grow an epitaxial layer 110 on a substrate 100.

[0060] S200, Refer to Figure 5 , divide a gate contact region 200, an active region 300, a termination region 400, and a termination peripheral region 500 in a horizontal direction, form a gate interconnection structure 211 in the gate contact region 200, form a trench gate 311 in the active region 300, and form a plurality of breakdown voltage rings 411 and a cut-off ring 421 in the termination region 400. This step may include the following sub-steps:

[0061] S210, Divide the gate contact region 200, the active region 300, the termination region 400, and the termination peripheral region 500 in a horizontal direction on the epitaxial layer 110.

[0062] S220, Form a gate interconnection trench 210 in the gate contact region 200, form a gate trench 310 in the active region 300, form a plurality of breakdown voltage ring trenches 410 and at least one cut-off ring trench 420 in the termination region 400.

[0063] S230, Form a trench gate 311 in the gate trench 310, form a gate interconnection structure 211 in the gate interconnection trench 210, form a breakdown voltage ring 411 in the breakdown voltage ring trench 410, and form a cut-off ring 421 in the cut-off ring trench 420. The manufacturing methods of the above structures are all conventional processes in the prior art and are not related to the improvement of this application, so no further description is given here.

[0064] S300, Refer to Figure 6 , form a first implantation region 120 by ion implantation on the upper part of the epitaxial layer 110. The thickness of the first implantation region 120 is less than the depth of the cut-off ring 421, and the first implantation regions 120 in the gate contact region 200 and the active region 300 form a body region 121.

[0065] S400, Refer to Figure 7 , form a source region 130 by ion implantation on one side of the trench gate 311.

[0066] S500. Deposit an isolation layer 140 on the epitaxial layer 110, and fabricate a gate interconnection contact 231, a source region 130 contact, a cutoff ring 421 contact, and a drain contact 531 that penetrate the isolation layer 140. The gate interconnection contact 231 is connected to the gate interconnection structure 211, the source region 130 contact is connected to the source region 130, the cutoff ring 421 contact is connected to the cutoff ring 421, and the drain contact 531 is connected to the first implantation region 120 of the terminal peripheral region 500. This step may include the following sub-steps:

[0067] S510. Refer to Figure 8 , deposit silicon dioxide on the epitaxial layer 110 to form the isolation layer 140.

[0068] S520. Refer to Figure 9 , form a gate interconnection contact hole 230 that penetrates the isolation layer 140 and extends into the gate interconnection structure 211 on the isolation layer 140 in the gate contact region 200; form a first active region contact hole 330 that penetrates the isolation layer 140 and extends into the source region 130 and a second active region contact hole 340 that penetrates the isolation layer 140 and extends into the body region 121 between the gate trench 310 and the breakdown voltage ring trench 410 on the isolation layer 140 in the active region 300; form a first cutoff ring contact hole 430 that penetrates the isolation layer 140 and extends into the cutoff ring 421 and a second cutoff ring contact hole 440 that penetrates the isolation layer 140 and extends into the first implantation region 120 on the side of the cutoff ring 421 adjacent to the terminal peripheral region 500 on the isolation layer 140 in the terminal region 400; form a drain pad contact hole 530 that penetrates the isolation layer 140 and extends into the first implantation region 120 on the isolation layer 140 in the terminal peripheral region 500.

[0069] S530. Continue to refer to Figure 9 , form the gate interconnection contact 231 in the gate interconnection contact hole 230, form the first source region contact 331 in the first active region contact hole 330, form the second source region contact 341 in the second active region contact hole 340, form the first cutoff ring contact 431 in the first cutoff ring contact hole 430, form the second cutoff ring contact 441 in the second cutoff ring contact hole 440, and form the drain contact 531 in the drain pad contact hole 530 by depositing metal.

[0070] S600. Refer to Figure 10, metallization deposition is performed on the isolation layer 140, and mutually isolated gate metal 250, source metal 350, cutoff ring metal 450, and drain metal 550 are formed through photolithography and etching. The gate metal 250 is connected to the gate interconnection contact 231, the source metal 350 is in contact connection with the source region 130, the cutoff ring metal 450 is in contact connection with the cutoff ring 421, and the drain metal 550 is connected to the drain contact 531.

[0071] S700, deposit silicon dioxide and / or silicon nitride to form a passivation layer, and perform photolithography and etching on the passivation layer to form a first isolation passivation layer 151 between the gate metal 250 and the source metal 350. The first isolation passivation layer 151 extends to the upper ends of the gate metal 250 and the source metal 350 respectively on both sides. Isolation between the gate metal 250 and the source metal 350 can be achieved through the first isolation passivation layer 151. A second isolation passivation layer 152 is formed at the upper end and on both sides of the cutoff ring metal 450. The second isolation passivation layer 152 extends to the upper ends of the source metal 350 and the drain metal 550 respectively on both sides. Isolation between the cutoff ring structure and the gate metal 250, and isolation between the cutoff ring structure and the source metal 350 can be achieved through the second isolation passivation layer 152.

[0072] In this embodiment, the drain metal 550 of the power device is changed to be disposed in the terminal peripheral region 500 on the front surface of the power device, so that the three terminals of the source metal 350, the drain metal 550, and the gate metal 250 of the power device are all located on the same plane, which can effectively reduce the requirement for clip materials, improve the performance of the power device, and reduce parasitic effects.

[0073] The above embodiments only represent the preferred implementation modes of the present invention. The description is relatively specific and detailed, but it should not be understood as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent should be subject to the appended claims.

Claims

1. A power device with a positive drain lead-out, characterized in that: It includes a substrate, an epitaxial layer disposed on the substrate, and an isolation layer disposed on the epitaxial layer. The power device is horizontally divided into a gate contact region, an active region, a termination region, and a termination peripheral region. A first implantation region is provided on the upper part of the epitaxial layer. The first implantation regions in the gate contact region and the active region form a body region. A gate interconnection structure is provided in the epitaxial layer of the gate contact region. Gate metal is provided on the isolation layer of the gate contact region, and the gate metal is connected to the gate interconnection structure. Multiple trench gates are provided in the epitaxial layer of the active region. A second implantation region is respectively provided on one side of each trench gate, and the second implantation region forms a source region. Source metal is provided on the isolation layer of the active region, and the source metal is connected to the source region. The termination region is provided with a breakdown voltage ring and a cutoff ring structure. Drain metal is provided on the isolation layer of the termination peripheral region, and the drain metal is connected to the first implantation region of the termination peripheral region.

2. The power device with a front-drain lead as claimed in claim 1, wherein: A first isolation passivation layer is formed between the gate metal and the source metal, and a second isolation passivation layer is formed at the upper end and on both sides of the cutoff ring metal.

3. The power device with a front-drawn drain according to claim 1, characterized in that: A gate interconnection trench is formed in the gate contact region. The depth of the gate interconnection trench is greater than the depth of the body region. The gate interconnection structure is formed by depositing polysilicon in the gate interconnection trench. A gate trench is formed in the active region. The depth of the gate trench is greater than the depth of the body region. The trench gate is formed by depositing polysilicon in the gate trench. Multiple breakdown voltage ring trenches and at least one cutoff ring trench are formed in the termination region. The cutoff ring trench is located on the side of the termination region away from the active region. The depths of the breakdown voltage ring trench and the cutoff ring trench are both greater than the depth of the body region. The breakdown voltage ring is formed by depositing polysilicon in the breakdown voltage ring trench, and the cutoff ring is formed by depositing polysilicon in the cutoff ring trench.

4. The power device with a positive drain lead as described in any one of claims 1 to 3, characterized in that: A gate interconnection contact hole penetrating the isolation layer and extending into the gate interconnection structure is formed on the isolation layer of the gate contact region. A gate interconnection contact is formed in the gate interconnection contact hole, and the gate metal is connected to the gate interconnection structure through the gate interconnection contact. A first active region contact hole penetrating the isolation layer and extending into the source region, and a second active region contact hole penetrating the isolation layer and extending into the body region between the trench gate and the breakdown voltage ring are formed on the isolation layer of the active region. A first source region contact is formed in the first active region contact hole, and a second source region contact is formed in the second active region contact hole. The source metal is connected to the source region through the first source region contact and is connected to the body region between the gate trench and the breakdown voltage ring trench through the second source region contact.

5. The power device with a front drain lead as described in any one of claims 1 to 3, characterized in that: A first cutoff ring contact hole penetrating the isolation layer and extending into the cutoff ring and a second cutoff ring contact hole penetrating the isolation layer and extending into the first implantation region on one side of the cutoff ring adjacent to the terminal peripheral region are formed on the isolation layer of the terminal region; a first cutoff ring contact is formed in the first cutoff ring contact hole, and a second cutoff ring contact is formed in the second cutoff ring contact hole; cutoff ring metal is further formed on the isolation layer of the terminal region, the cutoff ring metal covers the upper ends of the first cutoff ring contact hole and the second cutoff ring contact hole, and the cutoff ring metal is connected to the cutoff ring through the first cutoff ring contact and connected to the first implantation region through the second cutoff ring contact, thereby forming a cutoff ring structure.

6. The power device with a positive drain lead as described in any one of claims 1 to 3, characterized in that: A drain pad contact hole penetrating the isolation layer and extending into the first implantation region is formed on the isolation layer of the terminal peripheral region, a drain contact is formed in the drain pad contact hole, and the drain metal is connected to the first implantation region of the terminal peripheral region through the drain contact.

7. A manufacturing method of a power device with a front drain lead-out, characterized in that, It includes the following steps: S100. Grow an epitaxial layer on a substrate; S200. Horizontally divide a gate contact region, an active region, a terminal region, and a terminal peripheral region, form a gate interconnection structure in the gate contact region, form trench gates in the active region, and form a plurality of breakdown voltage rings and a cutoff ring in the terminal region; S300. Form a first implantation region by ion implantation in the upper part of the epitaxial layer, the thickness of the first implantation region is less than the depth of the cutoff ring, and the first implantation regions in the gate contact region and the active region form a body region; S400. Form a source region by ion implantation on one side of the trench gate; S500. Deposit an isolation layer on the epitaxial layer, and fabricate gate interconnection contacts, source contacts, cutoff ring contacts, and drain contacts penetrating the isolation layer; the gate interconnection contacts are connected to the gate interconnection structure, the source contacts are connected to the source regions, the cutoff ring contacts are connected to the cutoff rings, and the drain contacts are connected to the first implantation regions of the terminal peripheral regions; S600. Perform metallization deposition on the isolation layer, and form mutually isolated gate metal, source metal, cutoff ring metal, and drain metal through photolithography and etching; the gate metal is connected to the gate interconnection contacts, the source metal is connected to the source contacts, the cutoff ring metal is connected to the cutoff ring contacts, and the drain metal is connected to the drain contacts.

8. The manufacturing method of the power device with a positive drain lead as claimed in claim 7, wherein The step S200 includes the following sub-steps: S210. Horizontally divide a gate contact region, an active region, a terminal region, and a terminal peripheral region on the epitaxial layer; S220. Form gate interconnection trenches in the gate contact region, form gate trenches in the active region, form a plurality of breakdown voltage ring trenches and at least one cutoff ring trench in the terminal region; S230. Form trench gates in the gate trenches, form gate interconnection structures in the gate interconnection trenches, form breakdown voltage rings in the breakdown voltage ring trenches, and form cutoff rings in the cutoff ring trenches.

9. The manufacturing method of the power device with a drain front lead-out according to claim 7, characterized in that The step S500 includes the following sub-steps: S510. Deposit silicon dioxide on the epitaxial layer to form an isolation layer; S520. Form a gate interconnect contact hole that penetrates the isolation layer on the isolation layer in the gate contact region and extends into the gate interconnect structure, form a first active region contact hole that penetrates the isolation layer on the isolation layer in the active region and extends into the source region, and a second active region contact hole that penetrates the isolation layer and extends into the body region between the gate trench and the breakdown voltage ring trench, form a first cutoff ring contact hole that penetrates the isolation layer on the isolation layer in the terminal region and extends into the cutoff ring, and a second cutoff ring contact hole that penetrates the isolation layer and extends into the first implantation region on the side of the cutoff ring adjacent to the terminal peripheral region, and form a drain pad contact hole that penetrates the isolation layer on the isolation layer in the terminal peripheral region and extends into the first implantation region; S530. Form a gate interconnect contact in the gate interconnect contact hole, form a first source region contact in the first active region contact hole, form a second source region contact in the second active region contact hole, form a first cutoff ring contact in the first cutoff ring contact hole, form a second cutoff ring contact in the second cutoff ring contact hole, and form a drain contact in the drain pad contact hole by depositing metal.

10. The manufacturing method of the power device with a positive drain lead as described in any one of claims 7 to 9, characterized in that: After the step S600, the following steps are further executed: S700. Deposit silicon dioxide and / or silicon nitride to form a passivation layer, perform photolithography and etching on the passivation layer to form a first isolation passivation layer between the gate metal and the source metal, and form a second isolation passivation layer on the upper end and both sides of the cutoff ring metal.

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