Field effect transistor and preparation method thereof
By forming a tilted second-type secondary doping region in the SiC MOSFET, the problems of low channel mobility and short channel effects of SiC MOS are solved, which improves the electrical performance of the transistor and simplifies the preparation process.
Patent Information
- Application Number
- CN202311830536.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-07-08
AI Technical Summary
Due to SiC material reasons and the influence of the interface state in the gate oxygen film formation process, the SiC MOS channel mobility is relatively low, and the channel resistance proportion increases, resulting in a significant reduction in drain induction barrier (DIBL) phenomenon, and the short channel effect is serious, affecting the electrical performance of field effect transistors.
During the preparation of SiC MOSFET, a second type well region arranged spaced apart is formed in the first type epitaxial material layer, and an inclined second type secondary doping region is formed at the top of the interface between the first type source region and the second type well region to increase the doping concentration of the interface, and suppress the potential barrier reduction caused by the leakage field through the secondary doping region with a longer morphology.
It effectively improves the short channel effect caused by the reduction of drain induction barrier, improves the electrical performance of field effect transistors, simplifies the process flow and reduces the preparation cost.
Smart Images
Figure CN120282508A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular, to a field effect transistor and a method for manufacturing the same. Background Art
[0002] As a third-generation semiconductor material, silicon carbide (SiC) has advantages such as a wide bandgap, a high critical breakdown electric field, and a high saturation drift velocity compared with existing silicon materials. A metal-oxide-semiconductor field effect transistor (MOSFET) device fabricated with SiC material has advantages such as a high breakdown voltage, a low on-resistance, and a fast switching speed compared with a silicon-based MOSFET with the same epitaxial thickness.
[0003] However, due to the SiC material and the influence of interface states in the gate oxide film formation process, the channel mobility is relatively low, and the proportion of channel resistance increases. Therefore, the SiC MOS channel is generally relatively short, and the Drain Induced Barrier Low (DIBL) phenomenon is relatively obvious. Summary of the Invention
[0004] Based on this, embodiments of this application provide a field effect transistor and a method for manufacturing the same, which can effectively improve the short-channel effect caused by the reduction of the drain-induced barrier and enhance the electrical performance of the field effect transistor.
[0005] According to some embodiments, on the one hand, this application provides a method for manufacturing a field effect transistor, including:
[0006] Forming a first-type epitaxial material layer;
[0007] Forming a plurality of second-type well regions arranged at intervals in the first-type epitaxial material layer, and forming a plurality of first-type source regions in each of the second-type well regions in a one-to-one correspondence;
[0008] Forming a second-type secondary doping region at the top of the interface between each of the first-type source regions and the corresponding second-type well region; the second-type secondary doping region is inclined in a direction close to the corresponding first-type source region.
[0009] In some embodiments, the forming a plurality of second-type well regions arranged at intervals in the first-type epitaxial material layer, and forming a plurality of first-type source regions in each of the second-type well regions in a one-to-one correspondence includes:
[0010] Performing a plurality of ion implantation processes on the first-type epitaxial material layer to form a plurality of the second-type well regions arranged at intervals;
[0011] The forming a second-type secondary doping region at the top of the interface between each of the first-type source regions and the corresponding second-type well region includes:
[0012] During the process of performing the multiple ion implantation processes on the first-type epitaxial material layer, a second-type doping ion is implanted into the top of the interface between each first-type source region and the corresponding second-type well region by using the ion implantation process having an inclined angle, so as to form the second-type secondary doping region.
[0013] In some embodiments, the implanting the second-type doping ion into the top of the interface between each first-type source region and the corresponding second-type well region by using the ion implantation process having an inclined angle includes:
[0014] When implanting the second-type doping ion into the top of the interface between each first-type source region and the corresponding second-type well region, the included angle between the inclined angle of the ion implantation process and the normal line of the first-type epitaxial layer ranges from 4° to 15°.
[0015] In some embodiments, forming a plurality of second-type well regions arranged at intervals in the first-type epitaxial material layer, and forming a plurality of first-type source regions in one-to-one correspondence in each second-type well region includes:
[0016] Forming a first-type drift region between adjacent second-type well regions; there is a gap between each first-type source region and the first-type drift region.
[0017] In some embodiments, forming the second-type secondary doping region at the top of the interface between each first-type source region and the corresponding second-type well region includes:
[0018] The doping concentration of the second-type secondary doping region continuously increases in the direction close to the corresponding first-type source region.
[0019] In some embodiments, the doping concentration range of the second-type secondary doping region is 1×10 12 cm -2 ~3×10 13 cm -2 .
[0020] In some embodiments, the material of the first-type epitaxial material layer includes silicon carbide.
[0021] In some embodiments, forming a plurality of second-type well regions arranged at intervals in the first-type epitaxial material layer includes:
[0022] Performing an aluminum ion implantation process on the surface of the first-type epitaxial material layer to form a plurality of second-type well regions arranged at intervals in the first-type epitaxial material layer;
[0023] A plurality of first-type source regions are formed in a one-to-one correspondence in each of the second-type well regions, including:
[0024] Performing a nitrogen ion implantation process on the surface of each of the second-type well regions to form a plurality of the first-type source regions in a one-to-one correspondence in each of the second-type well regions.
[0025] According to some embodiments, another aspect of the present application provides a field effect transistor, including:
[0026] A first-type epitaxial layer;
[0027] A plurality of second-type well regions, which are arranged on the first-type epitaxial layer at intervals;
[0028] A plurality of first-type source regions, which are arranged in a one-to-one correspondence in a plurality of the second-type well regions;
[0029] Wherein, at the top of the interface between each of the first-type source regions and the corresponding second-type well region, there is a second-type secondary doping region; the second-type secondary doping region inclines towards the direction close to the corresponding first-type source region.
[0030] In some embodiments, the field effect transistor further includes: a first-type drift region, which is arranged between adjacent second-type well regions; there is a gap between each of the first-type source regions and the first-type drift region;
[0031] The doping concentration of the second-type secondary doping region continuously increases along the direction close to the corresponding first-type source region.
[0032] The field effect transistor and its manufacturing method provided by the present application can / at least have the following advantages:
[0033] In the embodiments of the present application, in the first-type epitaxial material layer, at the top of the interface between each first-type source region and the corresponding second-type well region, a second-type secondary doping region is formed, thereby increasing the doping concentration at the interface between the first-type source region and the second-type well region; and, in the embodiments of the present application, the second-type secondary doping region inclines towards the direction close to the corresponding first-type source region, and the reduction of the barrier height between the first-type source region and the channel caused by the leakage electric field is suppressed through the second-type secondary doping region with a longer morphology, thereby preventing the threshold voltage from decreasing as the drain voltage increases, effectively improving the short-channel effect caused by Drain Induction Barrier Lower (abbreviated as DIBL), and further improving the electrical performance of the field effect transistor. Description of the Drawings
[0034] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0035] Figure 1 A schematic flowchart of a method for manufacturing a field-effect transistor provided by some embodiments of the present application;
[0036] Figure 2 A schematic cross-sectional structure diagram of the structure obtained after forming a second-type secondary doping region in the method for manufacturing a field-effect transistor provided by some embodiments of the present application;
[0037] Figure 3 For Figure 2 A partial enlarged schematic diagram of region A in the shown structure.
[0038] Explanation of reference numerals:
[0039] 100, first-type epitaxial layer; 210, second-type well region; 220, first-type source region; 230, first-type drift region; 240, second-type contact region; 300, second-type secondary doping region; 410, gate; 420, gate dielectric layer. Detailed implementation manners
[0040] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0042] It should be understood that when an element or layer is referred to as "on" or "adjacent to" another element or layer, it can be directly on or adjacent to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below can be denoted as the second element, component, region, layer, or portion.
[0043] Spatial relationship terms such as "on" can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as "on" will be oriented "under" other elements or features. Thus, the exemplary term "on" can include both the upper and lower orientations. In addition, the device can also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0044] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from the presence or addition. At the same time, as used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0045] Due to the reasons of SiC materials and the influence of interface states in the gate oxide film formation process, the channel mobility is relatively low and the proportion of channel resistance increases. Therefore, generally, the SiC MOS channels are basically relatively short, and thus the Drain Induced Barrier Low (DIBL) phenomenon is relatively obvious.
[0046] Based on this, the embodiments of this application provide a field effect transistor and a preparation method thereof, which can effectively improve the short channel effect caused by the reduction of the drain induced barrier and enhance the electrical performance of the field effect transistor. The detailed content will be elaborated in the subsequent embodiments.
[0047] As an example, the field-effect transistor involved in the present application may include a double-diffused metal-oxide semiconductor field-effect transistor (DMOS). In DMOS, there is a double-diffusion structure between the source and the drain, that is, formed through two different diffusion processes, and this structure helps to improve the electrical performance of the field-effect transistor. Exemplarily, the aforementioned DMOS may include a vertical double-diffused metal-oxide semiconductor field-effect transistor (VDMOS). In VDMOS, the current flows along the vertical direction of the field-effect transistor, which helps to achieve a higher power density within a smaller area and further improve the electrical performance of the field-effect transistor.
[0048] According to some embodiments, on the one hand, the present application provides a method for manufacturing a field-effect transistor. Please refer to Figure 1 , the method for manufacturing the field-effect transistor may include the following steps:
[0049] S100: Form a first-type epitaxial material layer.
[0050] S200: Form a plurality of second-type well regions arranged at intervals within the first-type epitaxial material layer, and form a plurality of first-type source regions in one-to-one correspondence within each second-type well region.
[0051] S300: Form a second-type secondary doping region at the top of the interface between each first-type source region and the corresponding second-type well region; the second-type secondary doping region is inclined towards the direction close to the corresponding first-type source region.
[0052] In the method for manufacturing a field-effect transistor provided by the embodiments of the present application, in the first-type epitaxial material layer, a second-type secondary doping region is formed at the top of the interface between each first-type source region and the corresponding second-type well region, thereby increasing the doping concentration at the interface between the first-type source region and the second-type well region; and, in the embodiments of the present application, the second-type secondary doping region is inclined towards the direction close to the corresponding first-type source region, and the reduction of the barrier height between the first-type source region and the channel caused by the drain electric field is suppressed through the relatively long-shaped second-type secondary doping region, thereby preventing the threshold voltage from decreasing as the drain voltage increases, effectively improving the short-channel effect caused by Drain Induction Barrier Lower (DIBL for short), and further improving the electrical performance of the field-effect transistor. In addition, the method for manufacturing a field-effect transistor provided by the embodiments of the present application does not require additional steps to adjust the threshold voltage, which is beneficial to simplifying the process flow and reducing the manufacturing cost.
[0053] It can be understood that in the embodiments of the present application, the first type can be referred to as the second type, and similarly, the second type can also be referred to as the first type; the first type and the second type are different doping types. For example, the first type can refer to the P type and the second type can refer to the N type, or the first type can refer to the N type and the second type can refer to the P type. The following takes the first type as the N type and the second type as the P type for exemplary illustration.
[0054] In addition, it should be noted that although Figure 1 the steps in the flowchart of Figure 1 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover,
[0055] In order to more clearly illustrate the preparation methods in some of the above embodiments, please refer to the following in combination with Figures 2 to 3 to understand some embodiments of the present application.
[0056] In step S100, a first-type epitaxial material layer is formed.
[0057] In some embodiments, the material of the first-type epitaxial material layer is silicon carbide (SiC).
[0058] SiC has a high electron mobility. Compared with the traditional silicon (Si) material, electrons can move faster in SiC. Therefore, the first-type epitaxial material layer made of SiC material is beneficial to improving the switching speed and performance of the field effect transistor, reducing the on-resistance, and lowering the power loss. SiC has a higher breakdown electric field strength, which means that the first-type epitaxial material layer made of SiC material can enable the field effect transistor to operate at a higher electric field without breakdown, which is beneficial to compatible with more high-voltage application scenarios. In addition, SiC has a large energy gap, so the first-type epitaxial material layer made of SiC material can also reduce the leakage current. In the switched state, this helps to reduce the static power consumption of the field effect transistor.
[0059] In step S200, as Figure 2 shown, a plurality of second-type well regions 210 arranged at intervals are formed in the first-type epitaxial material layer, and a plurality of first-type source regions 220 are formed in each second-type well region 210 in one-to-one correspondence.
[0060] Please refer to Figure 2It is understood that in the embodiments of the present application, a portion of the first-type epitaxial material layer that has not been converted into the second-type well region 210 or the first-type source region 220 after forming the plurality of second-type well regions 210 and the plurality of first-type source regions 220 can be defined as the first-type epitaxial layer 100.
[0061] In some embodiments, the following steps can be adopted to form a plurality of second-type well regions 210 arranged at intervals within the first-type epitaxial material layer, for example:
[0062] Perform multiple ion implantation processes on the first-type epitaxial material layer to form a plurality of second-type well regions 210 arranged at intervals.
[0063] As an example, the process of forming a plurality of second-type well regions 210 arranged at intervals within the first-type epitaxial material layer can specifically be shown as the following steps:
[0064] Perform an aluminum ion implantation process on the surface of the first-type epitaxial material layer to form a plurality of second-type well regions 210 arranged at intervals within the first-type epitaxial material layer.
[0065] As an example, a light ion implantation process can be performed on the surface of each second-type well region 210 to form a plurality of first-type source regions 220 in one-to-one correspondence within each second-type well region 210.
[0066] The light ions can be, for example, nitrogen (N) ions. In some embodiments, the process of forming a plurality of first-type source regions 220 in one-to-one correspondence within each second-type well region 210 can specifically be shown as the following steps:
[0067] Perform a nitrogen ion implantation process on the surface of each second-type well region 210 to form a plurality of first-type source regions 220 in one-to-one correspondence within each second-type well region 210.
[0068] Compared with heavy ions such as arsenic (As) ions and indium (In) ions, light ions (such as nitrogen ions) can result in a higher electron mobility. Therefore, adopting the light ion implantation process is beneficial to improving the conductivity of the field-effect transistor, reducing the on-resistance, and thus enabling the field-effect transistor to have a higher response speed.
[0069] Please continue to refer to Figure 2 , in some embodiments, during the process of forming a plurality of second-type well regions 210 arranged at intervals within the first-type epitaxial material layer and forming a plurality of first-type source regions 220 in one-to-one correspondence within each second-type well region 210 in step S200, the following steps can further be included:
[0070] Form a first-type drift region 230 between adjacent second-type well regions 210.
[0071] It can be understood that there may be a gap between each first-type source region 220 formed in step S200 and the aforementioned first-type drift region 230.
[0072] It should be noted that in the manufacturing method provided in the above embodiment, the step of forming a plurality of second-type well regions 210 arranged at intervals in the first-type epitaxial material layer, the step of forming a plurality of first-type source regions 220 in each second-type well region 210 in one-to-one correspondence, and the step of forming a first-type drift region 230 between adjacent second-type well regions 210 have no order restrictions, that is, any one of the three can be executed first, or they can be executed simultaneously, which are all allowed.
[0073] It should also be noted that in the manufacturing method provided in the above embodiment, the first-type epitaxial layer 100 may refer to: after forming a plurality of second-type well regions 210, a plurality of first-type source regions 220, and a first-type drift region 230, a part of the first-type epitaxial material layer in the first-type epitaxial material layer that has not been converted into any one of the second-type well regions 210, the first-type source regions 220, or the first-type drift region 230.
[0074] In step S300, as Figure 2 and Figure 3 ( Figure 3 as Figure 2 shown in the partial enlarged schematic diagram of region A in the structure shown), a second-type secondary doping region 300 is formed at the top of the interface between each first-type source region 220 and the corresponding second-type well region 210; the second-type secondary doping region 300 is inclined towards the direction close to the corresponding first-type source region 220.
[0075] In some embodiments, during the process of performing multiple ion implantation processes on the first-type epitaxial material layer, a second-type doping ion may be implanted into the top of the interface between each first-type source region 220 and the corresponding second-type well region 210 by using an ion implantation process with an inclined angle to form the second-type secondary doping region 300.
[0076] In the manufacturing method provided in the above embodiment, during the multiple ion implantation processes performed on the first-type epitaxial material layer, by making several of the ion implantation processes have an inclined angle, a second-type doping ion is implanted into the top of the interface between each first-type source region 220 and the corresponding second-type well region 210, thereby forming the second-type secondary doping region 300. The above manufacturing method does not require an additional doping step to form the second-type secondary doping region 300, and the second-type secondary doping region 300 can be formed synchronously during the process of forming the second-type well region 210, which is beneficial to simplifying the process flow and reducing the production cost.
[0077] As an example, in multiple ion implantation processes for the first-type epitaxial material layer, several ion implantation processes with shallower implantation levels can have an inclined angle for forming the second-type secondary doping region 300. Exemplarily, the implantation energy range of the several ion implantation processes with shallower implantation levels can be 30K to 200K.
[0078] In some embodiments, the range of the included angle between the inclined angle of the ion implantation process used for implanting the second-type doping ions at the top of the interface between each first-type source region 220 and the corresponding second-type well region 210 and the normal line of the first-type epitaxial layer 100 can be 4° to 15°. As an example, the included angle between the inclined angle and the normal line of the first-type epitaxial layer can be 4°, 8°, 15°, 12°, or 15°, etc.
[0079] In some embodiments, the doping concentration of the second-type secondary doping region 300 can continuously increase in the direction close to the corresponding first-type source region 220.
[0080] As an example, the doping concentration of the second-type secondary doping region 300 can gradually increase in an equal gradient in the direction close to the corresponding first-type source region 220.
[0081] In some embodiments, the doping concentration range of the second-type secondary doping region 300 can be 1×10 12 cm -2 ~3×10 13 cm -2 . As an example, the doping concentration of the second-type secondary doping region 300 can be 1×10 12 cm -2 , 5×10 12 cm -2 , 1×10 13 cm -2 , 1×10 13 cm -2 or 3×10 13 cm -2 etc.
[0082] According to some embodiments, on the other hand, the present application provides a field effect transistor. The field effect transistor in the embodiments of the present application can be prepared by using the preparation method of the field effect transistor provided in the foregoing some embodiments. Therefore, the technical effects that can be achieved by the foregoing preparation method can also be achieved by the field effect transistor in the embodiments of the present application.
[0083] Please continue to refer to Figure 2 and Figure 3 , in some embodiments, the field effect transistor may specifically include a first-type epitaxial layer 100, a plurality of second-type well regions 210, and a plurality of first-type source regions 220.
[0084] A plurality of second-type well regions 210 are arranged at intervals on the first-type epitaxial layer 100; a plurality of first-type source regions 220 are correspondingly arranged in the plurality of second-type well regions 210. Wherein, at the top of the interface between each first-type source region 220 and the corresponding second-type well region 210, there is a second-type secondary doping region 300; the second-type secondary doping region 300 is inclined towards the direction close to the corresponding first-type source region 220.
[0085] For the field-effect transistor provided by the embodiment of the present application, in the first-type epitaxial material layer 100, a second-type secondary doping region 300 is arranged at the top of the interface between each first-type source region 220 and the corresponding second-type well region 210, thereby increasing the doping concentration at the interface between the first-type source region 220 and the second-type well region 210; and, in the field-effect transistor provided by the embodiment of the present application, the second-type secondary doping region 300 is inclined towards the direction close to the corresponding first-type source region 220. By means of the second-type secondary doping region 300 with a longer morphology, the reduction of the barrier height between the first-type source region 220 and the channel caused by the drain electric field is suppressed, thereby preventing the threshold voltage from decreasing as the drain voltage increases, effectively improving the short-channel effect caused by the drain-induced barrier lowering, and further improving the electrical performance of the field-effect transistor.
[0086] In some embodiments, as Figure 2 shown, the field-effect transistor may further include a first-type drift region 230. The first-type drift region 230 is arranged between adjacent second-type well regions 210; there is a gap between each first-type source region 220 and the first-type drift region 230.
[0087] It can be understood that the first-type drift region 230 includes a JFET (Junction Field-effect Transistor) region. When an appropriate voltage is applied to the field-effect transistor, the charge state of the JFET region changes, forming a conduction channel to allow current to flow.
[0088] As an example, the doping concentration of the second-type secondary doping region 300 may continuously increase along the direction close to the corresponding first-type source region 220.
[0089] In some embodiments, as Figure 2 shown, in each second-type well region 210, a second-type contact region 240 corresponding to the first-type source region 220 may also be arranged, which is used to lead out the corresponding second-type well region 210.
[0090] As an example, as Figure 2 and Figure 3As shown, the field effect transistor may further include a gate dielectric layer 420. The gate dielectric layer 420 may be disposed on the second-type well region 210 and the first-type drift region 230, and there is a partial overlapping region with the first-type source region 220.
[0091] Please continue to refer to Figure 2 and Figure 3 , in some embodiments, the field effect transistor may further include a gate 410 disposed on a side of the gate dielectric layer 420 away from the second-type well region 210 and the first-type drift region 230.
[0092] As an example, the field effect transistor may further include a drain region. It is defined that the first-type epitaxial layer 100 has opposite first and second surfaces. Each second-type well region 210 and each first-type source region 220 are disposed on the first surface of the first-type epitaxial layer 100, and the drain region is correspondingly disposed on the second surface of the first-type epitaxial layer 100.
[0093] It should be noted that the preparation methods of the field effect transistors in the embodiments of the present application can all be used to prepare the corresponding field effect transistors. Therefore, the technical features between the method embodiments and the structure embodiments can be mutually replaced and supplemented without conflict, so that those skilled in the art can learn the technical content of the present application.
[0094] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0095] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for manufacturing a field effect transistor, characterized in that, Comprising: Forming a first-type epitaxial material layer; Forming a plurality of second-type well regions arranged at intervals within the first-type epitaxial material layer, and forming a plurality of first-type source regions in one-to-one correspondence within each of the second-type well regions; Forming a second-type secondary doping region at the top of the interface between each of the first-type source regions and the corresponding second-type well region; the second-type secondary doping region is inclined in a direction approaching the corresponding first-type source region.
2. The manufacturing method of the field effect transistor according to claim 1, characterized in that The forming of a plurality of second-type well regions arranged at intervals within the first-type epitaxial material layer, and forming a plurality of first-type source regions in one-to-one correspondence within each of the second-type well regions, includes: Performing a plurality of ion implantation processes on the first-type epitaxial material layer to form a plurality of the second-type well regions arranged at intervals; The forming of a second-type secondary doping region at the top of the interface between each of the first-type source regions and the corresponding second-type well region, includes: During the process of performing a plurality of the ion implantation processes on the first-type epitaxial material layer, using the ion implantation process with an inclined angle to implant second-type doping ions at the top of the interface between each of the first-type source regions and the corresponding second-type well region to form the second-type secondary doping region.
3. The manufacturing method of the field effect transistor according to claim 2, characterized in that The using of the ion implantation process with an inclined angle to implant second-type doping ions at the top of the interface between each of the first-type source regions and the corresponding second-type well region, includes: When implanting the second-type doping ions at the top of the interface between each of the first-type source regions and the corresponding second-type well region, the included angle between the inclined angle of the ion implantation process and the normal of the first-type epitaxial layer ranges from 4° to 15°.
4. The manufacturing method of the field effect transistor according to claim 1, wherein The forming of a plurality of second-type well regions arranged at intervals within the first-type epitaxial material layer, and forming a plurality of first-type source regions in one-to-one correspondence within each of the second-type well regions, includes: Forming a first-type drift region between adjacent second-type well regions; there is a gap between each of the first-type source regions and the first-type drift region.
5. The method for manufacturing a field effect transistor according to claim 1, wherein, The forming of a second-type secondary doping region at the top of the interface between each of the first-type source regions and the corresponding second-type well region, includes: The doping concentration of the second-type secondary doping region continuously increases in a direction approaching the corresponding first-type source region.
6. The manufacturing method of the field effect transistor according to claim 5, characterized in that, The doping concentration range of the second-type secondary doping region is 1×10 12 cm -2 ~3×10 13 cm -2 .
7. The manufacturing method of the field effect transistor according to claim 1, wherein, The material of the first-type epitaxial material layer includes silicon carbide.
8. The manufacturing method of the field effect transistor according to claim 1, characterized in that, The forming of a plurality of second-type well regions arranged at intervals within the first-type epitaxial material layer, includes: Performing an aluminum ion implantation process on the surface of the first-type epitaxial material layer to form a plurality of the second-type well regions arranged at intervals within the first-type epitaxial material layer; The forming of a plurality of first-type source regions in one-to-one correspondence within each of the second-type well regions, includes: Performing a nitrogen ion implantation process on the surface of each of the second-type well regions to form a plurality of the first-type source regions in one-to-one correspondence within each of the second-type well regions.
9. A field effect transistor, characterized in that, Comprising: A first-type epitaxial layer; A plurality of second-type well regions, arranged at intervals on the first-type epitaxial layer; A plurality of first-type source regions, arranged in one-to-one correspondence within a plurality of the second-type well regions; Among them, the top of the interface between each of the first-type source regions and the corresponding second-type well region has a second-type secondary doping region; the second-type secondary doping region is inclined in a direction close to the corresponding first-type source region.
10. The field effect transistor according to claim 9, characterized in that, The field effect transistor further includes: a first-type drift region disposed between adjacent second-type well regions; there is a gap between each of the first-type source regions and the first-type drift region; The doping concentration of the second-type secondary doping region continuously increases in a direction close to the corresponding first-type source region.