Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate and an epitaxial structure located on one side of the substrate. The source electrode and the drain electrode are located on the side, away from the substrate, of the epitaxial structure, extend in the first direction and are arranged in the second direction; the back electrode is located on the side, away from the epitaxial structure, of the substrate, and the back electrode is electrically connected with the source electrode through a connecting structure located in the substrate and the epitaxial structure; the same drain comprises at least two drain subsections and at least one isolation region, the at least two drain subsections extend along the first direction and are arranged along the second direction, and the isolation region is located between the two adjacent drain subsections along the second direction; the isolation region overlaps the back electrode in a thickness direction of the semiconductor device. By adopting the technical means, the isolation region and the back electrode are overlapped along the thickness direction of the semiconductor device, so that the opposite area between the back electrode and the drain electrode can be reduced, the parasitic capacitance between the back electrode and the drain electrode is further reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and particularly to a semiconductor device. Background Art

[0002] Due to characteristics such as a large bandgap width, a high electron saturation drift velocity, a high breakdown field strength, and good thermal conductivity, gallium nitride semiconductor material has become a current research hotspot.

[0003] For semiconductor devices, in traditional designs, the back metal electrode is usually connected to the source electrode, and the back metal electrode exists on the entire back of the device, resulting in a parasitic capacitance between the back metal electrode and the drain ohmic electrode, which affects the performance of the device.

[0004] Therefore, how to improve the performance of semiconductor devices is an urgent problem to be solved currently. Summary of the Invention

[0005] The present invention provides a semiconductor device, which can reduce the parasitic capacitance between the back electrode and the drain, and improve the performance of the semiconductor device.

[0006] An embodiment of the present invention provides a semiconductor device, including:

[0007] A substrate and an epitaxial structure located on one side of the substrate;

[0008] A source electrode, a drain electrode, and a back electrode. The source electrode and the drain electrode are located on the side of the epitaxial structure away from the substrate, and both the source electrode and the drain electrode extend along a first direction and are arranged along a second direction; the back electrode is located on the side of the substrate away from the epitaxial structure, and the back electrode is electrically connected to the source electrode through a connection structure located in the substrate and the epitaxial structure; the first direction and the second direction intersect and are both parallel to the plane where the substrate is located;

[0009] The same drain electrode includes at least two drain electrode segments and at least one isolation region. The at least two drain electrode segments extend along the first direction and are arranged along the second direction. Along the second direction, the isolation region is located between two adjacent drain electrode segments; along the thickness direction of the semiconductor device, the isolation region overlaps with the back electrode.

[0010] Optionally, along the second direction, the width d of the drain electrode segment satisfies 0 < d < 10 μm.

[0011] Optionally, the drain electrode further includes a drain connection portion, and the drain connection portion extends along the second direction;

[0012] Along the first direction, the drain connection part is located between the drain branch part and the drain power supply electrode. The drain connection part connects at least two of the drain branch parts in the same drain and is electrically connected to the drain power supply electrode.

[0013] Optionally, the isolation region includes a passive region.

[0014] Optionally, the semiconductor device further includes a gate. Along the second direction, the gate is located between the source and the drain, and the gate forms a Schottky contact with the epitaxial structure.

[0015] The semiconductor device further includes a first compensation gate. The first compensation gate extends along the first direction and is at least partially located in the isolation region. At least one first compensation gate is provided in the same isolation region.

[0016] The semiconductor device further includes a gate connection part. The gate connection part extends along the second direction, and the same first compensation gate is electrically connected to the gate through at least one gate connection part.

[0017] Optionally, along the second direction, the width of the first compensation gate is greater than the width of the gate.

[0018] Optionally, the gate connection part includes a first connection part, a second connection part, and a third connection part. The first connection part is in contact connection with the gate and the second connection part respectively, and the third connection part is in contact connection with the first compensation gate and the second connection part respectively.

[0019] At least part of the first connection part is exposed to the air, the second connection part is exposed to the air, and at least part of the third connection part is exposed to the air.

[0020] Optionally, the gate connection part includes a first connection part, a second connection part, and a third connection part. The first connection part is in contact connection with the gate and the second connection part respectively, and the third connection part is in contact connection with the first compensation gate and the second connection part respectively.

[0021] The semiconductor device further includes a first insulating layer. The first insulating layer is located between the film layer where the drain is located and the film layer where the second connection part is located, and the thickness h1 of the first insulating layer satisfies h1 > 1 μm.

[0022] Optionally, the isolation region includes an active region.

[0023] Optionally, the semiconductor device further includes a compensating source and a second compensating gate. The compensating source extends along the first direction and is at least partially located in the isolation region. The second compensating gate extends along the first direction and is at least partially located in the isolation region;

[0024] The compensating source forms an ohmic contact with the epitaxial structure, and the second compensating gate forms a Schottky contact with the epitaxial structure;

[0025] One compensating source and two second compensating gates are provided in the same isolation region. Along the second direction, the second compensating gate is located between the compensating source and the drain section.

[0026] Optionally, along the second direction, the width of the compensating source is smaller than the width of the source, and along the thickness direction of the semiconductor device, the compensating source does not overlap with the connection structure;

[0027] Moreover, the semiconductor device further includes a source connection portion that extends along the second direction. The compensating source is electrically connected to the source through the source connection portion.

[0028] Optionally, the source connection portion includes a fourth connection portion, a fifth connection portion, and a sixth connection portion. The fourth connection portion is in contact connection with the source and the fifth connection portion respectively. The sixth connection portion is in contact connection with the compensating source and the fifth connection portion respectively;

[0029] At least part of the fourth connection portion is exposed to the air, the fifth connection portion is exposed to the air, and at least part of the sixth connection portion is exposed to the air.

[0030] Optionally, the source connection portion includes a fourth connection portion, a fifth connection portion, and a sixth connection portion. The fourth connection portion is in contact connection with the source and the fifth connection portion respectively. The sixth connection portion is in contact connection with the compensating source and the fifth connection portion respectively;

[0031] The semiconductor device further includes a second insulating layer that is located between the film layer where the gate is located and the film layer where the fifth connection portion is located, and the thickness h2 of the second insulating layer satisfies h2 > 0.3 μm.

[0032] In the technical solution of the embodiment of the present invention, the same drain includes at least two drain segments and at least one isolation region. Along the second direction, the isolation region is located between two adjacent drain segments, that is, the same drain is divided into at least two drain segments by the isolation region. Along the thickness direction of the semiconductor device, the isolation region overlaps with the back electrode, that is, along the thickness direction of the semiconductor device, the facing area between the back electrode and the drain is small, so that the parasitic capacitance between the back electrode and the drain can be reduced, and the performance of the semiconductor device can be improved. Description of the Drawings

[0033] Figure 1 FIG. 6 is a top view schematic diagram of a semiconductor device in the prior art;

[0034] Figure 2 is Figure 1 FIG. 7 is a cross-sectional structure schematic diagram of a semiconductor device provided along the section line A-A';

[0035] Figure 3 FIG. 16 is a top view schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0036] Figure 4 is Figure 3 FIG. 22 is a cross-sectional structure schematic diagram of a semiconductor device provided along the section line B-B';

[0037] Figure 5 FIG. 26 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0038] Figure 6 is Figure 5 FIG. 32 is a first cross-sectional structure schematic diagram of a semiconductor device provided along the section line C-C';

[0039] Figure 7 is Figure 5 FIG. 38 is a second cross-sectional structure schematic diagram of a semiconductor device provided along the section line C-C';

[0040] Figure 8 FIG. 42 is a top view schematic diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0041] Figure 9 is Figure 8 FIG. 48 is a first cross-sectional structure schematic diagram of a semiconductor device provided along the section line D-D';

[0042] Figure 10 is Figure 8 FIG. 54 is a second cross-sectional structure schematic diagram of a semiconductor device provided along the section line D-D'. Detailed Embodiments

[0043] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0045] Before elaborating on the technical solutions of the embodiments of the present invention, the prior art will be introduced first. Figure 1 FIG. is a top view schematic diagram of a semiconductor device in the prior art. Figure 2 is Figure 1 FIG. provides a cross-sectional structure schematic diagram of a semiconductor device along the section line A-A', as Figure 1 and Figure 2 shown, the source electrode 30' can be connected to the back electrode 50' of the semiconductor device through the via 301'. Exemplarily, the via 301' can penetrate through the substrate 10' and the epitaxial structure 20', that is to say, the back electrode 50' is electrically connected to the source electrode 30' through the via 301'. The back electrode 50' is a continuous whole layer of metal electrode. Thus, the facing area between the drain electrode 40' and the back electrode 50' is relatively large, resulting in a relatively large parasitic capacitance between the drain electrode 40' and the back electrode 50', which affects the performance of the semiconductor device.

[0046] In the embodiments of the present invention, by providing an isolation region in the drain electrode, no drain metal is provided in the isolation region, the facing area between the drain electrode and the back electrode is reduced, the parasitic capacitance between the drain electrode and the back electrode can be reduced, and further the parasitic capacitance between the source electrode and the drain electrode can be reduced, the thermal resistance can be lowered, and the performance of the semiconductor device can be improved. Next, the technical solutions provided by the embodiments of the present invention will be elaborated in detail.

[0047] Figure 3 FIG. is a top view schematic diagram of a semiconductor device provided by an embodiment of the present invention. Figure 4 is Figure 3 FIG. provides a cross-sectional structure schematic diagram of a semiconductor device along the section line B-B', as Figure 3 and Figure 4As shown, the semiconductor device includes: a substrate 10 and an epitaxial structure 20 located on one side of the substrate 10; a source electrode 30, a drain electrode 40, and a back electrode 50. The source electrode 30 and the drain electrode 40 are located on the side of the epitaxial structure 20 away from the substrate 10, and both the source electrode 30 and the drain electrode 40 extend along a first direction (the X direction shown in the figure) and are arranged along a second direction (the Y direction shown in the figure); the back electrode 50 is located on the side of the substrate 10 away from the epitaxial structure 20, and the back electrode 50 is electrically connected to the source electrode 30 through a connection structure 301 located in the substrate 10 and the epitaxial structure 20; the first direction X and the second direction Y intersect and are both parallel to the plane where the substrate 10 is located; the same drain electrode 40 includes at least two drain segments 401 and at least one isolation region 402. The at least two drain segments 401 extend along the first direction X, are arranged along the second direction Y, and along the second direction Y, the isolation region 402 is located between two adjacent drain segments 401; along the thickness direction of the semiconductor device (the Z direction shown in the figure), the isolation region 402 overlaps with the back electrode 50.

[0048] Specifically, the semiconductor device may include an active region aa and a passive region bb. The active region aa can be understood as a region where a two-dimensional electron gas, electrons, or holes exist below it, and its working state and characteristics are affected by an external circuit, which is the active working region of the semiconductor device. The passive region bb participates in the operation of the semiconductor device, but its working state is not affected by the external circuit. For example, an extraction structure of the electrode in the active region aa can be provided in the passive region bb, and the passive region bb can be arranged around the active region aa.

[0049] Specifically, both the source electrode 30 and the drain electrode 40 can form an ohmic contact with the epitaxial structure 20. Exemplarily, the source electrode 30 can be used as the input end of the semiconductor device, and the drain electrode 40 can be used as the output end of the semiconductor device. It should be noted that the semiconductor device may further include a gate electrode 60. Figure 3 Taking the semiconductor device including multiple gate electrodes 60 as an example for illustration, that is, the semiconductor device is a multi-cell structure. It can be understood that the semiconductor device may also include only one gate electrode 60, that is, the cell structure is a single-cell structure of the source electrode 30, the gate electrode 60, and the drain electrode 40.

[0050] Specifically, the source electrode 30 can be connected to the back electrode 50 of the semiconductor device through the connection structure 301. Exemplarily, the connection structure 301 can penetrate through the substrate 10 and the epitaxial structure 20, that is to say, the back electrode 50 is electrically connected to the source electrode 30 through the connection structure 301. Exemplarily, the connection structure 301 can be understood as a source via. And the connection structure 301 can be located in the active region aa, such as 3 and Figure 4As shown, in the thickness direction of the semiconductor device, the connection structure 301 overlaps with the source electrode 30. Alternatively, the connection structure 301 may also be located in a passive region (not shown in the figure), and the semiconductor device may further include a source power supply electrode (not shown in the figure) located in the passive region bb. The source power supply electrode is electrically connected to the source electrode 30 and is electrically connected to the back electrode through the connection structure 301.

[0051] Exemplarily, the back electrode 50 may be made of a metal conductive material such as gold. The embodiment of the present invention does not specifically limit the material of the back electrode 50.

[0052] Specifically, the same drain electrode 40 includes at least two drain electrode segments 401 and at least one isolation region 402. The isolation region 402 is located between two adjacent drain electrode segments 401, and along the second direction, the width of the isolation region 402 may be greater than the width of the drain electrode segment 401. For Figure 3 example, the isolation region 402 divides the drain electrode 40 into two parts arranged along the second direction Y, and along the thickness direction Z of the semiconductor device, the isolation region 402 overlaps with the back electrode 50. In this way, the facing area between the back electrode 50 and the drain electrode 40 can be reduced, and thus the parasitic capacitance between the back electrode 50 and the drain electrode 40 can be reduced, the thermal resistance can be decreased, and the performance of the semiconductor device can be improved.

[0053] Exemplarily, the substrate 10 may be formed of one of the materials such as silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure 20 located on one side of the substrate 10 may be formed of one or more of group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0054] Exemplarily, continuing to refer to Figure 4 , the epitaxial structure 20 may include a nucleation layer 201, a buffer layer 202, a channel layer 203, and a barrier layer 204; the channel layer 203 and the barrier layer 204 may form a heterojunction structure.

[0055] Exemplarily, continuing to refer to Figure 4 , the material of the nucleation layer 201 may be aluminum nitride, which is located between the substrate 10 and the buffer layer 202 and serves to bond the semiconductor material layers to be grown next.

[0056] Exemplarily, continuing to refer to Figure 4 , the buffer layer 202 is located on one side of the substrate 10. The material of the buffer layer 202 may be gallium nitride, and the buffer layer 202 may include iron atoms, which is beneficial to achieving the high-resistance performance of the buffer layer 202, ensuring that vertical leakage can be blocked and the pinch-off performance of the semiconductor device can be improved.

[0057] Exemplarily, continuing to refer to Figure 4 , the channel layer 203 may be a group III nitride, such as Alx Ga 1－x N, where 0 ≤ x < 1, that is, at the interface between the channel layer 203 and the barrier layer 204, namely, the energy of the conduction band edge of the channel layer 203 is less than the energy of the conduction band edge of the barrier layer 204. Exemplarily, x = 0 indicates that the channel layer 203 is GaN. The channel layer 203 can also be other group III nitrides, such as InGaN or AlInGaN. The channel layer 203 can be undoped or unintentionally doped. The channel layer 203 can also be a multi-layer structure, such as a combination of superlattice, GaN, or AlGaN.

[0058] Exemplarily, continuing to refer to Figure 4 , the barrier layer 204 can be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 204 has a sufficient thickness and a sufficiently high Al component to form a significant carrier concentration at the interface between the channel layer 203 and the barrier layer 204.

[0059] Exemplarily, continuing to refer to Figure 4 , the channel layer 203 can include GaN, while the barrier layer 204 can include AlGaN, that is, the material of the barrier layer 204 has a higher bandgap than the material of the channel layer 203, and the channel layer 203 can also have a greater electron affinity than the barrier layer 204. Due to the bandgap difference between the barrier layer 204 and the channel layer 203 and the piezoelectric effect at the interface between the barrier layer 204 and the channel layer 203, a two-dimensional electron gas (2DEG) is formed in the channel layer 203 and the barrier layer 204.

[0060] It can be understood that the epitaxial structure 20 can also include a cap layer (not shown in the figure), and the cap layer is located on the surface of the barrier layer 204 away from the substrate 10. The cap layer can reduce surface states, reduce surface leakage of subsequent semiconductor devices, suppress current collapse, and thus improve the performance and reliability of the epitaxial structure 20 and the semiconductor device.

[0061] It should be noted that Figure 3 only one drain 40 including two drain segments 401 and one isolation region 402 is shown as an example for illustration. It can be understood that one drain 40 can also include other numbers of drain segments and isolation regions. For example, the drain can include three drain segments and two isolation regions, or include four drain segments and three isolation regions. The embodiments of the present invention do not limit the number of drain segments and the number of isolation regions included in the drain, and only one isolation region needs to exist between any two adjacent drain segments along the second direction in the same drain.

[0062] In the semiconductor device provided by the embodiment of the present invention, the same drain includes at least two drain segments and at least one isolation region. Along the second direction, the isolation region is located between two adjacent drain segments. That is to say, the same drain is divided into at least two drain segments by the isolation region. Along the thickness direction of the semiconductor device, the isolation region overlaps with the back electrode. That is, along the thickness direction of the semiconductor device, the facing area between the back electrode and the drain is small. In this way, the parasitic capacitance between the back electrode and the drain can be reduced, and the performance of the semiconductor device can be improved.

[0063] Optionally, continue to refer to Figure 3 , along the second direction Y, the width d of the drain segment 401 satisfies 0 < d < 10 μm.

[0064] Specifically, along the second direction Y, the width d of the drain segment 401 satisfies 0 < d < 10 μm, so as to ensure the working performance of the drain 40. Exemplarily, when d > 10 μm, on the one hand, it will cause the area of the isolation region 402 to be small, and then cause the overlapping region between the isolation region 402 and the back metal to be small, which is not conducive to reducing the facing area between the drain 40 and the back electrode 50, and thus has a limited effect on reducing the parasitic capacitance between the source 30 and the drain 40. On the other hand, it will increase the area of the drain 40 along the second direction Y, which is not conducive to the miniaturization design of the semiconductor device.

[0065] Optionally, continue to refer to Figure 3 , the drain further includes a drain connection portion 403, and the drain connection portion 403 extends along the second direction Y; along the first direction X, the drain connection portion 403 is located between the drain segment 401 and the drain power supply electrode 404, and the drain connection portion 403 connects at least two drain segments 403 in the same drain 40 and is electrically connected to the drain power supply electrode 404.

[0066] Specifically, the drain power supply electrode 404 can be understood as a drain pad. The drain 40 in the active region aa can be connected to the drain power supply electrode 404 located in the passive region bb. The drain 40 can receive a voltage signal through the drain power supply electrode 404 to ensure the normal operation of the semiconductor device.

[0067] Specifically, compared with the technical solution in which the drain segment 403 is directly connected to the drain power supply electrode 404, by connecting at least two drain segments 403 in the same drain 40 through the drain connection portion 403 located between the drain segment 401 and the drain power supply electrode 404 and being electrically connected to the drain power supply electrode 404, the contact area between the drain 40 and the drain power supply electrode 404 can be increased, which is conducive to ensuring the connection stability between the drain segment 401 and the drain power supply electrode 404, improving the stability of the semiconductor device while reducing the connection resistance, and ensuring the normal transmission of signals.

[0068] Optionally,Figure 5 A top view schematic diagram of another semiconductor device provided by an embodiment of the present invention Figure 6 is Figure 5 A first cross-sectional structure schematic diagram of a semiconductor device provided along the section line C-C'. The isolation region 402 includes a passive region bb, that is, the two-dimensional electron gas in the isolation region 402 can be consumed to make it into the passive region bb. By setting the isolation region 402 to include the passive region bb, a structure that does not require two-dimensional electrons can be set in the passive region bb, thereby improving the performance while reducing the area of the semiconductor device and enhancing the integration degree of the semiconductor device.

[0069] Further, continuing to refer to Figure 5 and Figure 6 , the semiconductor device further includes a gate 60. Along the second direction Y, the gate 60 is located between the source 30 and the drain 40 and the gate 60 forms a Schottky contact with the epitaxial structure 20; the semiconductor device further includes a first compensation gate 70, the first compensation gate 70 extends along the first direction X and at least part of it is located in the isolation region 402; at least one first compensation gate 70 is provided in the same isolation region 402; the semiconductor device further includes a gate connection part 80, the gate connection part 80 extends along the second direction Y, and the same first compensation gate 70 is electrically connected to the gate 60 through at least one gate connection part 80.

[0070] Specifically, the first compensation gate 70 is located in the isolation region 402, and the same first compensation gate 70 is electrically connected to the gate 60 through at least one gate connection part 80. That is to say, the first compensation gate 70 is electrically connected to the gate 60 through the gate connection part 80, which is equivalent to the first compensation gate 70 and the gate 60 being connected in parallel through the gate connection part 80. In this way, the resistance of the gate 60 can be reduced and the working performance of the semiconductor device can be improved.

[0071] Further, continuing to refer to Figure 5 shown, the semiconductor device provided by the embodiment of the present invention may further include a gate power supply electrode 140 located in the passive region bb, and the first compensation gate 70 can be electrically connected to the gate power supply electrode 140 to further reduce the resistance of the gate 60 and improve the working performance of the semiconductor device.

[0072] It should be noted that Figure 5For illustration purposes, only the example where the first compensation gate 70 is electrically connected to the gate power supply electrode 140 is described. It can be understood that the first compensation gate 70 may not be electrically connected to the gate power supply electrode 140. In this case, the same first compensation gate 70 can be arranged to be electrically connected to the gate 60 through at least two gate connection parts 80 to ensure that the resistance of the gate 60 can be sufficiently reduced. Moreover, along the first direction, the distance between the gate connection part 80 and the gate power supply electrode 140 can be relatively large. For example, there is at least one gate connection part 80, and the distance between it and the gate power supply electrode 140 is greater than the distance between it and the drain power supply electrode 404, so as to ensure the stable transmission of the gate signal.

[0073] It should also be noted that since the isolation region 402 includes a passive region bb, and the first compensation gate 70 is arranged in the passive region bb in the isolation region 402, that is, the first compensation gate 70 does not need to form a Schottky contact with the epitaxial structure 20, and the first compensation gate 70 plays a role in circuit conduction.

[0074] Exemplarily, the first compensation gate 70 and the gate connection part 80 can adopt the same metal material as the gate 60 or a metal material different from the gate 60. The embodiments of the present invention do not specifically limit the materials of the first compensation gate 70 and the gate connection part 80, as long as the resistance of the gate 60 can be reduced. Exemplarily, the gate 60 and the first compensation gate 70 can be arranged on the same layer or on different layers.

[0075] Optionally, continuing to refer to Figure 5 , along the second direction Y, the width of the first compensation gate 70 is greater than the width of the gate 60.

[0076] Specifically, along the second direction Y, the width of the first compensation gate 70 is greater than the width of the gate 60. In this way, on the one hand, by increasing the width of the first compensation gate 70, it is beneficial to reduce the gate resistance.

[0077] It can be understood that Figure 5 Only the technical solution where each isolation region 402 includes one first compensation gate 70 is shown, and each first compensation gate 70 is electrically connected to the gate 60 through two gate connection parts 80. It should be noted that each isolation region 402 may also include multiple first compensation gates 70, and each first compensation gate 70 and the gate 60 can be electrically connected through one or more gate connection parts 80. The embodiments of the present invention do not specifically limit the number of the first compensation gate 70 and the gate connection part 80.

[0078] It should be noted that along the thickness direction Z of the semiconductor device, the thickness of the first compensation gate 70 can be greater than the thickness of the gate 60. In this way, the gate resistance can also be reduced, and the performance of the semiconductor device can be improved.

[0079] Optionally, continue to refer to Figure 6 , the gate connection part 80 includes a first connection part 801, a second connection part 802 and a third connection part 803. The first connection part 801 is in contact connection with the gate 60 and the second connection part 802 respectively, and the third connection part 803 is in contact connection with the first compensation gate 70 and the second connection part 802 respectively; at least part of the first connection part 801 is exposed to the air, the second connection part 802 is exposed to the air, and at least part of the third connection part 803 is exposed to the air.

[0080] Specifically, the first connection part 801, the second connection part 802 and the third connection part 803 surround the drain 40. At least part of the first connection part 801 is exposed to the air, the second connection part 802 is exposed to the air, and at least part of the third connection part 803 is exposed to the air. That is to say, along the thickness direction Z of the semiconductor device, there is air between the drain 40 and the gate connection part 80, rather than other supporting materials. That is, the gate connection part 80 forms an air bridge structure. In this way, on the one hand, the breakdown voltage can be increased and the voltage withstand performance of the semiconductor device can be improved. On the other hand, there is air between the drain 40 and the gate connection part 80, which can increase the distance between the gate connection part 80 and the drain 40, thereby reducing the parasitic capacitance between the gate 60 and the drain 40 and improving the working performance of the semiconductor device.

[0081] It can be understood that before preparing the gate connection part 80, photoresist or some other sacrificial materials can be prepared between the film layer where the drain 40 is located and the film layer where the second connection part 802 is located, and then the photoresist or sacrificial materials are removed after preparing the gate connection part 80. In this way, the medium between the drain 40 and the gate connection part 80 is air.

[0082] Optionally, Figure 7 is Figure 5 a second cross-sectional structure schematic diagram of a semiconductor device along the section line C-C', as Figure 7 shown, the gate connection part 80 includes a first connection part 801, a second connection part 802 and a third connection part 803. The first connection part 801 is in contact connection with the gate 60 and the second connection part 802 respectively, and the third connection part 803 is in contact connection with the first compensation gate 70 and the second connection part 802 respectively; the semiconductor device further includes a first insulating layer 90. The first insulating layer 90 is located between the film layer where the drain 40 is located and the film layer where the second connection part 802 is located, and the thickness h1 of the first insulating layer 90 satisfies h1>1μm.

[0083] Specifically, the first insulating layer 90 is located between the film layer where the drain 40 is located and the film layer where the second connection part 802 is located. In this way, the second connection part 802 can be supported by the first insulating layer 90, that is, the gate connection part 80 forms a dielectric bridge structure, so that the stability of the gate connection part 80 can be ensured.

[0084] Furthermore, the thickness h1 of the first insulating layer 90 satisfies h1 > 1 μm. In this way, it can be ensured that along the semiconductor thickness direction Z, the distance between the second connection portion 802 and the drain 40 is relatively large, the parasitic capacitance between the gate connection portion 80 and the drain 40 can be reduced, and further the parasitic capacitance between the gate 60 and the drain 40 can be reduced, improving the performance of the semiconductor device. And setting the thickness h1 of the first insulating layer 90 to satisfy h1 > 1 μm can also prevent breakdown between the gate 60 and the drain 40.

[0085] It can be understood that Figure 5 only the technical solution in which the isolation region 402 includes the passive region bb, and a first compensation gate and a gate connection portion are provided in the isolation region 402 to reduce the gate resistance is taken as an example. It should be noted that other structures can also be provided in the isolation region 402 to improve the performance of the semiconductor device.

[0086] Optionally, Figure 8 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. Figure 9 is Figure 8 a first cross-sectional structure schematic diagram of a semiconductor device along the section line D-D', as Figure 8 and Figure 9 shown, the isolation region 402 includes the active region aa. By setting the isolation region 402 to include the active region aa, other structures that require two-dimensional electron gas can be provided in the active region aa. For example, the working primitive cells of the semiconductor device can be increased in this isolation region. The total gate width is increased on the premise of keeping the total area of the semiconductor device unchanged.

[0087] Specifically, continuing to refer to Figure 8 and Figure 9 , the semiconductor device further includes a compensation source electrode 100 and a second compensation gate 110. The compensation source electrode 100 extends along the first direction X and at least partially lies in the isolation region 402. The second compensation gate 110 extends along the first direction X and at least partially lies in the isolation region 402. The compensation source electrode 100 forms an ohmic contact with the epitaxial structure 20, and the second compensation gate 110 forms a Schottky contact with the epitaxial structure 20. One compensation source electrode 100 and two second compensation gates 110 are provided in the same isolation region 402. Along the second direction Y, the second compensation gate 110 is located between the compensation source electrode 100 and the drain distribution 401.

[0088] Specifically, along the second direction Y, the second compensation gate 110 is located between the compensation source 100 and the drain segment 401. By disposing the compensation source 100 in the isolation region 402, and the isolation region 402 includes the active region aa, the compensation source 100 forms an ohmic contact with the epitaxial structure 20, that is, the compensation source 100 has the same function as the source 30 outside the isolation region 402. In addition, by disposing the second compensation gate 110 in the isolation region 402, and the isolation region 402 includes the active region aa, the second compensation gate 110 forms a Schottky contact with the epitaxial structure 20, that is, the second compensation gate 110 has the same function as the gate 60 outside the isolation region 402. By adding the second compensation gate 110 in the isolation region 402, on the one hand, the gate width can be increased, and the working area of the semiconductor can be increased within the limited area of the semiconductor device, that is, a cell structure of the compensation source 100 - the second compensation gate 110 - the drain segment 401 can be formed within the same drain 40, thereby improving the working performance of the semiconductor device.

[0089] Optionally, continue to refer to Figure 8 , along the second direction Y, the width of the compensation source 100 is smaller than the width of the source 30, and along the thickness direction Z of the semiconductor device, the compensation source 100 does not overlap with the connection structure 301; and, the semiconductor device further includes a source connection portion 120, and the source connection portion 120 extends along the second direction Y; the compensation source 100 is electrically connected to the source 30 through the source connection portion 120.

[0090] Specifically, along the second direction Y, the width of the compensation source 100 is smaller than the width of the source 30, and along the thickness direction Z of the semiconductor device, the compensation source 100 does not overlap with the connection structure 301, that is, the connection structure 301 is not provided in the compensation source 100, but is electrically connected to the source 30 through the source connection portion 120, which is beneficial to realizing the miniaturized design of the semiconductor device.

[0091] It should be noted that Figure 8 taking the source connection portion 120 located in the passive region bb as an example for illustration, it can be understood that the source connection portion 120 can also be located in the active region (not shown in the figure), and the specific setting position of the source connection portion 120 in the embodiments of the present invention is not limited, as long as the electrical connection between the compensation source 100 and the source 30 is realized through the source connection portion 120.

[0092] Optionally, continue to refer to Figure 9, the source connection portion 120 includes a fourth connection portion 1201, a fifth connection portion 1202, and a sixth connection portion 1203. The fourth connection portion 1201 is in contact connection with the source electrode 30 and the fifth connection portion 1202 respectively, and the sixth connection portion 1203 is in contact connection with the compensation source electrode 100 and the fifth connection portion 1202 respectively; at least part of the fourth connection portion 1201 is exposed to the air, the fifth connection portion 1202 is exposed to the air, and at least part of the sixth connection portion 1203 is exposed to the air.

[0093] Specifically, the fourth connection portion 1201, the fifth connection portion 1202, and the sixth connection portion 1203 surround the gate 60 and the second compensation gate 110. At least part of the fourth connection portion 1201 is exposed to the air, the fifth connection portion 1202 is exposed to the air, and at least part of the sixth connection portion 1203 is exposed to the air. That is to say, along the thickness direction Z of the semiconductor device, there is air between the gate 60 and the source connection portion 120, and there is air between the second compensation gate 110 and the source connection portion 120, rather than other supporting materials. That is, the source connection portion 120 forms an air bridge structure. In this way, on the one hand, the breakdown voltage can be increased, and the breakdown voltage resistance performance of the semiconductor device can be improved. On the other hand, there is air between the gate 60 and the source connection portion 120, which can increase the distance between the source connection portion 120 and the gate 60 and the second compensation gate 110, thereby reducing the parasitic capacitance between the gate 60 and the source electrode 30 and improving the working performance of the semiconductor device.

[0094] It can be understood that before preparing the source connection portion 120, photoresist or some other sacrificial materials can be prepared between the film layer where the gate 60 is located and the film layer where the fifth connection portion 1202 is located, and then the photoresist or sacrificial materials are removed after preparing the source connection portion 120. In this way, the medium between the gate 60 and the source connection portion 120 is air.

[0095] Optionally, Figure 10 is Figure 8 a second cross-sectional structure schematic diagram of a semiconductor device along the section line D-D’, as Figure 10 shown, the source connection portion 120 includes a fourth connection portion 1201, a fifth connection portion 1202, and a sixth connection portion 1203. The fourth connection portion 1201 is in contact connection with the source electrode 30 and the fifth connection portion 1202 respectively, and the sixth connection portion 1203 is in contact connection with the compensation source electrode 100 and the fifth connection portion 1202 respectively; the semiconductor device further includes a second insulating layer 130. The second insulating layer 130 is located between the film layer where the gate 60 is located and the film layer where the fifth connection portion 1202 is located, and the thickness h2 of the second insulating layer 130 satisfies h2 > 0.3μm.

[0096] Specifically, the second insulating layer 130 is located between the film layer where the gate 60 is located and the film layer where the fifth connecting portion 1202 is located. In this way, the fifth connecting portion 1202 can be supported by the second insulating layer 130, that is, the source connecting portion 120 forms a dielectric bridge structure, and thus the stability of the source connecting portion 120 can be ensured.

[0097] Furthermore, the thickness h2 of the second insulating layer 130 satisfies h2 > 0.3 μm. In this way, it can be ensured that the distance between the fifth connecting portion 1202 and the gate 60 is large along the semiconductor thickness direction Z, and thus the parasitic capacitance between the gate 60 and the source 30 can be reduced, improving the performance of the semiconductor device.

[0098] It can be understood that Figure 8 only taking the technical solution that the isolation region 402 includes the active region aa, and a second compensation gate 110 is provided in the isolation region 402 to reduce the gate resistance and the working area can be increased within the limited area of the semiconductor device by providing a compensation source 100 and a second compensation gate 110 in the isolation region 402 as an example. It should be noted that other structures can also be provided in the isolation region to improve the performance of the semiconductor device.

[0099] It should be understood that, from the perspective of semiconductor device design, in the embodiments of the present invention, by overlapping the isolation region and the back electrode along the thickness direction of the semiconductor device, the parasitic capacitance between the back metal and the drain can be reduced, thereby improving the performance of the semiconductor device. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMTs) operating in high-voltage and high-current environments, transistors with a silicon-on-insulator (SOI) structure, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors. The isolation regions provided in the semiconductor devices according to the embodiments of the present invention can be widely used in the manufacturing fields of semiconductor devices such as radio frequency microwaves and power electronics. In particular, for gallium nitride electronic devices with a wide bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, the advantages are more obvious, and they can better meet the high-performance requirements of rapidly developing fields such as electronic communication.

[0100] Note that the above are only the preferred embodiments of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate and an epitaxial structure located on one side of the substrate; A source electrode, a drain electrode, and a back electrode. The source electrode and the drain electrode are located on the side of the epitaxial structure away from the substrate, and both the source electrode and the drain electrode extend along a first direction and are arranged along a second direction; the back electrode is located on the side of the substrate away from the epitaxial structure, and the back electrode is electrically connected to the source electrode through a connection structure located in the substrate and the epitaxial structure; the first direction and the second direction intersect and are both parallel to the plane of the substrate; The same drain electrode includes at least two drain segments and at least one isolation region. The at least two drain segments extend along the first direction and are arranged along the second direction. Along the second direction, the isolation region is located between two adjacent drain segments; along the thickness direction of the semiconductor device, the isolation region overlaps with the back electrode.

2. The semiconductor device according to claim 1, wherein, Along the second direction, the width d of the drain segment satisfies 0 < d < 10 μm.

3. The semiconductor device according to claim 1, wherein The drain electrode further includes a drain connection portion that extends along the second direction; Along the first direction, the drain connection portion is located between the drain segment and the drain power supply electrode. The drain connection portion connects at least two drain segments in the same drain electrode and is electrically connected to the drain power supply electrode.

4. The semiconductor device according to claim 1, characterized in that, The isolation region includes a passive region.

5. The semiconductor device according to claim 4, wherein The semiconductor device further includes a gate electrode. Along the second direction, the gate electrode is located between the source electrode and the drain electrode and the gate electrode forms a Schottky contact with the epitaxial structure; The semiconductor device further includes a first compensation gate electrode that extends along the first direction and at least partially located in the isolation region; at least one first compensation gate electrode is provided in the same isolation region; The semiconductor device further includes a gate connection portion that extends along the second direction, and the same first compensation gate electrode is electrically connected to the gate electrode through at least one gate connection portion.

6. The semiconductor device according to claim 5, wherein, Along the second direction, the width of the first compensation gate electrode is greater than the width of the gate electrode.

7. The semiconductor device according to claim 5, wherein The gate connection portion includes a first connection portion, a second connection portion, and a third connection portion. The first connection portion is in contact connection with the gate electrode and the second connection portion respectively. The third connection portion is in contact connection with the first compensation gate electrode and the second connection portion respectively; At least part of the first connection portion is exposed to the air, the second connection portion is exposed to the air, and at least part of the third connection portion is exposed to the air.

8. The semiconductor device according to claim 5, wherein, The gate connection portion includes a first connection portion, a second connection portion, and a third connection portion. The first connection portion is in contact connection with the gate electrode and the second connection portion respectively. The third connection portion is in contact connection with the first compensation gate electrode and the second connection portion respectively; The semiconductor device further includes a first insulating layer that is located between the film layer where the drain electrode is located and the film layer where the second connection portion is located, and the thickness h1 of the first insulating layer satisfies h1 > 1 μm.

9. The semiconductor device according to claim 1, wherein The isolation region includes an active region.

10. The semiconductor device according to claim 9, wherein The semiconductor device further includes a compensation source electrode and a second compensation gate electrode. The compensation source electrode extends along the first direction and is at least partially located in the isolation region. The second compensation gate electrode extends along the first direction and is at least partially located in the isolation region; The compensation source electrode forms an ohmic contact with the epitaxial structure, and the second compensation gate electrode forms a Schottky contact with the epitaxial structure; One compensation source electrode and two second compensation gate electrodes are provided in the same isolation region. Along the second direction, the second compensation gate electrode is located between the compensation source electrode and the drain portion.

11. The semiconductor device according to claim 10, wherein, Along the second direction, the width of the compensation source electrode is smaller than the width of the source electrode, and along the thickness direction of the semiconductor device, the compensation source electrode does not overlap with the connection structure; Moreover, the semiconductor device further includes a source electrode connection portion that extends along the second direction. The compensation source electrode is electrically connected to the source electrode through the source electrode connection portion.

12. The semiconductor device according to claim 11, wherein, The source electrode connection portion includes a fourth connection portion, a fifth connection portion, and a sixth connection portion. The fourth connection portion is in contact connection with the source electrode and the fifth connection portion respectively. The sixth connection portion is in contact connection with the compensation source electrode and the fifth connection portion respectively; At least part of the fourth connection portion is exposed to the air, the fifth connection portion is exposed to the air, and at least part of the sixth connection portion is exposed to the air.

13. The semiconductor device according to claim 11, wherein, The source electrode connection portion includes a fourth connection portion, a fifth connection portion, and a sixth connection portion. The fourth connection portion is in contact connection with the source electrode and the fifth connection portion respectively. The sixth connection portion is in contact connection with the compensation source electrode and the fifth connection portion respectively; The semiconductor device further includes a second insulating layer that is located between the film layer where the gate electrode is located and the film layer where the fifth connection portion is located, and the thickness h2 of the second insulating layer satisfies h2 > 0.3 μm.

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