Method for improving gate oxide residue and semiconductor device
By forming a second hard mask layer covering in the second device region and removing the oxide layer, the post-etch residue problem caused by the difference in the thickness of the oxide layer in the short region of the gate channel length is solved, and the reliability and performance of the semiconductor device are ensured.
Patent Information
- Application Number
- CN202510332167.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, the difference in the thickness of the dielectric oxide layer of the long gate channel and the short region leads to a gate defect after dry etching, which cannot be covered by the side wall protective layer, resulting in the residual oxide layer and corrosion in subsequent processes, resulting in device failure.
Before the second device region forms the second gate structure, a second hard mask layer is deposited to cover the first device region, expose and remove the second oxide layer by etching, and completely cover the oxide layer at the bottom of the second gate structure when forming the side wall to avoid chemical reagent corrosion.
It effectively avoids corrosion of the gate structure by residual oxide layer, improves the pass rate and performance reliability of semiconductor devices, and prevents device failure.
Smart Images
Figure CN120282531A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the residue of a gate oxide layer and a semiconductor device. Background Art
[0002] In the prior art, for gate regions with different channel lengths, since the thickness of the dielectric oxide layer in the region with a longer gate channel is greater than that in the region with a shorter gate channel, before dry etching to form a gate, there are already significant differences in the thickness of the oxide layers in the two regions. The gate etching process is carried out in a high selectivity manner. To avoid damaging the substrate, there is a residue of the dielectric oxide layer in the region with a longer gate channel. Since the remaining dielectric oxide layer cannot be covered by the sidewall protection layer, it is easily corroded by chemical reagents in subsequent processes, thereby causing the problem of gate defects and ultimately leading to the failure of the device.
[0003] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for improving the residue of a gate oxide layer and a semiconductor device to solve the problem of residue in the dielectric oxide layer of the gate.
[0005] To solve the above technical problems, the present invention provides a method for improving the residue of a gate oxide layer, including:
[0006] Providing a substrate, on the surface of which an isolation region is formed to define an active region, at least a first device region and a second device region are formed on the active region, an oxide layer and a polysilicon layer are sequentially deposited on the surface of the substrate from the substrate upwards, the oxide layer in the first device region is defined as the first oxide layer, the oxide layer in the second device region is defined as the second oxide layer, and the thickness of the first oxide layer is less than that of the second oxide layer;
[0007] Forming a first gate structure in the first device region;
[0008] Forming a second hard mask layer, which covers the first device region and the second device region;
[0009] Forming a second gate structure in the second device region and exposing the remaining second oxide layer in the second device region;
[0010] Removing the second hard mask layer and simultaneously removing the remaining second oxide layer in the second device region.
[0011] Preferably, forming the first gate structure in the first device region includes:
[0012] Deposit a first hard mask layer and a photoresist on the surface of the polysilicon layer in sequence;
[0013] Pattern the photoresist to form a first photoresist pattern;
[0014] Using the first photoresist pattern as a mask, etch the first hard mask layer, the polysilicon layer, and the first oxide layer to form a first gate structure in the first device region.
[0015] Preferably, forming the second gate structure in the second device region and exposing the remaining second oxide layer in the second device region includes:
[0016] Deposit a photoresist, which fills the first device region and covers the surface of the second device region;
[0017] Pattern the photoresist to form a second photoresist pattern;
[0018] Using the second photoresist pattern as a mask, etch the second hard mask layer, the first hard mask layer, the polysilicon layer, and the second oxide layer in the second device region to form a second gate structure in the second device region and expose the remaining second oxide layer in the second device region.
[0019] Preferably, after removing the second hard mask layer and simultaneously removing the remaining second oxide layer in the second device region, the method further includes:
[0020] Form sidewalls on both sides of the first gate structure and the second gate structure, and the sidewalls cover the second oxide layer at the bottom of the second gate structure.
[0021] Preferably, the second hard mask layer and the second oxide layer are made of the same material.
[0022] Preferably, the material of the second hard mask layer includes one or any combination of silicon dioxide, silicon oxynitride, and high-K materials.
[0023] Preferably, the second hard mask layer and the second oxide layer have the same thickness.
[0024] Preferably, the thickness of the second hard mask layer and the second oxide layer is 50 μm to 100 μm.
[0025] Preferably, dry etching or wet etching is used to remove the second hard mask layer and the remaining second oxide layer.
[0026] Based on the same inventive concept, the present invention also provides a semiconductor device, including:
[0027] Manufactured by using the method for improving the gate oxide layer residue as described above.
[0028] Compared with the prior art, the method for improving the gate oxide layer residue of the present invention has the following advantages:
[0029] Before forming the second gate structure in the second device region, the present invention deposits a second hard mask layer to protect the first gate structure in the first device region, thereby avoiding affecting the first gate structure when removing the residual second oxide layer. By exposing the residual second oxide layer while forming the second gate structure, the residual second oxide layer can be removed while removing the second hard mask layer. When forming the sidewall of the second gate structure, the second oxide layer at the bottom of the second gate structure can be completely coated, thereby avoiding the technical problem of defects in the second gate structure caused by the corrosion of the second oxide layer at the bottom of the second gate structure by chemical reagents in subsequent processes such as etching and cleaning, improving the qualification rate of semiconductor devices, ensuring the reliability of the performance of semiconductor devices, and avoiding the failure of semiconductor devices.
[0030] The semiconductor device provided by the present invention and the method for improving the gate oxide layer residue provided by the present invention belong to the same inventive concept. Therefore, the semiconductor device provided by the present invention has at least all the advantages of the method for improving the gate oxide layer residue provided by the present invention, improving the qualification rate of semiconductor devices, ensuring the reliability of the performance of semiconductor devices, and avoiding the failure of semiconductor devices. Description of the Drawings
[0031] Figure 1 It is a schematic diagram of the distribution of the first device region and the second device region in an embodiment;
[0032] Figure 2 It is a schematic diagram of forming the first gate structure and the second gate structure on the surface of the substrate in an embodiment;
[0033] Figure 3 It is a schematic diagram of having an oxide layer remaining in the second device region in an embodiment;
[0034] Figure 4 It is a flowchart of the method for improving the gate oxide layer residue in an embodiment of the present invention;
[0035] Figure 5 It is a schematic diagram of patterning the first gate structure in an embodiment of the present invention;
[0036] Figure 6 It is a schematic diagram of forming the first gate structure in an embodiment of the present invention;
[0037] Figure 7 It is a schematic diagram of forming the second hard mask layer in an embodiment of the present invention;
[0038] Figure 8 It is a schematic diagram of patterning the second gate structure in an embodiment of the present invention;
[0039] Figure 9 It is a schematic diagram of forming the second gate structure in an embodiment of the present invention;
[0040] Figure 10 It is a schematic diagram after removing the photoresist in an embodiment of the present invention;
[0041] Figure 11 It is a schematic diagram of removing the second hard mask layer in an embodiment of the present invention;
[0042] Figure 12 It is a schematic diagram of forming sidewalls on the first gate structure and the second gate structure in an embodiment of the present invention;
[0043] In the figure,
[0044] 100 - substrate; 110 - first gate structure;
[0045] 120 - second gate structure; 130 - sidewall;
[0046] 210 - first oxide layer; 220 - second oxide layer;
[0047] 300 - polysilicon layer; 400 - first hard mask layer;
[0048] 500 - isolation region; 600 - photoresist;
[0049] 700 - second hard mask layer. Detailed implementation manners
[0050] To make the objectives, advantages, and features of the present invention clearer, the following further elaborates on the method for improving the residual of the gate oxide layer and the semiconductor device proposed by the present invention in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in extremely simplified forms and use non - precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used between different drawings to represent the same part or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0051] Furthermore, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0052] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0053] As shown in Figures 1 to 3 For the normal pressure CMOS operating voltage, it is divided into a first device region and a second device region. The first device region and the second device region are formed on the substrate 100. The first device region therein is the core device region. The second device region is the input / output (IO) device region. A thin first oxide layer 210 is formed on the core device region, and its operating voltage is usually 0.9V or 1.8V. A thick second oxide layer 220 is formed on the input / output device region, and its operating voltage is usually 0.9V or 2.5V.
[0054] Before gate etching, the thicknesses of the oxide layers in the two regions are as Figure 1 shown, and there are already significant differences. When etching the polysilicon layer 300 and the oxide layer in the core device region and the input / output device region through an etching process, a high selectivity method is selected to prevent damage to the underlying oxide layer (i.e., the substrate 100). As Figure 2 shown, there will be a residual second oxide layer 220 in the input / output device region. At the second gate structure 120 after the finally formed sidewall 130, there are still residual second oxide layers 220 at positions b and c as in Figure 3 . The second oxide layer 220 at this position cannot be covered by the sidewall 130 protection layer. In subsequent processes, such as etching, cleaning, and other process steps, chemical reagents are likely to corrode the second oxide layer 220, resulting in defects in the gates of the input / output region.
[0055] The core idea of the present invention is to provide a method for improving the residual of the gate oxide layer, which can solve the technical problem of the residual of the gate oxide layer in the input / output device region.
[0056] To achieve the above idea, the present invention provides a method for improving the residual of the gate oxide layer, referring to Figures 4 to 12 a specific implementation manner of a method for improving the residual of the gate oxide layer disclosed. The method for improving the residual of the gate oxide layer includes the following steps S1 to S5.
[0057] Step S1: Provide a substrate 100, on the surface of which an isolation region 500 is formed to define an active region, and at least a first device region and a second device region are formed on the active region. An oxide layer and a polysilicon layer 300 are sequentially deposited on the surface of the substrate 100 from the substrate 100 upwards. Define the oxide layer of the first device region as the first oxide layer 210, and define the oxide layer of the second device region as the second oxide layer 220. The thickness of the first oxide layer 210 is less than the thickness of the second oxide layer 220.
[0058] Specifically, referring to Figure 4 and Figure 5 as shown, provide a substrate 100. The material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, etc., or it can be silicon on insulator, germanium on insulator, or it can also be other materials, for example, III-V group compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is silicon. An isolation region 500 is formed on the surface of the substrate 100. The isolation region therein can be shallow trench isolation (STI). The isolation region 500 is used to define an active region, and at least a first device region and a second device region are formed on the active region. The first device region and the second device region can be used to form a normally-on CMOS. That is, the first device region can be the core device region in the above text. The second device region can be the input / output region in the above text. The first device region and the second device region can also be used to form semiconductor devices with different oxide layer thicknesses such as a central processing unit, a graphics processing unit, and an analog integrated circuit.
[0059] On the surface of the substrate 100, an oxide layer and a polysilicon layer 300 are sequentially formed upward from the substrate 100. The oxide layer and the polysilicon layer 300 are used to form the gate structures of the first device region and the second device region. The material of the oxide layer can be silicon dioxide (SiO2), silicon oxynitride (SiON), high-K material, or any combination thereof. The high-K materials include hafnium oxide (HfO2), zirconium oxide (ZrO2), etc. The oxide layer of the first device region is defined as the first oxide layer 210, and the oxide layer of the second device region is defined as the second oxide layer 220. The thickness of the first oxide layer 210 is less than the thickness of the second oxide layer 220. The first oxide layer 210 and the second oxide layer 220 are etched through subsequent processes to form gate oxide layers respectively.
[0060] The active region may also form a cutting area as Figure 5 shown. This cutting area is used to protect the structure at the edge of the chip (composed of multiple semiconductor devices). In practical applications, it does not belong to a part of the chip function, but is an auxiliary area in the chip manufacturing process. Since this cutting area has nothing to do with the inventive point of the present invention, it will not be elaborated in detail here.
[0061] Step S2: Form a first gate structure 110 in the first device region.
[0062] Specifically, referring to Figures 4 to 6 shown, forming the first gate structure 110 in the first device region includes:
[0063] First, deposit a first hard mask layer 400 and a photoresist 600 on the surface of the polysilicon layer 300 in sequence. The first hard mask layer 400 serves as a protection layer and an etch stop layer for subsequent etching processes. The material of the first hard mask layer 400 can be silicon nitride (SiN), silicon oxide (OX), etc. In this embodiment, SiN is preferably used as the first hard mask layer 400. The photoresist 600 can be a positive photoresist or a negative photoresist. Preferably, the photoresist 600 is a positive photoresist.
[0064] Next, pattern the photoresist 600 to form a first photoresist pattern. Transfer the pattern of the gate structure in the first device region to the photoresist. The photoresist 600 in the second device region is retained, and the retained photoresist 600 plays a protective role in the subsequent photolithography process to prevent the second device region from being etched.
[0065] Then, using the first photoresist pattern as a mask, etch the first hard mask layer 400, the polysilicon layer 300, and the first oxide layer 210 to form a first gate structure 110 in the first device region, that is, form a structure as Figure 6 shown. The first oxide layer 210 of the first gate structure 110 is defined as the first gate oxide layer.
[0066] Step S3: Form a second hard mask layer 700 that covers the first device region and the second device region.
[0067] Specifically, referring Figure 4 and Figure 7 as shown, form a second hard mask layer 700, and the second hard mask layer 700 completely covers the first device region and the second device region, forming a structure as Figure 7 shown. The method for forming the second hard mask layer 700 can be any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The material of the second hard mask layer 700 can be SiN, OX, etc. In this embodiment, preferably, the material of the second hard mask layer 700 is the same as the material of the second oxide layer 220. The material of the second oxide layer 220 can be silicon dioxide (SiO2), silicon oxynitride (SiON), high-K material, or any combination thereof. Then, the material of the second hard mask layer 700 can also be silicon dioxide (SiO2), silicon oxynitride (SiON), high-K material, or any combination thereof.
[0068] Step S4: Form a second gate structure 120 in the second device region and expose the remaining second oxide layer 220 in the second device region.
[0069] Specifically, referring Figures 4 to 9 as shown, forming a second gate structure 120 in the second device region and exposing the remaining second oxide layer 220 in the second device region includes:
[0070] First, deposit a photoresist 600, and the photoresist 600 fills the first device region and covers the surface of the second device region. Fill the gaps between the first gate structures 110 in the first device region. The height of the photoresist 600 filled in the first device region is higher than the height of the first gate structures 110. The surface of the second hard mask layer 700 in the second device region is also covered with the photoresist 600.
[0071] Then, pattern the photoresist 600 to form a second photoresist pattern. Transfer the gate pattern in the second device region to the photoresist 600 to form a photoresist pattern as Figure 8 shown, that is, form a second photoresist pattern. The photoresist 600 in the first device region remains, and the remaining photoresist 600 plays a protective role in the subsequent etching process for the first device region.
[0072] Next, using the second photoresist pattern as a mask, etch the second hard mask layer 700, the first hard mask layer 400, the polysilicon layer 300, and the second oxide layer 220 in the second device region to form a structure as Figure 9The second gate structure 120 shown is provided, and the remaining second oxide layer 220 in the second device region is exposed. The second oxide layer 220 in the second gate structure 120 is defined as the second gate oxide layer. The thickness of the second gate oxide layer is greater than that of the first gate oxide layer. The thickness range of the second gate oxide layer is 50μm to 100μm. That is, the thickness of the second gate oxide layer can be 50μm, 60μm, 80μm, 100μm, or any thickness within the range of 50μm to 100μm. In this embodiment, preferably, the materials of both the first gate oxide layer and the second gate oxide layer are silicon dioxide, and the material of the second hard mask layer 700 is also silicon dioxide. In subsequent process steps, it is necessary to remove both the second hard mask layer 700 and the remaining second oxide layer 220 simultaneously. Therefore, preferably, the thickness range of the second hard mask layer 700 is 50μm to 100μm. That is, the thickness of the second hard mask layer 700 can be 50μm, 60μm, 80μm, 100μm, or any thickness within the range of 50μm to 100μm. Further, preferably, the thickness of the second oxide layer 220 is the same as that of the second hard mask layer 700. The length of the second gate structure 120 is greater than that of the first gate structure 110. That is, the channel length of the second gate structure 120 is greater than the channel length of the first gate structure 110.
[0073] Step S5: Remove the second hard mask layer 700 and simultaneously remove the remaining second oxide layer 220 in the second device region.
[0074] Specifically, referring to Figure 4 、 Figures 10 to 12 shown, after removing the photoresist 600, the structure shown in Figure 10 is formed. Then, wet etching or dry etching is used to remove the second hard mask layer 700. Since the second hard mask layer 700 and the remaining second oxide layer 220 have the same material and the same thickness. Therefore, when removing the second hard mask layer 700, the remaining second oxide layer 220 can be removed simultaneously, forming the structure shown in Figure 11 . Finally, spacers 130 are formed on both sides of the first gate structure 110 and the second gate structure 120 as protective layers. As can be seen from Figure 12 at b and c, there is no remaining second oxide layer 220. Therefore, the spacer 130 can cover the second gate oxide layer. By using the covered spacer 130 as the protective layer of the second gate oxide layer, chemical reagents are prevented from corroding the second gate oxide layer during subsequent etching, cleaning and other processes.
[0075] In this embodiment, before forming the second gate structure 120 in the second device region, a second hard mask layer 700 is deposited to protect the first gate structure 110 in the first device region, so as to avoid affecting the first gate structure 110 when removing the remaining second oxide layer 220. By exposing the remaining second oxide layer 220 while forming the second gate structure 120, the remaining second oxide layer 220 can be removed while removing the second hard mask layer 700. Thus, when forming the sidewall 130 of the second gate structure 120, the second gate oxide layer can be completely coated, so as to avoid the technical problem of defects in the second gate structure 120 caused by the corrosion of the second gate oxide layer 200 by chemical reagents in subsequent processes such as etching and cleaning, improve the qualified rate of semiconductor devices, ensure the reliability of the performance of semiconductor devices, and avoid the failure of semiconductor devices.
[0076] To implement the above idea, this embodiment also discloses a semiconductor device, including:
[0077] Manufactured by using the method for improving the residue of the gate oxide layer as described above.
[0078] The semiconductor device provided in this embodiment and the method for improving the residue of the gate oxide layer provided in this embodiment belong to the same inventive concept. Therefore, the semiconductor device provided in this embodiment has at least all the advantages of the method for improving the residue of the gate oxide layer provided in this embodiment, improves the qualified rate of semiconductor devices, ensures the reliability of the performance of semiconductor devices, and avoids the failure of semiconductor devices.
[0079] In summary, the above embodiments have described in detail the method for improving the residue of the gate oxide layer and different configurations of semiconductor devices. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation on the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the content of the above embodiments. Any changes and modifications made by ordinary technical personnel in the field of the present invention based on the above disclosure fall within the protection scope of the claims.
Claims
1. A method for improving the residue of the gate oxide layer, characterized in that, Including: Providing a substrate, an isolation region is formed on the surface of the substrate to define an active region, at least a first device region and a second device region are formed on the active region, an oxide layer and a polysilicon layer are sequentially deposited on the surface of the substrate from the substrate upwards, the oxide layer of the first device region is defined as a first oxide layer, the oxide layer of the second device region is defined as a second oxide layer, and the thickness of the first oxide layer is less than the thickness of the second oxide layer; Forming a first gate structure in the first device region; Forming a second hard mask layer, the second hard mask layer covering the first device region and the second device region; Forming a second gate structure in the second device region and exposing the remaining second oxide layer in the second device region; Removing the second hard mask layer and simultaneously removing the remaining second oxide layer in the second device region.
2. The method for improving the residue of the gate oxide layer according to claim 1, wherein The forming the first gate structure in the first device region includes: Sequentially depositing a first hard mask layer and a photoresist on the surface of the polysilicon layer; Patterning the photoresist to form a first photoresist pattern; Using the first photoresist pattern as a mask, etching the first hard mask layer, the polysilicon layer and the first oxide layer to form a first gate structure in the first device region.
3. The method for improving the residue of the gate oxide layer according to claim 2, wherein The forming the second gate structure in the second device region and exposing the remaining second oxide layer in the second device region includes: Depositing a photoresist, the photoresist filling the first device region and covering the surface of the second device region; Patterning the photoresist to form a second photoresist pattern; Using the second photoresist pattern as a mask, etching the second hard mask layer, the first hard mask layer, the polysilicon layer and the second oxide layer in the second device region to form a second gate structure in the second device region and exposing the remaining second oxide layer in the second device region.
4. The method for improving the residual of the gate oxide layer according to claim 1, wherein, After removing the second hard mask layer and simultaneously removing the remaining second oxide layer remaining in the second device region, the method further includes: Forming sidewalls on both sides of the first gate structure and the second gate structure, the sidewalls covering the second oxide layer at the bottom of the second gate structure.
5. The method for improving the residue of the gate oxide layer according to claim 1, wherein The material of the second hard mask layer is the same as that of the second oxide layer.
6. The method for improving the residue of the gate oxide layer according to claim 5, wherein, The material of the second hard mask layer includes one or any combination of silicon dioxide, silicon oxynitride, and high-K materials.
7. The method for improving the residue of the gate oxide layer according to claim 1, characterized in that The thickness of the second hard mask layer is equal to the thickness of the second oxide layer.
8. The method for improving the residue of the gate oxide layer according to claim 1, wherein The thickness of the second hard mask layer and the second oxide layer is 50μm - 100μm.
9. The method for improving the residue of the gate oxide layer according to claim 1, wherein Removing the second hard mask layer and the remaining second oxide layer by dry etching or wet etching.
10. A semiconductor device, characterized in that, Including: Manufactured by using the method for improving the residue of the gate oxide layer according to any one of claims 1 - 9.