Groove type power metal-oxide-semiconductor field effect transistor and preparation process thereof

Abstract

The invention belongs to the field of semiconductor devices, and discloses a trench type power metal oxide semiconductor field effect transistor and a preparation process thereof, and the process comprises the following steps: S1, completing a second conductive type Body layer in an implantation manner, completing a first conductive type Body layer and a plurality of trenches I in an active region, and completing a trench II in a terminal region; s2, filling first conductive type polycrystalline silicon on the surface of the gate oxide layer; s3, dry etching is carried out on the first conduction type polycrystalline silicon, so that a concave hole II in the groove II extends to the gate electrode oxide layer at the bottom; s4, filling second conductive type polycrystalline silicon on the surface of the first conductive type polycrystalline silicon; s5, wet etching is carried out on the second conduction type polycrystalline silicon, so that the second conduction type polycrystalline silicon is only filled in the concave hole II; and S6, sequentially manufacturing an interlayer dielectric layer, gate metal and source metal on the surface of the device. According to the invention, the gate-source end electrostatic protection design of NPN can be formed on the premise of not additionally providing the cost of a photomask, so that the ESD protection of the device is realized.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a trench-type power metal-oxide-semiconductor field-effect transistor and a manufacturing process thereof. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a widely used semiconductor device, mainly used for signal amplification and switching control in electronic circuits. The working principle of a MOSFET is to control the current flow between the source and the drain by applying a voltage to the gate. The gate is separated from the semiconductor material by an extremely thin oxide insulating layer, which gives the MOSFET the characteristics of high input impedance and low power consumption. Due to its efficient, reliable, and easy-to-integrate characteristics, the MOSFET plays a crucial role in modern electronic devices such as computers, mobile phones, and power management systems.

[0003] Most metal-oxide-semiconductor field-effect transistors (MOSFETs) have a relatively thin oxide layer, and only a thin oxide layer is used as an insulating material to isolate the gate from the transistors inside the MOSFET. This thin gate oxide layer is extremely vulnerable to damage caused by electrostatic discharge (ESD), and in severe cases, it may even lead to device failure. To effectively prevent accidental failures of MOSFETs caused by ESD, an ESD protection structure is usually integrated into the device.

[0004] However, the design of many ESD protection structures requires additional lithography steps to improve the yield rate, or this protection design is achieved by increasing the device area. However, increasing lithography will increase the process complexity, cost, and production cycle of the process flow. And increasing the device area will occupy more chip space, increase the cost, affect the circuit performance, and increase the difficulty of thermal management. Summary of the Invention

[0005] To solve the deficiencies in the prior art, the present invention provides a trench-type power metal-oxide-semiconductor field-effect transistor and a manufacturing process thereof, which can form an NPN gate-source electrostatic protection design without incurring additional photomask costs, thereby achieving ESD protection for the device.

[0006] The main technical solution adopted in the present invention is as follows: A manufacturing process of a trench-type power metal-oxide-semiconductor field-effect transistor, comprising the following steps: S1: Completing a second-conductivity-type Body layer in a first-conductivity-type epitaxial layer by implantation, and completing a first-conductivity-type Body layer, a plurality of trenches I in the active region, and a trench II in the termination region; S2: Form a gate oxide layer on the device surface at a certain temperature, fill polysilicon of the first conductivity type on the surface of the gate oxide layer, form a cavity I on the surface of the polysilicon of the first conductivity type above the trench I, and form a cavity II on the surface of the polysilicon of the first conductivity type in the trench II; S3: Perform dry etching on the polysilicon of the first conductivity type, so that the cavity II in the trench II extends to the bottom gate oxide layer, and the polysilicon of the first conductivity type on both sides is segmented; S4: Fill polysilicon of the second conductivity type on the surface of the polysilicon of the first conductivity type, and form a cavity III on the surface of the polysilicon of the second conductivity type above the trench II; S5: Perform wet etching on the polysilicon of the second conductivity type, so that the polysilicon of the second conductivity type is only filled in the cavity II, and ensure that the polysilicon of the first conductivity type is removed from the surface; S6: Fabricate an interlayer dielectric layer, a gate metal, and a source metal on the device surface in sequence to obtain a trench-type power metal-oxide-semiconductor field-effect transistor.

[0007] Preferably, in the step S1, the specific processing methods in the active region and the termination region are as follows: S1-1: Complete the Body layer of the first conductivity type in the active region by using the first photolithography process; S1-2: Use the second photolithography process to complete several trenches I in the active region and the trench II in the termination region respectively.

[0008] Preferably, in the step S2, the specific filling method of the polysilicon of the first conductivity type is as follows: Adopt the low-pressure chemical vapor deposition process to fill from the bottom and side walls of the trench I and the trench II towards the middle direction, and form a cavity I on the surface of the polysilicon of the first conductivity type above the trench I, and form a cavity II on the surface of the polysilicon of the first conductivity type in the trench II.

[0009] Preferably, the specific steps of the S6 are as follows: S6-1: Deposit an interlayer dielectric layer on the device surface, and use the photolithography process to etch a gate metal connection channel and several source metal connection channels on the device, wherein the gate metal connection channel is used for the gate metal to connect the polysilicon of the first conductivity type, and the source metal connection channel is used for the source metal to connect the polysilicon of the first conductivity type in the termination region and the Body layer of the second conductivity type in the active region; S6-2: Deposit a metal layer on the surface of the interlayer dielectric layer, in the gate metal connection channel and the source metal connection channel, and use the photolithography process to separate the metal layer to form a gate metal and a source metal.

[0010] Preferably, the width of the trench I is 0.18 - 0.2 um, and the depth > 0.8 um.

[0011] Preferably, the width of the groove II is greater than 2d, and the depth is > 0.8 um, where d is the distance from the side wall of the cavity II to the side wall of the gate oxide layer.

[0012] Preferably, the minimum width of the gate metal connection channel is ≥ 0.1 um.

[0013] Preferably, the minimum width of the source metal connection channel is ≥ 0.1 um.

[0014] A trench-type power metal-oxide-semiconductor field-effect transistor is prepared by the above preparation process.

[0015] Beneficial effects: The present invention provides a trench-type power metal-oxide-semiconductor field-effect transistor and its preparation process, having the following advantages: (1) By forming an NPN structure in the large trench in the present invention and utilizing the synergistic effect of multi-polar polysilicon, an efficient current path is established between the gate and the source, significantly improving the electrostatic discharge (ESD) protection ability at the gate-source end, effectively preventing the device from failing due to electrostatic damage, and ensuring the stability of the device under normal working conditions.

[0016] (2) The present invention makes full use of the large trench structure in the existing process. By filling polysilicon with different polarities and adopting a differential etching process, an electrostatic protection structure at the gate-source end of the NPN structure is constructed in the large trench, skillfully utilizing the existing process without additional photomasks, realizing both the electrostatic protection function and effectively reducing the manufacturing cost and process complexity.

[0017] (3) The present invention directly utilizes the large trench structure in the peripheral terminal area to realize the electrostatic protection function without additional occupation of chip area, improving the chip integration and space utilization rate. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of step S1 of Embodiment 1; Figure 2 It is a schematic structural diagram of step S2 of Embodiment 1; Figure 3 It is a schematic structural diagram of step S3 of Embodiment 1; Figure 4 It is a schematic structural diagram of step S4 of Embodiment 1; Figure 5 It is a schematic structural diagram of step S5 of Embodiment 1; Figure 6 It is a schematic structural diagram of step S6-1 of Embodiment 1 Figure Ⅰ ; Figure 7 It is a schematic structural diagram of step S6-1 of Embodiment 1 Figure Ⅱ ; Figure 8 Schematic diagram of the final device structure of Embodiment 1; In the figure: N-type epitaxial layer 100, P-Body layer 001, N-Body layer 002, trench Ⅰ 003a, trench Ⅱ 003b, gate oxide layer 004, cavity Ⅰ 005a, cavity Ⅱ 005b, cavity Ⅲ 005c, N-type polysilicon 006a, P-type polysilicon 006b, interlayer dielectric layer 007, gate metal connection channel 008a, source metal connection channel 008b, gate metal 009a, source metal 009b. Specific implementation manners

[0019] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application. Embodiment 1

[0020] The following takes the first conduction type as N-type and the second conduction type as P-type as an example to describe the specific implementation manners of Embodiment 1.

[0021] A preparation process of a trench-type power metal-oxide-semiconductor field-effect transistor includes the following steps: S1: As Figure 1 shown, the P-Body layer 001 is completed by implantation in the N-type epitaxial layer 100, and the N-Body layer 002 and trench Ⅰ 003a are completed in the active region A, and trench Ⅱ 003b is completed in the terminal region B; among them, the specific processing methods in the active region A and the terminal region B are as follows: S1-1: The N-Body layer 002 is completed in the active region A by using the first photolithography process; S1-2: The trench Ⅰ 003a is completed in the active region A and the trench Ⅱ 003b is completed in the terminal region by using the second photolithography process.

[0022] In this Embodiment 1, the P-Body layer 001 is formed by boron ion implantation, and its doping concentration is 4e12~3e13 cm -2 ; among them, the N-Body layer 002 can be formed by phosphorus ion or arsenic ion implantation, and its doping concentration is 5e15~1e16 cm -2 ; the width of the trench Ⅰ 003a is 0.18~0.2um, and the depth > 0.8um; the width of the trench Ⅱ 003b is greater than 2d, and the depth > 0.8um, where d is the distance from the side wall surface of the cavity Ⅱ 005b to the side wall surface of the gate oxide layer 004, asFigure 2 As shown, the number of trenches I 003a is set according to the channel design requirements of the actual active region structure.

[0023] In the present invention, the types of implanted ions, the ion doping concentration, the specific widths and depths of the trenches I 003a and the trenches II 003b adopted in the P-Body layer and the N-Body layer can all be selectively designed by those skilled in the art according to actual requirements.

[0024] S2: As Figure 2 shown, a gate oxide layer 004 is formed on the device surface at a temperature of 900 - 1100°C, and N-type polysilicon 006a is filled on the surface of the gate oxide layer 004; wherein, the specific filling method of the N-type polysilicon 006a is as follows: using the low-pressure chemical vapor deposition process, filling from the bottom and side walls of the trenches I 003a and the trenches II 003b towards the middle direction, and forming a cavity I 005a on the surface of the N-type polysilicon 006a above the trench I 003a, and forming a cavity II 005b on the surface of the N-type polysilicon 006a above the trench II 003b.

[0025] In this Embodiment 1, based on the above preparation process of the N-type polysilicon 006a, as Figure 2 shown, the distance from the surface of the N-type polysilicon 006a to the top surface of the gate oxide layer 004 is basically the same as the distance from the side wall surface of the cavity II 005b in the trench II 003b to the side wall surface of the gate oxide layer 004, denoted as d.

[0026] In this Embodiment 1, because the width of the trench II 003b is larger, the cavity II 005b left after filling is larger, while for the trench I 003a in the active region A, due to its smaller width, the cavity I 005a left after filling is smaller or nearly horizontal.

[0027] S3: As Figure 3 shown, dry etching is performed on the N-type polysilicon 006a, so that the cavity II 005b in the trench II 003b extends to the bottom gate oxide layer 004, and the N-type polysilicon 006a on both sides of it is segmented. In this Embodiment 1, non-isotropic etching is used, so that the original cavity II 005b still exists, while the cavity I 005a almost disappears.

[0028] S4: As Figure 4 shown, P-type polysilicon 006b is filled on the surface of the N-type polysilicon 006a, and a cavity III 005c is formed on the surface of the P-type polysilicon 006b above the trench II 003b. In this Embodiment 1, the filling principle of the P-type polysilicon 006b is the same as that in step S2.

[0029] S5: As Figure 5As shown, wet etching is performed on the P-type polysilicon 006b such that the P-type polysilicon 006b only fills the cavity II 005b, ensuring that the surface of the N-type polysilicon 006a is free of the P-type polysilicon 006b.

[0030] S6: An interlayer dielectric layer 007, a gate metal 009a, and a source metal 009b are sequentially formed on the device surface to obtain a trench-type power metal-oxide-semiconductor field-effect transistor. The specific steps of step S6 are as follows: S6-1: As Figure 6 shown, an interlayer dielectric layer 007 is deposited on the device surface, and a gate metal connection channel 008a and a plurality of source metal connection channels 008b are etched on the device using a photolithography process, as Figure 7 shown. The gate metal connection channel 008a is used for the gate metal 009a to connect to the N-type polysilicon 006a, and the source metal connection channel 008b is used for the source metal 009b to connect to the N-type polysilicon 006a in the terminal region and the P-Body layer 001 in the active region. In this embodiment 1, a plurality of source metal connection channels 008b are distributed in the trench II 003b in the terminal region and the active region, and the minimum width of the gate metal connection channel 008a ≥ 0.1 um; the minimum width of the source metal connection channel 008b ≥ 0.1 um.

[0031] S6-2: A metal layer is deposited on the surface of the interlayer dielectric layer 007, in the gate metal connection channel 008a, and in the source metal connection channel 008b, and the metal layer is separated using a photolithography process to form the gate metal 009a and the source metal 009b, as Figure 8 shown, to form a trench-type power metal-oxide-semiconductor field-effect transistor having a gate-source end clamping structure.

[0032] The trench-type power metal-oxide-semiconductor field-effect transistor having a gate-source end clamping structure can be fabricated using the manufacturing process described in Embodiment 1. The working principle of this trench-type power metal-oxide-semiconductor field-effect transistor is as follows: In the traditional trench-type power MOSFET design, the peripheral terminal region B usually uses a large trench structure as the gate ring, and this structure surrounds and connects to the internal gate from the periphery to improve the gate conduction speed. The present invention utilizes this existing large trench structure (trench II 003b), and by filling polysilicon materials of different polarities and using different etching processes, a current path as Figure 8 shown is successfully constructed - this path extends from the gate end to the source end, thereby forming a gate-source end electrostatic protection device having an NPN structure in the large trench. This design not only significantly enhances the electrostatic protection performance of the device, but also is fully realized based on the existing process without additional photomask steps, effectively reducing the manufacturing cost while improving the device reliability, demonstrating excellent process compatibility and economic benefits.

[0033] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A preparation process of a trench-type power metal-oxide-semiconductor field-effect transistor, characterized in that, It includes the following steps: S1: Complete the second-conductivity-type Body layer in the first-conductivity-type epitaxial layer by implantation, and complete the first-conductivity-type Body layer, several trenches Ⅰ (003a) in the active region, and trench Ⅱ (003b) in the terminal region; S2: Form a gate oxide layer (004) on the device surface at a certain temperature, fill the first-conductivity-type polysilicon on the surface of the gate oxide layer (004), form a cavity Ⅰ (005a) on the surface of the first-conductivity-type polysilicon above the trench Ⅰ (003a), and form a cavity Ⅱ (005b) on the surface of the first-conductivity-type polysilicon in the trench Ⅱ (003b); S3: Dry-etch the first-conductivity-type polysilicon so that the cavity Ⅱ (005b) in the trench Ⅱ (003b) extends to the bottom gate oxide layer (004), and break the first-conductivity-type polysilicon on both sides of it; S4: Fill the second-conductivity-type polysilicon on the surface of the first-conductivity-type polysilicon, and form a cavity Ⅲ (005c) on the surface of the second-conductivity-type polysilicon above the trench Ⅱ (003b); S5: Wet-etch the second-conductivity-type polysilicon so that the second-conductivity-type polysilicon only fills the cavity Ⅱ (005b), ensuring that the second-conductivity-type polysilicon on the surface of the first-conductivity-type polysilicon is removed; S6: Fabricate an interlayer dielectric layer (007), gate metal (009a), and source metal (009b) on the device surface in sequence to obtain a trench-type power metal-oxide-semiconductor field-effect transistor.

2. The manufacturing process of the trench-type power MOSFET according to claim 1, wherein, In the step S1, the specific processing methods in the active region and the terminal region are as follows: S1-1: Complete the first-conductivity-type Body layer in the active region by using the first photolithography process; S1-2: Use the second photolithography process to complete several trenches Ⅰ (003a) in the active region and trench Ⅱ (003b) in the terminal region respectively.

3. The manufacturing process of the trench-type power MOSFET according to claim 1, characterized in that, In the step S2, the specific filling method of the first-conductivity-type polysilicon is as follows: Adopt the low-pressure chemical vapor deposition process to fill from the bottom and side walls of the trench Ⅰ (003a) and the trench Ⅱ (003b) towards the middle direction, and form a cavity Ⅰ (005a) on the surface of the first-conductivity-type polysilicon above the trench Ⅰ (003a), and form a cavity Ⅱ (005b) on the surface of the first-conductivity-type polysilicon in the trench Ⅱ (003b).

4. The manufacturing process of the trench-type power MOSFET according to claim 1, wherein, The specific steps of S6 are as follows: S6-1: Deposit an interlayer dielectric layer (007) on the device surface, and use the photolithography process to etch a gate metal connection channel (008a) and several source metal connection channels (008b) on the device. Among them, the gate metal connection channel (008a) is used for the gate metal (009a) to connect the first-conductivity-type polysilicon, and the source metal connection channel (008b) is used for the source metal (009b) to connect the first-conductivity-type polysilicon in the terminal region and the second-conductivity-type Body layer in the active region; S6-2: Deposit a metal layer on the surface of the interlayer dielectric layer (007), within the gate metal connection channel (008a) and the source metal connection channel (008b), and use photolithography to separate the metal layer to form the gate metal (009a) and the source metal (009b).

5. The manufacturing process of the trench-type power MOSFET according to claim 1, characterized in that, The width of the trench Ⅰ (003a) is 0.18 - 0.2 um, and the depth > 0.8 um.

6. The manufacturing process of the trench-type power MOSFET according to claim 1, characterized in that, The width of the trench Ⅱ (003b) is greater than 2d, and the depth > 0.8 um, where d is the distance from the side wall surface of the cavity Ⅱ (005b) to the side wall surface of the gate oxide layer (004).

7. The manufacturing process of the trench-type power MOSFET according to claim 4, characterized in that, The minimum width of the gate metal connection channel ≥ 0.1 um.

8. The manufacturing process of the trench-type power MOSFET according to claim 4, characterized in that, The minimum width of the source metal connection channel ≥ 0.1 um.

9. A trench-type power metal-oxide-semiconductor field-effect transistor, characterized in that, Prepared by the preparation process described in any one of claims 1 to 8.

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