A trench power metal oxide semiconductor field effect transistor and its preparation process

Abstract

The present invention belongs to the field of semiconductor devices and discloses a trench power metal oxide semiconductor field effect transistor and its preparation process, comprising the following steps: S1: forming a second conductivity type body layer by implantation, and forming a first conductivity type body layer, a plurality of trenches I in the active region, and trenches II in the terminal region; S2: filling the surface of the gate oxide layer with first conductivity type polysilicon; S3: dry etching the first conductivity type polysilicon so that recess II in trench II extends to the bottom of the gate oxide layer; S4: filling the surface of the first conductivity type polysilicon with second conductivity type polysilicon; S5: wet etching the second conductivity type polysilicon so that the second conductivity type polysilicon is only filled in recess II; S6: sequentially forming an interlayer dielectric layer, gate metal, and source metal on the device surface. The present invention can form an NPN gate-source electrostatic protection design without the cost of an additional photomask, thereby achieving ESD protection for the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a trench power metal oxide semiconductor field effect transistor and a preparation process thereof. Background Art

[0002] The metal oxide semiconductor field-effect transistor (MOSFET) is a widely used semiconductor device primarily used for signal amplification and switching control in electronic circuits. The MOSFET operates by controlling the flow of current between the source and drain electrodes by applying a voltage to the gate. The gate is separated from the semiconductor material by an extremely thin oxide insulating layer, which gives the MOSFET high input impedance and low power consumption. Due to its high efficiency, reliability, and ease of integration, the MOSFET plays a vital role in modern electronic devices such as computers, mobile phones, and power management systems.

[0003] Most metal-oxide-semiconductor field-effect transistors (MOSFETs) have a thin oxide layer, serving only as insulation to isolate the gate from the transistor inside the MOSFET. This thin gate oxide layer is highly susceptible to damage from electrostatic discharge (ESD), which can even lead to device destruction in severe cases. To effectively prevent ESD-induced MOSFET failures, ESD protection structures are often integrated into the device.

[0004] However, many ESD protection designs require additional photolithography steps to improve yield, or they can achieve this protection by increasing device area. However, adding photolithography increases process complexity, costs, and production cycle time. Increasing device area also occupies more chip space, increases costs, impacts circuit performance, and complicates thermal management. Summary of the Invention

[0005] To address the deficiencies in the prior art, the present invention provides a trench power MOSFET and its preparation process, which can form an NPN gate-source electrostatic protection design without incurring an additional mask cost, thereby achieving ESD protection of the device.

[0006] The main technical solutions adopted in the present invention are:

[0007] A process for preparing a trench power metal oxide semiconductor field effect transistor comprises the following steps:

[0008] S1: completing the second conductivity type body layer on the first conductivity type epitaxial layer by implantation, and completing the first conductivity type body layer, a plurality of trenches I in the active region, and trenches II in the terminal region;

[0009] S2: forming a gate oxide layer on the surface of the device at a certain temperature, and filling the surface of the gate oxide layer with first conductive type polysilicon, forming a recess I on the surface of the first conductive type polysilicon above trench I, and forming a recess II on the surface of the first conductive type polysilicon in trench II;

[0010] S3: dry-etching the first conductive type polysilicon so that the cavity II in the trench II extends to the gate oxide layer at the bottom, thereby separating the first conductive type polysilicon on both sides thereof;

[0011] S4: filling the surface of the first conductive type polysilicon with the second conductive type polysilicon, and forming a recess III on the surface of the second conductive type polysilicon above the trench II;

[0012] S5: wet-etching the second conductive type polysilicon so that the second conductive type polysilicon is only filled in the recess II, ensuring that the second conductive type polysilicon is removed from the surface of the first conductive type polysilicon;

[0013] S6: An interlayer dielectric layer, a gate metal, and a source metal are sequentially formed on the surface of the device to obtain a trench power metal oxide semiconductor field effect transistor.

[0014] Preferably, in step S1, the specific processing methods in the active area and the terminal area are as follows:

[0015] S1-1: Complete the first conductive type body layer in the active area using the first photolithography process;

[0016] S1-2: A second photolithography process is used to complete a plurality of trenches I in the active region and trenches II in the terminal region.

[0017] Preferably, in step S2, the specific filling method of the first conductive type polysilicon is as follows: using a low-pressure chemical vapor deposition process, filling from the bottom and sidewalls of trench I and trench II toward the middle, and forming a cavity I on the surface of the first conductive type polysilicon above trench I, and forming a cavity II on the surface of the first conductive type polysilicon in trench II.

[0018] Preferably, the specific steps of S6 are as follows:

[0019] S6-1: Depositing an interlayer dielectric layer on the surface of the device, and etching a gate metal connection channel and a plurality of source metal connection channels on the device using a photolithography process, wherein the gate metal connection channel is used for the gate metal to connect to the first conductive type polysilicon, and the source metal connection channel is used for the source metal to connect to the first conductive type polysilicon in the terminal region and the second conductive type body layer in the active region;

[0020] S6-2: depositing a metal layer on the surface of the interlayer dielectric layer, in the gate metal connection channel and the source metal connection channel, and using a photolithography process to separate the metal layer to form a gate metal and a source metal.

[0021] Preferably, the width of the groove I is 0.18-0.2 um, and the depth is greater than 0.8 um.

[0022] Preferably, the width of the trench II is greater than 2d, and the depth is greater than 0.8 um, where d is the distance from the side wall of the cavity II to the side wall of the gate oxide layer.

[0023] Preferably, the minimum width of the gate metal connection channel is ≥0.1 um.

[0024] Preferably, the minimum width of the source metal connection channel is ≥0.1 um.

[0025] A trench power metal oxide semiconductor field effect transistor is prepared by the above preparation process.

[0026] Beneficial effects: The present invention provides a trench power metal oxide semiconductor field effect transistor and a preparation process thereof, which has the following advantages:

[0027] (1) The present invention forms an NPN structure in a large trench and utilizes the synergistic effect of multipolar polysilicon to establish an efficient current path between the gate and the source, significantly improving the electrostatic discharge (ESD) protection capability of the gate and source ends, effectively preventing the device from failing due to electrostatic damage, and ensuring the stability of the device under normal working conditions.

[0028] (2) The present invention makes full use of the large trench structure in the existing process. By filling polysilicon with different polarities and adopting a differentiated etching process, an electrostatic protection structure of the gate and source ends of the NPN structure is constructed in the large trench. This cleverly utilizes the existing process without the need for additional masks, thus achieving the electrostatic protection function and effectively reducing the manufacturing cost and process complexity.

[0029] (3) The present invention directly utilizes the large trench structure in the peripheral terminal area to achieve the electrostatic protection function without occupying additional chip area, thereby improving the chip integration and space utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic structural diagram of step S1 of this embodiment 1;

[0031] Figure 2 This is a schematic structural diagram of step S2 of Example 1;

[0032] Figure 3 This is a schematic diagram of the structure of step S3 of this embodiment 1;

[0033] Figure 4 This is a schematic structural diagram of step S4 of Example 1;

[0034] Figure 5 This is a schematic diagram of the structure of step S5 of this embodiment 1;

[0035] Figure 6 This is a schematic diagram of the structure of step S6-1 of this embodiment 1. Figure I ;

[0036] Figure 7 This is a schematic diagram of the structure of step S6-1 of this embodiment 1. Figure II ;

[0037] Figure 8 Schematic diagram of the final device structure of Example 1;

[0038] In the figure: N-type epitaxial layer 100, P-Body layer 001, N-Body layer 002, trench I 003a, trench II 003b, gate oxide layer 004, recess I 005a, recess II 005b, recess III 005c, N-type polysilicon 006a, P-type polysilicon 006b, interlayer dielectric layer 007, gate metal connection channel 008a, source metal connection channel 008b, gate metal 009a, source metal 009b. DETAILED DESCRIPTION

[0039] In order to help those skilled in the art better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0040] Example 1: The specific implementation of Example 1 is described below by taking the first conductivity type as N type and the second conductivity type as P type as an example.

[0041] A process for preparing a trench power metal oxide semiconductor field effect transistor comprises the following steps:

[0042] S1: If Figure 1 As shown, a P-Body layer 001 is implanted in the N-type epitaxial layer 100, and an N-Body layer 002 and trench I 003a are formed in the active region A, and trench II 003b is formed in the terminal region B. The specific processing methods in the active region A and the terminal region B are as follows:

[0043] S1-1: Use the first photolithography process to complete the N-Body layer 002 in the active area A;

[0044] S1-2: A second photolithography process is used to complete trench I 003a in the active area A and trench II 003b in the terminal area.

[0045] In this embodiment 1, the P-Body layer 001 is formed by implanting boron ions with a doping concentration of 4e12~3e13 cm -2 The N-Body layer 002 can be implanted with phosphorus ions or arsenic ions, with a doping concentration of 5e15~1e16 cm -2 The width of the trench Ⅰ003a is 0.18~0.2um, and the depth is greater than 0.8um; the width of the trench Ⅱ003b is greater than 2d, and the depth is greater than 0.8um, where d is the distance from the side wall of the cavity Ⅱ005b to the side wall of the gate oxide layer 004. Figure 2 The number of trenches I003a is set according to the actual channel design requirements of the active region structure.

[0046] In the present invention, the types of implanted ions used in the P-Body layer and the N-Body layer, the ion doping concentration, and the specific widths and depths of trench I 003a and trench II 003b can all be selectively designed by those skilled in the art according to actual needs.

[0047] S2: If Figure 2 As shown, a gate oxide layer 004 is formed on the surface of the device at a temperature of 900-1100°C, and N-type polysilicon 006a is filled on the surface of the gate oxide layer 004; wherein, the specific filling method of the N-type polysilicon 006a is as follows: a low-pressure chemical vapor deposition process is used to fill from the bottom and sidewall of trench I 003a and trench II 003b toward the middle, and a concave hole I 005a is formed on the surface of the N-type polysilicon 006a above trench I 003a, and a concave hole II 005b is formed on the surface of the N-type polysilicon 006a above trench II 003b.

[0048] In this embodiment 1, based on the above-mentioned preparation process of N-type polysilicon 006a, as shown in FIG. Figure 2 As shown, the distance from the surface of the N-type polysilicon 006a to the top surface of the gate oxide layer 004 is substantially the same as the distance from the side wall of the recess II 005b in the trench II 003b to the side wall of the gate oxide layer 004, which is denoted as d.

[0049] In the first embodiment, since the width of the trench II 003 b is larger, the cavity II 005 b left after filling is larger. However, since the width of the trench I 003 a in the active area A is smaller, the cavity I 005 a left after filling is smaller or nearly horizontal.

[0050] S3: If Figure 3As shown, the N-type polysilicon 006a is dry-etched, extending the cavity II 005b within the trench II 003b to the bottom gate oxide layer 004, thereby separating the N-type polysilicon 006a on both sides. This embodiment 1 employs anisotropic etching, so that the original cavity II 005b remains while the cavity I 005a is almost eliminated.

[0051] S4: As Figure 4 As shown, P-type polysilicon 006b is filled on the surface of N-type polysilicon 006a, and a cavity III 005c is formed on the surface of P-type polysilicon 006b above trench II 003b. In this embodiment 1, the filling principle of P-type polysilicon 006b is the same as step S2.

[0052] S5: If Figure 5 As shown, the P-type polysilicon 006b is wet-etched so that the P-type polysilicon 006b only fills the cavity II 005b, ensuring that the P-type polysilicon 006b is removed from the surface of the N-type polysilicon 006a.

[0053] S6: An interlayer dielectric layer 007, a gate metal 009a, and a source metal 009b are sequentially formed on the device surface to obtain a trench power MOSFET. The specific steps of step S6 are as follows:

[0054] S6-1: If Figure 6 As shown, an interlayer dielectric layer 007 is deposited on the surface of the device, and a gate metal connection channel 008a and a plurality of source metal connection channels 008b are etched on the device using a photolithography process, as shown in FIG. Figure 7 As shown. Gate metal connection channel 008a is used to connect gate metal 009a to N-type polysilicon 006a, and source metal connection channel 008b is used to connect source metal 009b to N-type polysilicon 006a in the terminal region and P-Body layer 001 in the active region. In this embodiment 1, several source metal connection channels 008b are distributed within trench II 003b in the terminal region and in the active region. The minimum width of gate metal connection channel 008a is ≥ 0.1 μm; the minimum width of source metal connection channel 008b is ≥ 0.1 μm.

[0055] S6-2: Deposit a metal layer on the surface of the interlayer dielectric layer 007, in the gate metal connection channel 008a and the source metal connection channel 008b, and separate the metal layer into gate metal 009a and source metal 009b by photolithography process, as shown in FIG. Figure 8 As shown, a trench power MOSFET with a gate-source clamping structure is formed.

[0056] A trench power MOSFET with a gate-source pinch-off structure can be manufactured using the manufacturing process described in Example 1. The operating principle of the trench power MOSFET is as follows:

[0057] In traditional trench power MOSFET designs, the peripheral terminal region B typically uses a large trench structure as a gate ring. This structure surrounds the periphery and connects to the internal gate to increase gate conduction speed. The present invention utilizes this existing large trench structure (trench II003b) and successfully constructs a gate ring by filling it with polysilicon materials of different polarities and using different etching processes. Figure 8 The current path shown here extends from the gate to the source, forming an NPN-structured gate-source ESD protection device within the large trench. This design not only significantly enhances the device's ESD protection performance, but is also implemented entirely within existing processes, eliminating the need for additional photomasking steps. This improves device reliability while effectively reducing manufacturing costs, demonstrating excellent process compatibility and economic benefits.

[0058] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A process for preparing a trench power metal oxide semiconductor field effect transistor, characterized in that: The following steps are involved: S1: completing the second conductive type body layer by implantation on the first conductive type epitaxial layer, and completing the first conductive type body layer, a plurality of trenches I (003a) in the active region, and completing trenches II (003b) in the terminal region; S2: forming a gate oxide layer (004) on the surface of the device at a temperature of 900-1100° C., filling the surface of the gate oxide layer (004) with first conductive type polysilicon, forming a recess I (005a) on the surface of the first conductive type polysilicon above the trench I (003a), and forming a recess II (005b) on the surface of the first conductive type polysilicon in the trench II (003b); S3: dry-etching the first conductive type polysilicon so that the cavity II (005b) in the groove II (003b) extends to the gate oxide layer (004) at the bottom, thereby separating the first conductive type polysilicon on both sides thereof; S4: filling the surface of the first conductive type polysilicon with the second conductive type polysilicon, and forming a recess III (005c) on the surface of the second conductive type polysilicon above the trench II (003b); S5: wet-etching the second conductive type polysilicon so that the second conductive type polysilicon is only filled in the recess II (005b), ensuring that the second conductive type polysilicon is removed from the surface of the first conductive type polysilicon; S6: An interlayer dielectric layer (007), a gate metal (009a) and a source metal (009b) are sequentially fabricated on the surface of the device to obtain a trench power metal oxide semiconductor field effect transistor.

2. The process for preparing a trench power MOSFET according to claim 1, wherein: In step S1, the specific processing methods in the active area and the terminal area are as follows: S1-1: Complete the first conductive type body layer in the active area using the first photolithography process; S1-2: A second photolithography process is used to complete a plurality of trenches I (003a) in the active region and trenches II (003b) in the terminal region.

3. The process for preparing a trench power MOSFET according to claim 1, wherein: In step S2, the specific filling method of the first conductive type polysilicon is as follows: using a low-pressure chemical vapor deposition process, filling from the bottom and sidewall of trench I (003a) and trench II (003b) toward the middle, and forming a cavity I (005a) on the surface of the first conductive type polysilicon above trench I (003a), and forming a cavity II (005b) on the surface of the first conductive type polysilicon in trench II (003b).

4. The process for preparing a trench power MOSFET according to claim 1, wherein: The specific steps of S6 are as follows: S6-1: depositing an interlayer dielectric layer (007) on the surface of the device, and etching a gate metal connection channel (008a) and a plurality of source metal connection channels (008b) on the device using a photolithography process, wherein the gate metal connection channel (008a) is used for the gate metal (009a) to connect the first conductive type polysilicon, and the source metal connection channel (008b) is used for the source metal (009b) to connect the first conductive type polysilicon in the terminal region and the second conductive type body layer in the active region; S6-2: depositing a metal layer on the surface of the interlayer dielectric layer (007), in the gate metal connection channel (008a) and the source metal connection channel (008b), and separating the metal layer by a photolithography process to form a gate metal (009a) and a source metal (009b).

5. The process for preparing a trench power MOSFET according to claim 1, wherein: The width of the groove I (003a) is 0.18~0.2um, and the depth is greater than 0.8um.

6. The process for preparing a trench power MOSFET according to claim 1, wherein: The width of the groove II (003b) is greater than 2d, and the depth is greater than 0.8um, wherein d is the distance from the side wall surface of the cavity II (005b) to the side wall surface of the gate oxide layer (004).

7. The process for preparing a trench power MOSFET according to claim 4, wherein: The minimum width of the gate metal connection channel is ≥0.1 um.

8. The process for preparing a trench power MOSFET according to claim 4, wherein: The minimum width of the source metal connection channel is ≥0.1 um.

9. A trench power metal oxide semiconductor field effect transistor, characterized in that: Prepared by the preparation process according to any one of claims 1 to 8.

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