Preparation method of TOPCon double-sided battery and TOPCon double-sided battery prepared by same

Abstract

The invention provides a preparation method of a TOPCon double-sided cell and the TOPCon double-sided cell prepared by the preparation method, and relates to the technical field of solar cells. The preparation method of the TOPCon double-sided battery comprises the following steps: preparing a back tunneling oxide layer and an intrinsic amorphous silicon layer on the back of a silicon wafer obtained by double-sided polishing; preparing a P-type polycrystalline silicon layer and a BSG layer; first-time polishing and first-time cleaning are carried out; preparing a front tunneling oxide layer; preparing an N-type polycrystalline silicon layer and a PSG layer on the front side; removing the BSG layer in a non-grid line area on the front surface of the silicon wafer; carrying out secondary polishing and secondary cleaning; and preparing an aluminum oxide layer and a silicon nitride layer on the two sides of the obtained silicon wafer, printing electrodes on the two sides, and sintering to obtain the TOPCon double-sided battery. According to the method, P-Poly is deposited on the front surface of double-surface passivation contact, B-Poly is deposited on the back surface of the double-surface passivation contact, and BSG post-texturing is adopted, so that the conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a preparation method of a TOPCon double-sided cell and a TOPCon double-sided cell prepared thereby. Background Art

[0002] The TOPCon cell (Tunnel Oxide Passivated Contact Solar Cell) is one of the highly efficient crystalline silicon solar cell technologies that have received much attention in the photovoltaic field in recent years. Its core advantage lies in significantly reducing the carrier recombination loss through a unique passivated contact structure, thereby improving the conversion efficiency of the cell.

[0003] Existing processes: 1) Conventional TOPCon cells use a back poly technology, which reduces the back surface field recombination rate and back metal contact recombination. The cell achieves back surface passivation and reduces the recombination generated by metal contact, but there is still metal contact recombination on the front surface; 2) The manufacturing process of conventional TOPCon cells gives priority to texturing and forms a BSG layer on the textured surface. The BSG layer is relatively difficult to remove, and the textured surface structure is easily damaged during cleaning, affecting the cell conversion efficiency.

[0004] In view of this, the present invention is specifically proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a preparation method of a TOPCon double-sided cell and a TOPCon double-sided cell prepared thereby.

[0006] In order to achieve the above object of the present invention, the following technical solutions are specifically adopted:

[0007] In the first aspect, the present invention provides a preparation method of a TOPCon double-sided cell, including:

[0008] (1) Performing double-sided polishing treatment on an N-type silicon substrate;

[0009] (2) Sequentially preparing a back tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon wafer obtained in step (1);

[0010] (3) Incorporating boron into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) to prepare a P-type polysilicon layer and a BSG layer;

[0011] (4) Performing first polishing and first cleaning on the silicon wafer obtained in step (3);

[0012] (5) Preparing a front tunneling oxide layer on the front surface of the silicon wafer obtained in step (4);

[0013] (6) Prepare an N-type polycrystalline silicon layer and a PSG layer on the front side of the silicon wafer obtained in step (5);

[0014] (7) Remove the BSG layer in the non-grid line area on the front side of the silicon wafer obtained in step (6);

[0015] (8) Perform a second polishing and a second cleaning on the silicon wafer obtained in step (7);

[0016] (9) Prepare an alumina layer on both sides of the silicon wafer obtained in step (8);

[0017] (10) Prepare a silicon nitride layer on both sides of the silicon wafer obtained in step (9);

[0018] (11) Print a positive electrode on the front side of the silicon wafer obtained in step (10), print a back electrode on the back side, and sinter to obtain the TOPCon double-sided battery.

[0019] Preferably, in step (1), the solution used for the double-sided polishing treatment includes an aqueous solution of potassium hydroxide.

[0020] Preferably, the mass percentage content of the aqueous solution of potassium hydroxide is 3-5 wt%.

[0021] Preferably, the temperature of the polishing treatment is 50-80 °C; the time of the polishing treatment is 300-600 s.

[0022] Preferably, in step (2), the process for preparing the back tunneling oxide layer and the intrinsic amorphous silicon layer includes an LPCVD deposition process.

[0023] Preferably, in step (2), the thickness of the back tunneling oxide layer is 1.2-1.8 nm.

[0024] Preferably, in step (2), the process parameters for preparing the back tunneling oxide layer by the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000-30000 sccm; the deposition time is 300-500 s; the deposition temperature is 500-700 °C.

[0025] Preferably, in step (2), the thickness of the intrinsic amorphous silicon layer is 100-150 nm.

[0026] Preferably, in step (2), the process parameters for preparing the intrinsic amorphous silicon layer by the LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 10000-20000 sccm; the flow rate of the gas N2 introduced is 15000-25000 sccm; the deposition time is 1000-2000 s; the deposition temperature is 500-700 °C.

[0027] Preferably, in step (3), boron is doped into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) by means of a high-temperature boron diffusion process.

[0028] Preferably, in step (3), the thickness of the P-type polysilicon layer is 80 - 100 nm.

[0029] Preferably, in step (3), the thickness of the BSG layer is 90 - 110 nm.

[0030] Preferably, in step (3), the parameters of the high-temperature boron diffusion process include: the flow rate of the introduced gas BCl3 is 200 - 500 sccm; the flow rate of the introduced gas O2 is 20000 - 30000 sccm; the diffusion temperature is 850 - 950 °C; the diffusion time is 100 - 200 min.

[0031] Preferably, in step (4), the silicon wafer obtained in step (3) is polished for the first time and cleaned for the first time successively by means of a chain polishing process and a tank cleaning process.

[0032] Preferably, in step (4), the solution used for the first polishing includes an aqueous hydrofluoric acid solution.

[0033] Preferably, the mass percentage content of the aqueous hydrofluoric acid solution is 4 - 8%.

[0034] Preferably, in step (4), the temperature of the first polishing is 50 - 80 °C; the time of the first polishing is 300 - 600 s.

[0035] Preferably, in step (4), the first cleaning uses an alkaline solution, and the alkaline solution includes, by mass percentage: 3 - 5% potassium hydroxide, 5 - 10% hydrogen peroxide, and 0.5 - 1.5% additive, with the balance being water.

[0036] Preferably, the additive includes any one or a combination of at least two of isopropanol, sodium silicate, ethanol, or ethylenediaminetetraacetic acid.

[0037] Preferably, in step (4), the temperature of the first cleaning is 50 - 80 °C; the time of the first cleaning is 300 - 600 s.

[0038] Preferably, in step (5), the process for preparing the front tunneling oxide layer includes an LPCVD deposition process.

[0039] Preferably, in step (5), the thickness of the front tunneling oxide layer is 1.2 - 1.8 nm.

[0040] Preferably, in step (5), the process parameters for preparing the front tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000 - 30000 sccm; the deposition time is 300 - 500 s; the deposition temperature is 500 - 700 °C.

[0041] Preferably, in step (6), the PECVD deposition process and the annealing process are successively used to prepare the N-type polysilicon layer and the PSG layer.

[0042] Preferably, in step (6), the thickness of the N-type polysilicon layer is 80 - 150 nm.

[0043] Preferably, in step (6), the process parameters for preparing the N-type polysilicon layer by PECVD deposition process include: the gases used are PH3, H2 and SiH4; the gas flow rate ratio of PH3 and SiH4 is 1:(2 - 5); the deposition temperature is 400 - 500 °C; the pressure is 1500 - 1700 mtorr; the H2 flow rate is 4000 - 6000 sccm.

[0044] Preferably, in step (6), the thickness of the PSG layer is 20 - 50 nm.

[0045] Preferably, in step (6), the process parameters for preparing the PSG layer by PECVD deposition process include: the gases used are SiH4 and N2O; the gas flow rate ratio of SiH4 and N2O is 1:(4 - 8); the deposition temperature is 400 - 500 °C; the pressure is 1500 - 1700 mtorr.

[0046] Preferably, in step (7), the laser patterning process is used to remove the BSG layer in the non-gate line area on the front side of the silicon wafer obtained in step (6).

[0047] Preferably, in step (7), the process parameters of the laser patterning process include: the laser power percentage is 30 - 70%; the scanning speed is 20000 - 40000 mm / s.

[0048] Preferably, in step (8), the second polishing and the second cleaning of the silicon wafer obtained in step (7) are successively carried out by the chain polishing process and the tank cleaning process.

[0049] Preferably, in step (8), the solution used for the second polishing includes an aqueous hydrofluoric acid solution.

[0050] Preferably, the mass percentage content of the aqueous hydrofluoric acid solution is 4 - 8%.

[0051] Preferably, in step (8), the temperature of the second polishing is 50 - 80 °C; the time of the second polishing is 300 - 600 s.

[0052] Preferably, in step (8), the second cleaning is performed using an alkaline solution; the alkaline solution comprises, by mass percentage: 3-5% of potassium hydroxide, 5-10% of hydrogen peroxide, and 0.5-1.5% of an additive, with the balance being water.

[0053] Preferably, the additive comprises any one or a combination of at least two of isopropanol, sodium silicate, ethanol, or ethylenediaminetetraacetic acid.

[0054] Preferably, in step (8), the temperature of the second cleaning is 50-80 °C; the time of the second cleaning is 300-600 s.

[0055] Preferably, in step (9), the process for preparing the alumina layer includes an atomic layer deposition process.

[0056] Preferably, in step (9), the thickness of the alumina layer prepared on the front and back surfaces of the silicon wafer is independently 4-6 nm.

[0057] Preferably, in step (9), the process parameters for preparing the alumina layer by atomic layer deposition include: the flow rate ratio of TMA to water vapor is 1:(3-4); the deposition temperature is 200-300 °C; the deposition time is 30-50 min.

[0058] Preferably, in step (10), the process for preparing the silicon nitride layer includes a PECVD deposition process.

[0059] Preferably, in step (10), the thickness of the silicon nitride layer prepared on the front and back surfaces of the silicon wafer is independently 70-120 nm.

[0060] Preferably, in step (10), the process parameters for preparing the silicon nitride layer by PECVD deposition include: the flow rate ratio of gases N3H, SiH4, and N2O is (1-3):(5-15):(3-13); the deposition temperature is 400-500 °C; the deposition time is 40-80 min.

[0061] Preferably, in step (11), the positive electrode and the back electrode are silver electrodes.

[0062] Preferably, in step (11), the sintering temperature is 500-900 °C.

[0063] In a second aspect, the present invention provides a TOPCon double-sided battery, which is prepared by the preparation method as described in the first aspect.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] (1) The double-sided passivated contact adopted by the present invention reduces the recombination of metallized contacts and improves the battery conversion efficiency;

[0066] (2) The present invention adopts the BSG post-texturing process, which reduces the damage to the textured surface during the removal of BSG and improves the battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0068] Figure 1 It is a schematic structural diagram of the TOPCon double-sided battery described in the present invention.

[0069] Among them, 10 is an N-type silicon substrate, 21 is a front tunneling oxide layer, 22 is a back tunneling oxide layer, 31 is an N-type polysilicon layer, 32 is a P-type polysilicon layer, 40 is an alumina layer, 50 is a silicon nitride layer, 61 is a positive electrode, and 62 is a back electrode. SPECIFIC EMBODIMENTS

[0070] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meanings and scopes of the terms should be clear. However, in any case of potential ambiguity, the definitions provided herein shall prevail over any dictionary or extrinsic definition. In this application, unless otherwise specified, the use of "or" means "and / or". In addition, the use of the term "comprising" and other forms is non-restrictive.

[0071] It should be noted that specific details are set forth in the following description to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0072] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0073] In a first aspect, the present invention provides a method for preparing a TOPCon double-sided battery, and the method for preparing the TOPCon double-sided battery includes the following steps:

[0074] (1) Double-side polish the N-type silicon substrate.

[0075] (2) Sequentially prepare a back tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer obtained in step (1).

[0076] (3) Incorporate boron into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) to prepare a P-type polycrystalline silicon layer and a BSG layer.

[0077] (4) Perform the first polishing and the first cleaning on the silicon wafer obtained in step (3).

[0078] (5) Prepare a front tunneling oxide layer on the front side of the silicon wafer obtained in step (4).

[0079] (6) Prepare an N-type polycrystalline silicon layer and a PSG layer on the front side of the silicon wafer obtained in step (5).

[0080] (7) Remove the BSG layer in the non-grid-line area on the front side of the silicon wafer obtained in step (6).

[0081] (8) Perform the second polishing and the second cleaning on the silicon wafer obtained in step (7).

[0082] (9) Prepare an alumina layer on both sides of the silicon wafer obtained in step (8).

[0083] (10) Prepare a silicon nitride layer on both sides of the silicon wafer obtained in step (9).

[0084] (11) Print a positive electrode on the front side of the silicon wafer obtained in step (10), print a back electrode on the back side, and sinter to obtain the TOPCon double-sided battery.

[0085] In the present invention, a front doping structure is prepared by the laser surface scanning method, with double-sided passivated contacts to reduce metallization contacts; P-Poly is deposited on the front side and B-Poly is deposited on the back side for double-sided passivated contacts, reducing metallization contact recombination and improving the battery conversion efficiency; and BSG post-texturing is adopted to simplify the process flow, reduce the damage to the textured surface when removing BSG, and improve the battery conversion efficiency.

[0086] Among them, in step (1), it is necessary to first double-side polish the N-type silicon substrate. Double-side polishing and then depositing the tunneling oxide layer are key process steps, which can eliminate surface defects, improve the interface quality, ensure the uniformity and integrity of the subsequent tunneling oxide layer, be compatible with the subsequent polycrystalline silicon layer deposition process, ensure the process consistency of the expansion of double-sided passivated contacts on the front and back sides, avoid the tunneling path being contaminated and blocked, and at the same time improve the long-term stability of the device.

[0087] Among them, in step (2), a back tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially prepared on the back surface, and a tunneling oxide layer and an intrinsic amorphous silicon layer (i-poly-Si) are sequentially prepared on the front surface. The purpose is to improve the battery efficiency and stability through multi-level passivation and carrier transport optimization.

[0088] Among them, in step (3), by doping boron into the intrinsic amorphous silicon layer of the obtained silicon wafer, a P-type polysilicon layer and a BSG layer (borosilicate glass layer) are prepared. During the diffusion process, the BSG layer provides a boron source and diffuses boron into the polysilicon layer through high temperature, while protecting the substrate and synergistically optimizing the efficiency and reliability of the cell.

[0089] Among them, in step (4), a BSG post-texturing process is adopted to reduce the damage to the textured surface when removing BSG and improve the battery conversion efficiency.

[0090] Among them, in step (5), a tunneling oxide layer is prepared on the front surface of the silicon wafer. Through the synergistic effect of surface passivation and quantum tunneling transport, without increasing the resistance significantly, the dangling bonds are neutralized by chemical passivation, significantly reducing the surface recombination loss and improving the battery efficiency.

[0091] Among them, in step (6), the combination of an N-type polysilicon layer and a PSG layer (phosphosilicate glass layer) can significantly reduce the carrier recombination on the surface, improving the open-circuit voltage and overall efficiency of the device. The polysilicon layer has a high doping characteristic, allowing electrons (majority carriers) to pass through the oxide layer through the tunneling effect while blocking hole recombination, achieving efficient carrier selective transport. As the interface layer between the metal electrode and the silicon substrate, the polysilicon layer can optimize the energy band matching, form a low-resistance ohmic contact, and reduce power loss.

[0092] Among them, in step (7), removing the BSG layer in the non-grid line area on the front surface can accurately realize the selective emitter structure and improve the battery efficiency.

[0093] Among them, in step (8), a BSG post-texturing process is adopted to reduce the damage to the textured surface when removing BSG and improve the battery conversion efficiency.

[0094] As an optional implementation manner, in step (1), the solution used for the double-sided polishing treatment includes an aqueous solution of potassium hydroxide.

[0095] As an optional implementation manner, in step (1), the mass percentage content of the aqueous solution of potassium hydroxide is 3-5 wt%, for example, it can be 3 wt%, 3.2 wt%, 3.4 wt%, 3.6 wt%, 3.8 wt%, 4 wt%, 4.2 wt%, 4.4 wt%, 4.6 wt%, 4.8 wt%, 5 wt%, etc.

[0096] As an alternative embodiment, in step (1), the temperature of the polishing treatment is 50 to 80 °C, for example, it can be 50 °C, 55 °C, 60 °C, 65 °C, 70 °C, 75 °C, 80 °C, etc., and the time of the polishing treatment is 300 to 600 s, for example, it can be 300 s, 320 s, 340 s, 350 s, 360 s, 380 s, 400 s, 420 s, 440 s, 450 s, 460 s, 480 s, 500 s, 520 s, 540 s, 550 s, 560 s, 580 s, 600 s, etc.

[0097] As an alternative embodiment, in step (2), the process for preparing the back tunneling oxide layer and the intrinsic amorphous silicon layer includes the LPCVD deposition process.

[0098] As an alternative embodiment, in step (2), the thickness of the back tunneling oxide layer is 1.2 to 1.8 nm, for example, it can be 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, etc.

[0099] As an alternative embodiment, in step (2), the process parameters for preparing the back tunneling oxide layer by the LPCVD deposition process include: the gas introduced is O2, and the gas flow rate is 20000 to 30000 sccm (for example, it can be 20000 sccm, 22000 sccm, 24000 sccm, 25000 sccm, 26000 sccm, 28000 sccm, 30000 sccm, etc.); the deposition time is 300 to 500 s (for example, it can be 300 s, 320 s, 340 s, 350 s, 360 s, 380 s, 400 s, 420 s, 440 s, 450 s, 460 s, 480 s, 500 s, etc.); the deposition temperature is 500 to 700 °C (for example, it can be 500 °C, 520 °C, 540 °C, 550 °C, 560 °C, 580 °C, 600 °C, 620 °C, 640 °C, 650 °C, 660 °C, 680 °C, 700 °C, etc.).

[0100] As an alternative embodiment, in step (2), the thickness of the intrinsic amorphous silicon layer is 100 to 150 nm, for example, it can be 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, etc.

[0101] As an alternative embodiment, in step (2), the process parameters for preparing the intrinsic amorphous silicon layer by LPCVD deposition process include: the flow rate of the introduced gas SiH4 is 10,000 to 20,000 sccm (for example, it can be 10,000 sccm, 12,000 sccm, 14,000 sccm, 15,000 sccm, 16,000 sccm, 18,000 sccm, 20,000 sccm, etc.); the flow rate of the introduced gas N2 is 15,000 to 25,000 sccm (for example, it can be 15,000 sccm, 16,000 sccm, 18,000 sccm, 20,000 sccm, 22,000 sccm, 24,000 sccm, 25,000 sccm, etc.); the deposition time is 1,000 to 2,000 s (for example, it can be 1,000 s, 1,200 s, 1,400 s, 1,500 s, 1,600 s, 1,800 s, 2,000 s, etc.); the deposition temperature is 500 to 700 °C (for example, it can be 500 °C, 520 °C, 540 °C, 550 °C, 560 °C, 580 °C, 600 °C, 620 °C, 640 °C, 660 °C, 680 °C, 700 °C, etc.).

[0102] As an alternative embodiment, in step (3), boron is doped into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) by a high-temperature boron diffusion process.

[0103] As an alternative embodiment, in step (3), the thickness of the P-type polysilicon layer is 80 to 100 nm, for example, it can be 80 nm, 82 nm, 84 nm, 85 nm, 86 nm, 88 nm, 90 nm, 92 nm, 94 nm, 95 nm, 96 nm, 98 nm, 100 nm, etc.

[0104] As an alternative embodiment, in step (3), the thickness of the BSG layer is 90 to 110 nm, for example, it can be 90 nm, 92 nm, 94 nm, 95 nm, 96 nm, 98 nm, 100 nm, 102 nm, 104 nm, 105 nm, 106 nm, 108 nm, 110 nm, etc.

[0105] As an alternative embodiment, in step (3), the process parameters of the high-temperature boron diffusion include: the flow rate of the introduced gas BCl3 is 200-500 sccm (for example, it can be 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm, 500 sccm, etc.); the flow rate of the introduced gas O2 is 20000-30000 sccm (for example, it can be 20000 sccm, 22000 sccm, 24000 sccm, 25000 sccm, 26000 sccm, 28000 sccm, 30000 sccm, etc.); the diffusion temperature is 850-950 °C (for example, it can be 850 °C, 860 °C, 870 °C, 880 °C, 890 °C, 900 °C, 910 °C, 920 °C, 930 °C, 940 °C, 950 °C, etc.); the diffusion time is 100-200 min (for example, it can be 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, 190 min, 200 min, etc.).

[0106] As an alternative embodiment, the silicon wafer obtained in step (3) is polished for the first time and cleaned for the first time by using a chain polishing process and a tank cleaning process in sequence.

[0107] As an alternative embodiment, in step (4), the solution used for the first polishing includes an aqueous hydrofluoric acid solution.

[0108] As an alternative embodiment, in step (4), the mass percentage content of the aqueous hydrofluoric acid solution is 4-8%, for example, it can be 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, etc.

[0109] As an alternative embodiment, in step (4), the temperature of the first polishing is 50-80 °C, for example, it can be 50 °C, 55 °C, 60 °C, 65 °C, 70 °C, 75 °C, 80 °C, etc.; the time of the first polishing is 300-600 s, for example, it can be 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, etc.

[0110] As an alternative embodiment, in step (4), the first cleaning uses an alkaline solution, and the alkaline solution includes, by mass percentage: 3-5% of potassium hydroxide, 5-10% of hydrogen peroxide, and 0.5-1.5% of an additive, and the balance is water.

[0111] As an alternative embodiment, in step (4), the additive includes any one or a combination of at least two of isopropanol, sodium silicate, ethanol, or ethylenediaminetetraacetic acid.

[0112] As an alternative embodiment, in step (4), the temperature of the first cleaning is 50 - 80°C, for example, it can be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, etc.; the time of the first cleaning is 300 - 600 s, for example, it can be 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, etc.

[0113] As an alternative embodiment, in step (5), the process for preparing the front tunneling oxide layer includes the LPCVD deposition process.

[0114] As an alternative embodiment, in step (5), the thickness of the front tunneling oxide layer is 1.2 - 1.8 nm, for example, it can be 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, etc.

[0115] As an alternative embodiment, in step (5), the process parameters for preparing the front tunneling oxide layer by the LPCVD deposition process include: the gas introduced is O2, and the gas flow rate is 20000 - 30000 sccm (for example, it can be 20000 sccm, 22000 sccm, 24000 sccm, 25000 sccm, 26000 sccm, 28000 sccm, 30000 sccm, etc.); the deposition time is 300 - 500 s (for example, it can be 300 s, 320 s, 340 s, 350 s, 360 s, 380 s, 400 s, 420 s, 440 s, 450 s, 460 s, 480 s, 500 s, etc.); the deposition temperature is 500 - 700°C (for example, it can be 500°C, 520°C, 540°C, 550°C, 560°C, 580°C, 600°C, 620°C, 640°C, 650°C, 660°C, 680°C, 700°C, etc.).

[0116] As an alternative embodiment, in step (6), the PECVD deposition process and the annealing process are successively used to prepare the N - type polysilicon layer and the PSG layer.

[0117] As an alternative embodiment, in step (6), the thickness of the N - type polysilicon layer is 80 - 150 nm, for example, it can be 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, etc.

[0118] As an alternative embodiment, in step (6), the process parameters for preparing the N-type polysilicon layer by PECVD deposition process include: the gases used are PH3, H2 and SiH4, and the gas flow ratio of PH3 and SiH4 is 1:(2 - 5), for example, it can be 1:2, 1:3, 1:4, 1:5, etc.; the deposition temperature is 400 - 500 °C, for example, it can be 400 °C, 420 °C, 440 °C, 450 °C, 460 °C, 480 °C, 500 °C, etc.; the pressure is 1500 - 1700 mtorr, for example, it can be 1500 mtorr, 1550 mtorr, 1600 mtorr, 1650 mtorr, 1700 mtorr, etc.; the H2 flow rate is 4000 - 6000 sccm, for example, it can be 4000 sccm, 4500 sccm, 5000 sccm, 5500 sccm, 6000 sccm, etc.

[0119] As an alternative embodiment, in step (6), the thickness of the PSG layer is 20 - 50 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0120] As an alternative embodiment, in step (6), the process parameters for preparing the PSG layer by PECVD deposition process include: the gases used are SiH4 and N2O; the gas flow ratio of SiH4 and N2O is 1:(4 - 8), for example, it can be 1:4, 1:5, 1:6, 1:7, 1:8, etc.; the deposition temperature is 400 - 500 °C, for example, it can be 400 °C, 420 °C, 440 °C, 450 °C, 460 °C, 480 °C, 500 °C, etc.; the pressure is 1500 - 1700 mtorr, for example, it can be 1500 mtorr, 1550 mtorr, 1600 mtorr, 1650 mtorr, 1700 mtorr, etc.

[0121] As an alternative embodiment, in step (7), the BSG layer in the non-gate line area on the front side of the silicon wafer obtained in step (6) is processed by a laser patterning process.

[0122] As an alternative embodiment, in step (7), the process parameters of the laser patterning process include: the laser power percentage is 30 to 70%, for example, it can be 30%, 32%, 34%, 36%, 38%, 40%, 42%, 44%, 46%, 48%, 50%, 52%, 54%, 56%, 58%, 60%, 62%, 64%, 66%, 68%, 70%, etc.; the scanning speed is 20,000 to 40,000 mm / s, for example, it can be 20,000 mm / s, 22,000 mm / s, 24,000 mm / s, 25,000 mm / s, 26,000 mm / s, 28,000 mm / s, 30,000 mm / s, 32,000 mm / s, 34,000 mm / s, 35,000 mm / s, 36,000 mm / s, 38,000 mm / s, 40,000 mm / s, etc.

[0123] As an alternative embodiment, in step (8), the silicon wafer obtained in step (7) is subjected to a second polishing and a second cleaning by a chain polishing process and a tank cleaning process in sequence;

[0124] As an alternative embodiment, in step (8), the solution used for the second polishing includes an aqueous hydrofluoric acid solution.

[0125] As an alternative embodiment, in step (8), the mass percentage content of the aqueous hydrofluoric acid solution is 4 to 8%, for example, it can be 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, etc.

[0126] As an alternative embodiment, in step (8), the temperature of the second polishing is 50 to 80 °C, for example, it can be 50 °C, 55 °C, 60 °C, 65 °C, 70 °C, 75 °C, 80 °C, etc., and the time of the second polishing is 300 to 600 s, for example, it can be 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, etc.

[0127] As an alternative embodiment, in step (8), the second cleaning uses an alkaline solution, and the alkaline solution by mass percentage includes: 3 to 5% of potassium hydroxide, 5 to 10% of hydrogen peroxide, and 0.5 to 1.5% of an additive, and the balance is water.

[0128] As an alternative embodiment, in step (8), the additive includes any one or a combination of at least two of isopropyl alcohol, sodium silicate, ethanol, or ethylenediaminetetraacetic acid.

[0129] As an alternative embodiment, in step (8), the temperature of the second cleaning is 50 to 80 °C, for example, it can be 50 °C, 55 °C, 60 °C, 65 °C, 70 °C, 75 °C, 80 °C, etc., and the time of the second cleaning is 300 to 600 s, for example, it can be 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, etc.

[0130] As an alternative embodiment, in step (9), the process for preparing the alumina layer includes an atomic layer deposition process.

[0131] As an alternative embodiment, in step (9), the thickness of the alumina layer prepared on the front and back of the silicon wafer is independently 4 to 6 nm, for example, it can be 4 nm, 4.2 nm, 4.4 nm, 4.5 nm, 4.6 nm, 4.8 nm, 5 nm, 5.2 nm, 5.4 nm, 5.5 nm, 5.6 nm, 5.8 nm, 6 nm, etc.

[0132] As an alternative embodiment, in step (9), the process parameters for preparing the alumina layer by atomic layer deposition process include: the flow rate ratio of TMA to water vapor is 1:(3 to 4), for example, it can be 1:3, 1:3.2, 1:3.4, 1:3.5, 1:3.6, 1:3.8, 1:4, etc.; the deposition temperature is 200 to 300 °C, for example, it can be 200 °C, 220 °C, 240 °C, 250 °C, 260 °C, 280 °C, 300 °C, etc.; the deposition time is 30 to 50 min, for example, it can be 30 min, 35 min, 40 min, 45 min, 50 min, etc.

[0133] As an alternative embodiment, in step (10), the process for preparing the silicon nitride layer includes a PECVD deposition process.

[0134] As an alternative embodiment, in step (10), the thickness of the silicon nitride layer prepared on the front and back of the silicon wafer is independently 70 to 120 nm, for example, it can be 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, etc.

[0135] As an optional implementation manner, in step (10), the process parameters for preparing the silicon nitride layer by PECVD deposition process include: the flow rate ratio of gases N3H, SiH4 and N2O is (1-3):(5-15):(3-13); where, "1-3" can be, for example, 1, 1.2, 1.4, 1.6, 1.8, 2, 2.2, 2.4, 2.6, 2.8, 3, etc., "5-15" can be, for example, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, etc., "3-13" can be, for example, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, etc.; the deposition temperature is 400-500 °C, for example, it can be 400 °C, 420 °C, 440 °C, 450 °C, 460 °C, 480 °C, 500 °C, etc.; the deposition time is 40-80 min, for example, it can be 40 min, 45 min, 50 min, 55 min, 60 min, 65 min, 70 min, 75 min, 80 min, etc.

[0136] As an optional implementation manner, in step (11), the positive electrode and the back electrode are silver electrodes.

[0137] As an optional implementation manner, in step (11), the sintering temperature is 500-900 °C, for example, it can be 500 °C, 550 °C, 600 °C, 650 °C, 700 °C, 750 °C, 800 °C, 850 °C, 900 °C, etc.

[0138] In a second aspect, the present invention provides a TOPCon double-sided battery (as Figure 1 shown), and the TOPCon double-sided battery is prepared by the preparation method of the TOPCon double-sided battery as described in the first aspect.

[0139] The present invention will be further described below through examples. Unless otherwise specified, the materials in the examples are prepared according to existing methods or directly purchased from the market.

[0140] Example 1

[0141] This example provides a preparation method of a TOPCon double-sided battery, and the preparation method of the TOPCon double-sided battery includes the following steps:

[0142] (1) Perform double-sided polishing treatment on the N-type silicon substrate; where, the double-sided polishing treatment uses an aqueous solution of potassium hydroxide, the mass percentage content of the aqueous solution of potassium hydroxide is 4 wt%, the temperature of the polishing treatment is 55 °C, and the time of the polishing treatment is 350 s.

[0143] (2) The back tunneling oxide layer and the intrinsic amorphous silicon layer are sequentially prepared on the back side of the silicon wafer obtained in step (1) by using the LPCVD deposition process; wherein the thickness of the back tunneling oxide layer is 1.5 nm, and the process parameters for preparing the back tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 25000 sccm, the deposition time is 400 s, and the deposition temperature is 600 °C; the thickness of the intrinsic amorphous silicon layer is 125 nm, and the process parameters for preparing the intrinsic amorphous silicon layer by using the LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 15000 sccm, the flow rate of the gas N2 introduced is 20000 sccm, the deposition time is 1500 s, and the deposition temperature is 600 °C.

[0144] (3) Boron is doped into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) by using the high-temperature boron diffusion process to prepare a P-type polysilicon layer and a BSG layer; wherein, the thickness of the P-type polysilicon layer is 90 nm, the thickness of the BSG layer is 100 nm, and the process parameters of the high-temperature boron diffusion process include: the flow rate of the gas BCl3 introduced is 350 sccm, the flow rate of the gas O2 introduced is 25000 sccm, the diffusion temperature is 900 °C, and the diffusion time is 150 min.

[0145] (4) The silicon wafer obtained in step (3) is subjected to the first polishing and the first cleaning by using the chain polishing process and the tank cleaning process in sequence; wherein, the first polishing uses an aqueous hydrofluoric acid solution, the mass percentage content of the aqueous hydrofluoric acid solution is 6%, the temperature of the first polishing is 55 °C, and the time of the first polishing is 350 s; the first cleaning uses an alkali solution, and the alkali solution includes, by mass percentage: potassium hydroxide 4%, hydrogen peroxide 7.5%, and an additive 1%, and the balance is water; the 1% additive includes 0.3% isopropyl alcohol, 0.3% sodium silicate, 0.2% ethanol, and 0.2% ethylenediaminetetraacetic acid; the temperature of the first cleaning is 55 °C, and the time of the first cleaning is 350 s.

[0146] (5) The front tunneling oxide layer is prepared on the front side of the silicon wafer obtained in step (4) by using the LPCVD deposition process; wherein, the thickness of the front tunneling oxide layer is 1.5 nm, and the process parameters for preparing the front tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 25000 sccm, the deposition time is 400 s, and the deposition temperature is 600 °C.

[0147] (6) The N-type polysilicon layer and the PSG layer are prepared on the front side of the silicon wafer obtained in step (5) by using the PECVD deposition process and the annealing process; wherein, the thickness of the N-type polysilicon layer is 115 nm, and the process parameters for preparing the N-type polysilicon layer by using the PECVD deposition process include: the gases used are PH3, H2 and SiH4, the gas flow ratio of PH3 and SiH4 is 1:3.5, the deposition temperature is 450 °C, the pressure is 1600 mtorr, and the H2 flow rate is 5000 sccm; the thickness of the PSG layer is 35 nm, and the process parameters for preparing the PSG layer by using the PECVD deposition process include: the gases used are SiH4 and N2O, the gas flow ratio of SiH4 and N2O is 1:6, the deposition temperature is 450 °C, and the pressure is 1600 mtorr.

[0148] (7) The BSG layer in the non-gate line area on the front side of the silicon wafer obtained in step (6) is removed by using the laser patterning process; the process parameters of the laser patterning process include: the laser power percentage is 50%, and the scanning speed is 30000 mm / s.

[0149] (8) The silicon wafer obtained in step (7) is subjected to the second polishing and the second cleaning by using the chain polishing process and the tank cleaning process in sequence; wherein, the second polishing uses an aqueous hydrofluoric acid solution, the mass percentage content of the aqueous hydrofluoric acid solution is 6%, the temperature of the second polishing is 55 °C, and the time of the second polishing is 350 s; the second cleaning uses an alkaline solution, and the alkaline solution includes by mass percentage: potassium hydroxide 4%, hydrogen peroxide 7.5% and additive 1%, and the balance is water; the 1% additive includes 0.3% isopropyl alcohol, 0.3% sodium silicate, 0.2% ethanol and 0.2% ethylenediaminetetraacetic acid; the temperature of the second cleaning is 55 °C, and the time of the second cleaning is 350 s.

[0150] (9) The alumina layer is prepared on both sides of the silicon wafer obtained in step (8) by using the atomic layer deposition process; the thickness of the alumina layer prepared on the front side and the back side of the silicon wafer is 5 nm, and the process parameters for preparing the alumina layer by using the atomic layer deposition process include: the flow ratio of TMA and water vapor is 1:3.5, the deposition temperature is 250 °C, and the deposition time is 40 min.

[0151] (10) The silicon nitride layer is prepared on both sides of the silicon wafer obtained in step (9) by using the PECVD deposition process; wherein, the thickness of the silicon nitride layer prepared on the front side and the back side of the silicon wafer is 95 nm, and the process parameters for preparing the silicon nitride layer by using the PECVD deposition process include: the flow ratio of the gases N3H, SiH4 and N2O is 2:10:5, the deposition temperature is 450 °C, and the deposition time is 60 min.

[0152] (11) Print a front electrode (silver electrode) on the front side of the silicon wafer obtained in step (10), print a back electrode (silver electrode) on the back side, and sinter at 700 °C to obtain the TOPCon bifacial cell.

[0153] Example 2

[0154] This example provides a method for preparing a TOPCon bifacial cell. The method for preparing the TOPCon bifacial cell includes the following steps:

[0155] (1) Perform double-sided polishing on the N-type silicon substrate; wherein, the double-sided polishing is performed using an aqueous solution of potassium hydroxide, the mass percentage content of the aqueous solution of potassium hydroxide is 3 wt%, the temperature of the polishing treatment is 50 °C, and the time of the polishing treatment is 400 s.

[0156] (2) Use the LPCVD deposition process to sequentially prepare a back tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer obtained in step (1); wherein the thickness of the back tunneling oxide layer is 1.4 nm, and the process parameters for preparing the back tunneling oxide layer using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 24000 sccm, the deposition time is 380 s, and the deposition temperature is 580 °C; the thickness of the intrinsic amorphous silicon layer is 120 nm, and the process parameters for preparing the intrinsic amorphous silicon layer using the LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 14000 sccm, the flow rate of the gas N2 introduced is 18000 sccm, the deposition time is 1400 s, and the deposition temperature is 580 °C.

[0157] (3) Use the high-temperature boron diffusion process to dope boron into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) to prepare a P-type polycrystalline silicon layer and a BSG layer; wherein, the thickness of the P-type polycrystalline silicon layer is 85 nm, the thickness of the BSG layer is 95 nm, and the process parameters of the high-temperature boron diffusion process include: the flow rate of the gas BCl3 introduced is 320 sccm, the flow rate of the gas O2 introduced is 24000 sccm, the diffusion temperature is 870 °C, and the diffusion time is 120 min.

[0158] (4) The silicon wafer obtained in step (3) is polished for the first time and cleaned for the first time by using a chain polishing process and a tank cleaning process in sequence; wherein, hydrofluoric acid aqueous solution is used for the first polishing, the mass percentage content of the hydrofluoric acid aqueous solution is 5%, the temperature of the first polishing is 50 °C, and the time of the first polishing is 400 s; an alkali solution is used for the first cleaning, and the alkali solution includes, by mass percentage: 3% of potassium hydroxide, 10% of hydrogen peroxide, and 1.2% of an additive, and the balance is water; the 1.2% additive includes 0.5% of isopropyl alcohol, 0.5% of sodium silicate, 0.1% of ethanol, and 0.1% of ethylenediaminetetraacetic acid, the temperature of the first cleaning is 50 °C, and the time of the first cleaning is 400 s.

[0159] (5) A front tunneling oxide layer is prepared on the front of the silicon wafer obtained in step (4) by using an LPCVD deposition process; wherein, the thickness of the front tunneling oxide layer is 1.4 nm, and the process parameters for preparing the front tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 24000 sccm, the deposition time is 380 s, and the deposition temperature is 580 °C.

[0160] (6) An N-type polysilicon layer and a PSG layer are prepared on the front of the silicon wafer obtained in step (5) by using a PECVD deposition process and an annealing process; wherein, the thickness of the N-type polysilicon layer is 110 nm, and the process parameters for preparing the N-type polysilicon layer by using the PECVD deposition process include: the gases used are PH3, H2, and SiH4, the gas flow rate ratio of PH3 and SiH4 is 1:3, the deposition temperature is 420 °C, the pressure is 1500 mtorr, and the H2 flow rate is 4500 sccm; the thickness of the PSG layer is 30 nm, and the process parameters for preparing the PSG layer by using the PECVD deposition process include: the gases used are SiH4 and N2O, the gas flow rate ratio of SiH4 and N2O is 1:5, the deposition temperature is 420 °C, and the pressure is 1500 mtorr.

[0161] (7) The BSG layer in the non-gate line area on the front of the silicon wafer obtained in step (6) is removed by using a laser patterning process; the process parameters of the laser patterning process include: the laser power percentage is 45%, and the scanning speed is 32000 mm / s.

[0162] (8) The silicon wafers obtained in step (7) are subjected to a second polishing and a second cleaning using a chain polishing process and a tank cleaning process in sequence; wherein, for the second polishing, an aqueous hydrofluoric acid solution is used, the mass percentage content of the aqueous hydrofluoric acid solution is 5%, the temperature of the second polishing is 50 °C, and the time of the second polishing is 400 s; for the second cleaning, an alkaline solution is used, and the alkaline solution by mass percentage includes: 3% potassium hydroxide, 10% hydrogen peroxide, and 1.2% additives, with the balance being water; the 1.2% additives include 0.5% isopropyl alcohol, 0.5% sodium silicate, 0.1% ethanol, and 0.1% ethylenediaminetetraacetic acid, the temperature of the second cleaning is 50 °C, and the time of the second cleaning is 400 s.

[0163] (9) An alumina layer is prepared on both sides of the silicon wafers obtained in step (8) by atomic layer deposition; the thickness of the prepared alumina layer on the front and back of the silicon wafers is 4.5 nm, and the process parameters for preparing the alumina layer by atomic layer deposition include: the flow ratio of TMA to water vapor is 1:3.2, the deposition temperature is 280 °C, and the deposition time is 45 min.

[0164] (10) A silicon nitride layer is prepared on both sides of the silicon wafers obtained in step (9) by PECVD deposition; wherein, the thickness of the prepared silicon nitride layer on the front and back of the silicon wafers is 90 nm, and the process parameters for preparing the silicon nitride layer by PECVD deposition include: the flow ratio of gases N3H, SiH4, and N2O is 2:10:5, the deposition temperature is 420 °C, and the deposition time is 65 min.

[0165] (11) A positive electrode (silver electrode) is printed on the front of the silicon wafers obtained in step (10), a back electrode (silver electrode) is printed on the back, and sintering is carried out at 680 °C to obtain the TOPCon bifacial cell.

[0166] Example 3

[0167] This example provides a method for preparing a TOPCon bifacial cell, and the method for preparing the TOPCon bifacial cell includes the following steps:

[0168] (1) The N-type silicon substrate is subjected to double-sided polishing; wherein, for the double-sided polishing, an aqueous potassium hydroxide solution is used, the mass percentage content of the aqueous potassium hydroxide solution is 5 wt%, the temperature of the polishing is 60 °C, and the time of the polishing is 300 s.

[0169] (2) The back tunneling oxide layer and the intrinsic amorphous silicon layer are successively prepared on the back surface of the silicon wafer obtained in step (1) by using the LPCVD deposition process; wherein the thickness of the back tunneling oxide layer is 1.6 nm, and the process parameters for preparing the back tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 26000 sccm, the deposition time is 420 s, and the deposition temperature is 620 °C; the thickness of the intrinsic amorphous silicon layer is 130 nm, and the process parameters for preparing the intrinsic amorphous silicon layer by using the LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 16000 sccm, the flow rate of the gas N2 introduced is 24000 sccm, the deposition time is 1600 s, and the deposition temperature is 620 °C.

[0170] (3) Boron is doped into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) by using the high-temperature boron diffusion process to prepare a P-type polysilicon layer and a BSG layer; wherein, the thickness of the P-type polysilicon layer is 95 nm, the thickness of the BSG layer is 105 nm, and the process parameters of the high-temperature boron diffusion process include: the flow rate of the gas BCl3 introduced is 360 sccm, the flow rate of the gas O2 introduced is 26000 sccm, the diffusion temperature is 920 °C, and the diffusion time is 180 min.

[0171] (4) The silicon wafer obtained in step (3) is subjected to the first polishing and the first cleaning by using the chain polishing process and the tank cleaning process in sequence; wherein, the first polishing uses an aqueous hydrofluoric acid solution, the mass percentage content of the aqueous hydrofluoric acid solution is 7%, the temperature of the first polishing is 60 °C, and the time of the first polishing is 300 s; the first cleaning uses an alkaline solution, and the alkaline solution includes by mass percentage: potassium hydroxide 5%, hydrogen peroxide 5%, and additive 1.5%, and the balance is water; the 1.5% additive includes 0.6% isopropyl alcohol, 0.5% sodium silicate, 0.2% ethanol, and 0.2% ethylenediaminetetraacetic acid; the temperature of the first cleaning is 60 °C, and the time of the first cleaning is 300 s.

[0172] (5) The front tunneling oxide layer is prepared on the front surface of the silicon wafer obtained in step (4) by using the LPCVD deposition process; wherein, the thickness of the front tunneling oxide layer is 1.6 nm, and the process parameters for preparing the front tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 26000 sccm, the deposition time is 420 s, and the deposition temperature is 620 °C.

[0173] (6) The N-type polysilicon layer and the PSG layer are prepared on the front side of the silicon wafer obtained in step (5) by using the PECVD deposition process and the annealing process; wherein, the thickness of the N-type polysilicon layer is 120 nm, and the process parameters for preparing the N-type polysilicon layer by using the PECVD deposition process include: the gases used are PH3, H2 and SiH4, the gas flow ratio of PH3 and SiH4 is 1:4, the deposition temperature is 460 °C, the pressure is 1700 mtorr, and the H2 flow rate is 6000 sccm; the thickness of the PSG layer is 40 nm, and the process parameters for preparing the PSG layer by using the PECVD deposition process include: the gases used are SiH4 and N2O, the gas flow ratio of SiH4 and N2O is 1:7, the deposition temperature is 460 °C, and the pressure is 1700 mtorr.

[0174] (7) The BSG layer in the non-gate line area on the front side of the silicon wafer obtained in step (6) is removed by using the laser patterning process; the process parameters of the laser patterning process include: the laser power percentage is 55%, and the scanning speed is 28000 mm / s.

[0175] (8) The silicon wafer obtained in step (7) is subjected to secondary polishing and secondary cleaning by using the chain polishing process and the tank cleaning process in sequence; wherein, the secondary polishing uses an aqueous hydrofluoric acid solution, the mass percentage content of the aqueous hydrofluoric acid solution is 7%, the temperature of the secondary polishing is 60 °C, and the time of the secondary polishing is 300 s; the secondary cleaning uses an alkaline solution, and the alkaline solution includes by mass percentage: potassium hydroxide 5%, hydrogen peroxide 5% and additive 1.5%, and the balance is water; the 1.5% additive includes 0.6% isopropyl alcohol, 0.5% sodium silicate, 0.2% ethanol and 0.2% ethylenediaminetetraacetic acid; the temperature of the secondary cleaning is 60 °C, and the time of the secondary cleaning is 300 s.

[0176] (9) An alumina layer is prepared on both sides of the silicon wafer obtained in step (8) by using the atomic layer deposition process; the thickness of the alumina layer prepared on the front side and the back side of the silicon wafer is 5.5 nm, and the process parameters for preparing the alumina layer by using the atomic layer deposition process include: the flow ratio of TMA and water vapor is 1:3, the deposition temperature is 240 °C, and the deposition time is 50 min.

[0177] (10) A silicon nitride layer is prepared on both sides of the silicon wafer obtained in step (9) by using the PECVD deposition process; wherein, the thickness of the silicon nitride layer prepared on the front side and the back side of the silicon wafer is 90 nm, and the process parameters for preparing the silicon nitride layer by using the PECVD deposition process include: the flow ratio of the gases N3H, SiH4 and N2O is 2:10:5, the deposition temperature is 420 °C, and the deposition time is 65 min.

[0178] (11) Print the front electrode (silver electrode) on the front side of the silicon wafer obtained in step (10), print the back electrode (silver electrode) on the back side, and sinter at 750 °C to obtain the TOPCon bifacial cell.

[0179] Example 4

[0180] This example provides a method for preparing a TOPCon bifacial cell, which is different from Example 1 in that in step (1), the mass percentage content of the aqueous potassium hydroxide solution is 2 wt%; the temperature of the polishing treatment is 80 °C, and the time of the polishing treatment is 600 s; other steps are the same as those in Example 1.

[0181] Example 5

[0182] This example provides a method for preparing a TOPCon bifacial cell, which is different from Example 1 in that in step (1), the mass percentage content of the aqueous potassium hydroxide solution is 6 wt%; the temperature of the polishing treatment is 40 °C, and the time of the polishing treatment is 300 s; other steps are the same as those in Example 1.

[0183] Example 6

[0184] This example provides a method for preparing a TOPCon bifacial cell, which is different from Example 1 in that in step (2), the process parameters for preparing the back tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000 sccm, the deposition time is 300 s, and the deposition temperature is 700 °C; other steps are the same as those in Example 1.

[0185] Example 7

[0186] This example provides a method for preparing a TOPCon bifacial cell, which is different from Example 1 in that in step (2), the process parameters for preparing the back tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 30000 sccm, the deposition time is 500 s, and the deposition temperature is 500 °C; other steps are the same as those in Example 1.

[0187] Example 8

[0188] This example provides a method for preparing a TOPCon bifacial cell, which is different from Example 1 in that in step (2), the process parameters for preparing the intrinsic amorphous silicon layer by LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 10000 sccm, the flow rate of the gas N2 introduced is 25000 sccm, the deposition time is 2000 s, and the deposition temperature is 500 °C; other steps are the same as those in Example 1.

[0189] Example 9

[0190] This embodiment provides a method for preparing a TOPCon bifacial cell. The difference from Embodiment 1 is that in step (2), the process parameters for preparing the intrinsic amorphous silicon layer by LPCVD deposition process include: the flow rate of the gas SiH4 is 20000 sccm, the flow rate of the gas N2 is 15000 sccm, the deposition time is 1000 s, and the deposition temperature is 700 °C; other steps are the same as those in Embodiment 1.

[0191] Embodiment 10

[0192] This embodiment provides a method for preparing a TOPCon bifacial cell. The difference from Embodiment 1 is that in step (3), the process parameters of the high-temperature boron diffusion include: the flow rate of the gas BCl3 is 200 sccm, the flow rate of the gas O2 is 30000 sccm, the diffusion temperature is 820 °C, and the diffusion time is 90 min; other steps are the same as those in Embodiment 1.

[0193] Embodiment 11

[0194] This embodiment provides a method for preparing a TOPCon bifacial cell. The difference from Embodiment 1 is that in step (3), the process parameters of the high-temperature boron diffusion include: the flow rate of the gas BCl3 is 500 sccm, the flow rate of the gas O2 is 20000 sccm, the diffusion temperature is 980 °C, and the diffusion time is 220 min; other steps are the same as those in Embodiment 1.

[0195] Embodiment 12

[0196] This embodiment provides a method for preparing a TOPCon bifacial cell. The difference from Embodiment 1 is that in step (4), the mass percentage content of the hydrofluoric acid aqueous solution is 3%; the temperature of the first polishing is 80 °C, and the time of the first polishing is 300 s; other steps are the same as those in Embodiment 1.

[0197] Embodiment 13

[0198] This embodiment provides a method for preparing a TOPCon bifacial cell. The difference from Embodiment 1 is that in step (4), the mass percentage content of the hydrofluoric acid aqueous solution is 10%; the temperature of the first polishing is 50 °C, and the time of the first polishing is 600 s; other steps are the same as those in Embodiment 1.

[0199] Embodiment 14

[0200] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1. In step (4), the first cleaning uses an alkaline solution, which by mass percentage includes: 2% potassium hydroxide, 12% hydrogen peroxide, and 2% additive, with the balance being water; the temperature of the first cleaning is 80°C, and the time of the first cleaning is 300 s; other steps are the same as those in Embodiment 1.

[0201] Embodiment 15

[0202] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1. In step (4), the first cleaning uses an alkaline solution, which by mass percentage includes: 6% potassium hydroxide, 4% hydrogen peroxide, and 0.4% additive, with the balance being water; the temperature of the first cleaning is 50°C, and the time of the first cleaning is 600 s; other steps are the same as those in Embodiment 1.

[0203] Embodiment 16

[0204] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1. In step (5), the process parameters for preparing the front tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000 sccm, the deposition time is 500 s, and the deposition temperature is 500°C; other steps are the same as those in Embodiment 1.

[0205] Embodiment 17

[0206] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1. In step (5), the process parameters for preparing the front tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 30000 sccm, the deposition time is 300 s, and the deposition temperature is 700°C; other steps are the same as those in Embodiment 1.

[0207] Embodiment 18

[0208] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1. In step (6), the process parameters for preparing the N-type polysilicon layer by PECVD deposition process include: the gases used are PH3, H2, and SiH4, the gas flow rate ratio of PH3 to SiH4 is 1:1, the deposition temperature is 500°C, the pressure is 1700 mtorr, and the H2 flow rate is 6000 sccm; other steps are the same as those in Embodiment 1.

[0209] Embodiment 19

[0210] This embodiment provides a method for fabricating a TOPCon bifacial solar cell. The difference from Embodiment 1 lies in that in step (6), the process parameters for depositing the N-type polysilicon layer using the PECVD deposition process include: the gases used are PH3, H2, and SiH4, the gas flow ratio of PH3 to SiH4 is 1:6, the deposition temperature is 400 °C, the pressure is 1500 mtorr, and the H2 flow rate is 4000 sccm; other steps are the same as those in Embodiment 1.

[0211] Embodiment 20

[0212] This embodiment provides a method for fabricating a TOPCon bifacial solar cell. The difference from Embodiment 1 lies in that in step (6), the process parameters for depositing the PSG layer using the PECVD deposition process include: the gases used are SiH4 and N2O, the gas flow ratio of SiH4 to N2O is 1:3, the deposition temperature is 400 °C, and the pressure is 1700 mtorr; other steps are the same as those in Embodiment 1.

[0213] Embodiment 21

[0214] This embodiment provides a method for fabricating a TOPCon bifacial solar cell. The difference from Embodiment 1 lies in that in step (6), the process parameters for depositing the PSG layer using the PECVD deposition process include: the gases used are SiH4 and N2O, the gas flow ratio of SiH4 to N2O is 1:9, the deposition temperature is 500 °C, and the pressure is 1500 mtorr; other steps are the same as those in Embodiment 1.

[0215] Embodiment 22

[0216] This embodiment provides a method for fabricating a TOPCon bifacial solar cell. The difference from Embodiment 1 lies in that in step (7), the process parameters of the laser patterning process include: the laser power percentage is 30%, and the scanning speed is 40000 mm / s; other steps are the same as those in Embodiment 1.

[0217] Embodiment 23

[0218] This embodiment provides a method for fabricating a TOPCon bifacial solar cell. The difference from Embodiment 1 lies in that in step (7), the process parameters of the laser patterning process include: the laser power percentage is 70%, and the scanning speed is 20000 mm / s; other steps are the same as those in Embodiment 1.

[0219] Embodiment 24

[0220] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (8), the mass percentage content of the hydrofluoric acid aqueous solution is 3%; the temperature of the second polishing is 80 °C, and the time of the second polishing is 300 s; other steps are the same as those in Embodiment 1.

[0221] Embodiment 25

[0222] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (8), the mass percentage content of the hydrofluoric acid aqueous solution is 10%; the temperature of the second polishing is 50 °C, and the time of the second polishing is 600 s; other steps are the same as those in Embodiment 1.

[0223] Embodiment 26

[0224] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (8), the second cleaning is carried out using an alkaline solution, and the alkaline solution includes, by mass percentage: 2% potassium hydroxide, 12% hydrogen peroxide, and 2% additive, with the balance being water; the temperature of the second cleaning is 80 °C, and the time of the second cleaning is 300 s; other steps are the same as those in Embodiment 1.

[0225] Embodiment 27

[0226] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (8), the second cleaning is carried out using an alkaline solution, and the alkaline solution includes, by mass percentage: 6% potassium hydroxide, 4% hydrogen peroxide, and 0.4% additive, with the balance being water; the temperature of the second cleaning is 50 °C, and the time of the second cleaning is 600 s; other steps are the same as those in Embodiment 1.

[0227] Embodiment 28

[0228] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (9), the process parameters for preparing the alumina layer by atomic layer deposition process include: the flow rate ratio of TMA to water vapor is 1:2, the deposition temperature is 300 °C, and the deposition time is 30 min; other steps are the same as those in Embodiment 1.

[0229] Embodiment 29

[0230] This embodiment provides a method for preparing a TOPCon bifacial cell, which is different from Embodiment 1 in that in step (9), the process parameters for preparing the alumina layer by atomic layer deposition process include: the flow rate ratio of TMA to water vapor is 1:5, the deposition temperature is 200 °C, and the deposition time is 50 min; other steps are the same as those in Embodiment 1.

[0231] Example 30

[0232] This example provides a method for preparing a TOPCon bifacial cell. The difference from Example 1 is that in step (10), the process parameters for preparing the silicon nitride layer by PECVD deposition process include: the flow ratio of gases N3H, SiH4, and N2O is 1:5:13, the deposition temperature is 400 °C, and the deposition time is 80 min; other steps are the same as those in Example 1.

[0233] Example 31

[0234] This example provides a method for preparing a TOPCon bifacial cell. The difference from Example 1 is that in step (10), the process parameters for preparing the silicon nitride layer by PECVD deposition process include: the flow ratio of gases N3H, SiH4, and N2O is 1:15:3, the deposition temperature is 500 °C, and the deposition time is 40 min; other steps are the same as those in Example 1.

[0235] Comparative Example 1

[0236] This comparative example provides a method for preparing a TOPCon bifacial cell. The preparation method includes the following steps:

[0237] (1) Texturize the silicon wafer using a trough cleaning process; the texturization uses an alkaline solution, and the alkaline solution includes, by mass percentage: 4% potassium hydroxide, 7.5% hydrogen peroxide, and 1% additive, with the balance being water; the 1% additive includes 0.3% isopropyl alcohol, 0.3% sodium silicate, 0.2% ethanol, and 0.2% ethylenediaminetetraacetic acid. The cleaning temperature for texturization is 55 °C, and the cleaning time for texturization is 350 s.

[0238] (2) Sequentially deposit a back surface tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon wafer obtained in step (1) using an LPCVD deposition process; wherein the thickness of the back surface tunneling oxide layer is 1.5 nm, and the process parameters for preparing the back surface tunneling oxide layer by LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 25000 sccm, the deposition time is 400 s, and the deposition temperature is 600 °C; the thickness of the intrinsic amorphous silicon layer is 125 nm, and the process parameters for preparing the intrinsic amorphous silicon layer by LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 15000 sccm, the flow rate of the gas N2 introduced is 20000 sccm, the deposition time is 1500 s, and the deposition temperature is 600 °C.

[0239] (3) The boron is doped into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) by using a high-temperature boron diffusion process to prepare a P-type polysilicon layer and a BSG layer; wherein, the thickness of the P-type polysilicon layer is 90 nm, the thickness of the BSG layer is 100 nm, and the process parameters of the high-temperature boron diffusion process include: the flow rate of the introduced gas BCl3 is 350 sccm, the flow rate of the introduced gas O2 is 25000 sccm, the diffusion temperature is 900 °C, and the diffusion time is 150 min.

[0240] (4) The BSG layer in the back gate line region of the silicon wafer obtained in step (3) is removed by using a laser patterning process; the process parameters of the laser patterning process include: the laser power percentage is 50%, and the scanning speed is 30000 mm / s.

[0241] (5) The silicon wafer obtained in step (4) is subjected to the first polishing and the first cleaning by using a chain polishing process and a tank cleaning process in sequence; wherein, the first polishing uses an aqueous hydrofluoric acid solution, the mass percentage content of the aqueous hydrofluoric acid solution is 7%, the temperature of the first polishing is 60 °C, and the time of the first polishing is 300 s; the first cleaning uses an alkali solution, and the alkali solution includes, by mass percentage: 5% potassium hydroxide, 5% hydrogen peroxide, and 1.5% additive, and the balance is water; the 1.5% additive includes 0.6% isopropyl alcohol, 0.5% sodium silicate, 0.2% ethanol, and 0.2% ethylenediaminetetraacetic acid, the temperature of the first cleaning is 60 °C, and the time of the first cleaning is 300 s.

[0242] (6) An N-type polysilicon layer and a PSG layer are prepared on the front side of the silicon wafer obtained in step (5) by using a PECVD deposition process and an annealing process; wherein, the thickness of the N-type polysilicon layer is 115 nm, and the process parameters of preparing the N-type polysilicon layer by using the PECVD deposition process include: the used gases are PH3, H2, and SiH4, the gas flow ratio of PH3 and SiH4 is 1:3.5, the deposition temperature is 450 °C, the pressure is 1600 mtorr, and the H2 flow rate is 5000 sccm; the thickness of the PSG layer is 35 nm, and the process parameters of preparing the PSG layer by using the PECVD deposition process include: the used gases are SiH4 and N2O, the gas flow ratio of SiH4 and N2O is 1:6, the deposition temperature is 450 °C, and the pressure is 1600 mtorr.

[0243] (7) The silicon wafers obtained in step (6) are polished for the second time and cleaned for the second time by using a chain polishing process and a tank cleaning process in sequence; wherein, hydrofluoric acid aqueous solution is used for the second polishing, the mass percentage content of the hydrofluoric acid aqueous solution is 6%, the temperature of the second polishing is 55 °C, and the time of the second polishing is 350 s; an alkali solution is used for the second cleaning, and the alkali solution includes, by mass percentage: 4% of potassium hydroxide, 7.5% of hydrogen peroxide, and 1% of an additive, with the balance being water; the 1% additive includes 0.3% of isopropyl alcohol, 0.3% of sodium silicate, 0.2% of ethanol, and 0.2% of ethylenediaminetetraacetic acid, the temperature of the second cleaning is 55 °C, and the time of the second cleaning is 350 s.

[0244] (8) An alumina layer is prepared on both sides of the silicon wafers obtained in step (8) by using an atomic layer deposition process; the thickness of the prepared alumina layer on the front and back sides of the silicon wafers is 5 nm, and the process parameters for preparing the alumina layer by using the atomic layer deposition process include: the flow rate ratio of TMA and water vapor is 1:3.5, the deposition temperature is 250 °C, and the deposition time is 40 min.

[0245] (9) A silicon nitride layer is prepared on both sides of the silicon wafers obtained in step (8) by using a PECVD deposition process; wherein, the thickness of the prepared silicon nitride layer on the front and back sides of the silicon wafers is 95 nm, and the process parameters for preparing the silicon nitride layer by using the PECVD deposition process include: the flow rate ratio of gases N3H, SiH4, and N2O is 2:10:5, the deposition temperature is 450 °C, and the deposition time is 60 min.

[0246] (10) A positive electrode (silver electrode) is printed on the front side of the silicon wafers obtained in step (9), a back electrode (silver electrode) is printed on the back side, and sintering is performed at 700 °C to obtain the TOPCon double-sided battery.

[0247] Test Example 1

[0248] Test samples: The TOPCon double-sided batteries provided in Examples 1 to 31, and the TOPCon double-sided battery provided in Comparative Example 1.

[0249] Test method: An IV tester is used for efficiency testing, and the characterization contents include open-circuit voltage (Uoc), short-circuit current (Isc), fill factor (FF), and photoelectric conversion efficiency (Eta).

[0250] The test results are shown in Table 1 below:

[0251] Table 1

[0252]

[0253]

[0254] As shown in Table 1, the present invention adopts double-sided passivated contacts to reduce metallization contact recombination and improve the battery conversion efficiency; and adopts the BSG post-texturing process to reduce the damage to the textured surface when removing BSG, thereby improving the battery conversion efficiency.

[0255] It can be seen from the comparison between Example 1 and Examples 4-5 that the parameters of the double-sided polishing process are not in the preferred range, and the quality of the silicon wafer interface is not conducive to the subsequent deposition of the tunneling oxide layer and the Poly-Si layer. Therefore, the efficiency of the prepared battery is relatively low.

[0256] It can be seen from the comparison between Example 1 and Examples 6-7 that the parameters of the process for preparing the back tunneling oxide layer are not in the preferred range, and the quality of the back tunneling oxide layer is poor, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0257] It can be seen from the comparison between Example 1 and Examples 8-9 that the parameters of the process for preparing the intrinsic amorphous silicon layer are not in the preferred range, and the quality of the intrinsic amorphous silicon layer is poor, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0258] It can be seen from the comparison between Example 1 and Examples 10-11 that the parameters of the high-temperature boron diffusion process are not in the preferred range. During the diffusion process, it affects the boron diffusion from the BSG layer to the polycrystalline silicon layer, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0259] It can be seen from the comparison between Example 1 and Examples 12-13 that the parameters of the first polishing process are not in the preferred range, which affects the polishing effect. Therefore, the efficiency of the battery cells is relatively low.

[0260] It can be seen from the comparison between Example 1 and Examples 14-15 that the parameters of the first cleaning process are not in the preferred range, which affects the cleaning effect. Therefore, the efficiency of the battery cells is relatively low.

[0261] It can be seen from the comparison between Example 1 and Examples 16-17 that the parameters of the process for preparing the front tunneling oxide layer are not in the preferred range, and the quality of the front tunneling oxide layer is poor, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0262] It can be seen from the comparison between Example 1 and Examples 18-19 that the process for preparing the N-type polycrystalline silicon layer is not in the preferred range, and the quality of the N-type polycrystalline silicon layer is poor, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0263] It can be seen from the comparison between Example 1 and Examples 20-21 that the process for preparing the PSG layer is not in the preferred range, and the quality of the PSG layer is poor, which in turn leads to relatively low efficiency and reliability of the battery cells.

[0264] It can be seen from the comparison between Example 1 and Examples 22 to 23 that the laser patterning process is not in the preferred range, or it may cause certain thermal damage, and the effect of removing the BSG layer is poor, which consequently leads to lower efficiency and reliability of the solar cell.

[0265] It can be seen from the comparison between Example 1 and Examples 24 to 25 that the second polishing process is not in the preferred range, which affects the polishing effect, so the efficiency of the solar cell is low.

[0266] It can be seen from the comparison between Example 1 and Examples 26 to 27 that the second cleaning process is not in the preferred range, which affects the texturing effect, so the efficiency of the solar cell is low.

[0267] It can be seen from the comparison between Example 1 and Examples 28 to 29 that the process for preparing the alumina layer is not in the preferred range, and the passivation effect is poor, so the efficiency of the solar cell is low.

[0268] It can be seen from the comparison between Example 1 and Examples 30 to 31 that the process for preparing the silicon nitride is not in the preferred range, and the passivation effect is poor, so the efficiency of the solar cell is low.

[0269] It can be seen from the comparison between Example 1 and the comparative example that the method of the present invention has double-sided passivated contacts with P-Poly deposited on the front side and B-Poly deposited on the back side, and post-texturing after BSG is adopted, which improves the conversion efficiency of the solar cell.

[0270] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preparation method of a TOPCon bifacial battery, characterized in that, Including: (1) Perform double-sided polishing on the N-type silicon substrate; (2) Sequentially prepare a back tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon wafer obtained in step (1); (3) Incorporate boron into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2) to prepare a P-type polysilicon layer and a BSG layer; (4) Perform the first polishing and the first cleaning on the silicon wafer obtained in step (3); (5) Prepare a front tunneling oxide layer on the front surface of the silicon wafer obtained in step (4); (6) Prepare an N-type polysilicon layer and a PSG layer on the front surface of the silicon wafer obtained in step (5); (7) Remove the BSG layer in the non-grid line area on the front surface of the silicon wafer obtained in step (6); (8) Perform the second polishing and the second cleaning on the silicon wafer obtained in step (7); (9) Prepare an alumina layer on both sides of the silicon wafer obtained in step (8); (10) Prepare a silicon nitride layer on both sides of the silicon wafer obtained in step (9); (11) Print a positive electrode on the front surface of the silicon wafer obtained in step (10), print a back electrode on the back surface, and sinter to obtain the TOPCon double-sided battery.

2. The preparation method according to claim 1, characterized in that, In step (1), the solution used for the double-sided polishing treatment includes an aqueous solution of potassium hydroxide; Preferably, the mass percentage content of the aqueous solution of potassium hydroxide is 3-5 wt%; Preferably, the temperature of the polishing treatment is 50-80 °C; the time of the polishing treatment is 300-600 s.

3. The preparation method according to claim 1, wherein In step (2), the process for preparing the back tunneling oxide layer and the intrinsic amorphous silicon layer includes the LPCVD deposition process; Preferably, in step (2), the thickness of the back tunneling oxide layer is 1.2-1.8 nm; Preferably, in step (2), the process parameters for preparing the back tunneling oxide layer by the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000-30000 sccm; the deposition time is 300-500 s; the deposition temperature is 500-700 °C; Preferably, in step (2), the thickness of the intrinsic amorphous silicon layer is 100-150 nm; Preferably, in step (2), the process parameters for preparing the intrinsic amorphous silicon layer by the LPCVD deposition process include: the flow rate of the gas SiH4 introduced is 10000-20000 sccm; the flow rate of the gas N2 introduced is 15000-25000 sccm; the deposition time is 1000-2000 s; the deposition temperature is 500-700 °C; Preferably, in step (3), high-temperature boron diffusion process is used to incorporate boron into the intrinsic amorphous silicon layer of the silicon wafer obtained in step (2); Preferably, in step (3), the thickness of the P-type polysilicon layer is 80-100 nm; Preferably, in step (3), the thickness of the BSG layer is 90-110 nm; Preferably, in step (3), the process parameters of the high-temperature boron diffusion process include: the flow rate of the gas BCl3 introduced is 200-500 sccm; the flow rate of the gas O2 introduced is 20000-30000 sccm; the diffusion temperature is 850-950 °C; the diffusion time is 100-200 min.

4. The preparation method according to claim 1, characterized in that, In step (4), the silicon wafer obtained in step (3) is polished for the first time and cleaned for the first time by using a chain polishing process and a tank cleaning process in sequence; Preferably, in step (4), the solution used for the first polishing includes an aqueous hydrofluoric acid solution; Preferably, the mass percentage content of the aqueous hydrofluoric acid solution is 4-8%; Preferably, in step (4), the temperature of the first polishing is 50-80 °C; the time of the first polishing is 300-600 s; Preferably, in step (4), the first cleaning uses an alkaline solution, and the alkaline solution includes, by mass percentage: 3-5% of potassium hydroxide, 5-10% of hydrogen peroxide, and 0.5-1.5% of an additive, with the balance being water; Preferably, the additive includes any one or a combination of at least two of isopropyl alcohol, sodium silicate, ethanol, or ethylenediaminetetraacetic acid; Preferably, in step (4), the temperature of the first cleaning is 50-80 °C; the time of the first cleaning is 300-600 s.

5. The preparation method according to claim 1, wherein In step (5), the process for preparing the front tunneling oxide layer includes an LPCVD deposition process; Preferably, in step (5), the thickness of the front tunneling oxide layer is 1.2-1.8 nm; Preferably, in step (5), the process parameters for preparing the front tunneling oxide layer by using the LPCVD deposition process include: the gas introduced is O2, the gas flow rate is 20000-30000 sccm; the deposition time is 300-500 s; the deposition temperature is 500-700 °C; Preferably, in step (6), the PECVD deposition process and the annealing process are used in sequence to prepare the N-type polysilicon layer and the PSG layer; Preferably, in step (6), the thickness of the N-type polysilicon layer is 80-150 nm; Preferably, in step (6), the process parameters for preparing the N-type polysilicon layer by using the PECVD deposition process include: the gases used are PH3, H2, and SiH4; the gas flow rate ratio of PH3 to SiH4 is 1:(2-5); the deposition temperature is 400-500 °C; the pressure is 1500-1700 mtorr; the H2 flow rate is 4000-6000 sccm; Preferably, in step (6), the thickness of the PSG layer is 20-50 nm; Preferably, in step (6), the process parameters for preparing the PSG layer by using the PECVD deposition process include: the gases used are SiH4 and N2O; the gas flow rate ratio of SiH4 to N2O is 1:(4-8); the deposition temperature is 400-500 °C; the pressure is 1500-1700 mtorr.

6. The preparation method according to claim 1, characterized in that, In step (7), the BSG layer in the non-gate line area on the front of the silicon wafer obtained in step (6) is removed by using a laser patterning process; Preferably, in step (7), the process parameters of the laser patterning process include: the laser power percentage is 30-70%; the scanning speed is 20000-40000 mm / s.

7. The preparation method according to claim 1, characterized in that, In step (8), the silicon wafer obtained in step (7) is polished for the second time and cleaned for the second time by using a chain polishing process and a tank cleaning process in sequence; Preferably, in step (8), the solution used for the second polishing comprises an aqueous hydrofluoric acid solution; Preferably, the mass percentage content of the aqueous hydrofluoric acid solution is 4-8%; Preferably, in step (8), the temperature of the second polishing is 50-80 °C; the time of the second polishing is 300-600 s; Preferably, in step (8), the second cleaning is carried out using an alkaline solution; the alkaline solution comprises, by mass percentage: 3-5% of potassium hydroxide, 5-10% of hydrogen peroxide and 0.5-1.5% of an additive, with the balance being water; Preferably, the additive comprises any one or a combination of at least two of isopropanol, sodium silicate, ethanol or ethylenediaminetetraacetic acid; Preferably, in step (8), the temperature of the second cleaning is 50-80 °C; the time of the second cleaning is 300-600 s.

8. The preparation method according to claim 1, characterized in that, In step (9), the process for preparing the alumina layer comprises an atomic layer deposition process; Preferably, in step (9), the thickness of the alumina layer prepared on the front and back sides of the silicon wafer is independently 4-6 nm; Preferably, in step (9), the process parameters for preparing the alumina layer by atomic layer deposition include: the flow rate ratio of TMA to water vapor is 1:(3-4); the deposition temperature is 200-300 °C; the deposition time is 30-50 min.

9. The preparation method according to claim 1, characterized in that, In step (10), the process for preparing the silicon nitride layer comprises a PECVD deposition process; Preferably, in step (10), the thickness of the silicon nitride layer prepared on the front and back sides of the silicon wafer is independently 70-120 nm; Preferably, in step (10), the process parameters for preparing the silicon nitride layer by PECVD deposition include: the flow rate ratio of gases N3H, SiH4 and N2O is (1-3):(5-15):(3-13); the deposition temperature is 400-500 °C; the deposition time is 40-80 min; Preferably, in step (11), the positive electrode and the back electrode are silver electrodes; Preferably, in step (11), the sintering temperature is 500-900 °C.

10. A TOPCon bifacial cell, characterized in that, The TOPCon double-sided battery is prepared by the preparation method according to any one of claims 1-9.

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