Solar cell, preparation method thereof and photovoltaic module
By introducing a multi-layer diffusion adjustment layer structure into the solar cell, the problem of uneven distribution of doped atoms is solved, the uniformity of the PN junction and battery efficiency are improved, and the photoelectric conversion efficiency is achieved.
Patent Information
- Application Number
- CN202510550659.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-07-08
AI Technical Summary
In solar cells, during the formation of PN junctions, doped atoms are unevenly distributed on the surface of the silicon wafer, affecting the battery efficiency.
Before preparing the solar cell, a multi-layer diffusion adjustment layer is introduced, and the diffusion adjustment layer structure is reduced in sequence. By controlling the oxidation temperature, a silicon oxide layer with different density is formed, so that the doped atoms are evenly distributed on the surface of the silicon substrate, and the uniformity of the PN junction is optimized.
It improves the uniformity of the PN junction and the photoelectric conversion efficiency of the battery, reduces the surface recombination rate, and increases the short-circuit current and open-circuit voltage.
Smart Images
Figure CN120282580A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solar cells, and particularly relates to a solar cell, a preparation method thereof, and a photovoltaic module. Background Art
[0002] In a solar cell, the formation of a PN junction is achieved by doping doping atoms on one side of a silicon wafer. Taking the doping of phosphorus atoms on the surface of a P-type silicon wafer as an example, POCl3 is usually used as the source of phosphorus diffusion. Under high-temperature conditions, POCl3 decomposes to generate phosphorus pentachloride (PCl5) and diphosphorus pentoxide (P2O5). P2O5 reacts with silicon to generate SiO2 and phosphorus atoms, forming an N-type doping layer. However, the phosphorus atoms doped in the P-type silicon wafer are unevenly distributed on the surface of the silicon wafer, affecting the uniformity of the PN junction and thus the cell efficiency. Similarly, this problem also exists when boron atoms are doped in an N-type silicon wafer. Summary of the Invention
[0003] The present invention aims to at least partly solve one of the technical problems in the related art. To this end, an object of the present invention is to provide a solar cell in which doping atoms are uniformly doped on the surface of a silicon substrate, making the PN junction more uniform and thus improving the photoelectric conversion efficiency of the cell.
[0004] Specifically, a first aspect of the present invention provides a solar cell, including a silicon substrate, a doping layer, and a diffusion adjustment layer stacked in sequence. The diffusion adjustment layer includes a first diffusion adjustment layer, a second diffusion adjustment layer, and so on up to an nth diffusion adjustment layer with gradually decreasing density; the first diffusion adjustment layer is close to the silicon substrate, and the nth diffusion adjustment layer is far from the silicon substrate; n is an integer greater than or equal to 2.
[0005] In the process of manufacturing a solar cell, a diffusion adjustment layer is introduced in advance before doping treatment. It includes a multi-layer diffusion adjustment layer structure with gradually decreasing density. The nth diffusion adjustment layer (i.e., the outermost diffusion adjustment layer) has the loosest structure, making it easier for doping atoms to enter, with a higher solid solubility. When doping atoms, the nth diffusion adjustment layer can act as a solid doping source. During the high-temperature pushing and junction formation process, using the solid solubility difference between layers (the density of the layer closer to the silicon substrate is getting larger and the solid solubility is getting smaller), the doping atoms gradually enter the inner diffusion adjustment layers. These inner diffusion adjustment layers play a role in buffering diffusion, enabling the doping atoms to enter the silicon substrate more uniformly during the diffusion process, avoiding excessive local concentration, and overcoming the problem of chaotic diffusion of doping atoms after entering the silicon substrate when only using a single-layer dense silicon oxide layer as the diffusion adjustment layer, resulting in a large difference in diffusion within the substrate. The combination of diffusion adjustment layers with different densities can optimize the uniformity of doping atom diffusion, improve the quality of the PN junction, and thus enhance the photoelectric conversion efficiency of the cell. In addition, the multi-layer diffusion adjustment layer structure also has a passivation and blocking effect, which can significantly reduce surface recombination and improve the short-circuit current (Isc) and photoelectric conversion efficiency of the cell.
[0006] According to some embodiments of the present invention, the contact angle of each layer of the diffusion adjustment layer is within the range of 5° - 20°; and from the first diffusion adjustment layer to the nth diffusion adjustment layer, the contact angle shows a decreasing trend.
[0007] Diffusion adjustment layers with different densities exhibit different hydrophobicities. The layer with a greater density has better hydrophobicity, so the contact angle is larger; the layer with a smaller density has poorer hydrophobicity, so the contact angle is smaller. Controlling the density of the diffusion adjustment layer (equivalent to controlling the contact angle) is beneficial to improving the distribution uniformity of doping atoms on the surface of the silicon substrate, thereby enhancing the uniformity of the PN junction.
[0008] According to some embodiments of the present invention, n is 2, the contact angle of the first diffusion adjustment layer is 10° - 20°; the contact angle of the second diffusion adjustment layer is 5° - 10°.
[0009] According to some embodiments of the present invention, the thickness of each layer of the diffusion adjustment layer is 3nm - 10nm.
[0010] According to some embodiments of the present invention, n is 2, the thickness of the first diffusion adjustment layer is 5nm - 10nm, the thickness of the second diffusion adjustment layer is 3nm - 5nm; the thickness ratio of the first diffusion adjustment layer to the second diffusion adjustment layer is (1.5 - 2):1.
[0011] Optimizing the thicknesses of the first diffusion adjustment layer and the second diffusion adjustment layer is beneficial to improving the uniformity of the distribution of doped atoms on the surface of the silicon substrate, thereby improving the uniformity of the PN junction and further enhancing the cell efficiency. If the thicknesses of the first diffusion adjustment layer and the second diffusion adjustment layer are too small, they cannot achieve the effect of improving the uniform distribution of doped atoms. If the thicknesses of the first diffusion adjustment layer and the second diffusion adjustment layer are too large, it will result in an excessive blocking effect during the diffusion process, hindering atomic diffusion and being unfavorable for the formation of the PN junction. Optimizing the thickness ratio of the first diffusion adjustment layer and the second diffusion adjustment layer is beneficial to further improving the uniformity of the distribution of doped atoms on the surface of the silicon substrate, thereby improving the uniformity of the PN junction.
[0012] According to some embodiments of the present invention, n is an integer from 2 to 5; the material of the diffusion adjustment layer includes silicon oxide; the silicon substrate includes a P-type silicon substrate or an N-type silicon substrate.
[0013] The second aspect of the present invention provides a method for manufacturing the solar cell of the first aspect of the present invention, including the following steps:
[0014] Performing a first oxidation on the silicon substrate to form an n-th diffusion adjustment layer on the surface of the silicon substrate; performing a second oxidation on the silicon substrate to form an (n - 1)-th diffusion adjustment layer on the surface of the silicon substrate, and the (n - 1)-th diffusion adjustment layer is located between the silicon substrate and the n-th diffusion adjustment layer; and so on, until the n-th oxidation is performed on the silicon substrate to form a first diffusion adjustment layer on the surface of the silicon substrate, and the first diffusion adjustment layer is located between the silicon substrate and the second diffusion adjustment layer; from the first oxidation to the n-th oxidation, the oxidation temperature shows an increasing trend;
[0015] Doping atoms onto the surface of the silicon substrate to form a PN junction.
[0016] Before performing the diffusion treatment in the present invention, by performing n oxidations, diffusion adjustment layers with different degrees of densification are formed on the surface of the silicon substrate. The layer with a higher degree of densification is closer to the silicon substrate, and the layer with a lower degree of densification is farther from the silicon substrate. Such a multi-layer diffusion adjustment layer structure can enable the doped atoms to be uniformly distributed on the surface of the silicon substrate, improve the uniformity of the PN junction, and further enhance the cell efficiency.
[0017] According to some embodiments of the present invention, the oxidation temperature for each oxidation is within the range of 400°C - 800°C.
[0018] According to some embodiments of the present invention, n is 2, the oxidation temperature of the first oxidation is 400°C - 600°C; the oxidation temperature of the second oxidation is 750°C - 800°C. Oxidizing at a low temperature is beneficial to obtaining a porous silicon oxide layer; oxidizing at a high temperature is beneficial to obtaining a dense silicon oxide layer.
[0019] The third aspect of the present invention provides a photovoltaic module, comprising the solar cell of the first aspect of the present invention or the solar cell obtained by the method of the second aspect of the present invention. Since the solar cell of the present invention is adopted, the photovoltaic module of the present invention has all the advantages of the above-mentioned solar cell, which will not be elaborated herein.
[0020] The additional aspects and advantages of the present invention will be partly given in the following description, partly become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and / or additional aspects and advantages of the present invention will become obvious and be easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0022] Figure 1 is a schematic partial structure diagram of a conventional solar cell.
[0023] Figure 2 is a schematic partial structure diagram of an exemplary solar cell of the present invention.
[0024] Figure 3 is a schematic partial structure diagram of another exemplary solar cell of the present invention.
[0025] REFERENCE SIGNS:
[0026] 1000, solar cell; 100, silicon substrate; 200, doped layer; 300, dense silicon oxide layer; 400, diffusion adjustment layer; 1, first diffusion adjustment layer; 2, second diffusion adjustment layer; n, nth diffusion adjustment layer. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present invention, and should not be construed as a limitation to the present invention.
[0028] In the description of the present invention, unless otherwise specified, "a plurality of" means two or more. "A variety of" means two or more. In this article, the term "comprising" or "including" is an open expression, that is, it includes the content specified by the present invention, but does not exclude other aspects of the content.
[0029] The endpoints and any values in the ranges disclosed herein are not limited to the exact ranges or values. These ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the values between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed herein.
[0030] In a solar cell, the formation of a PN junction is achieved by doping doping atoms on one side of a silicon wafer. Taking the doping of phosphorus atoms on the surface of a P-type silicon wafer as an example, POCl3 is usually used as the source of phosphorus diffusion. Under high-temperature conditions, POCl3 decomposes to generate phosphorus pentachloride (PCl5) and diphosphorus pentoxide (P2O5). P2O5 reacts with silicon to generate SiO2 and phosphorus atoms, forming an N-type doped layer. However, the distribution of phosphorus atoms doped in the P-type silicon wafer on the surface of the silicon wafer is uneven, which affects the uniformity of the PN junction and thus the cell efficiency. Similarly, this problem also exists when doping boron atoms in an N-type silicon wafer.
[0031] In the manufacturing process of related solar cells, adding a layer of silicon oxide layer before the diffusion treatment is a common process step. This layer of silicon oxide layer is usually used to passivate the surface of the silicon wafer, reduce the recombination of surface carriers, and thus improve the efficiency of the cell. This silicon oxide layer is generally grown through a thermal oxidation step in the diffusion process (oxidation temperature is about 780 °C). The introduction of this silicon oxide layer can improve the surface quality of the silicon wafer, reduce surface defects, and thus improve the effect of the subsequent diffusion process. This pre-passivation treatment helps to reduce the reaction between the surface of the silicon wafer and the diffusion source, and thus is conducive to controlling the formation and distribution of the PN junction. Figure 1 A partial structural diagram of a related cell is shown, including a silicon substrate 100, a doped layer 200, and a dense silicon oxide layer 300. However, there is still a problem of uneven distribution of the PN junction in the cell with this structure, resulting in a low cell efficiency.
[0032] To solve the above problems, the present invention proposes a solar cell structure, which includes multiple diffusion adjustment layers with different degrees of density. The layer with a higher degree of density is closer to the silicon substrate, and the layer with a lower degree of density is farther from the silicon substrate. During the preparation of the solar cell, when doping doping atoms, this structure of multiple diffusion adjustment layers can make the doping atoms evenly distributed on the surface of the silicon substrate, improve the uniformity of the PN junction, and thus improve the cell efficiency.
[0033] Specifically, referring to Figure 2, in the first aspect of the present invention, a solar cell 1000 is provided, which includes a silicon substrate 100, a doping layer 200, and a diffusion adjustment layer 400 that are stacked in sequence. The diffusion adjustment layer 400 includes a first diffusion adjustment layer 1, a second diffusion adjustment layer 2, and so on up to an nth diffusion adjustment layer n with gradually decreasing compactness; the first diffusion adjustment layer 1 is close to the silicon substrate 100, and the nth diffusion adjustment layer n is far from the silicon substrate 100; n is an integer greater than or equal to 2.
[0034] The solar cell 1000 of the present invention not only has a uniformly distributed PN junction, but also, due to the introduction of a multi-layer diffusion adjustment layer structure, reduces surface defects, achieves more efficient surface passivation, and reduces surface recombination of carriers, thereby effectively improving the cell efficiency.
[0035] In some embodiments, the contact angle of each diffusion adjustment layer is within the range of 5° - 20°; and from the first diffusion adjustment layer 1 to the nth diffusion adjustment layer n, the contact angle shows a decreasing trend.
[0036] Diffusion adjustment layers with different compactness levels exhibit different hydrophobicities. The layer with greater compactness has better hydrophobicity, thus a larger contact angle; the layer with smaller compactness has poorer hydrophobicity, thus a smaller contact angle. Controlling the compactness of the diffusion adjustment layer (equivalent to controlling the contact angle) is beneficial to improving the distribution uniformity of doping atoms on the surface of the silicon substrate 100, thereby enhancing the uniformity of the PN junction.
[0037] In some specific embodiments, on the premise of satisfying the decreasing trend of the contact angle from the first diffusion adjustment layer 1 to the nth diffusion adjustment layer n, the contact angle of each diffusion adjustment layer can be any value within the range of 5° - 20°, such as 5°, 6°, 7°, 8°, 9°, 10°, 11°, 12°, 13°, 14°, 5°, 16°, 17°, 18°, 19°, or 20°.
[0038] In some embodiments, referring to Figure 3 , n is 2, and the diffusion adjustment layer 400 includes a first diffusion adjustment layer 1 and a second diffusion adjustment layer 2. The contact angle of the first diffusion adjustment layer 1 is 10° - 20°; the contact angle of the second diffusion adjustment layer 2 is 5° - 10°. Setting a double-layer diffusion adjustment layer with different compactness levels (i.e., different contact angles) can improve the distribution uniformity of doping atoms on the surface of the silicon substrate 100, thereby enhancing the uniformity of the PN junction.
[0039] In some specific embodiments, the contact angle of the second diffusion adjustment layer 2 can be 5°, 6°, 7°, 8°, 9°, or 10°.
[0040] In some specific embodiments, the contact angle of the first diffusion adjustment layer 1 may be 10°, 11°, 12°, 13°, 14°, 15°, 16°, 17°, 18°, 19° or 20°.
[0041] In some embodiments, the thickness of each diffusion adjustment layer may be 3 nm - 10 nm, for example, it may be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm. If the thickness of the diffusion adjustment layer is too large, the blocking effect is too large, which is not conducive to atomic diffusion; if the thickness is too small, the purpose of adjusting the uniformity of the distribution of doped atoms cannot be achieved.
[0042] In some embodiments, n = 2, the thickness of the first diffusion adjustment layer 1 is 5 nm - 10 nm, and the thickness of the second diffusion adjustment layer 2 is 3 nm - 5 nm.
[0043] Optimizing the thicknesses of the first diffusion adjustment layer 1 and the second diffusion adjustment layer 2 is beneficial to improving the uniformity of the distribution of doped atoms on the surface of the silicon substrate 100, thereby improving the uniformity of the PN junction and further improving the battery efficiency. If the thicknesses of the first diffusion adjustment layer 1 and the second diffusion adjustment layer 2 are too small, the effect of improving the uniform distribution of doped atoms cannot be achieved. If the thicknesses of the first diffusion adjustment layer 1 and the second diffusion adjustment layer 2 are too large, it will cause an excessive blocking effect during the diffusion process, hinder atomic diffusion, and is not conducive to the formation of the PN junction.
[0044] In some specific embodiments, the thickness of the first diffusion adjustment layer 1 may be 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm or 10 nm.
[0045] In some specific embodiments, the thickness of the second diffusion adjustment layer 2 may be 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm.
[0046] In some embodiments, the thickness ratio of the first diffusion adjustment layer 1 to the second diffusion adjustment layer 2 is (1.5 - 2):1. Optimizing the thickness ratio of the first diffusion adjustment layer 1 and the second diffusion adjustment layer 2 is beneficial to further improving the uniformity of the distribution of doped atoms on the surface of the silicon substrate 100, thereby improving the uniformity of the PN junction.
[0047] In some specific embodiments, the thickness ratio of the first diffusion adjustment layer 1 to the second diffusion adjustment layer 2 may be 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1 or 2:1.
[0048] In some embodiments, n may be an integer from 2 to 5, for example, it may be 2, 3, 4 or 5. That is, the diffusion adjustment layer may include 2 layers, 3 layers, 4 layers or 5 layers of diffusion adjustment layers with different degrees of compactness.
[0049] In some embodiments, the material of the diffusion adjustment layer includes silicon oxide. The diffusion adjustment layer can be formed by oxidizing the silicon substrate without changing the original production line, saving costs.
[0050] In some embodiments, the silicon substrate 100 includes a P-type silicon substrate or an N-type silicon substrate. The doping layer 200 includes an N-type doping layer or a P-type doping layer. The multi-layer diffusion adjustment layer structure of the present invention is applicable to both phosphorus diffusion and boron diffusion, and can improve the uniformity of the formed PN junction, thereby improving the battery efficiency.
[0051] In some embodiments, the solar cell 1000 includes any one of a PERC cell (Passivated Emitter and Rear Cell), a TOPCon cell (Tunnel Oxide Passivating Contact), and a BC cell (Back Contact). The multi-layer diffusion adjustment layer structure of the present invention is applicable to various solar cells and is not limited to those listed.
[0052] In some embodiments, the solar cell 1000 may include a positive electrode, a positive electrode passivation layer, a diffusion adjustment layer, a doping layer 200, a silicon substrate 100, a negative electrode passivation layer, and a negative electrode, which are sequentially stacked.
[0053] In some specific embodiments, the positive electrode passivation layer may include SiO x layer, SiN x layer, SiN x layer, SiN x layer, SiNO x layer, SiO x layer. Thus, an antireflection film is formed on the battery surface to improve the absorption of sunlight, perform surface passivation and bulk passivation, block the corrosion of metal ions, water, etc. to the battery chip, improve the open-circuit voltage (Voc) of the battery, reflect the long-wavelength light back into the silicon wafer body for re-absorption, and improve the short-circuit current (Isc).
[0054] The negative electrode passivation layer may include an AlO x layer, a SiO x layer, a SiN x layer, a SiN x layer, and a SiN x layer. The AlO x layer mainly plays a passivation role on the back surface (i.e., the negative electrode side) to improve the open-circuit voltage and short-circuit current. The SiO x layer and the SiN x layer mainly protect the AlO xLayer to prevent the back surface aluminum paste from penetrating the negative electrode passivation layer and damaging the passivation effect. Reduce the back surface recombination rate, improve the response of the back surface cell in the long wavelength band, and repair the back surface state.
[0055] The second aspect of the present invention provides a method for manufacturing the solar cell 1000 of the first aspect of the present invention, including the following steps:
[0056] Perform the first oxidation on the silicon substrate 100 to form the nth diffusion adjustment layer n on the surface of the silicon substrate 100; perform the second oxidation on the silicon substrate 100 to form the (n - 1)th diffusion adjustment layer on the surface of the silicon substrate 100, and the (n - 1)th diffusion adjustment layer is located between the silicon substrate 100 and the nth diffusion adjustment layer n; and so on, until the nth oxidation is performed on the silicon substrate 100 to form the first diffusion adjustment layer 1 on the surface of the silicon substrate 100, and the first diffusion adjustment layer 1 is located between the silicon substrate 100 and the second diffusion adjustment layer 2; from the first oxidation to the nth oxidation, the oxidation temperature shows an increasing trend;
[0057] Dope atoms on the surface of the silicon substrate 100 to form a PN junction.
[0058] Before the diffusion treatment of the present invention, the silicon substrate 100 is oxidized n times. The oxidation temperature determines the compactness of the formed diffusion adjustment layer, i.e., the silicon oxide layer, and the compactness of the silicon oxide layer increases with the increase of the oxidation temperature. By controlling the oxidation temperature, diffusion adjustment layers with different compactness can be formed on the surface of the silicon substrate 100. The layer with a higher compactness is closer to the silicon substrate 100, and the layer with a lower compactness is farther from the silicon substrate 100. This multi-layer diffusion adjustment layer structure can make the doped atoms evenly distributed on the surface of the silicon substrate 100, improve the uniformity of the PN junction, and thus improve the cell efficiency.
[0059] The present invention first prepares a silicon oxide layer (i.e., the nth diffusion adjustment layer) with a loose structure at a lower oxidation temperature, and then forms the (n - 1)th diffusion adjustment layer at a higher temperature, which is denser than the nth diffusion adjustment layer, and so on, to form the first diffusion adjustment layer with a dense structure. Thus, the multi-layer diffusion adjustment layer structure of the present invention is obtained. The silicon oxide layer of the present invention is formed by the reaction of oxygen with the silicon on the surface of the silicon substrate. Therefore, the first formed silicon oxide layer is far from the silicon substrate, and the last formed silicon oxide layer is close to the silicon substrate.
[0060] In some embodiments, the oxidation temperature for each oxidation is within the range of 400°C - 800°C.
[0061] In some specific embodiments, on the premise that the oxidation temperature shows an increasing trend from the first oxidation to the nth oxidation, the oxidation temperature for each oxidation can be any value within the range of 400°C to 800°C, such as 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C or 800°C.
[0062] In some embodiments, n is 2, the oxidation temperature of the first oxidation is 400°C to 600°C; the oxidation temperature of the second oxidation is 750°C to 800°C. Oxidation at a low temperature is beneficial to obtaining a porous silicon oxide layer; oxidation at a high temperature is beneficial to obtaining a dense silicon oxide layer.
[0063] In some specific embodiments, the temperature of the first oxidation can be 400°C, 450°C, 500°C, 550°C or 600°C. The time of the first oxidation can be 1 min to 6 min, such as 1 min, 2 min, 3 min, 4 min, 5 min or 6 min.
[0064] In some specific embodiments, the temperature of the second oxidation can be 750°C, 760°C, 770°C, 780°C, 790°C or 800°C. The time of the second oxidation can be 1 min to 6 min, such as 1 min, 2 min, 3 min, 4 min, 5 min or 6 min.
[0065] In some embodiments, the silicon substrate 100 is oxidized in an oxygen atmosphere.
[0066] In some embodiments, before the first oxidation of the silicon substrate 100, the method further includes texturing the silicon substrate 100. The present invention does not make special limitations on the specific texturing method, and any texturing method commonly used in the art can be used in the present invention. For example, an alkaline solution can be used for texturing.
[0067] In some embodiments, after the formation of the PN junction, the method further includes an SE (Selective Emitter) process. Heavy doping is performed at the front-side metallization gate lines to form electrode heavy doping. Light doping is performed between the electrodes, which can further reduce the recombination of carriers and, at the same time, reduce the contact resistance between the metal electrode and silicon, thereby improving the photoelectric conversion efficiency. The present invention does not particularly limit the method for preparing SE, and common methods in the art can be used in the present invention. For example, a method including the following steps can be adopted: (1) Mask preparation: A mask is made on the surface of the silicon wafer to define the heavy-doping and light-doping regions; (2) First diffusion: The entire surface is lightly doped to form a uniform emitter; (3) Mask removal: The mask in some regions is removed to expose the heavy-doping regions; (4) Second diffusion: The exposed regions are heavily doped to form electrode contact regions with low contact resistance; (5) Cleaning and annealing: The surface impurities are cleaned and annealing is performed to repair lattice damage.
[0068] In some embodiments, the method further includes sequentially forming a positive electrode passivation layer and a positive electrode on the diffusion adjustment layer; and sequentially forming a negative electrode passivation layer and a negative electrode on the surface of the silicon substrate 100 away from the doping layer 200. The present invention does not particularly limit the formation methods of the positive electrode, the positive electrode passivation layer, the negative electrode, and the negative electrode passivation layer, and common methods in the art can be used in the present invention. For example, the positive electrode passivation layer and the negative electrode passivation layer can be formed by plasma-enhanced chemical vapor deposition (PECVD). The negative electrode and the positive electrode can be formed by screen printing.
[0069] The solutions of the present invention will be explained below in conjunction with embodiments. Those skilled in the art will understand that the following embodiments are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention. For those without specific technical or conditions noted in the embodiments, the techniques or conditions described in the literature in the art or according to the product specifications are followed. Those reagents or instruments without the producer noted are all conventional products that can be obtained through commercial purchase.
[0070] Example 1
[0071] (1) Texturing process:
[0072] The P-type silicon wafer is textured according to the following steps:
[0073] ① Pre-cleaning:
[0074] The silicon wafer is cleaned with a mixed solution of NaOH and H2O2 to remove surface organic substances and metal impurities. Then it is rinsed with pure water to ensure the surface is clean.
[0075] ② Texturing:
[0076] The texturing reaction is carried out using a mixed solution of NaOH and a texturing additive (Hangzhou Xiaochen Technology Co., Ltd., model T35A-1) to form a textured surface structure. (Texturing reaction equation: Si + 2NaOH + H2O → Na2SiO3 + 2H2↑)
[0077] ③ Post-cleaning:
[0078] Clean again using a mixed solution of NaOH and H2O2 to remove the texturing residues. Rinse thoroughly with pure water.
[0079] ④ Pickling:
[0080] Clean using a mixed solution of HF and HCl to remove the surface oxide layer and metal impurities. Rinse thoroughly with pure water.
[0081] ⑤ Drying:
[0082] Dry the P-type silicon wafer to prepare for the next process.
[0083] (2) First oxidation: Oxygen is introduced at 500 °C to form a loose silicon oxide layer (i.e., the second diffusion adjustment layer) on the surface of the P-type silicon wafer, and the oxidation time is 4 min.
[0084] (3) Diffusion process: POCl3 is used as the phosphorus source to prepare a PN junction on the P-type silicon wafer to form an internal electric field. (Diffusion equations: 4POCl3 + 3O2 → 2P2O5 + 6Cl2↑, 2P2O5 + 5Si → 5SiO2 + 4P↓)
[0085] The phosphorus diffusion is carried out according to the following steps to form an N-type doping layer:
[0086] ① Boat loading: Feed the P-type silicon wafer into the furnace tube.
[0087] ② Vacuum pumping: Create a negative pressure inside the furnace tube to facilitate the rapid filling of the furnace tube with gas and improve the gas distribution uniformity.
[0088] ③ Leak detection: Check the airtightness of the furnace tube to prevent impurities in the air from entering the furnace tube due to poor airtightness.
[0089] ④ Second oxidation: Oxygen is introduced at 780 °C to form a dense silicon oxide layer (i.e., the first diffusion adjustment layer) on the surface of the P-type silicon wafer, and the oxidation time is 5 min.
[0090] ⑤ Source feeding: Introduce nitrogen gas carrying POCl3 to deposit the phosphorus source on the silicon wafer surface.
[0091] ⑥ Pushing: Make the phosphorus atoms diffuse into the silicon body to increase the depth.
[0092] ⑦ Temperature reduction: Slowly reduce the furnace temperature to prevent damage to the silicon wafer caused by rapid temperature changes during the backpressure stage.
[0093] ⑧Backpressure: Introduce nitrogen gas to return the pressure to the normal pressure to open the furnace door.
[0094] ⑨Taking out the boat: Take out the P-type silicon wafers from the furnace tube.
[0095] (4) SE (Selective Emitter) process: Adopt the laser doping method to perform heavy doping at the metallized gate lines on the front side (i.e., the side where the N-type doping layer is formed) to form electrode heavy doping; perform light doping between the metallized gate lines.
[0096] (5) Chain oxidation / removing PSG / polishing: ① Chain oxidation: Form an oxide film on the surface through the oxidation process; ② Removing PSG (phosphosilicate glass): Use HF solution to remove the phosphosilicate glass generated during the diffusion process; ③ Polishing: Slightly polish the back side of the silicon wafer to improve the surface quality.
[0097] (6) Post-oxidation: Through the high-temperature thermal oxidation process, reduce the density of defect states at the system interface.
[0098] (7) Depositing the film layer structure on the back side by PECVD, successively including: AlO x layer, SiO x layer, SiN x layer, SiN x layer, SiN x layer.
[0099] (8) Depositing the film layer structure on the front side by PECVD, successively including: SiO x layer, SiN x layer, SiN x layer, SiN x layer, SiNO x layer, SiO x layer.
[0100] (9) Back laser: Use a laser beam to remove part of the passivation layer on the back side according to a preset pattern.
[0101] (10) After screen printing and sintering, a solar cell is obtained.
[0102] (11) Electrical injection: Introduce current into the solar cell, and regulate the valence state and distribution of hydrogen in the solar cell electrically to achieve passivation of defects and impurities.
[0103] Example 2 - 11
[0104] Prepare a solar cell according to the method described in Example 1, except that the parameters listed in Table 1 are different.
[0105] Comparative Example 1
[0106] The solar cell was prepared by the method described in Example 1, except that the primary oxidation in Step 2 was not carried out.
[0107] Comparative Example 2
[0108] The solar cell was prepared by the method described in Example 1, except that the temperature of the primary oxidation was 780 °C, the temperature of the secondary oxidation was 500 °C, a porous silicon oxide layer was formed on the N-type doped layer, and a dense silicon oxide layer was formed on the porous silicon oxide layer.
[0109] Testing method
[0110] (1) Contact angle test and thickness test of the porous silicon oxide layer and the dense silicon oxide layer
[0111] Testing the contact angle of the porous silicon oxide layer: The (1) texturing process and (2) primary oxidation process of Example 1 were carried out in sequence, so as to oxidize and form a porous silicon oxide layer on the surface of the P-type silicon wafer. The thickness of the porous silicon oxide layer was tested by an ellipsometer. Then, a drop of water was dropped on the porous silicon oxide layer to test the contact angle of the porous silicon oxide layer. The test results are shown in Table 1 below.
[0112] Testing the contact angle of the dense silicon oxide layer: The (1) texturing process and steps ①-④ in the (3) diffusion process of Example 1 (the primary oxidation process was not carried out) were carried out in sequence, so as to oxidize and form a dense silicon oxide layer on the surface of the P-type silicon wafer. The thickness of the dense silicon oxide layer was tested by an ellipsometer. Then, a drop of water was dropped on the dense silicon oxide layer to test the contact angle of the dense silicon oxide layer. The test results are shown in Table 1 below.
[0113] (2) Photovoltaic conversion efficiency test of the solar cell
[0114] By measuring the current output of the cell at different voltages and plotting the I-V curve, the photovoltaic conversion efficiency of the cell was calculated. The test results are shown in Table 1 below.
[0115] Table 1
[0116] Table 1
[0117]
[0118] Results and discussion:
[0119] By comparing Examples 1-3 and Comparative Examples 1-2, it can be seen that before doping phosphorus atoms, a double-layer silicon oxide layer structure was pre-introduced in the present invention, which includes a porous silicon oxide layer and a dense silicon oxide layer. The porous silicon oxide layer is arranged on the dense silicon oxide layer, and the dense silicon oxide layer is close to the P-type silicon substrate. When doping phosphorus atoms, this double-layer silicon oxide layer structure can make the phosphorus atoms evenly distributed on the surface of the silicon substrate, improve the uniformity of the PN junction, and thus effectively improve the cell efficiency.
[0120] By comparing Example 1 and Example 4, it can be seen that the contact angle of the porous silica layer in Example 4 is too small and the structure is too porous, which is not conducive to the uniformity of PN, resulting in a 0.15% decrease in the photoelectric conversion efficiency.
[0121] By comparing Example 1 and Example 5, it can be seen that the contact angle of the dense silica layer in Example 5 is too large and the structure is too dense, which is not conducive to the diffusion of phosphorus atoms and the formation of a uniform PN junction, resulting in a 0.13% decrease in the photoelectric conversion efficiency.
[0122] By comparing Example 1 and Example 6, it can be seen that the contact angle of the porous silica layer in Example 6 is too large and not within the range of 5°-10°, and the structure is relatively dense; at the same time, the contact angle of the dense silica layer is too large and not within the range of 10°-20°, and the structure is also too dense; although the density of the two silica layers still remains different, due to the relatively dense layer structure, the photoelectric conversion efficiency decreases by 0.2% compared with Example 1.
[0123] By comparing Example 1 and Example 7, it can be seen that the contact angle of the porous silica layer in Example 7 is too small and not within the range of 5°-10°, and the structure is too porous; at the same time, the contact angle of the dense silica layer is too small and not within the range of 10°-20°, and the structure is relatively porous; although the density of the two silica layers still remains different, due to the relatively porous layer structure, the photoelectric conversion efficiency decreases by 0.22% compared with Example 1.
[0124] By comparing Example 1 and Examples 8-10, it can be seen that too large or too small a thickness ratio of the porous silica layer to the dense silica layer is not conducive to improving the photoelectric conversion efficiency of the battery.
[0125] The terms "first" and "second" in the text are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more unless otherwise specifically defined.
[0126] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0127] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.
Claims
1. A solar cell, characterized in that, It includes a silicon substrate, a doping layer, and a diffusion adjustment layer which are stacked in sequence. The diffusion adjustment layer includes a first diffusion adjustment layer, a second diffusion adjustment layer, and so on up to an nth diffusion adjustment layer with gradually decreasing compactness. The first diffusion adjustment layer is close to the silicon substrate, and the nth diffusion adjustment layer is far from the silicon substrate. n is an integer greater than or equal to 2.
2. The solar cell according to claim 1, wherein The contact angle of each layer of the diffusion adjustment layer is within the range of 5° - 20°; and from the first diffusion adjustment layer to the nth diffusion adjustment layer, the contact angle shows a decreasing trend.
3. The solar cell according to claim 1, characterized in that, When n is 2, the contact angle of the first diffusion adjustment layer is 10° - 20°; the contact angle of the second diffusion adjustment layer is 5° - 10°.
4. The solar cell according to claim 1, characterized in that, The thickness of each layer of the diffusion adjustment layer is 3nm - 10nm.
5. The solar cell according to claim 1, characterized in that, When n is 2, the thickness of the first diffusion adjustment layer is 5nm - 10nm, and the thickness of the second diffusion adjustment layer is 3nm - 5nm; the thickness ratio of the first diffusion adjustment layer to the second diffusion adjustment layer is (1.5 - 2):
1.
6. The solar cell according to claim 1, wherein n is an integer from 2 to 5; The material of the diffusion adjustment layer includes silicon oxide; The silicon substrate includes a P-type silicon substrate or an N-type silicon substrate.
7. A method for preparing a solar cell according to any one of claims 1-6, characterized in that, It includes the following steps: Perform a first oxidation on the silicon substrate to form the nth diffusion adjustment layer on the surface of the silicon substrate; Perform a second oxidation on the silicon substrate to form the (n - 1)th diffusion adjustment layer on the surface of the silicon substrate. The (n - 1)th diffusion adjustment layer is located between the silicon substrate and the nth diffusion adjustment layer; and so on until the nth oxidation of the silicon substrate is performed to form the first diffusion adjustment layer on the surface of the silicon substrate. The first diffusion adjustment layer is located between the silicon substrate and the second diffusion adjustment layer; From the first oxidation to the nth oxidation, the oxidation temperature shows an increasing trend; Dope atoms on the surface of the silicon substrate to form a PN junction.
8. The method according to claim 7, characterized in that The oxidation temperature of each oxidation is within the range of 400°C - 800°C.
9. The method according to claim 7, characterized in that When n is 2, the oxidation temperature of the first oxidation is 400°C - 600°C; the oxidation temperature of the second oxidation is 750°C - 800°C.
10. A photovoltaic module, characterized in that, It includes the solar cell according to any one of claims 1 - 6 or the solar cell obtained by the method according to any one of claims 7 - 9.