Back contact battery, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, the back contact cell comprises a silicon substrate (1), the back surface is provided with a first region (A), a second region (B) and a spacer region (C), the adjacent first region (A) and second region (B) are separated by the spacer region (C), the first region (A) comprises a first sub-region (A1) with a textured surface and a second sub-region (A2) with a polished surface, and the first sub-region (A1) and the second sub-region (A2) are adjacent to each other; the emitting electrode is provided with a first conductive type, is arranged on the back surface of the silicon substrate (1), and comprises a first emitting electrode part (3) positioned in the first sub-region (A1) and a second emitting electrode part (5) positioned in the second sub-region (A2); a carrier collection layer having a second conductivity type opposite to the first conductivity type, provided on the back surface of the silicon substrate (1) and located in the second region (B); and a first electrode (12) in ohmic contact with the first emitter portion (3). The back contact battery has excellent electrical properties.

Description

Technical Field

[0001] The present disclosure relates to the field of photovoltaic technology, and particularly to an interdigitated back contact cell, a preparation method thereof, and a photovoltaic module. Background Art

[0002] As one of the high-efficiency cell technologies, the interdigitated back contact cell (full name: "Interdigitated Back Contact", abbreviated as IBC) has the following characteristics: 1. There is no grid line occlusion on the front side, which can improve the utilization rate of incident light by 0.3% - 0.4%, facilitating the increase of current; 2. The optimal passivation structure design can be made on the front side to maximize the front passivation ability; 3. As a platform technology, it has a high structural compatibility with high-efficiency passivation technologies such as tunnel oxide passivated contact (full name: "Tunnel Oxide Passivated Contact", abbreviated as TOPCon) and heterojunction technology (full name: "Heterojunction Technology", abbreviated as HJT), etc., and the theoretical efficiency limit is higher.

[0003] Benefiting from the above advantages, IBC has developed rapidly in recent years, especially the tunnel back contact (full name: "Tunnel Back Contact", abbreviated as TBC) cell technology combining TOPCon and IBC technologies. Among them, TOPCon cell technology, as a type of high-efficiency crystalline silicon cell, its excellent passivation effect stems from the ultra-thin tunnel oxide / doped polysilicon layer structure, which allows majority carriers to pass through and isolates minority carriers, thereby achieving the low recombination function. TBC cells are more advantageous in terms of preparation difficulty, cost, etc., and are therefore considered to be a high-efficiency back contact cell technology that is easier to mass-produce.

[0004] The prior art provides an interdigitated back contact cell, the back side of which includes a first region, a second region, and a spacer region disposed between the two. The first region is provided with a P + emitter, the second region is provided with an N-type carrier collection layer, and the first region has a full-textured structure. A passivation and antireflection layer is further provided on the outermost layers of the first region, the second region, and the spacer region. However, the electrical performance of this interdigitated back contact cell is poor. Summary of the Invention

[0005] The present disclosure provides an interdigitated back contact cell, a preparation method thereof, and a photovoltaic module, which can improve the electrical performance of the interdigitated back contact cell.

[0006] In the first aspect of the present disclosure, an interdigitated back contact cell is provided, including: a silicon substrate having a first region, a second region, and a spacer region on the back side, the adjacent first region and second region being separated by the spacer region. The first region includes an adjacent first sub-region and second sub-region, the first sub-region being textured, and the second sub-region being polished; The emitter, having a first conductivity type, is provided on the back surface of the silicon substrate, and the emitter includes a first emitter portion located in a first sub-region and a second emitter portion located in a second sub-region; The carrier collection layer, having a second conductivity type opposite to the first conductivity type, is provided on the back surface of the silicon substrate and located in the second region; and The first electrode is in ohmic contact with the first emitter portion.

[0007] In some embodiments, the first sub-region and the second sub-region are arranged side by side along a preset direction, and the preset direction is perpendicular to the thickness direction of the silicon substrate.

[0008] In some embodiments, the second sub-regions are provided on both sides of the first sub-region along the preset direction; or the first sub-region is located on one side of the second sub-region along the preset direction.

[0009] In some embodiments, in the preset direction, the width of the first sub-region accounts for 5%-90% of the width of the first region.

[0010] In some embodiments, in the preset direction, the width of the polished surface between the first sub-region and the edge of the first region where it is located is 0.1-300 μm.

[0011] In some embodiments, the area ratio of the first sub-region to the area of the first region is 4%-88%.

[0012] In some embodiments, the back surface of the silicon substrate has a first distance between the first sub-region and the front surface, and the back surface of the silicon substrate has a second distance between the second sub-region and the front surface, and the first distance is less than the second distance.

[0013] In some embodiments, the height difference between the first distance and the second distance is 0.5-5 μm.

[0014] In some embodiments, in the first region, the matte surface and the polished surface are connected by an inclined surface, and the side length of the inclined surface in the cross-section is 0.8-8 μm.

[0015] In some embodiments, the doping concentration of the second emitter portion in the second sub-region is 1×10 18 -1×10 19 atoms / cm 3 , the junction depth is 0.2-1.5 μm, and the doping concentration of the first emitter portion in the first sub-region is 2×10 18 -3×10 19 atoms / cm 3 , and the junction depth is 0.5-2 μm.

[0016] In some embodiments, the silicon substrate is an N-type silicon wafer, with a resistivity of 0.1-100 Ω·cm and a thickness of 100-500 μm.

[0017] In some embodiments, the carrier collection layer includes a tunneling layer and a doped polysilicon layer. The tunneling layer is disposed on the back surface of the silicon substrate and located in the second region, and the doped polysilicon layer is provided on a side of the tunneling layer away from the silicon substrate. The doped polysilicon layer has a second conductivity type opposite to the first conductivity type. The back contact cell further includes: a second electrode, in ohmic contact with the doped polysilicon layer.

[0018] In some embodiments, the emitter is P-type, the doped polysilicon layer is N-type, the back surface of the silicon substrate has a first distance between the first sub-region and the front surface, the back surface of the silicon substrate has a second distance between the second sub-region and the front surface, and the back surface of the silicon substrate has a third distance between the second region and the front surface; wherein, the absolute value of the difference between the first distance and the third distance does not exceed a preset distance, and the second distance is greater than the third distance.

[0019] In some embodiments, the absolute value of the difference between the first distance and the third distance does not exceed 2 μm, and the height difference between the second distance and the third distance is 0.5 - 5 μm.

[0020] In some embodiments, the first distance is less than the third distance.

[0021] In some embodiments, the area of the first region accounts for 30% - 50% of the total area of the back surface of the silicon substrate, and the area of the second region accounts for 40% - 60% of the total area of the back surface of the silicon substrate.

[0022] In some embodiments, the thickness range of the tunneling layer is 0.5 - 2.5 nm, the thickness range of the doped polysilicon layer is 100 - 300 nm, and the doping concentration of the doped polysilicon layer is 3×10 20 -1×10 21 atoms / cm 3 。

[0023] In some embodiments, the first electrode is configured to be formed by printing Ag paste on the back surface of the first sub-region, and the second electrode is configured to be formed by printing Ag paste in the second region.

[0024] In some embodiments, the back surface of the silicon substrate is a textured surface or a polished surface in the spacer region; and / or, the second region is a polished surface; and / or, the back contact cell further includes a passivation layer or a passivation and antireflection layer provided on the front surface and / or the back surface of the silicon substrate.

[0025] The second aspect of the present disclosure provides a photovoltaic module, including the back contact cell of the above embodiments.

[0026] The third aspect of the present disclosure provides a method for manufacturing a back contact cell, including: S1. Form a mask layer on the surface of the silicon substrate. The back surface of the silicon substrate includes a first region, a second region, and a spacer region. The adjacent first region and second region are separated by the spacer region. The first region includes an adjacent first sub-region and a second sub-region, and the first region is a polished surface; S2. Use a laser to remove the mask layer in the first sub-region on the back surface of the silicon substrate, and perform texturing treatment on the first sub-region to form a textured surface; S3. Remove the remaining mask layer on the surface of the silicon substrate. The second sub-region is a polished surface; S4. Perform a first doping treatment on the silicon substrate to form an emitter with a first conduction type in the first region, and the emitter in the first region includes a first emitter portion in the first sub-region and a second emitter portion in the second sub-region; S5. Perform a second doping treatment on the silicon substrate to form a carrier collection layer with a conduction type opposite to the first conduction type in the second region; S6. Form a first electrode that makes an ohmic contact with the first emitter portion on the first emitter portion.

[0027] In some embodiments, S4 specifically includes: S41. Integrally form an emitter and a first protective layer on the surface of the silicon substrate; S42. Remove the emitter and the first protective layer on the front surface, the second region on the back surface, and the spacer region of the silicon substrate.

[0028] In some embodiments, S5 specifically includes: S51. Sequentially grow a tunneling layer and an intrinsic polysilicon on the surface of the silicon substrate, and perform a second doping treatment to integrally form a tunneling layer, a doped polysilicon layer, and a second protective layer on the surface of the silicon substrate. The doped polysilicon layer has a second conduction type opposite to the first conduction type; S52. Remove the second protective layer on the front surface of the silicon substrate and the second protective layer on the first region and the spacer region on the back surface; S53. Remove the first protective layer on the first region and the second protective layer on the second region on the back surface of the silicon substrate.

[0029] In some embodiments, between S52 and S53, the preparation method further includes: forming a textured surface on the front and back surfaces of the silicon substrate in the spacer region; And / or, S52 includes: The second protective layers in the first region and the spacer region are removed simultaneously by the same laser beam. The laser parameters include: the laser radiation power is 1 - 50 W, and / or the laser wavelength of the laser is 350 - 1070 nm.

[0030] In some embodiments, after S5, the preparation method further includes: depositing a passivation layer or a passivation and antireflection layer on the front and back surfaces of the silicon substrate; And / or, in the mask layer forming step, the thickness of the mask layer is 1-100 nm, and the material of the mask layer includes SiO2 or SiNx.

[0031] In the back-contact battery according to the embodiment of the present disclosure, the first region where the emitter is located is set to a structure combined with a matte surface and a polished surface, and only the region in contact with the first electrode is set to a matte surface to ensure high matching with the LECO technology to achieve high contact performance, and an ohmic contact can be formed at the interface between the metal first electrode and the matte silicon, reducing the contact resistance. Moreover, since only a small area of the emitter is a matte surface and most of it is a polished surface, when the second laser treatment is adopted, the influence of the laser on the emitter can be concentrated in the matte surface region, with little damage to the polished surface of the second sub-region, and the damage to the emitter is concentrated in the first sub-region, so as to reduce the influence of the damage of the emitter on the passivation effect of the subsequent passivation layer and improve the passivation effect of the battery.

[0032] Since the polished surface in the first region A can improve the passivation ability of the battery, but will reduce the bifaciality of the battery. Therefore, by setting the first sub-region to a matte surface to improve the bifaciality of the battery and match the LECO technology, and setting the second sub-region to a polished surface to improve the passivation ability of the battery, the passivation ability and the bifaciality of the battery can be better balanced and taken into account, thereby improving the efficiency of the battery to convert light energy into electrical energy. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 It is a schematic structural diagram of setting a matte surface in the first sub-region on the back surface of the silicon substrate provided by an embodiment of the present disclosure.

[0035] Figure 2 It is a schematic structural diagram of forming an emitter and a first protective layer in the first region of the silicon substrate provided by an embodiment of the present disclosure.

[0036] Figure 3 It is a schematic structural diagram of forming a tunneling layer, a doped polysilicon layer and a second protective layer on the surface of the silicon substrate provided by an embodiment of the present disclosure.

[0037] Figure 4 It is a schematic structural diagram of removing the second protective layer in the first region and the spacer region on the back surface of the silicon substrate provided by an embodiment of the present disclosure.

[0038] Figure 5Schematic diagram of the structure of a back-contact battery provided by an embodiment of the present disclosure.

[0039] Figure 6 Schematic diagram of the structure of a back-contact battery provided by another embodiment of the present disclosure.

[0040] Figure 7 Schematic diagram of the structure of forming a textured surface in the first sub-region on the back surface of a silicon substrate provided by another embodiment of the present disclosure.

[0041] Figure 8 Schematic diagram of the structure of forming an emitter and a first protective layer on the surface of a silicon substrate provided by another embodiment of the present disclosure.

[0042] Figure 9 Schematic diagram of the structure of forming a tunneling layer, a doped polysilicon layer, and a second protective layer on the surface of a silicon substrate provided by another embodiment of the present disclosure.

[0043] Figure 10 Schematic diagram of the structure of removing the second protective layer on the back surface of the silicon substrate in the first region and the spacer region provided by another embodiment of the present disclosure.

[0044] Figure 11 Schematic diagram of the structure of a back-contact battery provided by another embodiment of the present disclosure.

[0045] Figure 12 Schematic diagram of the process flow of the method for manufacturing a back-contact battery provided by an embodiment of the present disclosure.

[0046] Figure 13 Schematic diagram of the process flow of performing a first doping process on a silicon substrate provided by an embodiment of the present disclosure.

[0047] Figure 14 Schematic diagram of the process flow of performing a second doping process on a silicon substrate provided by an embodiment of the present disclosure.

[0048] Explanation of reference numerals: 1. Silicon substrate; A. First region; A1. First sub-region; A2. Second sub-region; B. Second region; C. Spacer region; 2. Preset textured region; 3. First emitter portion; 4. Recessed portion; 5. Second emitter portion; 6. First protective layer; 7. Tunneling layer; 8. Doped polysilicon layer; 9. Second protective layer; 10. Front surface; 11. Passivation and antireflection layer; 12. First electrode; 13. Second electrode. Detailed implementation manners

[0049] The following further describes in detail the implementation manners of the present disclosure in conjunction with the drawings and embodiments. The detailed descriptions and drawings of the following embodiments are used to exemplarily illustrate the principles of the present disclosure, but cannot be used to limit the scope of the present disclosure, that is, the present disclosure is not limited to the described embodiments.

[0050] The inventor found through research that when preparing a back - contact battery and using the laser - enhanced contact optimization technology (the full name is "Laser - enhanced Contact Optimization", abbreviated as LECO technology), and when the surface of the silicon substrate where the P + emitter is located has a textured surface, compared with the polished surface, the P + tips of the textured surface of the emitter are more likely to achieve a higher - density silver - silicon contact site (i.e., silver - silicon alloy), forming a good ohmic contact. Among them, the LECO technology means that after screen - printing the metal electrode, a high - intensity laser is used to irradiate the surface of the silicon wafer, exciting charge carriers and applying a deflection voltage to generate a local current to promote the mutual diffusion of metal (such as silver paste) and silicon, thereby reducing the contact resistivity.

[0051] Currently, the back of the back - contact battery includes a first region, a second region, and a spacer region disposed between the two. The first region is provided with a P + emitter, the second region is provided with an N - type carrier collection layer, and the first region has a full - textured structure. The outermost layers of the first region, the second region, and the spacer region are also provided with a passivation layer or a passivation and antireflection layer. When preparing the back - contact battery, it includes two laser processes. Specifically, after boron diffusion on the surface of the silicon substrate to form a P + emitter and a borosilicate glass layer, the first laser treatment is used to remove the borosilicate glass layer on the second region and the spacer region on the back of the silicon substrate. After phosphorus diffusion on the back of the silicon substrate to form a phosphorus - doped carrier collection layer and a phosphosilicate glass layer, the second laser treatment is used to remove the phosphosilicate glass layer on the first region and the spacer region on the back. However, due to the relatively high laser penetrability, when the laser removes the phosphosilicate glass layer on the surface of the first region, the laser has a greater impact on the textured P + emitter and damages the textured surface of the first region. Although a passivation layer or a passivation and antireflection layer will be deposited on the surface of the P + emitter before forming the electrode, it is difficult to make up for the damage to the P + emitter, which is not conducive to improving the passivation effect of the battery. Such a structure and the corresponding process are not conducive to preparing a high - performance back - contact battery.

[0052] Therefore, if we want to improve the performance of the back - contact battery, we need to reduce the impact of the laser on the first region to prevent affecting the final passivation effect of the battery. Reasonably designing the structure and preparation process of the emitter is crucial for forming a high - performance back - contact battery.

[0053] Based on the above ideas, the present disclosure provides a back - contact battery, hereinafter referred to as "the battery" for short. As Figures 1 to 11 shown, in some embodiments, the back - contact battery includes: The silicon substrate 1 has a first region A, a second region B, and a spacer region C on the back surface. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes an adjacent first sub-region A1 and a second sub-region A2. The first sub-region A1 is a textured surface, and the second sub-region A2 is a polished surface. The emitter, having a first conductivity type, is provided on the back surface of the silicon substrate 1 and located in the first region A. The emitter includes a first emitter portion 3 located in the first sub-region A1 and a second emitter portion 5 located in the second sub-region A2. Since the first sub-region A1 is a textured surface and the second sub-region A2 is a polished surface, the first emitter portion 3 also has a textured surface structure, and the second emitter portion 5 also has a polished surface structure. The carrier collection layer, having a second conductivity type opposite to the first conductivity type, is provided on the back surface of the silicon substrate 1 and located in the second region B; and The first electrode 12 is in ohmic contact with the first emitter portion 3.

[0054] For example, the silicon substrate 1 can be an N-type silicon wafer, such as a single-crystalline silicon wafer doped with phosphorus atoms, having a resistivity of 0.1 - 100 Ω·cm, such as 0.1 Ω·cm, 10 Ω·cm, 20 Ω·cm, 30 Ω·cm, 40 Ω·cm, 50 Ω·cm, 60 Ω·cm, 70 Ω·cm, 80 Ω·cm, 90 Ω·cm, or 100 Ω·cm, etc. Optionally, the front surface 10 of the silicon substrate 1 has a textured surface structure, which can reduce light reflection and increase light absorption, thereby improving the efficiency of the battery.

[0055] Among them, the first region A, the second region B, and the spacer region C are not physical components, but regions divided in the extended plane of the silicon substrate 1. The spacer region C is a void. At least one of the first region A and the second region B can be provided. In the case where multiple first regions A and multiple second regions B are provided, the multiple first regions A and the multiple second regions B can be alternately arranged, for example, alternately arranged along a preset direction, and the preset direction can be the length direction or the width direction of the silicon substrate 1.

[0056] The back surface of the silicon substrate 1 is provided with an emitter in the first region A. The emitter has a first conductivity type, such as P-type, and can be formed into a P + emitter by boron doping.

[0057] For example, the doping concentration of the emitter in the second sub-region A2 (i.e., the second emitter portion 5) is 1×10 18 -1×10 19 atoms / cm 3 , the junction depth is 0.2 - 1.5 μm, and the doping concentration of the emitter in the first sub-region A1 (the first emitter portion 3) is 2×10 18 -3×10 19 atoms / cm 3, the junction depth is 0.5 - 2 μm. Since the first sub-region A1 has a textured surface and the second sub-region A2 has a polished surface, their specific surface areas are different, and the surface area of the textured surface is larger. Therefore, under the same diffusion process, the doping concentration of the first sub-region A1 is higher than that of the second sub-region A2. Moreover, such a doping concentration can reduce the contact resistance between the first sub-region A1 and the first electrode.

[0058] See Figure 5 、 Figure 6 or Figure 11 , the carrier collection layer provided on the back surface of the silicon substrate 1 in the second region B includes a tunneling layer 7 and a doped polysilicon layer 8. The tunneling layer 7 is provided on the back surface of the silicon substrate 1 and is located in the second region B. The doped polysilicon layer 8 is provided on the side of the tunneling layer 7 away from the silicon substrate 1, and the doped polysilicon layer 8 has a second conductivity type opposite to the first conductivity type. Among them, the tunneling layer 7 is an ultra-thin dielectric layer, which allows electrons to pass through efficiently through the quantum tunneling effect, and at the same time blocks the recombination loss of other charges (such as holes). It can be made of silicon oxide (SiO2), silicon nitride (SiN x ), or aluminum oxide (Al2O3), etc.

[0059] The doped polysilicon layer 8 can be an N-type doped polysilicon layer. For example, an N + Poly Si is formed, that is, a SiO2 / N + Poly Si laminated structure is provided on the back surface of the silicon substrate 1 in the second region B. For example, the thickness range of the tunneling layer 7 is 0.5 - 2.5 nm, such as 0.5 nm, 1 nm, 2.5 nm, 2 nm or 2.5 nm, etc. The thickness range of the doped polysilicon layer 8 is 100 - 300 nm, such as 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc. The doping concentration of the doped polysilicon layer 8 is 3×10 20 -1×10 21 atoms / cm 3 .

[0060] See Figure 5 、 Figure 6 or Figure 11 , the first electrode 12 is in ohmic contact with the first emitter portion 3 and is located in the first sub-region A1. For example, the first electrode 12 is configured to be formed by printing Ag paste on the back surface of the first sub-region A1.

[0061] In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0062] In this embodiment, the first region A where the emitter is located is set to a structure that combines a matte surface and a polished surface, and only the region in contact with the first electrode 12 is set to a matte surface, ensuring high compatibility with the LECO technology to achieve high contact performance, enabling an ohmic contact to be formed at the interface between the metal first electrode 12 and the matte silicon, and reducing the contact resistance. Moreover, since only a small area of the emitter is the matte surface and most is the polished surface, when the second laser treatment is performed, the influence of the laser on the emitter can be concentrated in the matte surface region, avoiding accidental damage to the polished surface of the second sub-region A2, and the damage to the emitter is concentrated in the first sub-region A1, so as to reduce the impact of the damage to the emitter on the passivation performance of the subsequent passivation layer and improve the passivation effect of the battery.

[0063] Since the polished surface in the first region A can improve the passivation ability of the battery, but will reduce the bifaciality of the battery (the bifaciality is the ratio of the maximum power output on the back side to the maximum power output on the front side). Therefore, by setting the first sub-region A1 to a matte surface to improve the bifaciality of the battery and match the LECO technology, and setting the second sub-region A2 to a polished surface to improve the passivation ability of the battery, this can better balance and take into account the passivation ability and the bifaciality of the battery, thereby improving the efficiency of the battery in converting light energy into electrical energy.

[0064] Specifically, matte silicon can increase the effective contact area. The matte surface has a microscopically rough surface structure. Compared with a flat surface, its actual contact area with the first electrode 12 is larger, thus reducing the contact resistance and making it easier for electrons to be transmitted between the matte silicon and the first electrode 12. Moreover, matte silicon can optimize the interfacial charge transport, that is, it changes the interfacial characteristics between the first electrode 12 and the semiconductor material, making the charge distribution at the interface more uniform, reducing the accumulation and scattering of charges. When electrons are transmitted from the semiconductor material to the electrode, the uniform charge distribution helps the electrons to pass through the interface more smoothly, reducing the hindrance during the transmission process, and thus reducing the ohmic contact resistance. In addition, matte silicon can improve the wettability between materials, making the first electrode 12 fit better with the matte surface, reducing the gaps and voids between the two, reducing the transmission resistance of electrons at the interface, and being conducive to reducing the ohmic contact resistance. And when using the LECO technology, the matte surface is more conducive to the ohmic contact between the first emitter part 3 and the first electrode 12.

[0065] It should be noted that, compared with the matte surface, the polished surface can better reflect the laser, and the damage of the laser to the polished surface is small while the damage to the matte surface is large. Therefore, concentrating the laser on the small-area first sub-region A1 can reduce the damage of the laser to the emitter.

[0066] In some embodiments, such as Figure 5 、 Figure 6 or Figure 11As shown, the first sub-region A1 and the second sub-region A2 are arranged side by side in a preset direction, where the preset direction is perpendicular to the thickness direction of the silicon substrate 1. Here, "perpendicular" does not mean strictly perpendicular, but within the allowable error range. The first sub-region A1 and the second sub-region A2 can be in an interdigitated structure, or of course, in other regular or irregular structures. For example, if the second sub-region A2 is entirely located on the side of the first sub-region A1, "arranged side by side" means that the adjacent first sub-region A1 and second sub-region A2 are arranged in the preset direction, and both the first sub-region A1 and the second sub-region A2 can extend perpendicular to the preset direction; if the second sub-region A2 surrounds the first sub-region A1, in any preset direction perpendicular to the thickness direction of the silicon substrate 1, it can be considered that the adjacent first sub-region A1 and second sub-region A2 are "arranged side by side".

[0067] In some embodiments, as Figure 5 shown, the second sub-regions A2 are provided on both sides of the first sub-region A1 along the preset direction. Preferably, the first sub-region A1 is located in the middle region of the second sub-regions A2 along the preset direction.

[0068] This structure has polishing regions for protection on both sides where the first sub-region A1 is provided with a matte surface, which can better reduce the influence of the second laser treatment on the emitter, and thus is conducive to improving the passivation performance of the passivation layer on the battery. And if spacer regions C are provided on both sides of the first region A, when laser treatment is performed on the spacer regions C, since the adjacent polishing regions can better reflect the laser, the damage of the laser to the emitter can also be reduced.

[0069] In other embodiments, as Figure 6 shown, the first sub-region A1 is located on one side of the second sub-region A2 along the preset direction. For example, the first sub-region A1 is located on the side of the second sub-region A2 away from the spacer region C along the preset direction. This structure is more convenient for processing and is convenient for leaving a larger area for setting the first electrode 12.

[0070] In some embodiments, in the preset direction, the width of the first sub-region A1 accounts for 5% - 90% of the width of the first region A, such as 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 60%, 70%, 80% or 90%, etc.

[0071] By setting the width ratio range of the first sub-region A1, it can not only ensure sufficient space for setting the first electrode 12, but also make the second laser treatment focus on the textured surface area, avoiding accidentally damaging the polished surface of the second sub-region A2. The damage to the emitter is limited to the first sub-region A1, so as to reduce the impact of emitter damage on the subsequent passivation layer and improve the passivation effect of the battery. Moreover, setting a certain textured surface width range for the first sub-region A1 can ensure the bifaciality of the battery, thus balancing and taking into account the passivation ability and the bifaciality of the battery to the greatest extent, and then improving the efficiency of the battery to convert light energy into electrical energy.

[0072] In some embodiments, in the preset direction, the width of the polished surface between the first sub-region A1 and the edge of the first region A where it is located is 0.1 - 300 μm, and this width dimension can be set according to the width of the first region A. If the first sub-region A1 has a polished surface on only one side (i.e., the second sub-region A2), the width of the second sub-region A2 is 0.1 - 300 μm. For example, this width can be 0.1 μm, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, 210 μm, 220 μm, 230 μm, 240 μm, 250 μm, 260 μm, 270 μm, 280 μm, 290 μm, 300 μm, etc.

[0073] In some embodiments, the proportion of the area of the first sub-region A1 in the area of the first region A is 4% - 88%. For example, this proportion can be 4%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 88%. The value of this proportion can be selected according to the requirements for the passivation ability and the bifaciality of the battery. By setting the area proportion of the first sub-region A1 within the above range, it can not only ensure sufficient space for setting the first electrode 12, but also balance and take into account the passivation ability and the bifaciality of the battery to a certain extent, thereby improving the efficiency of the battery to convert light energy into electrical energy.

[0074] In some embodiments, the back surface of the silicon substrate 1 has a first distance between the first sub-region A1 and the front surface 10, and the back surface of the silicon substrate 1 has a second distance between the second sub-region A2 and the front surface 10, and the first distance is less than the second distance. Preferably, the height difference between the first distance and the second distance is 0.5 - 5 μm.

[0075] This structure is equivalent to that in the first region A, the matte surface is recessed relative to the polished surface towards the front side 10 of the silicon substrate 1, and the height difference between the matte surface and the polished surface is 0.5 - 5 μm. For example, the height difference is 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm. By making the matte surface recessed relative to the polished surface towards the front side 10 of the silicon substrate 1, it is convenient for processing. Optionally, the matte surface can also protrude relative to the polished surface towards the side away from the front side 10.

[0076] In some embodiments, as Figure 5 and Figure 6 shown, the emitter is P-type, the doped polysilicon layer 8 is N-type, the back side of the silicon substrate 1 has a first distance between the first sub-region A1 and the front side 10, the back side of the silicon substrate 1 has a second distance between the second sub-region A2 and the front side 10, and the back side of the silicon substrate 1 has a third distance between the second region B and the front side 10; wherein, the absolute value of the difference between the first distance and the third distance does not exceed a preset distance, and the second distance is greater than the third distance.

[0077] Among them, the first distance can be greater than, less than or equal to the third distance. Referring to the following preparation method, this distance relationship can be adjusted accordingly by adjusting the laser post-texturing time of the mask layer and the polishing time after laser etching the first protective layer 6 (BSG) in the second region B.

[0078] In this embodiment, the back side of the silicon substrate 1 is recessed inward in the second region B relative to the first region A to form a recess 4. Thus, a height difference is formed between the emitter and the doped polysilicon layer 8 in the thickness direction. Thus, a height difference is formed between the emitter and the doped polysilicon layer 8 in the thickness direction, increasing the surface area of the back side, increasing the light absorption area, improving the efficiency of the battery, and the light can form multiple reflections on the back side, which is more conducive to light absorption; moreover, the spacer region C can completely separate the emitter and the doped polysilicon layer 8 to avoid leakage problems. Moreover, the distances from the first sub-region A1 and the second region B to the front side 10 do not exceed the preset distance, so that the matte surface of the first sub-region A1 can be as close as possible to the front side 10, as Figure 11As shown, it is a preferred embodiment that the first distance is less than the third distance, which can reduce the distance between the first sub-region A1 and the front surface 10. Since the transport of minority carriers in the battery has a significant impact on battery performance, when the first distance is less than the third distance, photo-generated holes (minority carriers) are not easily affected by the electric field of the N region with a negative electric field while migrating towards the P region, so that the influence range and action time of the N region electric field on the holes during the transport process are reduced, and the holes can be transported to the first electrode 12 more directly and efficiently, reducing the possibility of carriers recombining with holes at the edge of the isolation region, increasing the lifetime of minority carriers, improving the photoelectric conversion efficiency, reducing energy loss, and being more conducive to the improvement of battery performance. Even if the first distance is greater than the third distance, as long as the absolute value of the difference between the first distance and the third distance does not exceed a preset distance, the distance between the first sub-region A1 and the front surface 10 can still be minimized as much as possible, which is still beneficial to the improvement of battery performance.

[0079] Preferably, the absolute value of the difference between the first distance and the third distance does not exceed 2 μm, and the height difference between the second distance and the third distance is 0.5 - 5 μm. By limiting the maximum value of this height difference, the P-type first region A can be closer to the front surface 10, so that the holes are not affected by the N region electric field during the transport process, reducing the possibility of carriers recombining at the edge of the isolation region, and being more conducive to the improvement of battery performance. In practice, after laser-etching the emitter of the second region B, a recess 4 can be formed by etching, and the depth of the recess 4 can be reduced by reducing the etching time.

[0080] In other embodiments, as Figure 6 shown, the first distance is greater than the third distance, and the second distance is greater than the third distance, and this also falls within the protection scope of the embodiments of the present disclosure.

[0081] In some embodiments, in the first region A, the matte surface and the polished surface are connected by an inclined surface, and the side length of the inclined surface in the cross-section is 0.8 - 8 μm, where the cross-section is a plane perpendicular to the extension direction of the inclined surface.

[0082] When forming the matte surface by chemical etching, the etching solution has different etching rates for different crystal planes on the surface of the silicon substrate 1. Some crystal planes are etched faster, and some crystal planes are etched relatively slower. When the polished surface is gradually etched to form the matte surface, due to the uneven etching, an inclined surface is naturally formed in the transition region between the polished surface and the matte surface. For example, the atomic arrangement of the (100) crystal plane is relatively loose and the etching rate is the fastest, the atomic arrangement of the (111) crystal plane is tight and the etching speed is the slowest, and the atomic arrangement tightness of the (110) crystal plane is between that of the (100) crystal plane and the (111) crystal plane, and the etching rate is also between the two. Moreover, the matte surface and the polished surface are connected by an inclined surface in a transitional manner, which can relieve the stress at the connection between the matte surface and the polished surface, prevent sharp boundaries from generating defects that cause the defect positions to become recombination centers of carriers, and improve the photoelectric conversion efficiency of the battery.

[0083] In some embodiments, the back-contact battery further includes: a second electrode 13, which is in ohmic contact with the doped polysilicon layer 8.

[0084] The first electrode 12 and the second electrode 13 have opposite polarities. For example, the first electrode 12 is configured to be formed by printing Ag paste on the back surface of the first sub-region A1, and the second electrode 13 is configured to be printed with Ag paste in the second region B.

[0085] In some embodiments, the area of the first region A accounts for 30% - 50% of the total back surface area of the silicon substrate 1, such as 30%, 35%, 40%, 45% or 50%, etc., and the area of the second region B accounts for 40% - 60% of the total back surface area of the silicon substrate 1, such as 40%, 45%, 50%, 55% or 60%, etc., to ensure the total amount of photo-generated carriers.

[0086] In some embodiments, the back surface of the silicon substrate 1 is a textured surface in the spacer region C, which can improve the bifaciality of the battery. Specifically, the back surface of the silicon substrate 1 is set as a textured surface in the spacer region C. When light irradiates on the textured surface, multiple reflections occur, and more light can be absorbed by the battery and converted into electrical energy, improving the light utilization rate of the back surface of the battery. Moreover, the textured surface structure has broadband antireflection characteristics, which can reduce the reflection of light in a relatively wide wavelength range and reduce reflection losses. Also, due to the undulating structure of the textured surface, the propagation path of light inside the battery is longer, increasing the probability of interaction between photons and the silicon substrate, generating more carriers, and optimizing the light absorption effect. All these advantages can improve the bifaciality of the battery.

[0087] Optionally, the back surface of the silicon substrate 1 is a polished surface in the spacer region C to obtain a better passivation effect. Specifically, the atoms on the polished surface are arranged neatly, the surface atoms are in stable lattice positions, the surface area is smaller, and the number of crystal defects is less; moreover, the polished surface can remove the damage generated in the spacer region C on the back surface of the silicon substrate 1, reducing the number of crystal defects, and reducing the probability of carrier recombination at the back surface defects; in addition, the polished surface provides a smooth and uniform substrate for the growth of the passivation film, increasing the adhesion between the passivation film and the polished surface, and facilitating the formation of a passivation film with a uniform thickness, effectively blocking the recombination of carriers. All these advantages are beneficial to obtaining a better passivation effect.

[0088] In some embodiments, the second region B is a polished surface, thus facilitating the improvement of the passivation performance of the back-contact battery.

[0089] In some embodiments, the back-contact battery further includes a passivation layer or a passivation and antireflection layer provided on the front and / or back surface of the silicon substrate 1. In this way, through the passivation layer or the passivation and antireflection layer, the passivation performance of the battery can be improved, and the influence caused by defects generated during the preparation process of the battery can be reduced or avoided.

[0090] Two specific embodiments will be given below.

[0091] In the first embodiment, as Figure 5 shown, the front surface of the silicon substrate 1 has no metal grid lines, and the back surface has a first region A and a second region B. A plurality of first regions A and second regions B can be provided, and they are arranged alternately. The back surface of the silicon substrate 1 is recessed inward in the second region B relative to the first region A. Thus, a height difference is formed between the emitter and the doped polysilicon layer 8 in the thickness direction, increasing the surface area of the back surface and the light absorption area, improving the efficiency of the battery, and the light can form multiple reflections on the back surface, which is more conducive to light absorption; moreover, the spacer region C can completely separate the emitter from the doped polysilicon layer 8 to avoid leakage problems.

[0092] The first region A includes a first sub-region A1 and a second sub-region A2 along a preset direction (such as the direction parallel to the front surface of the silicon wafer). The first sub-region A1 is a textured surface, and the first sub-region A1 is provided in the middle region of the second sub-region A2 along the preset direction. The first electrode 12 is in ohmic contact with the first emitter portion of the first sub-region A1.

[0093] For example, the first region A is a P region, the second region B is an N region, and the silicon substrate 1 has a P + emitter and a passivation and antireflection layer 11 from the inside to the outside in the first region A. The silicon substrate 1 has a tunneling layer 7, an N-type doped polysilicon layer 8, and a passivation and antireflection layer 11 in sequence from the inside to the outside in the second region B. The spacer region C adopts a textured surface.

[0094] For example, the first region A, the second region B, and the spacer region C are P + emitter, SiO2 / N + Poly Si structure, a stack of silicon nitride and silicon dioxide respectively. The spacer region C overlaps with both the first region A and the second region B.

[0095] In the second embodiment, as Figure 6 shown, the difference from the Figure 5 battery shown is that the first sub-region A1 is located on one side of the second sub-region A2 along the preset direction. For example, the first sub-region A1 is located on the side of the second sub-region A2 away from the spacer region C along the preset direction.

[0096] Secondly, the present disclosure provides a photovoltaic module including the back-contact battery of the above embodiments. Exemplarily, the photovoltaic module includes a laminate and a frame assembled at the edge of the laminate, wherein the laminate includes a cover plate, an encapsulant film, a back-contact battery, an encapsulant film, and a backsheet laminated in sequence. Since the first region A where the emitter of the battery is located is set to a structure of a textured surface and a polished surface composite, and only the region in contact with the first electrode 12 is set to a textured surface, an ohmic contact can be formed at the interface between the metal first electrode 12 and the textured silicon, reducing the contact resistance. Moreover, since the emitter only occupies a small area as the textured surface and most of it is the polished surface, the second laser treatment can be focused on the textured surface region, avoiding damaging the polished surface of the second sub-region A2, minimizing the damage to the emitter, and better balancing the passivation ability and the bifaciality of the battery. Thereby, the efficiency of converting light energy into electrical energy of the photovoltaic module can also be improved, enhancing the comprehensive performance.

[0097] Finally, the present disclosure provides a preparation method for the back-contact battery based on the above embodiments. In some embodiments, as Figure 12 shown, the preparation method includes: Step S1, mask layer formation step: forming a mask layer on the surface of the silicon substrate 1. The back surface of the silicon substrate 1 includes a first region A, a second region B, and a spacer region C. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes an adjacent first sub-region A1 and a second sub-region A2, and the first region A is a polished surface.

[0098] Step S2, texturing treatment: using a laser to remove the mask layer located on the back surface of the silicon substrate 1 in the first sub-region A1 and performing texturing treatment on the first sub-region A1 to form a textured surface.

[0099] Step S3, removing the remaining mask layer on the surface of the silicon substrate 1. The second sub-region A2 is a polished surface. Since other regions are covered by the mask layer and are not affected by the texturing treatment, the second sub-region A2 is a polished surface.

[0100] Step S4, performing a first doping treatment on the silicon substrate 1 to form an emitter with a first conductivity type in the first region A, and the emitter in the first region A includes a first emitter portion 3 located in the first sub-region A1 and a second emitter portion 5 located in the second sub-region A2.

[0101] Step S5, performing a second doping treatment on the silicon substrate 1 to form a carrier collection layer with a conductivity type opposite to that of the first conductivity type in the second region B.

[0102] Step S6, forming a first electrode 12 in ohmic contact with the first emitter portion 3 on the first emitter portion 3.

[0103] Among them, steps S1 to S6 are executed in sequence.

[0104] Before step S1, the silicon substrate 1 can be polished first.

[0105] In step S1, the mask layer can be an oxidation mask layer to protect the entire surface of the silicon substrate 1. For example, the thickness of the mask layer is 1-100 nm, such as 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc. The material of the mask layer includes SiO2 or SiNx.

[0106] In step S2, as Figure 1 or Figure 7 shown, a laser is used to remove a preset texturing area 2 with a width of 50-100 μm on the back surface of the silicon substrate 1, corresponding to the first sub-region A1. The preset texturing area 2 is recessed inward with respect to the back surface of the silicon substrate 1, and a texturing process is performed to make the laser-etched area become a matte surface, while the non-laser area is not affected and remains a polished surface.

[0107] In some embodiments, as Figure 13 shown, S4 specifically includes: S41. Form an emitter and a first protective layer 6 on the entire surface of the silicon substrate 1.

[0108] Specifically, an acid solution (such as HF acid) is used to remove the mask layer on the surface of the silicon substrate 1, and a first doping process is performed to form an emitter and a first protective layer 6 on the entire surface of the silicon substrate 1. For example, the first doping process can be a boron diffusion process to uniformly form a P + emitter and borosilicate glass (BSG) on the surface of the silicon substrate 1. Among them, the borosilicate glass layer can be called the first protective layer 6.

[0109] S42. Remove the emitter and the first protective layer 6 on the front surface 10, the second region B on the back surface, and the spacer region of the silicon substrate 1.

[0110] Specifically, a laser is used to etch the first protective layer 6 (such as BSG) on the back surface of the silicon substrate 1 in the second region B and the spacer region C, and a single-sided etching is used to remove the first protective layer 6 (such as BSG) on the front surface 10. For example, the front surface can be etched by a chain single-sided etching (acid bath). After the etching of the first protective layer 6 is completed, an alkaline solution can be used for polishing to remove the emitter on the back surface of the silicon substrate 1 in the second region B and the spacer region C and the front surface 10. Subsequently, a polishing process is performed to make the second region B, the spacer region C on the back surface of the silicon substrate 1, and the front surface 10 all become polished surfaces. Moreover, the second region B and the spacer region C on the back surface of the silicon substrate 1 are recessed inward with respect to the first region A with respect to the front surface 10 to form a recessed portion 4, that is, the distance between the back surface and the front surface 10 of the silicon substrate 1 is less in the second region B than in the first region A, forming a structure as Figure 2 shown. A structure as Figure 8 shown can also be formed.

[0111] In some embodiments, as Figure 14 shown, step S5 specifically includes: Step S51: A tunneling layer 7 and an intrinsic polysilicon are sequentially grown on the surface of the silicon substrate 1, and a second doping process is performed to integrally form a tunneling layer 7, a doped polysilicon layer 8, and a second protective layer 9 on the surface of the silicon substrate 1. The doped polysilicon layer 8 has a second conductivity type opposite to the first conductivity type; Step S52: Remove the second protective layer 9 on the front surface 10 of the silicon substrate 1 and on the back surface in the first region A and the spacer region C; Step S53: Remove the first protective layer 6 on the back surface of the silicon substrate 1 in the first region A and the second protective layer 9 in the second region B.

[0112] Among them, steps S51 to S53 are executed in sequence. Hereinafter, taking the first region A as a P region and the second region B as an N region as an example for illustration.

[0113] Specifically, step S51 may include growing a tunneling layer 7 and an intrinsic polysilicon on the surface of the silicon substrate 1 in sequence. The tunneling layer 7 may be a tunneling oxide layer, and a second doping process is performed to integrally form a tunneling layer 7, a doped polysilicon layer 8, and a second protective layer 9 on the surface of the silicon substrate 1, forming a structure as Figure 3 or Figure 9 shown. At this time, a multi-layer structure of tunneling layer 7 / doped polysilicon layer 8 / second protective layer 9 is formed from the inside to the outside in the second region B and the spacer region C on the back surface of the silicon substrate 1. An emitter / first protective layer 6 / doped polysilicon layer 8 / second protective layer 9 is formed in the first region A on the back surface of the silicon substrate 1. In fact, the tunneling layer 7 also adheres to the first protective layer 6, but since the tunneling layer 7 is relatively thin and is mixed with the oxide layer of the first protective layer 6 itself, it is called the first protective layer 6.

[0114] For example, the tunneling layer 7 is SiO2, and the second doping process may be a phosphorus diffusion process. After the treatment, a structure of SiO2 / N + Poly Si / phoshorus silicate glass (PSG) is formed from the inside to the outside in the second region B and the spacer region C on the back surface of the silicon substrate 1, and a structure of P + emitter / BSG / N + Poly Si / PSG is formed from the inside to the outside in the first region A on the back surface of the silicon substrate 1. The phoshorus silicate glass layer may be called the second protective layer.

[0115] Specifically, step S52 may include: when removing the second protective layer, laser-etching the second protective layer 9 on the back surface of the silicon substrate 1 in the first region A and the spacer region C, such as PSG, and removing the PSG on the front surface 10 by single-sided etching. For example, by utilizing the difference in acid-base corrosion characteristics, that is, alkaline solution mainly corrodes crystalline silicon and polycrystalline silicon, while the corrosion rate of the glass layer is extremely slow, and hydrofluoric acid (HF) mainly corrodes the glass layer and does not corrode crystalline silicon. The second protective layer 9 (such as PSG) on the front surface can be etched by a chain single-sided etching process in a 25% mass concentration hydrofluoric acid (HF) solution. The doped polycrystalline silicon layer 8 (N + Poly Si layer) inside the second protective layer 9 (such as PSG) can be removed by a 5% mass concentration potassium hydroxide (KOH) solution. At this time, the first region A of the silicon substrate 1 includes P + emitter / BSG, the spacer region C forms a textured surface or a polished surface, and the second region B remains in the SiO2 / N + Poly Si / phosilicate glass (PSG) structure.

[0116] Between step S52 and step S53, the manufacturing method provided by the present disclosure further includes: making the front surface 10 and the back surface of the silicon substrate 1 form a textured surface in the spacer region C. After removing the doped polycrystalline silicon layer 8 inside the second protective layer 9, an alkaline solution is used to texture the spacer region C to form a textured surface. It is also possible to make the front surface of the battery form a textured surface. In this embodiment, the front surface 10 of the silicon substrate 1 forms a textured surface, which can reduce the reflection of light, has a good light-limiting effect, and can further improve the light utilization rate. The back surface of the silicon substrate 1 forms a textured surface in the spacer region C, which can improve the bifaciality of the battery.

[0117] Specifically, step S53 may include: removing the first protective layer 6 (such as BSG) on the back surface of the silicon substrate 1 in the first region A and the second protective layer 9 (such as PSG) in the second region B with an acid solution (such as HF acid), forming a structure as Figure 4 or Figure 10 shown.

[0118] In some embodiments, between step S5 and step S6, the manufacturing method further includes: depositing a passivation and antireflection layer 11 or a passivation layer on the front surface 10 and the back surface of the silicon substrate 1, see the structure as Figure 5 shown.

[0119] For example, the passivation layer may include a silicon oxide layer, and the passivation and antireflection layer 11 includes a composite layer formed by at least one of silicon nitride and silicon oxynitride and a silicon oxide layer, with a thickness of 60 nm to 130 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm or 130 nm, etc. Both silicon oxide and silicon nitride can play a passivation role, and silicon nitride can play an antireflection role. By setting the passivation and antireflection layer 11, the reflectivity can be reduced and the light utilization rate can be improved.

[0120] In some embodiments, step 52 includes: the second protective layers 9 of the first region A and the spacer region C are removed simultaneously by the same laser beam. The laser parameters include: the laser radiation power is 1 - 50 W, and / or the laser wavelength of the laser is 350 - 1070 nm. This method can improve the manufacturing efficiency.

[0121] The laser wavelength can be selected within the above range. For example, the laser wavelength can be selected as 355 nm, 532 nm, 1064 nm, etc. When selecting a specific laser wavelength, the laser wavelength will also fluctuate within a small range in a preset interval.

[0122] In step S6, as Figure 5 、 Figure 6 or Figure 11 shown, a first electrode 12 is provided in the first sub-region A1 of the emitter.

[0123] In some embodiments, the manufacturing method further includes: providing a second electrode 13 on the doped polysilicon layer 8. In the embodiments of the present disclosure, the setting order of the first electrode 12 and the second electrode 13 is not specifically limited.

[0124] The manufacturing method of this embodiment sets the first region A where the emitter is located as a structure combined with a matte surface and a polished surface, and only the region in contact with the first electrode 12 is set as the matte surface, ensuring a high match with the LECO technology to achieve high contact performance, enabling the first electrode 12 to form an ohmic contact with the emitter at the matte silicon, and reducing the contact resistance. Moreover, since only a small area of the emitter is in the matte surface and most of it is located on the polished surface, when the second laser treatment is used to remove the carrier collection layer in the first region, the influence of the laser on the emitter can be concentrated on the matte surface region, reducing the accidental damage to the emitter in the second sub-region A2. The damage to the emitter is concentrated in the first sub-region A1, so as to reduce the ineffective passivation of the subsequent passivation layer or passivation and antireflection layer due to the damage of the emitter, which is beneficial to the passivation effect of the passivation layer or passivation and antireflection layer on the battery.

[0125] Since the polished surface in the first region A will improve the passivation ability of the battery, but will reduce the bifaciality of the battery (the bifaciality refers to the ratio of the maximum power output on the back to the maximum power output on the front). Therefore, by setting the first sub-region A1 as the matte surface to improve the bifaciality of the battery and match the LECO technology, and setting the second sub-region A2 as the polished surface to improve the passivation ability of the battery, the passivation ability and the bifaciality of the battery can be better balanced and considered, thereby improving the efficiency of the battery in converting light energy into electrical energy.

[0126] In addition, the process flow of this battery is simple and there is no other complex process. The original equipment can be used, such as the original equipment in the TOPCon workshop, which can be adapted to the layout of the TOPCon workshop and is easy to promote.

[0127] To better demonstrate the preparation method and its performance advantages of the embodiments of the present disclosure, two specific embodiments are given below for illustration.

[0128] (1) Example 1: The N-type silicon substrate 1 with a resistivity of 20 Ω·cm and a thickness of 150 μm is polished. Subsequently, the silicon substrate 1 is placed in a quartz boat, and oxygen is introduced to form a silicon oxide mask layer with a thickness of about 10 nm. Subsequently, the surface mask layer of the first sub-region A1 is removed using a 10W green picosecond laser, and texturing treatment is performed to form a textured surface on the first sub-region A1. Subsequently, the mask layer on the surface of the silicon substrate 1 is removed using an HF solution with a mass concentration of 5%. At this time, the part preset as the P region (corresponding to the first region A) is a polished surface / textured surface composite structure, and the two sides of the first sub-region A1 are the second sub-regions A2 (polished surfaces). The polished part is the non-metal contact area, and the textured surface part is the metal contact area. There is a height difference of 2 μm between the textured surface and the polished surface in the thickness direction of the silicon substrate 1, and the textured surface and the polished surface are connected by a bevel with a length of 3 μm, forming a structure as shown in Figure 1 the figure. In the preset direction where the first sub-region A1 and the second sub-region A2 are arranged side by side, the width of the first sub-region A1 accounts for 10% of the total width of the first region (P region). Subsequently, the silicon substrate 1 is loaded into a quartz boat for low-pressure chemical vapor deposition (fully named "Low Pressure Chemical Vapor Deposition", abbreviated as LPCVD), and a boron source is introduced to complete the boron diffusion process. At this time, a P + emitter and BSG are formed on the silicon wafer surface; the BSG reserved for the N region (corresponding to the second region B) and the spacer region on the back is etched off using a 45W green laser.

[0129] Immediately afterwards, it is placed in a 10% concentration HF solution using a single-sided etching process to remove the first protective layer 6 (BSG) on the front surface of the silicon substrate 1. Subsequently, a polishing process is performed in a KOH alkaline solution, and polished surfaces are formed on both the second region B (N region) and the spacer region C. The P region is not affected due to the protection of the BSG (see Figure 2 ).

[0130] Immediately afterwards, the dried silicon substrate 1 is placed in a quartz boat for low-pressure vapor deposition. Under low pressure, it is heated to 600 °C, and 2000 sccm of oxygen is introduced to grow a tunneling layer 7 (SiO2 layer) with a thickness of about 1.5 nm on the surface of the second region B (N region) on the back of the silicon substrate 1. Subsequently, silane is introduced to grow an intrinsic polysilicon (i-Poly Si) with a thickness of 250 nm on the surface of the tunneling layer 7 away from the silicon substrate 1. Subsequently, the temperature is raised and a phosphorus source is introduced to complete the phosphorus diffusion process. At this time, the second region B (N region) and the spacer region C are a stacked structure of the tunneling layer 7, the doped polysilicon layer 8, and the second protective layer 9 (SiO2 / N +Poly Si / PSG), the first region A (P region) is a stacked structure of an emitter, a first protective layer 6, a doped polysilicon layer 8, and a second protective layer 9 (P + / BSG / N + Poly Si / PSG) (see Figure 3 ).

[0131] Subsequently, the second protective layer 9 (PSG) on the surface of the spacer region C and the first region A (P region) was etched away with a 30W green laser, and then the PSG on the front surface of the silicon substrate 1 was etched away with a 5% HF etching solution.

[0132] Subsequently, a texturing process was carried out to make the spacer region C on the back surface and the front surface 10 of the silicon substrate 1 into a textured structure. Immediately afterwards, the second protective layer 9 (PSG) on the surface of the second region B (N region) and the first protective layer 6 (BSG) on the surface of the first region A (P region) were removed (see Figure 4 ).

[0133] Subsequently, Al2O3 was coated on the front surface of the silicon substrate 1. At 250 °C, trimethylaluminum and water were introduced, and a 6nm thick Al2O3 layer was grown on both the front and back surfaces. Immediately afterwards, in a plasma-enhanced chemical vapor deposition equipment, silane and ammonia were introduced at 540 °C to complete the deposition of SiN x thin films on both the front and back surfaces, with a thickness of 75nm each. Subsequently, silver paste was printed on the first sub-region A1 on the back surface and the second region B of the silicon substrate 1 by screen printing, sintered at high temperature, and combined with the LECO technology to complete metallization. Finally, after light injection treatment, a back-contact battery was obtained (see Figure 5 ).

[0134] Comparative example: An N-type silicon substrate with a resistivity of 20 Ω·cm and a thickness of 150 μm was textured. Subsequently, the silicon substrate was loaded into an LPCVD quartz boat, and a boron source was introduced to complete the boron diffusion process. At this time, a P + emitter and BSG were formed on the surface of the silicon substrate; the BSG reserved for the N region and the spacer region on the back surface was etched away with a 45W green laser. Immediately afterwards, a polishing process was carried out in a KOH alkaline solution, and polished surfaces were formed in both the N region and the spacer region, while the P region was not affected due to the protection of BSG.

[0135] Immediately afterwards, the dried silicon substrate was placed in a quartz boat, heated to 600 °C under low pressure, and 2000 sccm of oxygen was introduced to grow a tunneling layer (SiO2 layer) with a thickness of about 1.5nm on the N region on the back surface of the silicon substrate. Subsequently, silane was introduced to grow an intrinsic polysilicon (i-Poly Si) layer with a thickness of 250nm on the surface of the tunneling layer away from the silicon substrate. Subsequently, the temperature was raised and a phosphorus source was introduced to complete the phosphorus diffusion process. At this time, the N region is a stacked structure of a tunneling layer, a doped polysilicon layer, and a second protective layer (SiO2 / N+ Poly Si / PSG), the P region is P + Emitter, first protective layer, doped polysilicon layer and second protective layer superposition structure (P + / BSG / N + Poly Si / PSG). Subsequently, the PSG on the P region and the PSG on the spacer are etched away with a 30W green laser, and the PSG on the front is etched away with a 5% mass concentration HF etching solution. Subsequently, the texturing process is carried out to remove the doped polysilicon layer (N + Poly Si) on the P region, and the front and back spacers are made into a textured surface, and the PSG in the N region and the first protective layer (BSG) on the surface of the P region are removed with 10% mass concentration HF. Subsequently, Al2O3 is coated on the front of the silicon substrate. At 250 °C, trimethylaluminum and water are introduced, and a 6nm thick Al2O3 layer is grown on the front and back. Immediately afterwards, in a plasma-enhanced chemical vapor deposition equipment, silane and ammonia are introduced at 540 °C to complete the deposition of SiN x films on both the front and back, with a thickness of 75nm each. Subsequently, silver paste is printed on the P region and N region on the back of the silicon substrate by screen printing, sintered at high temperature, and combined with LECO technology to complete metallization. Finally, after light injection treatment, a back-contact battery is obtained.

[0136] The performance of the solar cells prepared by using the above-mentioned Example 1 and the comparative example was tested, and the test results are shown in Table 1 below: Table 1 Performance test results of Example 1 and the comparative example EFF(%) Voc(mV) Isc(A) FF(%) Example 1 26.53 741.3 14.52 81.65 Comparative example 24.79 725.2 14.45 78.35 Among them, EFF is the photoelectric conversion efficiency, that is, the percentage of the efficiency of converting sunlight into electric energy; Voc is the open-circuit voltage, which is the voltage across the solar cell when no load is connected; Isc is the short-circuit current, which is the current flowing through when the positive and negative electrodes of the battery are directly short-circuited; FF is the fill factor, which measures the efficiency of the solar cell at the maximum power point, that is, the ratio of the actual output power to the theoretical maximum power (Voc multiplied by Isc). A high fill factor means that the battery can convert light energy into electric energy more effectively and reduce internal losses.

[0137] The comparative example uses a full-textured surface laser etching scheme for the P region. Using a laser has a great impact on the textured P + emitter and damages the textured surface of the P region. Although a passivation film is coated before metallization, it is difficult for the passivation layer or the passivation and antireflection layer to make up for the damage caused to the P + emitter. Therefore, the overall passivation level is very poor, and while the recombination increases, it also causes losses in current and fill factor. As can be seen from Table 1, the above four performance indicators of the solar cell of Example 1 of the present disclosure are all better than those of the comparative example.

[0138] (2)Example 2: The N-type silicon substrate 1 with a resistivity of 20 Ω·cm and a thickness of 150 μm was polished. Subsequently, the silicon substrate 1 was placed in a quartz boat, and oxygen was introduced to form a silicon oxide mask layer with a thickness of about 10 nm. Subsequently, the surface mask layer of the first sub-region A1 was removed by a 10-W green picosecond laser, and texturing treatment was carried out to make the first sub-region A1 form a textured surface. In the preset direction where the first sub-region A1 and the second sub-region A2 are arranged side by side, the distance between the edge of the first sub-region A1 and the reserved spacer region C is 100 μm. Subsequently, the mask layer on the surface of the silicon substrate 1 was removed with a HF solution with a mass concentration of 5%. At this time, the part preset as the P region (corresponding to the first region A) is a polished surface / textured surface composite structure. The second sub-region A2 is located on one side of the first sub-region A1. The polished part is the non-metal contact area, and the textured part is the metal contact area. Subsequently, the silicon substrate 1 was loaded into an LPCVD quartz boat, and a boron source was introduced to complete the boron diffusion process. At this time, a P + emitter BSG was formed on the silicon wafer surface; the BSG reserved for the N region (corresponding to the second region B) and the spacer region on the back was etched off with a 45-W green laser.

[0139] Immediately afterwards, the front BSG of the silicon substrate 1 was removed in a HF solution with a mass concentration of 10%. Subsequently, a polishing process was carried out in a KOH alkaline solution. A polished surface was formed in both the second region B (N region) and the spacer region C. The first region A (P region) was not affected due to the protection of the first protective layer 6 (BSG).

[0140] Immediately afterwards, the dried silicon substrate 1 was placed in a quartz boat. Under low pressure, it was heated to 600 °C, and 2000 sccm of oxygen was introduced. A tunneling layer 7 (SiO2 layer) with a thickness of about 1.5 nm was grown on the back surface of the second region B (N region) of the silicon substrate 1. Subsequently, silane was introduced, and an intrinsic polysilicon (i-Poly Si) with a thickness of 250 nm was grown on the surface of the tunneling layer 7 away from the silicon substrate 1. Subsequently, the temperature was raised and a phosphorus source was introduced to complete the phosphorus diffusion process. At this time, the second region B (N region) and the spacer region C are a stacked structure of the tunneling layer 7, the doped polysilicon layer 8, and the second protective layer 9 (SiO2 / N + Poly Si / PSG), and the first region A (P region) is a stacked structure of the emitter, the first protective layer 6, the doped polysilicon layer 8, and the second protective layer 9 (P + / BSG / N + Poly Si / PSG). Subsequently, the second protective layer 9 (PSG) on the surface of the spacer region C and the first region A (P region) was etched off with a 30-W green laser. Subsequently, the second protective layer 9 (PSG) on the front surface of the silicon substrate 1 was etched off with a HF etching solution with a mass concentration of 5%.

[0141] Subsequently, the texturing process is carried out so that the spacer region C on the back side of the silicon substrate 1 and the front side 10 become a textured structure. Immediately afterwards, the second protective layer 9 (PSG) on the surface of the second region B (N region) and the first protective layer 6 (BSG) on the surface of the first region A (P region) are removed. Subsequently, Al2O3 coating is performed on the front side of the silicon substrate 1. At 250 °C, trimethylaluminum and water are introduced, and a 6-nm-thick Al2O3 layer is grown on both the front and back sides. Immediately afterwards, in a plasma-enhanced chemical vapor deposition apparatus, silane and ammonia are introduced at 540 °C to complete the deposition of SiN x thin films on both the front and back sides, each with a thickness of 75 nm. Subsequently, silver paste is printed on the first sub-region A1 on the back side and the second region B of the silicon substrate 1 by screen printing, sintered at high temperature, and combined with the LECO technology to complete metallization. Finally, after light injection treatment, a back-contact battery is obtained (see Figure 6 ). Among them, the difference between Example 2 and Example 1 is that the distance between the textured edge of the P region and the spacer region C is designed to be 100 μm, and one side of the textured surface of the P region extends to the edge of the P region, and a polished surface is provided only on one side of the first sub-region A1.

[0142] Performance tests were carried out on the solar cells prepared by using the above Example 2 and the comparative example, and the test results are shown in Table 2 below: Table 2 Performance test results of Example 2 and the comparative example EFF(%) Voc(mV) Isc(A) FF(%) Example 2 26.49 741.5 14.51 81.55 Comparative example 24.79 725.2 14.45 78.35 The comparative example is a scheme of using laser etching for the full-textured surface in the P region. The laser has a greater impact on the emitter in the textured region and damages the textured surface of the P region. Although a passivation film is coated before metallization, the passivation layer is difficult to make up for the damage to the P + emitter. Therefore, the overall passivation level is very poor, and while recombination increases, it also causes losses in current and fill factor. As can be seen from Table 2, the above four performance indicators of the solar cell of Example 2 of the present disclosure are all superior to those of the comparative example.

[0143] In summary, the back-contact battery provided by the present disclosure can effectively improve electrical properties such as photoelectric conversion efficiency, open-circuit voltage, short-circuit current, and fill factor through the cooperation of the textured surface and the polished surface in the first region.

[0144] Although the present disclosure has been described with reference to the preferred embodiments, various improvements can be made to it and components therein can be replaced with equivalents without departing from the scope of the present disclosure. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The present disclosure is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A back-contact battery, characterized in that, Comprising: A silicon substrate (1) having a first region (A), a second region (B) and a spacer region (C) on the back surface, the adjacent first region (A) and the second region (B) being separated by the spacer region (C), the first region (A) including adjacent first sub-region (A1) and second sub-region (A2), the first sub-region (A1) being a textured surface and the second sub-region (A2) being a polished surface; An emitter having a first conductivity type, provided on the back surface of the silicon substrate (1), and the emitter including a first emitter portion (3) located in the first sub-region (A1) and a second emitter portion (5) located in the second sub-region (A2); A carrier collection layer having a second conductivity type opposite to the first conductivity type, provided on the back surface of the silicon substrate (1) and located in the second region (B); And A first electrode (12) in ohmic contact with the first emitter portion (3).

2. The back-contact battery according to claim 1, wherein The first sub-region (A1) and the second sub-region (A2) are arranged side by side in a preset direction, wherein the preset direction is perpendicular to the thickness direction of the silicon substrate (1).

3. The back contact battery according to claim 2, wherein The second sub-regions (A2) are provided on both sides of the first sub-region (A1) along the preset direction; or The first sub-region (A1) is located on one side of the second sub-region (A2) along the preset direction.

4. The back contact battery according to claim 2, characterized in that, In the preset direction, the width of the first sub-region (A1) accounts for 5%-90% of the width of the first region (A).

5. The back contact battery according to claim 2, characterized in that, In the preset direction, the width of the polished surface between the first sub-region (A1) and the edge of the first region (A) where it is located is 0.1-300 μm.

6. The back-contact battery according to claim 1, characterized in that, The area ratio of the first sub-region (A1) to the area of the first region (A) is 4%-88%.

7. The back-contact battery according to claim 1, wherein, There is a first distance between the back surface of the silicon substrate (1) between the first sub-region (A1) and the front surface (10), and a second distance between the back surface of the silicon substrate (1) between the second sub-region (A2) and the front surface (10), and the first distance is less than the second distance.

8. The back-contact battery according to claim 7, characterized in that, The height difference between the first distance and the second distance is 0.5-5 μm.

9. The back-contact battery according to claim 1, characterized in that, In the first region (A), the textured surface and the polished surface are connected by an inclined surface, and the side length of the inclined surface in the cross-section is 0.8-8 μm.

10. The back-contact battery according to claim 1, characterized in that, The doping concentration of the second emitter portion (5) in the second sub-region (A2) is 1×10 18 -1×10 19 atoms / cm 3 , the junction depth is 0.2 - 1.5 μm, and the doping concentration of the first emitter portion (3) in the first sub-region (A1) is 2×10 18 -3×10 19 atoms / cm 3 , and the junction depth is 0.5 - 2 μm.

11. The back contact battery according to claim 1, characterized in that, The silicon substrate (1) is an N-type silicon wafer with a resistivity of 0.1-100 Ω·cm and a thickness of 100-500 μm.

12. The back-contact battery according to any one of claims 1 to 11, characterized in that, The carrier collection layer includes a tunneling layer (7) and a doped polysilicon layer (8), the tunneling layer (7) is provided on the back surface of the silicon substrate (1) and located in the second region (B), the doped polysilicon layer (8) is provided on the side of the tunneling layer (7) away from the silicon substrate (1), and the doped polysilicon layer (8) has a second conductivity type opposite to the first conductivity type; The back contact battery further includes: A second electrode (13) in ohmic contact with the doped polysilicon layer (8).

13. The back-contact battery according to claim 12, characterized in that, The emitter is of P type, the doped polysilicon layer (8) is of N type, the back surface of the silicon substrate (1) has a first distance between the first sub-region (A1) and the front surface (10), the back surface of the silicon substrate (1) has a second distance between the second sub-region (A2) and the front surface (10), and the back surface of the silicon substrate (1) has a third distance between the second region (B) and the front surface (10); wherein, the absolute value of the difference between the first distance and the third distance does not exceed a preset distance, and the second distance is greater than the third distance.

14. The back-contact battery according to claim 13, characterized in that, The absolute value of the difference between the first distance and the third distance does not exceed 2 μm, and the height difference between the second distance and the third distance is 0.5 - 5 μm.

15. The back-contact battery according to claim 13, characterized in that, The first distance is less than the third distance.

16. The back contact battery according to claim 13, characterized in that, The area of the first region (A) accounts for 30% - 50% of the total area of the back surface of the silicon substrate (1), and the area of the second region (B) accounts for 40% - 60% of the total area of the back surface of the silicon substrate (1).

17. The back-contact battery according to claim 13, characterized in that, The thickness range of the tunneling layer (7) is 0.5 - 2.5 nm, the thickness range of the doped polysilicon layer (8) is 100 - 300 nm, and the doping concentration of the doped polysilicon layer (8) is 3×10 20 - 1×10 21 atoms / cm 3 .

18. The back contact battery according to claim 12, characterized in that, The first electrode (12) is configured to be formed by printing Ag paste on the back surface of the first sub-region (A1), and the second electrode (13) is configured to be formed by printing Ag paste on the second region (B).

19. The back contact battery according to claim 1, characterized in that, The back surface of the silicon substrate (1) is a matte surface or a polished surface in the spacer region (C); and / or, the second region (B) is a polished surface; and / or, the back contact battery further includes a passivation layer or a passivation and antireflection layer provided on the front surface and / or the back surface of the silicon substrate (1).

20. A photovoltaic module, characterized in that, Comprising the back contact battery according to any one of claims 1 to 19.

21. A method for preparing a back-contact battery, characterized in that, Comprising: S1. Form a mask layer on the surface of the silicon substrate (1). The back surface of the silicon substrate (1) includes a first region (A), a second region (B), and a spacer region (C). The adjacent first region (A) and the second region (B) are separated by the spacer region (C). The first region (A) includes an adjacent first sub-region (A1) and a second sub-region (A2), and the first region (A) is a polished surface; S2. Use a laser to remove the mask layer located on the first sub-region (A1) of the back surface of the silicon substrate (1), and perform texturing treatment on the first sub-region (A1) to make it form a matte surface; S3. Remove the remaining mask layer on the surface of the silicon substrate (1), and the second sub-region (A2) is a polished surface; S4. Perform a first doping treatment on the silicon substrate (1) to form an emitter with a first conductivity type in the first region (A), and the emitter in the first region (A) includes a first emitter portion (3) located in the first sub-region (A1) and a second emitter portion (5) located in the second sub-region (A2); S5. Perform a second doping treatment on the silicon substrate (1) to form a carrier collection layer with a conductivity type opposite to the first conductivity type in the second region (B); S6. Form a first electrode (12) in ohmic contact with the first emitter portion (3) on the first emitter portion (3).

22. The preparation method according to claim 21, wherein, The specific content of S4 includes: S41. Integrally form an emitter and a first protective layer (6) on the surface of the silicon substrate (1); S42. Remove the emitter and the first protective layer (6) on the front surface (10), the second region (B) on the back surface, and the spacer region (C) of the silicon substrate (1).

23. The preparation method according to claim 22, wherein, The S5 specifically includes: S51. Sequentially grow a tunneling layer (7) and an intrinsic polysilicon on the surface of the silicon substrate (1), and perform a second doping process to integrally form a tunneling layer (7), a doped polysilicon layer (8), and a second protective layer (9) on the surface of the silicon substrate (1). The doped polysilicon layer (8) has a second conductivity type opposite to the first conductivity type; S52. Remove the second protective layer (9) on the front surface (10) of the silicon substrate (1) and on the first region (A) and the spacer region (C) on the back surface; S53. Remove the first protective layer (6) on the first region (A) and the second protective layer (9) on the second region (B) on the back surface of the silicon substrate (1).

24. The preparation method according to claim 23, characterized in that, Between the S52 and the S53, the preparation method further includes: forming a textured surface on the front surface (10) and the back surface of the silicon substrate (1) in the spacer region (C); And / or, the S52 includes: the second protective layers (9) in the first region (A) and the spacer region (C) are removed simultaneously by the same laser beam. The laser parameters include: the laser radiation power is 1 - 50 W, and / or the laser wavelength of the laser is 350 - 1070 nm.

25. The preparation method according to claim 21, characterized in that, After the S5, the preparation method further includes: depositing a passivation layer or a passivation and antireflection layer (11) on the front surface (10) and the back surface of the silicon substrate (1); And / or, in the mask layer formation step, the thickness of the mask layer is 1 - 100 nm, and the material of the mask layer includes SiO2 or SiNx.

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