Back contact cell and preparation method thereof, photovoltaic module

Abstract

The embodiment of the present disclosure provides a back contact cell and a preparation method thereof, and a photovoltaic module, wherein the back contact cell comprises: a silicon substrate (1), the back side of which has a first region (A), a second region (B) and a spacer region (C), the adjacent first region (A) and the second region (B) being separated by the spacer region (C), the first region (A) comprising a first sub-region (A1) being a velvet surface and a second sub-region (A2) being a polished surface; an emitter having a first conductivity type, arranged on the back side of the silicon substrate (1), and comprising a first emitter portion (3) located in the first sub-region (A1) and a second emitter portion (5) located in the second sub-region (A2); a carrier collection layer having a second conductivity type opposite to the first conductivity type, arranged on the back side of the silicon substrate (1) and located in the second region (B); and a first electrode (12) in ohmic contact with the first emitter portion (3). The back contact cell has excellent electrical properties.

Description

Technical Field

[0001] The present disclosure relates to the field of photovoltaic technology, and in particular to a back-contact cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] As one of the high-efficiency battery technologies, the back-contact battery (full name "Interdigitated Back Contact", abbreviated as IBC) has the following characteristics: 1. There is no grid line blocking the front, which can improve the utilization rate of incident light by 0.3%-0.4%, which is conducive to the increase of current; 2. The front side can be designed with an optimal passivation structure to maximize the front passivation capability; 3. As a platform technology, it has a high structural compatibility with high-efficiency passivation technologies such as tunnel oxide passivation contact (full name "Tunnel Oxide Passivated Contact", abbreviated as TOPCon) and intrinsic thin-layer heterojunction (full name "Heterojunction Technology", abbreviated as HJT), and has a higher theoretical efficiency limit.

[0003] Thanks to these advantages, IBC has experienced rapid development in recent years, particularly in tunnel back contact (TBC) cell technology, which combines TOPCon and IBC technologies. TOPCon cell technology, a type of high-efficiency crystalline silicon cell, derives its superior passivation from its ultra-thin tunnel oxide / doped polysilicon layer structure, allowing majority carriers to pass while isolating minority carriers, thereby achieving low recombination. TBC cells offer advantages in terms of manufacturing difficulty and cost, and are therefore considered a more readily mass-produced high-efficiency back contact cell technology.

[0004] The prior art provides a back contact battery, the back of which includes a first area, a second area and a spacer area arranged therebetween, wherein the first area is provided with a P + The emitter and the second region are provided with an N-type carrier collection layer, and the first region is a full suede structure. The outermost layers of the first, second and spacer regions are also provided with a passivation anti-reflection layer. However, the electrical performance of this back-contact cell is poor. Summary of the Invention

[0005] The present disclosure provides a back-contact cell and a preparation method thereof, and a photovoltaic module, which can improve the electrical performance of the back-contact cell.

[0006] A first aspect of the present disclosure provides a back-contact battery, comprising:

[0007] A silicon substrate having a first region, a second region, and a spacer region on its back side, wherein adjacent first and second regions are separated by the spacer region, the first region includes adjacent first and second sub-regions, the first sub-region is a suede surface, and the second sub-region is a polished surface;

[0008] An emitter, having a first conductivity type, is disposed on the back side of the silicon substrate, and includes a first emitter portion located in the first sub-region and a second emitter portion located in the second sub-region;

[0009] a carrier collection layer having a second conductivity type opposite to the first conductivity type, disposed on the back side of the silicon substrate and located in the second region; and

[0010] The first electrode is in partial ohmic contact with the first emitter.

[0011] In some embodiments, the first sub-region and the second sub-region are arranged side by side along a preset direction, and the preset direction is perpendicular to the thickness direction of the silicon substrate.

[0012] In some embodiments, the second sub-region is provided on both sides of the first sub-region along the preset direction; or the first sub-region is located on one side of the second sub-region along the preset direction.

[0013] In some embodiments, in a preset direction, the width of the first sub-region accounts for 5%-90% of the width of the first region.

[0014] In some embodiments, in a preset direction, a width of the polished surface between the first sub-region and an edge of the first region in which the first sub-region is located is 0.1-300 μm.

[0015] In some embodiments, the area of ​​the first sub-region accounts for 4%-88% of the area of ​​the first region.

[0016] In some embodiments, the back side of the silicon substrate has a first distance between the first sub-region and the front side, and the back side of the silicon substrate has a second distance between the second sub-region and the front side, and the first distance is smaller than the second distance.

[0017] In some embodiments, the height difference between the first distance and the second distance is 0.5-5 μm.

[0018] In some embodiments, in the first region, the suede surface and the polished surface are connected by an inclined surface, and the length of the side of the inclined surface in the cross section is 0.8-8 μm.

[0019] In some embodiments, the doping concentration of the second emitter portion in the second sub-region is 1×10 18 -1×10 19 atoms / cm 3 The junction depth is 0.2-1.5 μm, and the doping concentration of the first emitter part in the first sub-region is 2×10 18 -3×10 19 atoms / cm 3 , the junction depth is 0.5-2μm.

[0020] In some embodiments, the silicon substrate is an N-type silicon wafer with a resistivity of 0.1-100 Ω.cm and a thickness of 100-500 μm.

[0021] In some embodiments, the carrier collection layer includes a tunneling layer and a doped polysilicon layer, the tunneling layer is disposed on the back side of the silicon substrate and located in the second region, the doped polysilicon layer is disposed on a side of the tunneling layer away from the silicon substrate, and the doped polysilicon layer has a second conductivity type opposite to the first conductivity type;

[0022] The back contact cell further includes a second electrode in ohmic contact with the doped polysilicon layer.

[0023] In some embodiments, the emitter is P-type, the doped polysilicon layer is N-type, the back side of the silicon substrate has a first distance between the first sub-region and the front side, the back side of the silicon substrate has a second distance between the second sub-region and the front side, and the back side of the silicon substrate has a third distance between the second region and the front side; wherein the absolute value of the difference between the first distance and the third distance does not exceed the preset distance, and the second distance is greater than the third distance.

[0024] In some embodiments, the absolute value of the difference between the first distance and the third distance does not exceed 2 μm, and the height difference between the second distance and the third distance is 0.5-5 μm.

[0025] In some embodiments, the first distance is less than the third distance.

[0026] In some embodiments, the area of ​​the first region accounts for 30%-50% of the total area of ​​the back side of the silicon substrate, and the area of ​​the second region accounts for 40%-60% of the total area of ​​the back side of the silicon substrate.

[0027] In some embodiments, the thickness of the tunneling layer is in the range of 0.5-2.5 nm, the thickness of the doped polysilicon layer is in the range of 100-300 nm, and the doping concentration of the doped polysilicon layer is 3×10 20 -1×10 21 atoms / cm 3 .

[0028] In some embodiments, the first electrode is formed by printing with Ag paste on the back side of the first sub-region, and the second electrode is formed by printing with Ag paste on the second region.

[0029] In some embodiments, the back surface of the silicon substrate is a suede surface or a polished surface in the spacer area;

[0030] and / or, the second area is a polished surface;

[0031] And / or, the back contact cell further includes a passivation layer or a passivation anti-reflection layer provided on the front and / or back side of the silicon substrate.

[0032] A second aspect of the present disclosure provides a photovoltaic module comprising the back-contact cell of the above embodiment.

[0033] A third aspect of the present disclosure provides a method for preparing a back-contact battery, comprising:

[0034] S1. Forming a mask layer on a surface of a silicon substrate, wherein the back surface of the silicon substrate includes a first region, a second region, and a spacer region, adjacent first and second regions are separated by the spacer region, the first region includes adjacent first and second sub-regions, and the first region is a polished surface;

[0035] S2, using laser to remove the mask layer of the first sub-region on the back side of the silicon substrate, and performing a texturing process on the first sub-region to form a textured surface;

[0036] S3, removing the remaining mask layer on the surface of the silicon substrate, and the second sub-area becomes a polished surface;

[0037] S4, performing a first doping treatment on the silicon substrate, so that the first region forms an emitter having a first conductivity type, and the emitter of the first region includes a first emitter portion located in the first sub-region and a second emitter portion located in the second sub-region;

[0038] S5, performing a second doping treatment on the silicon substrate so that the second region forms a carrier collection layer having a conductivity type opposite to that of the first region;

[0039] S6. Form a first electrode in ohmic contact with the first emitter portion.

[0040] In some embodiments, S4 specifically includes:

[0041] S41, forming an emitter and a first protective layer on the entire surface of the silicon substrate;

[0042] S42, removing the emitter and the first protective layer in the second region and the spacer region on the front and back sides of the silicon substrate.

[0043] In some embodiments, S5 specifically includes:

[0044] S51, sequentially growing a tunneling layer and intrinsic polysilicon on the surface of the silicon substrate, and performing a second doping treatment, so that the entire surface of the silicon substrate forms a tunneling layer, a doped polysilicon layer, and a second protective layer, wherein the doped polysilicon layer has a second conductivity type opposite to the first conductivity type;

[0045] S52, removing the second protective layer in the first area and the spacer area from the front and back sides of the silicon substrate;

[0046] S53 , removing the first protective layer in the first area and the second protective layer in the second area on the back side of the silicon substrate.

[0047] In some embodiments, between S52 and S53, the preparation method further includes: forming a suede surface on the front and back sides of the silicon substrate in the spacer area;

[0048] And / or, S52 includes: the second protective layer in the first area and the spacer area is removed simultaneously by the same laser, and the laser parameters include: the laser radiation power is 1-50W, and / or the laser wavelength is 350-1070nm.

[0049] In some embodiments, after S5, the preparation method further includes: depositing a passivation layer or a passivation anti-reflection layer on the front surface and the back surface of the silicon substrate;

[0050] And / or, in the mask layer forming step, the thickness of the mask layer is 1-100 nm, and the material of the mask layer includes SiO2 or SiNx.

[0051] In the back-contact battery of the disclosed embodiment, the first region where the emitter is located is configured as a composite structure of a velvet surface and a polished surface, and the velvet surface is configured only in the region in contact with the first electrode, ensuring high compatibility with LECO technology to achieve high contact performance. It is capable of forming an ohmic contact at the interface between the first metal electrode and the velvet silicon, thereby reducing contact resistance. Moreover, because only a small area of ​​the emitter is velvet, and the majority is polished, when the second laser treatment is used, the effect of the laser on the emitter can be concentrated in the velvet region, with minimal damage to the polished surface of the second sub-region, and damage to the emitter concentrated in the first sub-region, thereby reducing the impact of emitter damage on the passivation effect of the subsequent passivation layer and improving the passivation effect of the battery.

[0052] Since the polished surface in the first area A improves the passivation ability of the cell but reduces the bifaciality of the cell, the first sub-area is set to a velvet surface to improve the bifaciality of the cell and match the LECO technology, and the second sub-area is set to a polished surface to improve the passivation ability of the cell. This can better balance and take into account the passivation ability and the bifaciality of the cell, thereby improving the efficiency of the cell in converting light energy into electrical energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0054] Figure 1 A schematic diagram of a structure in which a textured surface is provided in a first sub-region on the back side of a silicon substrate according to an embodiment of the present disclosure.

[0055] Figure 2A schematic structural diagram of forming an emitter and a first protective layer in a first region of a silicon substrate according to an embodiment of the present disclosure.

[0056] Figure 3 A schematic diagram of the structure of forming a tunneling layer, a doped polysilicon layer and a second protective layer on the surface of a silicon substrate provided in one embodiment of the present disclosure.

[0057] Figure 4 A schematic structural diagram of removing the second protective layer in the first area and the spacer area on the back side of the silicon substrate provided in one embodiment of the present disclosure.

[0058] Figure 5 A schematic structural diagram of a back-contact battery provided in one embodiment of the present disclosure.

[0059] Figure 6 A schematic structural diagram of a back-contact battery provided in yet another embodiment of the present disclosure.

[0060] Figure 7 A schematic structural diagram of providing a textured surface in a first sub-region on the back side of a silicon substrate according to another embodiment of the present disclosure.

[0061] Figure 8 A schematic structural diagram of forming an emitter and a first protective layer on the surface of a silicon substrate according to another embodiment of the present disclosure.

[0062] Figure 9 A schematic structural diagram of forming a tunneling layer, a doped polysilicon layer and a second protective layer on the surface of a silicon substrate is provided in another embodiment of the present disclosure.

[0063] Figure 10 A schematic structural diagram of removing the second protective layer in the first area and the spacer area on the back side of the silicon substrate according to another embodiment of the present disclosure.

[0064] Figure 11 A schematic structural diagram of a back-contact battery provided in yet another embodiment of the present disclosure.

[0065] Figure 12 A schematic flow chart of a method for preparing a back-contact battery according to an embodiment of the present disclosure.

[0066] Figure 13 This is a schematic diagram of the process of performing a first doping treatment on a silicon substrate according to an embodiment of the present disclosure.

[0067] Figure 14 This is a schematic diagram of the process of performing a second doping treatment on a silicon substrate according to an embodiment of the present disclosure.

[0068] Description of reference numerals:

[0069] 1. Silicon substrate; A. First region; A1. First sub-region; A2. Second sub-region; B. Second region; C. Spacer region; 2. Preset texturing area; 3. First emitter portion; 4. Recessed portion; 5. Second emitter portion; 6. First protective layer; 7. Tunneling layer; 8. Doped polysilicon layer; 9. Second protective layer; 10. Front side; 11. Passivation anti-reflection layer; 12. First electrode; 13. Second electrode. DETAILED DESCRIPTION

[0070] The following detailed description of the embodiments of the present disclosure is provided in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present disclosure, but are not intended to limit the scope of the present disclosure, that is, the present disclosure is not limited to the described embodiments.

[0071] The inventors found through research that when preparing back contact cells and using laser enhanced contact optimization technology (full name is "Laser-enhanced Contact Optimization", referred to as LECO technology), and P + When the surface of the silicon substrate where the emitter is located is a velvet structure, compared with the polished surface, P + The tip of the emitter's textured structure facilitates a higher density of silver-silicon contact sites (i.e., silver-silicon alloy), forming a good ohmic contact. LECO technology involves screen-printing metal electrodes and then irradiating the silicon wafer surface with a high-intensity laser to excite charge carriers and apply a deflection voltage. This generates a localized current that promotes interdiffusion between the metal (e.g., silver paste) and silicon, thereby reducing contact resistivity.

[0072] At present, the back side of the back contact battery includes a first area, a second area and a spacer area between the first area and the second area. + The emitter, the second region is provided with an N-type carrier collection layer, and the first region is a full suede structure. The outermost layers of the first region, the second region and the spacer region are also provided with a passivation layer or a passivation anti-reflection layer. The preparation of the back contact cell includes two laser processes. Specifically, boron diffusion is performed on the surface of the silicon substrate to form a P + Emitter and borosilicate glass layer, the first laser treatment is used to remove the borosilicate glass layer in the second area and the spacer area on the back of the silicon substrate. Phosphorus diffusion is performed on the back of the silicon substrate to form a phosphorus-doped carrier collection layer and a phosphorus-silicate glass layer. The second laser treatment is used to remove the phosphorus-silicate glass layer in the first area and the spacer area on the back. However, due to the high penetration of the laser, when removing the phosphorus-silicate glass layer on the surface of the first area, the laser has a negative impact on the textured P + The emitter has a greater impact on the texture of the first area. Although the electrode will be formed before the P + The emitter surface is plated with a passivation layer or a passivation anti-reflection layer, but it is difficult to make up for the P +The damage caused by the emitter is not conducive to improving the passivation effect of the battery. This structure and corresponding process are not conducive to the preparation of high-performance back-contact batteries.

[0073] Therefore, if the performance of back-contact cells is to be improved, it is necessary to reduce the impact of the laser on the first zone to prevent it from affecting the final passivation effect of the cell. Reasonable design of the emitter structure and preparation process is crucial to the formation of high-performance back-contact cells.

[0074] Based on the above ideas, the present disclosure provides a back contact battery, hereinafter referred to as "battery", such as Figures 1 to 11 As shown, in some embodiments, the back contact cell includes:

[0075] A silicon substrate 1 has a first region A, a second region B, and a spacer region C on its back side. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes a first sub-region A1 and a second sub-region A2 adjacent to each other. The first sub-region A1 is a suede surface, and the second sub-region A2 is a polished surface.

[0076] The emitter, having the first conductivity type, is disposed on the back side of the silicon substrate 1 and located in the first area A. The emitter includes a first emitter portion 3 located in the first sub-area A1 and a second emitter portion 5 located in the second sub-area A2. Since the first sub-area A1 is a suede surface and the second sub-area A2 is a polished surface, the first emitter portion 3 also has a suede surface structure, and the second emitter portion 5 also has a polished surface structure.

[0077] a carrier collection layer having a second conductivity type opposite to the first conductivity type, provided on the back side of the silicon substrate 1 and located in the second region B; and

[0078] The first electrode 12 is in ohmic contact with the first emitter portion 3 .

[0079] For example, the silicon substrate 1 may be an N-type silicon wafer, such as a phosphorus-doped single-crystal silicon wafer, with a resistivity of 0.1-100 Ω.cm, such as 0.1 Ω.cm, 10 Ω.cm, 20 Ω.cm, 30 Ω.cm, 40 Ω.cm, 50 Ω.cm, 60 Ω.cm, 70 Ω.cm, 80 Ω.cm, 90 Ω.cm, or 100 Ω.cm. Optionally, the front surface 10 of the silicon substrate 1 has a suede structure to reduce light reflection and increase light absorption, thereby improving the efficiency of the battery.

[0080] The first region A, the second region B, and the spacer C are not physical components, but rather are regions demarcated within the extended plane of the silicon substrate 1. The spacer C is a gap. At least one first region A and at least one second region B may be provided. If multiple first regions A and multiple second regions B are provided, the multiple first regions A and multiple second regions B may be alternately arranged, for example, along a predetermined direction. The predetermined direction may be the length or width of the silicon substrate 1.

[0081] An emitter is provided on the back of the silicon substrate 1 in the first region A. The emitter has a first conductivity type, for example, a P type, which can be formed by boron doping. + emitter.

[0082] For example, the doping concentration of the emitter in the second sub-region A2 (ie, the second emitter portion 5) is 1×10 18 -1×10 19 atoms / cm 3 , the junction depth is 0.2-1.5 μm, and the emitter doping concentration in the first sub-region A1 (first emitter part 3) is 2×10 18 -3×10 19 atoms / cm 3 , with a junction depth of 0.5-2μm. Because the first sub-region A1 has a suede surface and the second sub-region A2 has a polished surface, their specific surface areas differ, with the suede surface having a larger surface area. Therefore, under the same diffusion process, the doping concentration in the first sub-region A1 is higher than that in the second sub-region A2. Furthermore, this doping concentration can reduce the contact resistance between the first sub-region A1 and the first electrode.

[0083] See also Figure 5 、 Figure 6 or Figure 11 The carrier collection layer provided on the back of the silicon substrate 1 in the second region B includes a tunneling layer 7 and a doped polysilicon layer 8. The tunneling layer 7 is provided on the back of the silicon substrate 1 and is located in the second region B. The doped polysilicon layer 8 is provided on the side of the tunneling layer 7 away from the silicon substrate 1. The doped polysilicon layer 8 has a second conductivity type opposite to the first conductivity type. The tunneling layer 7 is an ultra-thin dielectric layer that allows electrons to pass through efficiently through the quantum tunneling effect while blocking the recombination loss of other charges (such as holes). Silicon oxide (SiO2) and silicon nitride (SiN x ) or aluminum oxide (Al2O3), etc.

[0084] The doped polysilicon layer 8 may be an N-type doped polysilicon layer, for example, + Poly Si, that is, the back of the silicon substrate 1 is provided with SiO2 / N +Poly Si stacked structure. For example, the thickness of the tunneling layer 7 is in the range of 0.5-2.5 nm, such as 0.5 nm, 1 nm, 2.5 nm, 2 nm or 2.5 nm, and the thickness of the doped polysilicon layer 8 is in the range of 100-300 nm, such as 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, and the doping concentration of the doped polysilicon layer 8 is 3×10 20 -1×10 21 atoms / cm 3 .

[0085] See also Figure 5 、 Figure 6 or Figure 11 The first electrode 12 is in ohmic contact with the first emitter portion 3 and is located in the first sub-region A1. For example, the first electrode 12 is formed by printing Ag paste on the back side of the first sub-region A1.

[0086] Furthermore, the terms “first,” “second,” etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0087] This embodiment configures the first region A where the emitter is located to have a composite structure of a velvet surface and a polished surface, with the velvet surface only in the area in contact with the first electrode 12. This ensures high compatibility with LECO technology to achieve high contact performance, enabling ohmic contact to be formed at the interface between the metal first electrode 12 and the velvet silicon, thereby reducing contact resistance. Furthermore, because only a small area of ​​the emitter is velvet, with the majority being polished, the effect of the laser on the emitter during the second laser treatment can be concentrated on the velvet area, avoiding accidental damage to the polished surface of the second sub-region A2. Damage to the emitter is concentrated in the first sub-region A1, thereby reducing the impact of emitter damage on the passivation performance of the subsequent passivation layer and improving the passivation effect of the battery.

[0088] Since the polished surface in the first area A improves the cell's passivation ability but reduces the cell's bifaciality (bifaciality refers to the ratio of the maximum power output of its rear side to the maximum power output of its front side), the first sub-area A1 is set as a velvet surface to improve the cell's bifaciality and match LECO technology, and the second sub-area A2 is set as a polished surface to improve the cell's passivation ability. This can better balance and take into account the passivation ability and cell bifaciality, thereby improving the cell's efficiency in converting light energy into electrical energy.

[0089] Specifically, velvet silicon can increase the effective contact area. Velvet is a structure with a microscopic rough surface. Compared with a flat surface, its actual contact area with the first electrode 12 is larger, thereby reducing the contact resistance and making it easier for electrons to be transmitted between the velvet silicon and the first electrode 12. Moreover, velvet silicon can optimize interface charge transfer, that is, it changes the interface characteristics between the first electrode 12 and the semiconductor material, making the charge distribution at the interface more uniform, and reducing the accumulation and scattering of charges. When electrons are transmitted from the semiconductor material to the electrode, the uniform charge distribution helps the electrons pass through the interface more smoothly, reducing the obstacles in the transmission process, and thus reducing the ohmic contact resistance. In addition, velvet silicon can improve the wettability between the materials, so that the first electrode 12 fits better with the velvet, reducing the gaps and voids between the two, reducing the transmission resistance of electrons at the interface, and helping to reduce the ohmic contact resistance. Moreover, when using LECO technology, velvet is more conducive to ohmic contact between the first emitter portion 3 and the first electrode 12.

[0090] It should be noted that the polished surface can better reflect the laser than the velvet surface, so the laser damages the polished surface less and the velvet surface more. Therefore, the laser is concentrated in the first sub-area A1 of a small area to reduce the damage to the emitter.

[0091] In some embodiments, as Figure 5 、 Figure 6 or Figure 11 As shown, the first sub-area A1 and the second sub-area A2 are arranged side by side along a preset direction, wherein the preset direction is perpendicular to the thickness direction of the silicon substrate 1. Here, "perpendicular" is not strictly perpendicular, but is within the allowable error range. The first sub-area A1 and the second sub-area A2 can be in an interdigitated structure, and of course can also be in other regular or irregular structures. For example, if the second sub-area A2 is entirely located on the side of the first sub-area A1, "arranged side by side" means that the adjacent first sub-area A1 and the second sub-area A2 are arranged along the preset direction, and the first sub-area A1 and the second sub-area A2 can both extend perpendicular to the preset direction; if the second sub-area A2 surrounds the first sub-area A1, in any preset direction perpendicular to the thickness direction of the silicon substrate 1, the adjacent first sub-area A1 and the second sub-area A2 can be considered to be "arranged side by side".

[0092] In some embodiments, as Figure 5 As shown, the second sub-area A2 is provided on both sides of the first sub-area A1 along the preset direction. Preferably, the first sub-area A1 is located in the middle area of ​​the second sub-area A2 along the preset direction.

[0093] This structure has polished areas on both sides of the velvet surface set in the first sub-area A1 for protection, which can better reduce the impact of the second laser treatment on the emitter, and thus help improve the passivation performance of the passivation layer on the battery. If there are spacer areas C on both sides of the first area A, when the spacer area C is laser treated, the polished area adjacent to the spacer area C can better reflect the laser, thereby reducing the damage of the laser to the emitter.

[0094] In other embodiments, Figure 6 As shown, the first sub-region A1 is located on one side of the second sub-region A2 along a predetermined direction. For example, the first sub-region A1 is located on the side of the second sub-region A2 away from the spacer C along the predetermined direction. This structure is more convenient to process and allows for a larger area to be set up for the first electrode 12.

[0095] In some embodiments, in a preset direction, the width of the first sub-region A1 accounts for 5%-90% of the width of the first region A, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 60%, 70%, 80% or 90%, etc.

[0096] By setting the width ratio range of the first sub-area A1, it is possible to ensure that there is sufficient space for setting the first electrode 12, and the second laser treatment can be concentrated on the velvet area to avoid accidentally damaging the polished surface of the second sub-area A2. The damage to the emitter is limited to the first sub-area A1, so as to reduce the impact of the destruction of the emitter on the subsequent passivation layer and improve the passivation effect of the battery. Moreover, setting a certain velvet width range in the first sub-area A1 can ensure the bifaciality of the battery, so that the passivation ability and the bifaciality of the battery can be balanced and taken into account to the greatest extent, thereby improving the efficiency of the battery in converting light energy into electrical energy.

[0097] In some embodiments, in a predetermined direction, the width of the polished surface between the first sub-area A1 and the edge of the first area A is 0.1-300 μm, and this width can be set according to the width of the first area A. If the polished surface is set on only one side of the first sub-area A1 (i.e., the second sub-area A2), the width of the second sub-area A2 is 0.1-300 μm. For example, the width can be 0.1μm, 1μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, 210μm, 220μm, 230μm, 240μm, 250μm, 260μm, 270μm, 280μm, 290μm, 300μm, etc.

[0098] In some embodiments, the area of ​​the first sub-region A1 accounts for 4%-88% of the area of ​​the first region A. For example, the proportion can be 4%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, or 88%. The numerical value of this proportion can be selected based on the requirements for passivation capability and battery bifaciality. By setting the area proportion of the first sub-region A1 within the above range, it is possible to ensure sufficient space for the first electrode 12 while balancing and taking into account the passivation capability and battery bifaciality to a certain extent, thereby improving the efficiency of the battery in converting light energy into electrical energy.

[0099] In some embodiments, a first distance is defined between the back surface of the silicon substrate 1 and the first sub-area A1 and the front surface 10, and a second distance is defined between the back surface of the silicon substrate 1 and the second sub-area A2 and the front surface 10. The first distance is smaller than the second distance. Preferably, the height difference between the first distance and the second distance is 0.5-5 μm.

[0100] This structure is equivalent to the first area A, where the suede surface is recessed relative to the polished surface toward the front surface 10 of the silicon substrate 1, and the height difference between the suede surface and the polished surface is 0.5-5 μm. For example, the height difference is 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, and 5 μm. By making the suede surface recessed relative to the polished surface toward the front surface 10 of the silicon substrate 1, processing is facilitated. Optionally, the suede surface can also convex relative to the polished surface toward the side away from the front surface 10.

[0101] In some embodiments, as Figure 5 and Figure 6 As shown, the emitter is P-type, the doped polysilicon layer 8 is N-type, the back side of the silicon substrate 1 has a first distance between the first sub-region A1 and the front side 10, the back side of the silicon substrate 1 has a second distance between the second sub-region A2 and the front side 10, and the back side of the silicon substrate 1 has a third distance between the second region B and the front side 10; wherein the absolute value of the difference between the first distance and the third distance does not exceed the preset distance, and the second distance is greater than the third distance.

[0102] The first distance can be greater than, less than, or equal to the third distance. Referring to the following preparation method, this distance relationship can be adjusted by adjusting the mask layer post-laser texturing time and the polishing time after laser etching the first protective layer 6 (BSG) of the second area B.

[0103] In this embodiment, the back side of the silicon substrate 1 is recessed inward in the second region B relative to the first region A to form a recessed portion 4, thereby forming a height difference between the emitter and the doped polysilicon layer 8 in the thickness direction. As a result, the height difference between the emitter and the doped polysilicon layer 8 in the thickness direction increases the surface area of ​​the back side, increases the light absorption area, and can improve the efficiency of the battery. In addition, the light can be reflected multiple times on the back side, which is more conducive to light absorption. Moreover, the spacer region C can completely separate the emitter from the doped polysilicon layer 8 to avoid leakage problems. Moreover, the distance between the first sub-region A1 and the second region B and the front side 10 does not exceed the preset distance, so that the velvet surface of the first sub-region A1 can be as close to the front side 10 as possible. Figure 11 As shown, a preferred embodiment in which the first distance is less than the third distance can reduce the distance between the first sub-region A1 and the front surface 10. Because the transmission of minority carriers in a battery significantly impacts battery performance, when the first distance is less than the third distance, photogenerated holes (minority carriers) are less susceptible to interference from the negatively charged electric field of the N region while migrating to the P region. This reduces the range and duration of influence of the N region's electric field on the holes during transmission, enabling more direct and efficient transmission to the first electrode 12. This reduces the likelihood of carriers recombining with holes at the edge of the isolation region, increases the minority carrier lifetime, improves photoelectric conversion efficiency, and reduces energy loss, further contributing to improved battery performance. Even if the first distance is greater than the third distance, as long as the absolute value of the difference between the first and third distances does not exceed the preset distance, the distance between the first sub-region A1 and the front surface 10 can be minimized, still contributing to improved battery performance.

[0104] Preferably, the absolute value of the difference between the first distance and the third distance does not exceed 2 μm, and the height difference between the second distance and the third distance is 0.5-5 μm. By limiting the maximum value of this height difference, the P-type first region A can be brought closer to the front surface 10, so that holes are not affected by the electric field of the N region during transmission, reducing the possibility of carrier recombination at the edge of the isolation region, and further promoting battery performance. In practice, the emitter of the second region B can be laser etched and then the recessed portion 4 can be formed by etching. The depth of the recessed portion 4 can be reduced by reducing the etching time.

[0105] In other embodiments, Figure 6 As shown, the first distance is greater than the third distance, and the second distance is greater than the third distance, which is also within the protection scope of the embodiment of the present disclosure.

[0106] In some embodiments, in the first region A, the suede surface and the polished surface are connected by an inclined surface, and the side length of the inclined surface in the cross section is 0.8-8 μm, wherein the cross section is a plane perpendicular to the extending direction of the inclined surface.

[0107] When the velvet surface is formed by chemical etching, the etching solution has different etching rates for different crystal planes on the surface of the silicon substrate 1. Some crystal planes etch faster, while others etch slower. When the polished surface is gradually etched to form the velvet surface, due to the uneven etching, a bevel is naturally formed in the transition area between the polished surface and the velvet surface. For example, the atomic arrangement of the (100) crystal plane is relatively loose and the etching rate is the fastest, while the atomic arrangement of the (111) crystal plane is dense and the etching rate is the slowest. The atomic arrangement of the (110) crystal plane is dense between the (100) crystal plane and the (111) crystal plane, and the etching rate is also between the two. Moreover, the velvet surface and the polished surface are connected by a bevel transition, which can relieve the stress at the connection between the velvet surface and the polished surface, prevent the sharp boundary from generating defects, and cause the defect position to become a recombination center of carriers, thereby improving the photoelectric conversion efficiency of the battery.

[0108] In some embodiments, the back-contact cell further includes: a second electrode 13 , in ohmic contact with the doped polysilicon layer 8 .

[0109] The first electrode 12 and the second electrode 13 have opposite polarities. For example, the first electrode 12 is formed by printing with Ag paste on the back of the first sub-region A1, and the second electrode 13 is formed by printing with Ag paste on the second region B.

[0110] In some embodiments, the area of ​​the first region A accounts for 30%-50% of the total area of ​​the back side of the silicon substrate 1, such as 30%, 35%, 40%, 45% or 50%, and the area of ​​the second region B accounts for 40%-60% of the total area of ​​the back side of the silicon substrate 1, such as 40%, 45%, 50%, 55% or 60%, to ensure the total amount of photogenerated carriers generated.

[0111] In some embodiments, the back side of the silicon substrate 1 is velvet-surfaced in the spacer region C, which can improve the bifaciality of the battery. Specifically, the back side of the silicon substrate 1 is set as a velvet-surface in the spacer region C. When light hits the velvet, multiple reflections occur, allowing more light to be absorbed by the battery and converted into electrical energy, thereby improving the utilization rate of light on the back side of the battery. The velvet structure has broadband anti-reflection properties, which can reduce light reflection over a wide wavelength range and reduce reflection loss. Moreover, due to the undulating structure of the velvet, the path of light propagating inside the battery is longer, increasing the probability of photons interacting with the silicon substrate, generating more carriers, and optimizing the light absorption effect. These advantages can all improve the bifaciality of the battery.

[0112] Optionally, the back side of the silicon substrate 1 is a polished surface in the spacer region C to achieve a better passivation effect. Specifically, the atoms on the polished surface are neatly arranged, the surface atoms are in stable lattice positions, the surface area is smaller, and the number of crystal defects is fewer. Moreover, the polished surface can remove damage caused by the previous period in the spacer region C on the back side of the silicon substrate 1, reducing the number of crystal defects and the probability of carrier recombination at the back side defects. In addition, the polished surface provides a smooth and uniform substrate for the growth of the passivation film, increases the adhesion between the passivation film and the polished surface, and facilitates the formation of a passivation film with uniform thickness, effectively preventing carrier recombination. These advantages all contribute to achieving a better passivation effect.

[0113] In some embodiments, the second region B is a polished surface, which is beneficial for improving the passivation performance of the back contact battery.

[0114] In some embodiments, the back-contact cell further includes a passivation layer or a passivation anti-reflection layer disposed on the front and / or back of the silicon substrate 1. Thus, the passivation layer or the passivation anti-reflection layer can improve the passivation performance of the cell and reduce or avoid the impact of defects generated during the cell manufacturing process.

[0115] Two specific embodiments are given below.

[0116] In the first embodiment, as Figure 5 As shown, there is no metal grid line on the front side of the silicon substrate 1, and there is a first area A and a second area B on the back side. Multiple first areas A and second areas B can be provided and are arranged alternately. The back side of the silicon substrate 1 is recessed inwardly in the second area B relative to the first area A. Thus, a height difference is formed between the emitter and the doped polysilicon layer 8 in the thickness direction, which increases the surface area of ​​the back side and the light absorption area, thereby improving the efficiency of the battery. In addition, the light can be reflected multiple times on the back side, which is more conducive to light absorption. Moreover, the spacer C can completely separate the emitter from the doped polysilicon layer 8 to avoid leakage problems.

[0117] The first region A includes a first sub-region A1 and a second sub-region A2 along a preset direction (for example, a direction parallel to the front surface of the silicon wafer). The first sub-region A1 is a velvet surface. The first sub-region A1 is arranged in the middle area of ​​the second sub-region A2 along the preset direction. The first electrode 12 is in ohmic contact with the first emitter part 3 of the first sub-region A1.

[0118] For example, the first region A is a P region, the second region B is an N region, and the silicon substrate 1 has P regions from the inside to the outside in the first region A. + The emitter and the passivation anti-reflection layer 11, the silicon substrate 1 has a tunneling layer 7, an N-type doped polysilicon layer 8 and a passivation anti-reflection layer 11 in the second area B from the inside to the outside. The spacer area C adopts a textured surface.

[0119] For example, the first region A, the second region B and the spacer region C are P + Emitter, SiO2 / N+ Poly Si structure, silicon nitride and silicon dioxide stacked layers, the spacer region C overlaps with the first region A and the second region B.

[0120] In the second embodiment, as Figure 6 As shown, Figure 5 The difference of the battery shown is that the first sub-area A1 is located on one side of the second sub-area A2 along a predetermined direction. For example, the first sub-area A1 is located on a side of the second sub-area A2 away from the spacer C along the predetermined direction.

[0121] Secondly, the present disclosure provides a photovoltaic module, including the back-contact cell of the above embodiment. Exemplarily, the photovoltaic module includes a laminate and a frame assembled on the edge of the laminate, wherein the laminate includes a cover plate, an adhesive film, a back-contact cell, an adhesive film and a back plate stacked in sequence. Since the first area A where the emitter of the cell is located is set to a composite structure of velvet and polished surface, and only the area in contact with the first electrode 12 is set to velvet, it can form an ohmic contact at the interface between the metal first electrode 12 and the velvet silicon to reduce the contact resistance, and only a small area of ​​the emitter is velvet, and most of it is polished surface. Therefore, the second laser treatment can be focused on the velvet area to avoid accidentally damaging the polished surface of the second sub-area A2, minimize damage to the emitter, and better balance the passivation ability and the cell bifaciality. This can also improve the efficiency of the photovoltaic module in converting light energy into electrical energy and improve the overall performance.

[0122] Finally, the present disclosure provides a method for preparing a back contact battery based on the above embodiment. In some embodiments, as Figure 12 As shown, the preparation method comprises:

[0123] Step S1, a mask layer forming step, forming a mask layer on the surface of a silicon substrate 1, the back side of the silicon substrate 1 includes a first area A, a second area B and a spacer area C, the adjacent first area A and second area B are separated by the spacer area C, the first area A includes adjacent first sub-area A1 and second sub-area A2, and the first area A is a polished surface.

[0124] Step S2 , texturing treatment, using laser to remove the mask layer in the first sub-area A1 on the back side of the silicon substrate 1 , and performing texturing treatment on the first sub-area A1 to form a suede surface.

[0125] Step S3: remove the remaining mask layer on the surface of the silicon substrate 1, and the second sub-area A2 is a polished surface. Since other areas are covered by the mask layer and are not affected by the texturing process, the second sub-area A2 is a polished surface.

[0126] Step S4: perform a first doping treatment on the silicon substrate 1 to form an emitter with a first conductivity type in the first region A. The emitter of the first region A includes a first emitter portion 3 located in the first sub-region A1 and a second emitter portion 5 located in the second sub-region A2.

[0127] Step S5: performing a second doping treatment on the silicon substrate 1 to form a carrier collection layer having a conductivity type opposite to that of the first region B.

[0128] Step S6 : forming a first electrode 12 on the first emitter portion 3 in ohmic contact with the first emitter portion 3 .

[0129] Among them, steps S1 to S6 are performed sequentially.

[0130] Before step S1 , the silicon substrate 1 may be polished.

[0131] In step S1, the mask layer may be an oxide mask layer to protect the entire surface of the silicon substrate 1. For example, the thickness of the mask layer is 1-100 nm, such as 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and the material of the mask layer includes SiO2 or SiNx.

[0132] In step S2, if Figure 1 or Figure 7 As shown, a laser is used to remove a preset texturing area 2 with a width of 50-100 μm on the back side of the silicon substrate 1. Corresponding to the first sub-area A1, the preset texturing area 2 is recessed inward relative to the back side of the silicon substrate 1, and a texturing process is performed so that the laser etched area becomes a velvet surface, and the non-laser area is not affected and remains a polished surface.

[0133] In some embodiments, as Figure 13 As shown, S4 specifically includes:

[0134] S41 , forming an emitter and a first protective layer 6 on the entire surface of the silicon substrate 1 .

[0135] Specifically, an acid solution (such as HF acid) is used to remove the mask layer on the surface of the silicon substrate 1, and a first doping treatment is performed to form an emitter and a first protective layer 6 on the entire surface of the silicon substrate 1. For example, the first doping treatment can be a boron diffusion treatment to form P on the surface of the silicon substrate 1. + Emitter and borosilicate glass (BSG). The borosilicate glass layer can be referred to as the first protective layer 6.

[0136] S42 , removing the front surface 10 of the silicon substrate 1 , the second region B on the back surface, and the emitter and the first protective layer 6 in the spacer region.

[0137] Specifically, the first protective layer 6 (for example, BSG) on the second area B and the spacer area C on the back side of the silicon substrate 1 is etched by laser, and the first protective layer 6 (for example, BSG) on the front side 10 is removed by single-sided etching. For example, the front side can be etched by chain single-sided etching (acid tank). After the etching of the first protective layer 6 is completed, alkaline polishing can be performed to remove the emitter on the second area B and the spacer area C and the front side 10 on the back side of the silicon substrate 1. Subsequently, a polishing process is performed to convert the second area B, the spacer area C and the front side 10 on the back side of the silicon substrate 1 into polished surfaces. Moreover, the back side of the silicon substrate 1 is concave inward relative to the first area A and the front side 10 in the second area B and the spacer area C to form a concave portion 4, that is, the distance between the back side and the front side 10 of the silicon substrate 1 in the second area B is smaller than that in the first area A, forming a concave portion 4. Figure 2 The structure shown. It can also be formed Figure 8 The structure shown.

[0138] In some embodiments, as Figure 14 As shown, step S5 specifically includes:

[0139] Step S51: sequentially growing a tunneling layer 7 and intrinsic polysilicon on the surface of the silicon substrate 1, and performing a second doping treatment, so that the entire surface of the silicon substrate 1 forms a tunneling layer 7, a doped polysilicon layer 8, and a second protective layer 9, wherein the doped polysilicon layer 8 has a second conductivity type opposite to the first conductivity type;

[0140] Step S52 , removing the second protective layer 9 on the front surface 10 and the back surface of the silicon substrate 1 in the first area A and the spacer area C;

[0141] Step S53 : removing the first protective layer 6 in the first area A and the second protective layer 9 in the second area B on the back side of the silicon substrate 1 .

[0142] Steps S51 to S53 are executed sequentially, and the following description is made by taking the first area A as a P area and the second area B as an N area as an example.

[0143] Specifically, step S51 may include sequentially growing a tunneling layer 7 and intrinsic polysilicon on the surface of the silicon substrate 1, wherein the tunneling layer 7 may be a tunneling oxide layer, and performing a second doping treatment to form a tunneling layer 7, a doped polysilicon layer 8, and a second protective layer 9 on the surface of the silicon substrate 1 as a whole, forming a structure as shown in FIG. Figure 3 or Figure 9 The structure shown. At this point, the second region B and the spacer region C on the back of the silicon substrate 1 form a multilayer structure of tunneling layer 7 / doped polysilicon layer 8 / second protective layer 9 from the inside out. The first region A on the back of the silicon substrate 1 forms the emitter / first protective layer 6 / doped polysilicon layer 8 / second protective layer 9. In fact, the tunneling layer 7 also adheres to the first protective layer 6, but because the tunneling layer 7 is thin, it mixes with the oxide layer of the first protective layer 6 itself and is therefore called the first protective layer 6.

[0144] For example, the tunneling layer 7 is SiO2, and the second doping treatment can be a phosphorus diffusion process. After the treatment, the second area B and the spacer area C on the back of the silicon substrate 1 form SiO2 / N from the inside to the outside. + Poly Si / phosphosilicate glass (PSG) structure, the first area A on the back of the silicon substrate 1 forms P from the inside to the outside + Emitter / BSG / N + Poly Si / PSG. The phosphosilicate glass layer can be called the second protective layer.

[0145] Specifically, step S52 may include: when removing the second protective layer, using a laser to etch the second protective layer 9, such as PSG, on the back side of the silicon substrate 1 in the first area A and the spacer area C, and removing the PSG on the front side 10 by single-side etching. For example, by utilizing the difference in acid-base corrosion characteristics, that is, the alkaline solution mainly corrodes the crystalline silicon and polycrystalline silicon, and corrodes the glass layer very slowly, while hydrofluoric acid (HF) mainly corrodes the glass layer and does not corrode the crystalline silicon, the front second protective layer 9 (such as PSG) can be etched in a 25% mass concentration hydrofluoric acid (HF) solution using a chain single-side etching process, and the doped polycrystalline silicon layer 8 (N) inside the second protective layer 9 (such as PSG) can be removed. + The poly Si layer) can be removed by a 5% mass concentration potassium hydroxide (KOH) solution. At this time, the first region A of the silicon substrate 1 includes P + Emitter / BSG, spacer C forms a velvet or polished surface, and the second area B is still SiO2 / N + Poly Si / phosphosilicate glass (PSG) structure.

[0146] Between step S52 and step S53, the preparation method provided by the present disclosure further includes: forming a velvet surface on the front side 10 and the back side of the silicon substrate 1 in the spacer area C. After removing the doped polysilicon layer 8 on the inner side of the second protective layer 9, an alkaline solution is used to texture the spacer area C to form a velvet surface. Velvet can also be formed on the front side of the battery. This embodiment forms a velvet surface on the front side 10 of the silicon substrate 1, which can reduce light reflection, has a good light limiting effect, and can further improve the utilization rate of light. The back side of the silicon substrate 1 forms a velvet surface in the spacer area C, which can improve the bifaciality of the battery.

[0147] Specifically, step S53 may include: removing the first protective layer 6 (eg BSG) in the first area A and the second protective layer 9 (eg PSG) in the second area B on the back side of the silicon substrate 1 with an acid solution (eg HF acid), forming Figure 4 or Figure 10 The structure shown.

[0148] In some embodiments, between step S5 and step S6, the preparation method further comprises:

[0149] A passivation anti-reflection layer 11 or a passivation layer is deposited on the front side 10 and the back side of the silicon substrate 1. Figure 5 The structure shown.

[0150] For example, the passivation layer may include a silicon oxide layer, and the passivation anti-reflection layer 11 may include a composite layer formed of at least one of silicon nitride and silicon oxynitride, and a silicon oxide layer, with a thickness of 60 nm to 130 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, or 130 nm. Both silicon oxide and silicon nitride can provide passivation, while silicon nitride can provide anti-reflection. The provision of the passivation anti-reflection layer 11 can reduce reflectivity and improve light utilization.

[0151] In some embodiments, step 52 includes simultaneously removing the second protective layer 9 in the first area A and the spacer area C using a single laser beam. Laser parameters include a laser radiation power of 1-50 W and / or a laser wavelength of 350-1070 nm. This approach can improve manufacturing efficiency.

[0152] The laser wavelength can be selected within the above range. For example, the laser wavelength can be selected as 355nm, 532nm or 1064nm. When a specific laser wavelength is selected, the laser wavelength will also fluctuate within a small range within the preset range.

[0153] In step S6, Figure 5 、 Figure 6 or Figure 11 As shown, a first electrode 12 is provided in the first sub-region A1 of the emitter.

[0154] In some embodiments, the preparation method further includes: disposing a second electrode 13 on the doped polysilicon layer 8. In the embodiment of the present disclosure, there is no specific limitation on the order of disposing the first electrode 12 and the second electrode 13.

[0155] The preparation method of this embodiment sets the first area A where the emitter is located to a composite structure of a velvet surface and a polished surface, and sets the velvet surface only in the area in contact with the first electrode 12, ensuring high compatibility with the LECO technology to achieve high contact performance, so that the first electrode 12 forms an ohmic contact with the emitter at the velvet silicon, reducing contact resistance. Moreover, because the emitter only occupies a small area on the velvet surface, and most of it is located on the polished surface, when the second laser treatment is used to remove the carrier collection layer in the first area, the effect of the laser on the emitter can be concentrated on the velvet area, reducing accidental damage to the emitter in the second sub-area A2, and concentrating the damage to the emitter in the first sub-area A1, so as to reduce the damage to the emitter and the inability to effectively passivate the subsequent passivation layer or passivation anti-reflection layer, which is beneficial to the passivation effect of the passivation layer or passivation anti-reflection layer on the battery.

[0156] Since the polished surface in the first area A improves the cell's passivation ability but reduces the cell's bifaciality (bifaciality refers to the ratio of the maximum power output of its rear side to the maximum power output of its front side), the first sub-area A1 is set as a velvet surface to improve the cell's bifaciality and match LECO technology, and the second sub-area A2 is set as a polished surface to improve the cell's passivation ability. This can better balance and take into account the passivation ability and cell bifaciality, thereby improving the cell's efficiency in converting light energy into electrical energy.

[0157] In addition, the process flow of this battery is simple and does not require any other complex processes. Existing equipment can be used, such as the existing equipment in the TOPCon factory. It can be adapted to the layout of the TOPCon factory and is easy to promote.

[0158] In order to better demonstrate the preparation method and performance advantages of the embodiments of the present disclosure, two specific embodiments are given below for illustration.

[0159] (1) Example 1:

[0160] An N-type silicon substrate 1 with a resistivity of 20 Ω.cm and a thickness of 150 μm was polished, and then the silicon substrate 1 was placed in a quartz boat and oxygen was introduced to form a silicon oxide mask layer with a thickness of about 10 nm. A 10W green picosecond laser was then used to remove the surface mask layer of the first sub-area A1, and a texturing treatment was performed to form a velvet surface in the first sub-area A1. An HF solution with a mass concentration of 5% was then used to remove the surface mask layer of the silicon substrate 1. At this time, the portion preset as the P area (corresponding to the first area A) is a polishing surface / velvet composite structure, and the two sides of the first sub-area A1 are the second sub-area A2 (polishing surface), the polishing part is a non-metallic contact area, and the velvet part is divided into a metal contact area. There is a height difference of 2 μm between the polishing surface and the velvet surface in the thickness direction of the silicon substrate 1, and the velvet surface and the polishing surface are connected as a bevel, and the length of the bevel is 3 μm, forming a structure as shown below. Figure 1 The structure shown. In the preset direction where the first sub-area A1 and the second sub-area A2 are arranged side by side, the width of the first sub-area A1 accounts for 10% of the total width of the first area (P area). The silicon substrate 1 is then loaded into a low-pressure chemical vapor deposition (LPCVD) quartz boat, and a boron source is introduced to complete the boron diffusion process. At this time, P is formed on the surface of the silicon wafer. + Emitter and BSG; use a 45W green laser to etch away the BSG on the back side reserved for the N region (corresponding to the second region B) and the spacer region.

[0161] Next, the substrate is placed in a 10% HF solution using a single-side etching process to remove the first protective layer 6 (BSG) on the front side of the silicon substrate 1. Subsequently, a polishing process is performed in a KOH alkaline solution. The second area B (N area) and the spacer area C are polished to form a polished surface. The P area is not affected due to the protection of BSG (see Figure 2 ).

[0162] Next, the dried silicon substrate 1 is placed in a quartz boat for low-pressure vapor deposition, heated to 600°C under low pressure, and 2000sccm of oxygen is introduced to grow a tunneling layer 7 (SiO2 layer) of about 1.5nm on the surface of the second region B (N region) on the back of the silicon substrate 1. Subsequently, silane is introduced to grow a 250nm thick intrinsic polysilicon (i-Poly Si) on the surface of the tunneling layer 7 away from the silicon substrate 1. Subsequently, the temperature is increased and a phosphorus source is introduced to complete the phosphorus diffusion process. At this time, the second region B (N region) and the spacer region C are a stacked structure of the tunneling layer 7, the doped polysilicon layer 8 and the second protective layer 9 (SiO2 / N + Poly Si / PSG), the first region A (P region) is a stacked structure of the emitter, the first protective layer 6, the doped polysilicon layer 8 and the second protective layer 9 (P + / BSG / N + Poly Si / PSG) (See Figure 3 ).

[0163] Then, the second protective layer 9 (PSG) on the surface of the spacer C and the first area A (P area) is etched away with a 30W green laser, and then the PSG on the front surface of the silicon substrate 1 is etched away with a 5% HF etching solution.

[0164] Then, a texturing process is performed to change the spacer area C on the back side of the silicon substrate 1 and the front side 10 into a textured structure. Next, the second protective layer 9 (PSG) on the surface of the second area B (N area) and the first protective layer 6 (BSG) on the surface of the first area A (P area) are removed (see Figure 4 ).

[0165] Subsequently, Al2O3 coating was performed on the front side of the silicon substrate 1. At 250°C, trimethylaluminum and water were introduced to grow a 6nm thick Al2O3 layer on both sides. Then, in a plasma enhanced chemical vapor deposition device, silane and ammonia were introduced at 540°C to complete the SiN coating on both sides. x The thickness of the film is 75nm. Then, silver paste is printed on the first sub-area A1 and the second sub-area B on the back of the silicon substrate 1 by screen printing. After high-temperature sintering and combined with LECO technology, metallization is completed. Finally, after light injection treatment, a back contact cell is obtained (see Figure 5 ).

[0166] Comparative Example:The N-type silicon substrate with a resistivity of 20 Ω.cm and a thickness of 150 μm was textured. The silicon substrate was then loaded into an LPCVD quartz boat and a boron source was introduced to complete the boron diffusion process. At this time, P + The emitter and BSG are etched away using a 45W green laser. The BSG on the backside, reserved for the N-region and spacer, is then polished in a KOH alkaline solution. The N-region and spacer are polished, while the P-region remains unaffected due to the BSG's protection.

[0167] Next, the dried silicon substrate is placed in a quartz boat and heated to 600°C under low pressure. 2000sccm of oxygen is introduced to grow a tunneling layer (SiO2 layer) of about 1.5nm in the N region on the back of the silicon substrate. Silane is then introduced to grow a 250nm thick intrinsic polysilicon (i-Poly Si) on the surface of the tunneling layer away from the silicon substrate. The temperature is then raised and a phosphorus source is introduced to complete the phosphorus diffusion process. At this time, the N region is a stacked structure of the tunneling layer, the doped polysilicon layer and the second protective layer (SiO2 / N + Poly Si / PSG), P region is P + Emitter, first protective layer, doped polysilicon layer and second protective layer stacked structure (P + / BSG / N + Poly Si / PSG). Then use 30W green laser to etch away the PSG on the P area and the PSG on the spacer area, and etch away the PSG on the front side with 5% HF etching solution. Then carry out the texturing process to remove the doped polysilicon layer (N + Poly Si), and the front and back spacers were made into a velvet surface, and 10% HF was used to remove the PSG of the N area and the first protective layer (BSG) on the surface of the P area. Subsequently, Al2O3 was coated on the front of the silicon substrate. At 250°C, trimethylaluminum and water were introduced to grow a 6nm thick Al2O3 layer on the front and back surfaces. Then, in a plasma-enhanced chemical vapor deposition device, silane and ammonia were introduced at 540°C to complete the SiN x The thin films are deposited to a thickness of 75nm. Subsequently, silver paste is screen-printed onto the P and N regions on the back of the silicon substrate. After high-temperature sintering and metallization using LECO technology, the resulting structure is treated with light injection to create a back-contact cell.

[0168] The solar cells prepared by using the above-mentioned embodiment 1 and the comparative example were subjected to performance tests. The test results are shown in Table 1 below:

[0169] Table 1 Performance test results of Example 1 and comparative example

[0170] EFF (%) Voc(mV) Isc(A) FF(%) Example 1 26.53 741.3 14.52 81.65 Comparative Example 24.79 725.2 14.45 78.35

[0171] Among them, EFF is the photoelectric conversion efficiency, which is the efficiency percentage of converting sunlight into electrical energy; Voc is the open circuit voltage, which is the voltage across the solar cell when no load is connected; Isc is the short-circuit current, which is the current flowing when the positive and negative poles of the battery are directly short-circuited; FF is the fill factor, which measures the efficiency of the solar cell at the maximum power point, that is, the ratio of the actual output power to the theoretical maximum power (Voc multiplied by Isc). A high fill factor means that the battery can convert light energy into electrical energy more efficiently and reduce internal losses.

[0172] The comparative example is the solution of laser etching the full suede surface in the P area. + The emitter has a greater impact and damages the texture of the P area. Although the film will be passivated before metallization, the passivation layer or passivation anti-reflection layer is difficult to make up for the damage to the P area. + The emitter is damaged, so the overall passivation level is very poor, and the increased recombination also causes a loss of current and fill factor. As can be seen from Table 1, the above four performance indicators of the solar cell of Example 1 of the present disclosure are all better than those of the comparative example.

[0173] (2) Example 2:

[0174] An N-type silicon substrate 1 with a resistivity of 20 Ω.cm and a thickness of 150 μm was polished, and then the silicon substrate 1 was placed in a quartz boat and oxygen was introduced to form a silicon oxide mask layer with a thickness of about 10 nm. Subsequently, a 10W green picosecond laser was used to remove the surface mask layer of the first sub-area A1, and a texturing treatment was performed to form a velvet surface in the first sub-area A1. In the preset direction in which the first sub-area A1 and the second sub-area A2 are arranged side by side, the edge distance of the first sub-area A1 is 100 μm from the distance reserved for the spacer C. Subsequently, an HF solution with a mass concentration of 5% was used to remove the surface mask layer of the silicon substrate 1. At this time, the portion preset as the P region (corresponding to the first region A) is a polished surface / velvet composite structure, and the second sub-area A2 is located on one side of the first sub-area A1. The polished portion is a non-metallic contact area, and the velvet portion is divided into a metal contact area. Subsequently, the silicon substrate 1 is loaded into an LPCVD quartz boat, and a boron source is introduced to complete the boron diffusion process. At this time, a P surface is formed on the surface of the silicon wafer. + Emitter BSG; use a 45W green laser to etch away the BSG on the back side reserved for the N region (corresponding to the second region B) and the spacer region.

[0175] Next, the BSG on the front surface of the silicon substrate 1 is removed in an HF solution with a mass concentration of 10%, and then a polishing process is performed in a KOH alkaline solution. The second area B (N area) and the spacer area C both form polished surfaces, and the first area A (P area) is not affected due to the protection of the first protective layer 6 (BSG).

[0176] Next, the dried silicon substrate 1 is placed in a quartz boat and heated to 600°C under low pressure. 2000sccm of oxygen is introduced to grow a tunneling layer 7 (SiO2 layer) of about 1.5nm in the second region B (N region) on the back of the silicon substrate 1. Then, silane is introduced to grow a 250nm thick intrinsic polysilicon (i-Poly Si) on the surface of the tunneling layer 7 away from the silicon substrate 1. Then, the temperature is increased and a phosphorus source is introduced to complete the phosphorus diffusion process. At this time, the second region B (N region) and the spacer region C are a stacked structure of the tunneling layer 7, the doped polysilicon layer 8 and the second protective layer 9 (SiO2 / N + Poly Si / PSG), the first region A (P region) is a stacked structure of the emitter, the first protective layer 6, the doped polysilicon layer 8 and the second protective layer 9 (P + / BSG / N + Poly Si / PSG). A 30W green laser is then used to etch away the second protective layer 9 (PSG) on the surface of the spacer region C and the first region A (P region). The second protective layer 9 (PSG) on the front surface of the silicon substrate 1 is then etched away using a 5% HF etching solution.

[0177] Then, the texturing process is carried out to transform the spacer area C on the back of the silicon substrate 1 and the front surface 10 into a velvet structure. Next, the second protective layer 9 (PSG) on the surface of the second area B (N area) and the first protective layer 6 (BSG) on the surface of the first area A (P area) are removed. Subsequently, Al2O3 is coated on the front surface of the silicon substrate 1. At 250°C, trimethylaluminum and water are introduced to grow a 6nm thick Al2O3 layer on the front and back surfaces. Next, in a plasma enhanced chemical vapor deposition device, silane and ammonia are introduced at 540°C to complete the SiN coating on both the front and back surfaces. x The thickness of the film is 75nm. Then, silver paste is printed on the first sub-area A1 and the second sub-area B on the back of the silicon substrate 1 by screen printing. After high-temperature sintering and combined with LECO technology, metallization is completed. Finally, after light injection treatment, a back contact cell is obtained (see Figure 6 ). The difference between Example 2 and Example 1 is that the distance between the edge of the suede surface of the P region and the spacer C is designed to be 100 μm, and one side of the suede surface of the P region extends to the edge of the P region, and a polishing surface is provided only on one side of the first sub-region A1.

[0178] The solar cells prepared by using the above-mentioned Example 2 and the comparative example were subjected to performance tests. The test results are shown in Table 2 below:

[0179] Table 2 Performance test results of Example 2 and Comparative Example

[0180] EFF (%) Voc(mV) Isc(A) FF(%) Example 2 26.49 741.5 14.51 81.55 Comparative Example 24.79 725.2 14.45 78.35

[0181] The comparative example is the scheme of laser etching the full velvet surface in the P area. The laser has a greater impact on the emitter of the velvet area and damages the velvet surface of the P area. Although the film will be passivated before metallization, the passivation layer is difficult to make up for the damage to the P area. + The emitter is damaged, so the overall passivation level is very poor, and the increased recombination also causes a loss of current and fill factor. As can be seen from Table 2, the above four performance indicators of the solar cell of Example 2 of the present disclosure are all better than those of the comparative example.

[0182] In summary, the back contact cell provided by the present disclosure can effectively improve electrical properties such as photoelectric conversion efficiency, open circuit voltage, short circuit current, and fill factor by combining the velvet surface and polished surface of the first zone.

[0183] While the present disclosure has been described with reference to preferred embodiments, various modifications may be made thereto and equivalent components may be substituted without departing from the scope of the present disclosure. In particular, the various technical features described in the various embodiments may be combined in any manner, provided no structural conflicts exist. The present disclosure is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate (1) having a first area (A), a second area (B) and a spacer area (C) on its back side, wherein the adjacent first area (A) and the second area (B) are separated by the spacer area (C), the first area (A) comprises a first sub-area (A1) and a second sub-area (A2) adjacent to each other, the first sub-area (A1) being a velvet surface, and the second sub-area (A2) being a polished surface; an emitter having a first conductivity type, arranged on the back side of the silicon substrate (1), and comprising a first emitter portion (3) located in the first sub-region (A1) and a second emitter portion (5) located in the second sub-region (A2), wherein the first conductivity type is P type; A carrier collection layer, comprising a tunneling layer (7) and a doped polysilicon layer (8), wherein the tunneling layer (7) is arranged on the back side of the silicon substrate (1) and is located in the second region (B), and the doped polysilicon layer (8) is arranged on a side of the tunneling layer (7) away from the silicon substrate (1), and the doped polysilicon layer (8) has a second conductivity type opposite to the first conductivity type, and the second conductivity type is N-type; and A first electrode (12) is in ohmic contact with the first emitter portion (3).

2. The back contact battery according to claim 1, characterized in that The first sub-area (A1) and the second sub-area (A2) are arranged side by side along a preset direction, wherein the preset direction is perpendicular to the thickness direction of the silicon substrate (1).

3. The back contact battery according to claim 2, wherein The second sub-area (A2) is provided on both sides of the first sub-area (A1) along the preset direction; or The first sub-area (A1) is located on one side of the second sub-area (A2) along the preset direction.

4. The back contact battery according to claim 2, characterized in that In the preset direction, the width of the first sub-region (A1) accounts for 5%-90% of the width of the first region (A).

5. The back contact battery according to claim 2, characterized in that In the preset direction, the width of the polished surface between the first sub-area (A1) and the edge of the first area (A) is 0.1-300 μm.

6. The back contact battery according to claim 1, characterized in that The area of ​​the first sub-region (A1) accounts for 4%-88% of the area of ​​the first region (A).

7. The back contact battery according to claim 1, characterized in that The back side of the silicon substrate (1) has a first distance between the first sub-area (A1) and the front side (10), and the back side of the silicon substrate (1) has a second distance between the second sub-area (A2) and the front side (10), wherein the first distance is smaller than the second distance.

8. The back contact battery according to claim 7, characterized in that A height difference between the first distance and the second distance is 0.5-5 μm.

9. The back contact battery according to claim 1, characterized in that In the first area (A), the suede surface and the polished surface are connected by an inclined surface, and the length of the side of the inclined surface in the cross section is 0.8-8 μm.

10. The back contact cell according to claim 1, wherein The doping concentration of the second emitter portion (5) in the second sub-region (A2) is 1×10 18 -1×10 19 atoms / cm 3 , the junction depth is 0.2-1.5 μm, the doping concentration of the first emitter portion (3) in the first sub-region (A1) is 2×10 18 -3×10 19 atoms / cm 3 , the junction depth is 0.5-2μm.

11. The back contact battery according to claim 1, characterized in that The silicon substrate (1) is an N-type silicon wafer with a resistivity of 0.1-100 Ω.cm and a thickness of 100-500 μm.

12. The back contact battery according to any one of claims 1 to 11, characterized in that: Also includes: The second electrode (13) is in ohmic contact with the doped polysilicon layer (8).

13. The back contact battery according to claim 12, characterized in that The emitter is of P type, the doped polysilicon layer (8) is of N type, the back side of the silicon substrate (1) has a first distance between the first sub-region (A1) and the front side (10), the back side of the silicon substrate (1) has a second distance between the second sub-region (A2) and the front side (10), and the back side of the silicon substrate (1) has a third distance between the second region (B) and the front side (10); wherein the absolute value of the difference between the first distance and the third distance does not exceed a preset distance, and the second distance is greater than the third distance.

14. The back contact battery according to claim 13, characterized in that An absolute value of a difference between the first distance and the third distance does not exceed 2 μm, and a height difference between the second distance and the third distance is 0.5-5 μm.

15. The back contact battery according to claim 13, characterized in that The first distance is smaller than the third distance.

16. The back contact battery according to claim 13, characterized in that The area of ​​the first region (A) accounts for 30%-50% of the total area of ​​the back side of the silicon substrate (1), and the area of ​​the second region (B) accounts for 40%-60% of the total area of ​​the back side of the silicon substrate (1).

17. The back contact cell according to claim 13, wherein The thickness of the tunneling layer (7) is in the range of 0.5-2.5 nm, the thickness of the doped polysilicon layer (8) is in the range of 100-300 nm, and the doping concentration of the doped polysilicon layer (8) is 3×10 20 -1×10 21 atoms / cm 3 .

18. The back contact battery according to claim 12, characterized in that The first electrode (12) is configured to be formed by printing Ag paste on the back side of the first sub-region (A1), and the second electrode (13) is configured to be formed by printing Ag paste on the second region (B).

19. The back contact cell according to claim 1, characterized in that The back surface of the silicon substrate (1) is a velvet surface or a polished surface in the spacer area (C); and / or, the second area (B) is a polished surface; And / or, the back contact cell further comprises a passivation layer or a passivation anti-reflection layer provided on the front and / or back side of the silicon substrate (1).

20. A photovoltaic module, characterized in that: A back contact battery comprising the method according to any one of claims 1 to 19.

21. A method for preparing a back contact battery, characterized in that: include: S1. Forming a mask layer on the surface of a silicon substrate (1), wherein the back surface of the silicon substrate (1) comprises a first region (A), a second region (B), and a spacer region (C), wherein the adjacent first region (A) and the second region (B) are separated by the spacer region (C), the first region (A) comprises a first sub-region (A1) and a second sub-region (A2) adjacent to each other, and the first region (A) is a polished surface; S2, using laser to remove the mask layer of the first sub-area (A1) located on the back side of the silicon substrate (1), and performing a texturing treatment on the first sub-area (A1) to form a velvet surface; S3, removing the remaining mask layer on the surface of the silicon substrate (1), and the second sub-area (A2) is a polished surface; S4, performing a first doping treatment on the silicon substrate (1), so that the first region (A) forms an emitter having a first conductivity type, and the emitter of the first region (A) includes a first emitter portion (3) located in the first sub-region (A1) and a second emitter portion (5) located in the second sub-region (A2), and the first conductivity type is P type; S5. Performing a second doping treatment on the silicon substrate (1) so that the second region (B) forms a carrier collection layer, the carrier collection layer comprising a tunneling layer (7) and a doped polysilicon layer (8), the tunneling layer (7) being arranged on the back side of the silicon substrate (1) and located in the second region (B), the doped polysilicon layer (8) being arranged on a side of the tunneling layer (7) away from the silicon substrate (1), the doped polysilicon layer (8) having a second conductivity type opposite to the first conductivity type, the second conductivity type being N-type; S6. Forming a first electrode (12) on the first emitter portion (3) in ohmic contact with the first emitter portion (3).

22. The preparation method according to claim 21, characterized in that The S4 specifically includes: S41, forming an emitter and a first protective layer (6) on the entire surface of the silicon substrate (1); S42, removing the emitter and the first protective layer (6) on the front side (10) and the second region (B) and the spacer region (C) on the back side of the silicon substrate (1).

23. The preparation method according to claim 22, characterized in that The S5 specifically includes: S51, sequentially growing a tunneling layer (7) and intrinsic polysilicon on the surface of the silicon substrate (1), and performing a second doping treatment, so that the surface of the silicon substrate (1) as a whole forms a tunneling layer (7), a doped polysilicon layer (8) and a second protective layer (9), wherein the doped polysilicon layer (8) has a second conductivity type opposite to the first conductivity type; S52, removing the second protective layer (9) on the front side (10) and the back side of the silicon substrate (1) in the first area (A) and the spacer area (C); S53, removing the first protective layer (6) in the first area (A) and the second protective layer (9) in the second area (B) on the back side of the silicon substrate (1).

24. The preparation method according to claim 23, characterized in that Between S52 and S53, the preparation method further comprises: forming a velvet surface on the front side (10) and the back side of the silicon substrate (1) in the spacer area (C); And / or, the S52 includes: the second protective layer (9) in the first area (A) and the spacer area (C) are removed simultaneously by the same laser, and the laser parameters include: the laser radiation power is 1-50W, and / or the laser wavelength of the laser is 350-1070nm.

25. The preparation method according to claim 21, characterized in that After S5, the preparation method further comprises: depositing a passivation layer or a passivation anti-reflection layer (11) on the front side (10) and the back side of the silicon substrate (1); And / or, in the mask layer forming step, the thickness of the mask layer is 1-100 nm, and the material of the mask layer includes SiO2 or SiNx.

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