Back contact laminated solar cell and preparation method thereof

Abstract

The invention relates to the field of solar cells, and discloses a back contact laminated solar cell and a preparation method thereof. The laminated solar cell has a unique back contact laminated cell structure, and the shading loss of the front electrode can be effectively avoided by adopting a full back electrode contact mode, so that the optical performance of the laminated cell can be remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and particularly to a back-contact tandem solar cell and a preparation method thereof. Background Art

[0002] As a new type of solar cell, the tandem cell can better utilize different wavelengths of the solar spectrum compared with the single-junction solar cell, solve the absorption loss and thermal loss of the single-junction cell, thereby improving the utilization rate of photons and the conversion efficiency of the solar cell, and overcoming the theoretical efficiency limit of the single-junction cell. Theoretical calculations show that the theoretical efficiency of the double-junction tandem cell can reach more than 46%, which is much higher than the theoretical efficiency of the single-crystalline silicon solar cell ~29.4%; therefore, the development of tandem cell technology is of great significance for improving the ultimate efficiency of solar energy, reducing the levelized cost of energy (LCOE) of solar power generation, and promoting the development of the new energy industry.

[0003] Common types of tandem cell structures can be divided into perovskite + crystalline silicon cells (CN118414005A), perovskite + perovskite cells, or perovskite + crystalline silicon + perovskite cells, etc. Although different combinations of cell types can enable the tandem cell to fully absorb incident light of each wavelength to improve the optical performance of the cell, it is still impossible to avoid the shading loss caused by the front electrode, resulting in limited improvement in the optical performance of the tandem cell. Therefore, it is of positive significance to develop a tandem cell that can reduce the shading loss of the front electrode of the cell. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a back-contact tandem solar cell and a preparation method thereof. The tandem solar cell of the present invention has a unique back-contact tandem cell structure, and the full back-electrode contact method can effectively avoid the shading loss of the front electrode, thereby significantly improving the optical performance of the tandem cell.

[0005] The specific technical solution of the present invention is as follows: In a first aspect, the present invention provides a back-contact tandem solar cell, which is a two-terminal wide-bandgap perovskite cell + crystalline silicon cell: from the front to the back of the cell, it includes a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnection layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of the extended area, and there is an isolation area between the positive electrode and the perovskite layer; A negative electrode penetrating the passivation film is provided on the back of the phosphorus-doped layer.

[0006] The preparation method of the above two-terminal wide-bandgap perovskite cell + crystalline silicon cell includes: S1 Prepare a crystalline silicon cell: S1.1, Texturize the front surface of the N-type silicon wafer.

[0007] S1.2. Boron diffusion is carried out to convert the surface of the N-type silicon wafer into a boron-doped layer and a BSG layer, while the undoped part is a phosphorus-doped layer (the N-type silicon wafer is a phosphorus-doped silicon).

[0008] S1.3. Remove the BSG layer deposited on the back and sides. During the boron diffusion process, the back and sides of the silicon wafer also generate a deposited layer. To reduce edge leakage, it is necessary to remove the deposited BSG layer.

[0009] S1.4. Alkaline cleaning to remove the deposited layer: Put the silicon wafer into the alkaline polishing tank to remove the boron-doped layer deposited on the back and sides of the silicon wafer.

[0010] S1.5. Deposit a passivation film on the back. To prevent the deposition of an insulating passivation film on the front of the silicon wafer, which affects the carrier transport between the subsequent perovskite solar cell and the crystalline silicon solar cell, plate-type ALD and PECVD equipment can be selected to deposit AlO x and SiN x passivation films on the back (single side) of the silicon wafer in sequence.

[0011] S1.6. Print the negative electrode paste on the back of the silicon wafer by screen printing, and then sinter it at 700 - 800 °C to form an ohmic contact and form the negative electrode.

[0012] S2. Deposit a hole transport layer on the back of the TCO layer.

[0013] S3. Use a mask to cover the designed areas of the perovskite layer and the isolation area on the back of the hole transport layer.

[0014] S4. Deposit a perovskite layer on the area without a mask on the back of the hole transport layer.

[0015] Preferably, S4 includes: Coating the exposed surface of the hole transport layer with a wide-bandgap perovskite precursor solution, and dropping an antisolvent to promote crystallization; first annealing at 60 - 80 °C in an environment isolated from water vapor and oxygen for the first time, and then annealing at 90 - 110 °C in an air environment with a humidity ≤ 30% RH for the second time to form the perovskite layer.

[0016] Further preferably, S4 includes: adjusting the perovskite composition or ratio according to the desired bandgap width. For wide-bandgap perovskites, halides with higher Br or Cl content can be used, such as MAPbBr3. These halogens have stronger electron affinities and larger energy bandwidths, thus resulting in wider bandgaps. Wide-bandgap perovskites use lead (Pb) as the main metal cation. To adjust the bandgap, tin (Sn) or germanium (Ge) can be doped, such as MAGeBr3. Wide-bandgap perovskites use small-radius cations, such as methylammonium (MA), cesium (Cs). These small cations are beneficial to improving crystal stability and bandgap width. Wide-bandgap perovskites further regulate the bandgap by mixing halogens (such as Br and Cl), such as MAPb(Br x Cl 1-x )3. Subsequently, it is dissolved in an appropriate solvent, such as a mixed solvent of DMF and DMSO, to prepare a uniform and stable wide-bandgap perovskite precursor solution. Subsequently, the precursor solution is uniformly applied to the surface of the hole transport layer using a doctor blade coating technique, and then an antisolvent (such as chlorobenzene) is immediately dropped to promote rapid crystallization. After that, in an environment isolated from water vapor and oxygen, it is first dried at 60 - 80 °C for the first time, and then annealed at 90 - 110 °C in an air environment with a humidity ≤ 30% RH to optimize the film quality and crystal structure.

[0017] S5. Deposit an electron transport layer in a semi-dry state on the surface of the perovskite layer.

[0018] Preferably, S5 includes: coating the electron transport layer precursor solution on the surface of the perovskite layer and drying it to a semi-dry state with a solid content of 10 - 60 wt%.

[0019] If the electron transport layer is in a dry state, the overall hardness of the corresponding perovskite solar cell is relatively large. Coupled with the textured structure on the surface of the crystalline silicon solar cell, it causes the subsequent crystalline silicon solar cell to be unable to closely adhere to the electron transport layer and the interconnect layer (with a smaller contact area), resulting in more voids between the perovskite solar cell and the crystalline silicon solar cell. On the one hand, it will introduce more air impurities, and on the other hand, it will hinder the carrier transport, seriously reducing the performance of the final tandem solar cell. If the initial electron transport layer is in a semi-dry state, during the subsequent covering process of the crystalline silicon solar cell, due to external force extrusion, the electron transport layer, etc. will undergo partial deformation under the action of the external force, and then can form a relatively tight fit with the crystalline silicon solar cell, expelling the air between the layers, which is helpful for the carrier transport between the subsequent perovskite solar cell and the crystalline silicon solar cell.

[0020] Further preferably, S5 includes: dissolving tetrabutyl titanate in an appropriate solvent (such as ethanol, isopropanol, etc.) to prepare an electron transport layer precursor solution. Then, this solution is uniformly coated on the perovskite layer using a doctor blade coating technique. After coating, it is first dried at a low temperature of 50 - 80 °C to make the electron transport layer in a semi-dry state.

[0021] S6. Deposit an interconnection layer on the surface of the electron transport layer in a semi-dry state, and remove the S3 mask.

[0022] S7. Cover the front side of the crystalline silicon cell on the surface of the interconnection layer, and anneal for crystallization.

[0023] Preferably, S7 includes: passing the crystalline silicon cell prepared in S1 through a chain machine to remove the natural oxide layer on the front side of the silicon wafer, wherein the concentration of the HF solution in the chain machine is 20-80 wt%, and the belt speed is 0.5-5 m / min. Immediately afterwards, connect the front side thereof to cover the interconnection layer (the area not covered by the mask layer), and then anneal the whole sample for crystallization to remove the residual solvents in each layer, and the temperature is 100-200 °C.

[0024] S8. Deposit a positive electrode on the surface of the exposed hole transport layer.

[0025] In a second aspect, the present invention provides a back-contact stacked solar cell, which is a four-terminal wide-bandgap perovskite cell + crystalline silicon cell, and includes, from the front side to the back side of the cell, a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnection layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back side of the area where the hole transport layer extends beyond the perovskite layer, and an isolation area is provided between the positive electrode and the perovskite layer; One side of the perovskite layer and the electron transport layer extends beyond the interconnection layer, and a negative electrode is provided on the back side of the area where the electron transport layer extends beyond the interconnection layer, and an isolation area is provided between the negative electrode and the interconnection layer; One side of the interconnection layer and the boron-doped layer extends beyond the phosphorus-doped layer; a positive electrode is provided on the back side of the area where the boron-doped layer extends beyond the phosphorus-doped layer, and an isolation area is provided between the positive electrode and the phosphorus-doped layer; A negative electrode penetrating the passivation film is provided on the back side of the phosphorus-doped layer.

[0026] The preparation method of the above four-terminal wide-bandgap perovskite cell + crystalline silicon cell includes: S1. Prepare a crystalline silicon cell: S1.1. Double-side polish the P-type silicon wafer.

[0027] S1.2. Phosphorus diffusion is carried out to change the back side of the P-type silicon wafer from P-type to N-type, forming a phosphorus-doped layer and a PSG layer, while the front side remains P-type (i.e., the boron-doped layer).

[0028] S1.3. Laser pattern grooving of the PSG layer on the back side.

[0029] S1.4. Remove the PSG layer on the front side and the side. During the phosphorus diffusion process, a diffusion-around layer inevitably appears on the front side and the side of the silicon wafer. In order to prevent the generation of edge leakage, this part needs to be removed.

[0030] S1.5, Cleaning and texturing.

[0031] S1.6, Depositing a passivation film on the back side.

[0032] Preferably, in order to prevent the deposition of an insulating passivation film on the front side of the silicon wafer, which may affect the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation and antireflection films on the back side (one side) of the silicon wafer in sequence.

[0033] S1.7, Forming a negative electrode and a positive electrode on the back side.

[0034] S2, Depositing a hole transport layer on the back side of the TCO layer.

[0035] S3, Using a mask to cover the designed areas of the perovskite layer and its adjacent isolation regions on the back side of the hole transport layer.

[0036] S4, Depositing a perovskite layer on the surface of the exposed hole transport layer.

[0037] Preferably, S4 includes: coating a wide-bandgap perovskite precursor solution on the surface of the exposed hole transport layer, dropping an antisolvent to promote crystallization; first annealing at 60 - 80 °C in an environment isolated from water vapor and oxygen, and then annealing at 90 - 110 °C in an air environment with a humidity ≤ 30% RH to form a perovskite layer.

[0038] More preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Wide-bandgap perovskites can use halides with a higher content of Br or Cl, such as MAPbBr3. These halogens have a stronger electron affinity and a larger energy bandwidth, so the bandgap is wider. Wide-bandgap perovskites use lead (Pb) as the main metal cation. To adjust the bandgap, tin (Sn) or germanium (Ge) can be doped, such as MAGeBr3. Wide-bandgap perovskites use small-radius cations, such as methylammonium (MA), cesium (Cs). These small cations are beneficial to improving crystal stability and bandgap width. Wide-bandgap perovskites further regulate the bandgap by mixing halogens (such as Br and Cl), such as MAPb(Br x Cl 1-x )3. Subsequently, it is dissolved in a suitable solvent, such as a mixed solvent of DMF and DMSO, to prepare a uniform and stable wide-bandgap perovskite precursor solution; then, the precursor solution is uniformly applied on the surface of the hole transport layer using a doctor blade coating technique, and then an antisolvent (such as chlorobenzene) is immediately dropped to promote rapid crystallization. After that, in an environment isolated from water vapor and oxygen, it is first dried at 60 - 80 °C, and then annealed at 90 - 110 °C in an air environment with a humidity ≤ 30% RH to optimize the film quality and crystal structure.

[0039] S5. Deposit an electron transport layer in a semi-dry state on the surface of the perovskite layer, and use a mask to cover the negative electrode and the isolation area design region on the surface of the electron transport layer.

[0040] Preferably, S5 includes: coating the perovskite layer surface with a precursor solution of the electron transport layer and drying it to a semi-dry state with a solid content of 10-60 wt% of the electron transport layer. Immediately afterwards, continue to use a mask (such as a high-temperature insulating tape) to cover the negative electrode and the isolation area design region on the surface of the electron transport layer, so that the subsequent interconnect layer is not deposited in this region and does not cover the crystalline silicon cell.

[0041] More preferably, dissolve tetrabutyl titanate in a suitable solvent (such as ethanol, isopropanol, etc.) to prepare a precursor solution of the electron transport layer. Then use a doctor blade coating technique to uniformly coat this solution onto the perovskite layer. After coating, first perform low-temperature drying at a temperature of 50-80 °C to make the electron transport layer in a semi-dry state.

[0042] S6. Deposit an interconnect layer on the surface of the semi-dry state electron transport layer, and remove the masks of S3 and S5.

[0043] S7. Cover the front side of the crystalline silicon cell on the surface of the interconnect layer and anneal to crystallize.

[0044] Preferably, S7 includes: first removing the natural oxide layer on the front side of the crystalline silicon cell, then covering its front side on the surface of the interconnect layer, and annealing and crystallizing at 100-200 °C to make the semi-dry state electron transport layer fully formed.

[0045] S8. Deposit the positive electrode and the negative electrode.

[0046] In a third aspect, the present invention provides a back-contact stacked solar cell: a two-terminal crystalline silicon cell + narrow-bandgap perovskite cell, which includes a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence from the front side to the back side of the cell; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back side of the region extending beyond the phosphorus-doped layer, and there is an isolation area between the positive electrode and the phosphorus-doped layer; a negative electrode is provided on the back side of the TCO layer.

[0047] The preparation method of the above two-terminal crystalline silicon cell + narrow-bandgap perovskite cell includes the following steps: S1 Prepare a crystalline silicon cell: S1.1. Double-side polish the P-type silicon wafer.

[0048] S1.2. Perform backside phosphorus diffusion to change the back side of the P-type silicon wafer from P-type to N-type.

[0049] S1.3. Perform backside laser patterning to groove the PSG layer.

[0050] S1.4, Remove the front and side PSG layers. During the phosphorus diffusion process, the wrap-around diffusion layers inevitably appear on both the front and side of the silicon wafer. To prevent the generation of edge leakage, this part needs to be removed.

[0051] S1.5, Clean and texture.

[0052] S1.6, Deposit a passivation film on the front.

[0053] S1.7, Form a positive electrode on the back.

[0054] S2, Place the crystalline silicon cell with its back facing up, cover the boron-doped layer area on the back of the crystalline silicon cell with a mask, and deposit an interconnection layer on the surface of the phosphorus-doped layer.

[0055] S3, Deposit a hole transport layer on the surface of the interconnection layer.

[0056] S4, Deposit a perovskite layer on the surface of the hole transport layer.

[0057] Preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Narrow-bandgap perovskites mainly use I, such as MAPbI3. The ionic radius of iodine is relatively large, and the energy band overlap is better, so the bandgap is relatively narrow. For narrow-bandgap perovskites, Sn can be selected to replace part or all of the lead to reduce the bandgap, such as MASnI3. Narrow-bandgap perovskites using large-radius cations, such as formamidine (FA), can reduce the internal stress in the crystal and lower the bandgap. The crystal properties and bandgap width of narrow-bandgap perovskites can be adjusted by co-doping Sn and Pb or Cs and FA. After deposition, anneal and crystallize at 100 - 200 °C to form the perovskite layer.

[0058] S5, Deposit an electron transport layer on the perovskite layer.

[0059] S6, Deposit a TCO layer on the surface of the electron transport layer and remove the mask in S2.

[0060] S7, Deposit a negative electrode.

[0061] Fourthly, the present invention provides a back-contact stacked solar cell, which is a four-terminal crystalline silicon cell + narrow-bandgap perovskite cell, and includes a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnection layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence from the front to the back of the cell; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back of the area extending beyond the phosphorus-doped layer, and an isolation area is between the positive electrode and the phosphorus-doped layer; One side of the phosphorus-doped layer (the same side as the extension area of the boron-doped layer) extends beyond the interconnection layer, and a negative electrode is provided on the back of the area extending beyond the interconnection layer; an isolation area is between the negative electrode and the interconnection layer; One side of the interconnect layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of the extended perovskite region; an isolation region is provided between the positive electrode and the perovskite layer; A negative electrode is provided on the back of the TCO layer.

[0062] The preparation method of the above four-terminal crystalline silicon cell + narrow-bandgap perovskite cell includes the following steps: S1 Prepare a crystalline silicon cell: S1.1, Double-side polish the P-type silicon wafer.

[0063] S1.2, Phosphorus diffusion on the back; convert the back of the P-type silicon wafer from P-type to N-type.

[0064] S1.3, Laser patterning and grooving the PSG layer on the back.

[0065] S1.4, Remove the PSG layer on the front and sides. During the phosphorus diffusion process, a diffusion layer inevitably appears on the front and sides of the silicon wafer. To prevent the generation of edge leakage, this part needs to be removed.

[0066] S1.5, Clean and texture.

[0067] S1.6, Deposit a passivation film on the front.

[0068] S1.7, Form a positive electrode and a negative electrode on the back.

[0069] S2, Place the crystalline silicon cell with the back facing up, cover the non-interconnect layer design area with a mask, and deposit an interconnect layer on the surface of the exposed phosphorus-doped layer.

[0070] S3, Deposit a hole transport layer on the surface of the interconnect layer; cover the non-perovskite layer design area on the surface of the hole transport layer with a mask.

[0071] S4, Deposit a perovskite layer on the surface of the exposed hole transport layer.

[0072] Preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Narrow-bandgap perovskites mainly use iodine, such as MAPbI3. Iodine has a larger ionic radius and better energy band overlap, so the bandgap is narrower. Narrow-bandgap perovskites can choose to replace part or all of the lead with tin to reduce the bandgap, such as MASnI3. Narrow-bandgap perovskites use large-radius cations, such as formamidine (FA), which can reduce the internal stress in the crystal and lower the bandgap. Narrow-bandgap perovskites can adjust the crystal properties and bandgap width through co-doping of Sn and Pb or Cs and FA. After deposition, anneal and crystallize at 100 - 200 °C to form a perovskite layer.

[0073] S5, Deposit an electron transport layer on the perovskite layer.

[0074] S6, Deposit a TCO layer on the surface of the electron transport layer; remove the masks in S2 and S3.

[0075] S7. Deposit the positive electrode and the negative electrode.

[0076] Compared with the prior art, the beneficial effects of the present invention are as follows: The stacked solar cell of the present invention has a unique back-contact stacked cell structure. The full-back electrode contact method can effectively avoid the shading loss of the front electrode, thereby significantly improving the optical performance of the stacked cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a schematic structural diagram of the two-terminal wide-bandgap perovskite cell + crystalline silicon cell of Embodiment 1 of the present invention.

[0078] Figure 2 It is a schematic structural diagram after the silicon wafer is textured in Step 1.1 of Embodiment 1.

[0079] Figure 3 It is a schematic structural diagram after the boron diffusion of the silicon wafer in Step 1.2 of Embodiment 1.

[0080] Figure 4 It is a schematic structural diagram after the BSG layer on the back of the silicon wafer is removed in Step 1.3 of Embodiment 1.

[0081] Figure 5 It is a schematic structural diagram after the silicon wafer is de-plated in Step 1.4 of Embodiment 1.

[0082] Figure 6 It is a schematic structural diagram after the passivation film is deposited on the back of the silicon wafer in Step 1.5 of Embodiment 1.

[0083] Figure 7 It is a schematic structural diagram after the electrode is printed on the back of the silicon wafer in Step 1.6 of Embodiment 1.

[0084] Figure 8 It is a schematic structural diagram after the hole transport layer is deposited on the TCO layer in Step 2 of Embodiment 1.

[0085] Figure 9 It is a schematic structural diagram after the hole transport layer is covered with a mask in Step 3 of Embodiment 1.

[0086] Figure 10 It is a schematic structural diagram after the interconnection layer is deposited in Step 6 of Embodiment 1.

[0087] Figure 11 It is a schematic structural diagram after the mask is removed from the perovskite cell in Step 6 of Embodiment 1.

[0088] Figure 12 It is a schematic structural diagram after the perovskite cell covers the crystalline silicon cell in Step 7 of Embodiment 1.

[0089] Figure 13Schematic diagram of the structure of the annealed crystallization and printed electrode back-contact cell in Step 8 of Example 1.

[0090] Figure 14 Schematic diagram of the structure of the four-terminal wide-bandgap perovskite cell + crystalline silicon cell of Example 2 of the present invention.

[0091] Figure 15 Schematic diagram of the structure of the two-terminal crystalline silicon cell + narrow-bandgap perovskite cell of Example 3 of the present invention.

[0092] Figure 16 Schematic diagram of the structure of the four-terminal crystalline silicon cell + narrow-bandgap perovskite cell of Example 4 of the present invention.

[0093] The reference numerals are: TCO layer 1; hole transport layer 2; perovskite layer 3; electron transport layer 4; interconnect layer 5; boron-doped layer 6; phosphorus-doped layer 7; passivation film 8; negative electrode 9; positive electrode 10; pyramid texture 11; BSG layer 12; mask 13; semi-dry electron transport layer 14. Detailed implementation manners

[0094] The present invention will be further described below in conjunction with the embodiments.

[0095] General embodiment In a first aspect, the present invention provides a back-contact stacked solar cell, which is a two-terminal wide-bandgap perovskite cell + crystalline silicon cell: from the front to the back of the cell, it includes a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnect layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of the extended area, and there is an isolation area between the positive electrode and the perovskite layer; A negative electrode is provided on the back of the phosphorus-doped layer and penetrates through the passivation film.

[0096] The preparation method of the above two-terminal wide-bandgap perovskite cell + crystalline silicon cell includes: S1 Prepare a crystalline silicon cell: S1.1, Texturize the front side of the N-type silicon wafer.

[0097] Preferably, S1.1 includes: selecting an N-type silicon wafer after wire sawing (the N-type silicon wafer can also be called a phosphorus-doped silicon wafer); subjecting the N-type silicon wafer to alkaline texturing treatment to form a light-trapping pyramid texture on its front side; the alkaline texturing conditions are: the concentration of the KOH solution is 1.7-2.2 wt%, the temperature is 75-85 °C, and the time is 5-8 min.

[0098] S1.2, Boron diffusion is carried out to convert the surface of the N-type silicon wafer into a boron-doped layer and a BSG layer, and the undoped part is a phosphorus-doped layer (the N-type silicon wafer is a phosphorus-doped silicon).

[0099] Preferably, the boron diffusion conditions are as follows: diffusion temperature 900 - 950 °C, time 10 - 60 min, BCl3 flow rate 20 - 100 sccm, O2 flow rate 200 - 1000 sccm; oxidation and propulsion temperature 1000 - 1050 °C, O2 flow rate 1000 - 20000 sccm, time 20 - 80 min, and the thickness of the obtained BSG layer is 30 - 80 nm.

[0100] S1.3. Remove the BSG layer on the back and sides that is overplated. During the boron diffusion process, overplated layers also form on the back and sides of the silicon wafer. To reduce edge leakage, it is necessary to remove the overplated BSG layer.

[0101] Preferably, a chain machine is used to remove the BSG layer on the back and sides of the silicon wafer. The concentration of the HF solution in the chain machine is 20 - 80 wt%, and the belt speed is 0.5 - 5 m / min.

[0102] S1.4. Alkaline cleaning to remove overplating: Place the silicon wafer in an alkaline polishing tank to remove the boron-doped layer overplated on the back and sides of the silicon wafer.

[0103] Preferably, the alkaline polishing conditions are as follows: the concentration of the KOH solution is 2.0 - 2.2 wt%, the temperature is 70 - 80 °C, and the time is 3 - 7 min.

[0104] S1.5. Deposit a passivation film on the back. To prevent the deposition of an insulating passivation film on the front of the silicon wafer, which may affect the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, plate-type ALD and PECVD equipment can be selected to deposit AlO x and SiN x passivation films on the back (single side) of the silicon wafer in sequence.

[0105] Preferably, the thicknesses of the AlO x and SiN x passivation films are 5 - 10 nm and 70 - 90 nm respectively.

[0106] S1.6. Print the negative electrode paste on the back of the silicon wafer by screen printing, and then sinter it at 700 - 800 °C to form an ohmic contact and form the negative electrode.

[0107] S2. Deposit a hole transport layer on the back of the TCO layer.

[0108] Preferably, S2 includes: Select a quartz glass with a TCO layer (such as ITO) plated on its surface as the substrate. Subsequently, prepare a hole transport layer precursor solution (such as nano-NiO x particle ink), coat it on the TCO layer, and anneal it at 100 - 200 °C for 5 - 20 min to form the final hole transport layer.

[0109] S3. Design areas of the perovskite layer and the isolation area on the back surface of the hole transport layer are covered with a mask.

[0110] Preferably, S3 includes: covering the design areas of the back perovskite layer and the isolation area by means of a mask (such as a high-temperature insulating tape), so that the subsequent deposition of the perovskite layer, the electron transport layer, etc. is not carried out on this part.

[0111] S4. A perovskite layer is deposited on the mask-free area on the back surface of the hole transport layer.

[0112] Preferably, S4 includes: coating a broadband-gap perovskite precursor solution on the surface of the exposed hole transport layer, and adding an antisolvent to promote crystallization; first annealing at 60-80 °C in an environment isolated from water vapor and oxygen, and then annealing at 90-110 °C in an air environment with a humidity ≤ 30% RH to form a perovskite layer.

[0113] More preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. For broadband-gap perovskites, halides with higher Br or Cl content can be used, such as MAPbBr3. These halogens have stronger electron affinity and larger energy bandwidths, so the bandgap is wider. Broadband-gap perovskites use lead (Pb) as the main metal cation. To adjust the bandgap, tin (Sn) or germanium (Ge) can be doped, such as MAGeBr3. Broadband-gap perovskites use small-radius cations, such as methylammonium (MA), cesium (Cs). These small cations are beneficial to improving crystal stability and bandgap width. The bandgap of broadband-gap perovskites is further regulated by mixing halogens (such as Br and Cl), such as MAPb(Br x Cl 1-x )3. Subsequently, it is dissolved in an appropriate solvent, such as a mixed solvent of DMF and DMSO, to prepare a uniform and stable broadband-gap perovskite precursor solution; then the precursor solution is uniformly applied on the surface of the hole transport layer using a doctor blade coating technique, and then an antisolvent (such as chlorobenzene) is immediately added to promote rapid crystallization. After that, in an environment isolated from water vapor and oxygen, it is first dried at 60-80 °C for the first time, and then annealed at 90-110 °C in an air environment with a humidity ≤ 30% RH for the second time to optimize the film quality and crystal structure.

[0114] S5. A semi-dry electron transport layer is deposited on the surface of the perovskite layer.

[0115] Preferably, S5 includes: coating an electron transport layer precursor solution on the surface of the perovskite layer and drying it to a semi-dry state with a solid content of 10-60 wt%.

[0116] Further preferably, S5 includes: dissolving tetrabutyl titanate in a suitable solvent (such as ethanol, isopropyl alcohol, etc.) to prepare a precursor solution for the electron transport layer. Then, using a blade coating technique, this solution is evenly coated onto the perovskite layer. After coating, first perform low-temperature drying at a temperature of 50 - 80 °C to make the electron transport layer in a semi-dry state.

[0117] S6. Deposit an interconnection layer on the surface of the semi-dry electron transport layer and remove the mask of S3.

[0118] As a preference, S6 includes: depositing an interconnection layer (such as an ITO layer) on the basis of the semi-dry electron transport layer by means of magnetron sputtering, etc., with a thickness of 50 - 200 nm and a refractive index of 1.5 - 2.5. Then remove the mask of S3 so that this area does not cover the perovskite layer, the electron transport layer, and the interconnection layer.

[0119] S7. Cover the front side of the crystalline silicon cell on the surface of the interconnection layer and anneal for crystallization.

[0120] As a preference, S7 includes: removing the natural oxide layer on the front side of the silicon wafer of the crystalline silicon cell prepared in S1 through a chain machine, where the concentration of the HF solution in the chain machine is 20 - 80 wt%, and the belt speed is 0.5 - 5 m / min. Immediately make its front side cover and connect with the interconnection layer (the area not covered by the mask layer), and then anneal and crystallize the entire sample to remove the residual solvents in each layer at a temperature of 100 - 200 °C.

[0121] S8. Deposit a positive electrode on the surface of the exposed hole transport layer.

[0122] As a preference, S8 includes: depositing a low-temperature positive electrode paste on the surface of the exposed part of the hole transport layer of the stacked cell by means of screen printing, etc., and then forming a contact at 100 - 300 °C; since there is already a corresponding negative electrode on the back side (N-type silicon substrate) of the crystalline silicon cell, the entire cell forms a final two-terminal (one positive electrode, one negative electrode) back-contact wide-bandgap perovskite cell + crystalline silicon stacked cell structure.

[0123] In a second aspect, the present invention provides a back-contact stacked solar cell, which is a four-terminal wide-bandgap perovskite cell + crystalline silicon cell, including a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnection layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence from the front side to the back side of the cell; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back side of the area where the hole transport layer extends beyond the perovskite layer, and there is an isolation area between the positive electrode and the perovskite layer; One side of the perovskite layer and the electron transport layer extends beyond the interconnection layer, and a negative electrode is provided on the back side of the area where the electron transport layer extends beyond the interconnection layer, and there is an isolation area between the negative electrode and the interconnection layer; One side of the interconnect layer and the boron-doped layer extends beyond the phosphorus-doped layer; on the back of the region where the boron-doped layer extends beyond the phosphorus-doped layer, there is a positive electrode, and there is an isolation region between the positive electrode and the phosphorus-doped layer; On the back of the phosphorus-doped layer, there is a negative electrode that penetrates the passivation film.

[0124] The preparation method of the above four-terminal wide-bandgap perovskite battery + crystalline silicon battery includes: S1. Prepare a crystalline silicon battery: S1.1. Double-side polish a P-type silicon wafer.

[0125] Preferably, S1.1 includes: Select a P-type silicon wafer after wire sawing (the P-type silicon wafer can also be called a boron-doped silicon wafer). Double-side polish the silicon wafer, where the concentration of the KOH solution is 2.0 - 2.2 wt%, the temperature is 70 - 80 °C, and the time is 3 - 7 min.

[0126] S1.2. Perform phosphorus diffusion to change the back of the P-type silicon wafer from P-type to N-type, forming a phosphorus-doped layer and a PSG layer, while the front remains P-type (i.e., a boron-doped layer).

[0127] Preferably, the conditions for the phosphorus diffusion are: the phosphorus diffusion temperature is 750 - 850 °C, the diffusion time is 10 - 50 min, the flow rate of POCl3 gas is 100 - 300 sccm, and the flow rate of O2 gas is 500 - 3000 sccm; the oxidation and push temperature is 850 - 950 °C, the flow rate of O2 gas is 1000 - 20000 sccm, the push time is 20 - 60 min, and the thickness of the obtained PSG layer is 20 - 60 nm.

[0128] S1.3. Laser pattern grooving on the back PSG layer.

[0129] Preferably, the conditions for the laser patterning treatment are: the laser wavelength is 400 - 600 nm, the frequency is 500 - 700 KHz, the marking speed is 40000 - 50000 mm / s, the power is 10 - 50 W, and the treatment time is 1 - 5 s.

[0130] S1.4. Remove the front and side PSG layers. During the phosphorus diffusion process, a diffusion layer inevitably appears on the front and side of the silicon wafer. To prevent edge leakage, this part needs to be removed.

[0131] Preferably, first use a chain machine to remove the front and side PSG layers of the silicon wafer, where the concentration of the HF solution in the chain machine is 20 - 80 wt%, and the belt speed is 0.5 - 5 m / min.

[0132] S1.5. Clean and texture.

[0133] Preferably, S1.5 includes: putting the silicon wafer into an alkaline texturing bath for integrated cleaning and texturing treatment; First, since the back PSG layer is laser-patterned and grooved in the S3 step, the phosphorus-doped layer at the bottom can be cleaned during the alkaline texturing process until the P-type silicon wafer is exposed. The non-laser-patterned area on the back is protected by the PSG layer, which can protect the phosphorus-doped layer at the bottom from being damaged. In addition, since there is no PSG layer on the front, the phosphorus-doped layer on the front can be etched first during the alkaline texturing process, and then a pyramid-shaped textured surface is formed on the front P-type silicon wafer. The alkaline concentration is 1.5 - 2.2 wt%, the temperature is 75 - 85 °C, and the time is 6 - 8 min. S1.6, deposit a passivation film on the back.

[0134] Preferably, in order to prevent the front of the silicon wafer from also depositing an insulating passivation film, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, a plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation and antireflection films on the back (single side) of the silicon wafer in sequence. Among them, the thicknesses of the AlO x and SiN x passivation films are 5 - 10 nm and 70 - 90 nm respectively.

[0135] S1.7, form a negative electrode and a positive electrode on the back.

[0136] Preferably, S1.7 includes: using screen printing to print a paste (positive electrode) on the P-type back of the silicon wafer and a paste (negative electrode) on the phosphorus-doped layer, and then sintering at 700 - 800 °C to form an ohmic contact. Finally, the back of the semi-finished crystalline silicon cell has a positive and a negative electrode, with a two-terminal structure.

[0137] S2, deposit a hole transport layer on the back of the TCO layer.

[0138] Preferably, S2 includes: selecting a quartz glass with a TCO layer (such as ITO) plated on the surface as the substrate, then preparing a hole transport layer precursor solution (such as nano-NiO x particle ink), then coating it on the ITO glass substrate, and annealing at 100 - 200 °C for 5 - 20 min to form the final hole transport layer.

[0139] S3, cover the designed areas of the perovskite layer and its adjacent isolation areas on the back of the hole transport layer with a mask.

[0140] Preferably, S3 includes: using a mask (such as a high-temperature insulating tape) to cover the designed areas of the perovskite layer and its adjacent isolation areas on the back of the hole transport layer, so that these parts will not deposit perovskite layers, electron transport layers, etc. later.

[0141] S4, deposit a perovskite layer on the surface of the exposed hole transport layer.

[0142] Preferably, S4 includes: coating a wide-bandgap perovskite precursor solution on the surface of the exposed hole transport layer, and dropping an antisolvent to promote crystallization; first annealing at 60-80 °C in an environment isolated from water vapor and oxygen, and then annealing at 90-110 °C in an air environment with a humidity ≤ 30%RH to form a perovskite layer.

[0143] More preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Wide-bandgap perovskites can use halides with higher Br or Cl content, such as MAPbBr3. These halogens have stronger electron affinities and larger energy bandwidths, so the bandgap is wider. Wide-bandgap perovskites use lead (Pb) as the main metal cation. To adjust the bandgap, tin (Sn) or germanium (Ge) can be doped, such as MAGeBr3. Wide-bandgap perovskites use small-radius cations, such as methylammonium (MA), cesium (Cs). These small cations are beneficial to improving crystal stability and bandgap width. The bandgap of wide-bandgap perovskites is further regulated by mixing halogens (such as Br and Cl), such as MAPb(Br x Cl 1-x )3. Subsequently, it is dissolved in a suitable solvent, such as a mixed solvent of DMF and DMSO, to prepare a uniform and stable wide-bandgap perovskite precursor solution; subsequently, the precursor solution is uniformly applied on the surface of the hole transport layer using a doctor blade coating technique, and then an antisolvent (such as chlorobenzene) is immediately dropped to promote rapid crystallization. After that, in an environment isolated from water vapor and oxygen, the first drying is carried out at 60-80 °C, and then the second annealing is carried out at 90-110 °C in an air environment with a humidity ≤ 30%RH to optimize the film quality and crystal structure.

[0144] S5. Deposit a semi-dry electron transport layer on the surface of the perovskite layer, and use a mask to cover the negative electrode and isolation area design regions on the surface of the electron transport layer.

[0145] Preferably, S5 includes: coating an electron transport layer precursor solution on the surface of the perovskite layer and drying it to a semi-dry state with a solid content of 10-60 wt%. Immediately afterwards, continue to use a mask (such as a high-temperature insulating tape) to cover the negative electrode and isolation area design regions on the surface of the electron transport layer, so that the subsequent interconnection layer is not deposited in this area and it is not covered by the crystalline silicon cell.

[0146] More preferably, tetrabutyl titanate is dissolved in a suitable solvent (such as ethanol, isopropanol, etc.) to prepare an electron transport layer precursor solution. Then, this solution is uniformly coated on the perovskite layer using a doctor blade coating technique. After coating, low-temperature drying is first carried out at a temperature of 50-80 °C to make the electron transport layer in a semi-dry state.

[0147] S6. Deposit an interconnection layer on the surface of the electron transport layer in a semi-dry state, and remove the masks of S3 and S5.

[0148] Preferably, a magnetron sputtering or other method is used to deposit an interconnection layer (such as an ITO layer) on the basis of the semi-dry electron transport layer, with a thickness of 50-200 nm and a refractive index of 1.5-2.5. Then, remove the masks of S3 and S5.

[0149] S7. Cover the front side of the crystalline silicon cell on the surface of the interconnection layer and anneal for crystallization.

[0150] Preferably, S7 includes: first remove the natural oxide layer on the front side of the crystalline silicon cell, then cover its front side on the surface of the interconnection layer, and anneal for crystallization at 100-200 °C to completely form the semi-dry state electron transport layer.

[0151] More preferably, S7 includes: passing the crystalline silicon cell through a chain machine to remove the natural oxide layer on the front side of the silicon wafer, where the concentration of the HF solution in the chain machine is 20-80 wt%, and the belt speed is 0.5-5 m / min. Immediately connect its front side to cover the interconnection layer, and then anneal the entire sample for crystallization to remove the residual solvents in each layer, with a temperature of 100-200 °C.

[0152] S8. Deposit the positive electrode and the negative electrode.

[0153] Preferably, S8 includes: using screen printing or other methods to deposit a low-temperature paste (positive electrode) on the surface of the exposed hole transport layer of the stacked cell, and deposit a low-temperature paste (negative electrode) on the surface of the exposed electron transport layer. Then, form a contact at 100-300 °C; since there is already one positive and one negative electrode on the back side (N-type silicon wafer) of the crystalline silicon cell, the entire cell forms a final four-terminal (two positive electrodes, two negative electrodes) back-contact wide-bandgap perovskite cell + crystalline silicon stacked cell structure.

[0154] In a third aspect, the present invention provides a back-contact stacked solar cell: a two-terminal crystalline silicon cell + narrow-bandgap perovskite cell, including a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnection layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence from the front side to the back side of the cell; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back side of the region extending beyond the phosphorus-doped layer, and there is an isolation region between the positive electrode and the phosphorus-doped layer; a negative electrode is provided on the back side of the TCO layer.

[0155] The preparation method of the above two-terminal crystalline silicon cell + narrow-bandgap perovskite cell includes the following steps: S1. Prepare the crystalline silicon cell: S1.1. Double-side polish the P-type silicon wafer.

[0156] Preferably, S1.1 includes: selecting a P-type silicon wafer after being cut by a diamond wire (the P-type silicon wafer can also be called a boron-doped silicon wafer). The silicon wafer is polished on both sides, where the concentration of the KOH solution is 2.0 - 2.2 wt%, the temperature is 70 - 80 °C, and the time is 3 - 7 min.

[0157] S1.2. Perform backside phosphorus diffusion to change the backside of the P-type silicon wafer from P-type to N-type.

[0158] Preferably, the conditions for the phosphorus diffusion are: the phosphorus diffusion temperature is 750 - 850 °C, the diffusion time is 10 - 50 min, the flow rate of POCl3 gas is 100 - 300 sccm, and the flow rate of O2 gas is 500 - 3000 sccm; the oxidation push temperature is 850 - 950 °C, the flow rate of O2 gas is 1000 - 20000 sccm, the push time is 20 - 60 min, and the thickness of the obtained PSG layer is 20 - 60 nm.

[0159] S1.3. Pattern the PSG layer on the backside by laser grooving.

[0160] Preferably, the conditions for the laser patterning process are: the laser wavelength is 400 - 600 nm, the frequency is 500 - 700 KHz, the marking speed is 40000 - 50000 mm / s, the power is 10 - 50 W, and the processing time is 1 - 5 s.

[0161] S1.4. Remove the PSG layer on the front and side surfaces. During the phosphorus diffusion process, a diffusion layer inevitably appears on the front and side surfaces of the silicon wafer. To prevent edge leakage, this part needs to be removed.

[0162] Preferably, a chain machine is used to remove the PSG layer on the front and side surfaces of the silicon wafer, where the concentration of the HF solution in the chain machine is 20 - 80 wt%, and the belt speed is 0.5 - 5 m / min.

[0163] S1.5. Clean and texture.

[0164] Preferably, the silicon wafer is placed in an alkaline texturing tank for integrated cleaning and texturing treatment; First, since the backside PSG layer is grooved by laser in step S3, the phosphorus-doped layer at the bottom can be cleaned during the alkaline texturing process until the P-type silicon wafer is exposed. The non-laser-patterned area on the backside can protect the phosphorus-doped layer at the bottom from being damaged due to the protection of the PSG layer. In addition, since there is no PSG layer on the front side, the phosphorus-doped layer on the front side can be corroded first during the alkaline texturing process, and then a pyramid-shaped textured surface is formed on the front P-type silicon wafer. The alkaline concentration is 1.5 - 2.2 wt%, the temperature is 75 - 85 °C, and the time is 6 - 8 min. S1.6. Deposit a passivation film on the front side.

[0165] Preferably, S1.6 includes: In order to prevent the deposition of an insulating passivation film on the back side of the silicon wafer, which may affect the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation films on the front side (single side) of the silicon wafer in sequence. Among them, the thicknesses of the AlO x and SiN x passivation films are 5 - 10 nm and 70 - 90 nm respectively.

[0166] S1.7. Form the positive electrode on the back side.

[0167] Preferably, S1.7 includes: Use screen printing to print the paste (positive electrode) on the back side of the P-type silicon wafer. Since the phosphorus-doped layer region needs to be connected to the subsequent perovskite cell, there is no need to print the electrode. Then, sinter at 700 - 800 °C to form an ohmic contact.

[0168] S2. Place the crystalline silicon cell with the back side facing up, cover the boron-doped layer region on the back side of the crystalline silicon cell with a mask, and deposit an interconnection layer on the surface of the phosphorus-doped layer.

[0169] Preferably, S2 includes: Using the crystalline silicon cell as a substrate, place the crystalline silicon cell with the back side facing up. First, use a mask (such as a high-temperature insulating tape) to cover the boron-doped layer region on the back side of the crystalline silicon cell, so that this layer will not deposit the interconnection layer and part of the perovskite cell subsequently. Then, deposit an interconnection layer (such as an ITO layer) on this basis by means of magnetron sputtering, etc. Its thickness is 50 - 200 nm and the refractive index is 1.5 - 2.5.

[0170] S3. Deposit a hole transport layer on the surface of the interconnection layer.

[0171] Preferably, S3 includes: Prepare a precursor solution for the hole transport layer of the perovskite cell (such as nano-NiO x particle ink), then coat it on the interconnection layer on the back side of the cell, and anneal at 100 - 200 °C for 5 - 20 min to form a hole transport layer.

[0172] S4. Deposit a perovskite layer on the surface of the hole transport layer.

[0173] Preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Narrow-bandgap perovskites mainly use I, such as MAPbI3. Iodine has a relatively large ionic radius, better energy band overlap, and thus a narrower bandgap. For narrow-bandgap perovskites, Sn can be selected to replace part or all of Pb to reduce the bandgap, such as MASnI3. Using large-radius cations, such as formamidinium (FA), in narrow-bandgap perovskites can reduce the internal stress in the crystal and lower the bandgap. The crystal properties and bandgap width of narrow-bandgap perovskites can be adjusted by co-doping of Sn and Pb or co-doping of Cs and FA. After deposition, annealing crystallization is carried out at 100-200 °C to form the perovskite layer.

[0174] S5. Deposit an electron transport layer on the perovskite layer.

[0175] Preferably, S5 includes: dissolving tetrabutyl titanate in a suitable solvent (such as ethanol, isopropanol, etc.) to prepare a precursor solution for the electron transport layer. Use a doctor blade coating technique to uniformly coat it on the perovskite layer. After coating, annealing crystallization is carried out to remove the residual solvent at a temperature of 100-200 °C to form the electron transport layer.

[0176] S6. Deposit a TCO layer on the surface of the electron transport layer and remove the S2 mask.

[0177] Preferably, a TCO layer (such as an ITO layer) is deposited on the surface of the electron transport layer by means of magnetron sputtering or the like, with a thickness of 50-200 nm and a refractive index of 1.5-2.5.

[0178] S7. Deposit the negative electrode.

[0179] Preferably, S8 includes: depositing a low-temperature paste (negative electrode) on the surface of the TCO layer of the tandem cell by means of screen printing or the like, and then forming a contact at 100-300 °C; since the positive electrode already exists on the left side (P-type silicon wafer) of the crystalline silicon cell, the entire cell forms a final two-terminal (one positive electrode and one negative electrode) back-contact crystalline silicon cell + narrow-bandgap perovskite tandem cell structure.

[0180] Fourthly, the present invention provides a back-contact tandem solar cell, which is a four-terminal crystalline silicon cell + narrow-bandgap perovskite cell, and includes a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnecting layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence from the front side to the back side of the cell; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back side of the region extending beyond the phosphorus-doped layer, and an isolation region is provided between the positive electrode and the phosphorus-doped layer; One side of the phosphorus-doped layer (the same side as the extension region of the boron-doped layer) extends beyond the interconnecting layer, and a negative electrode is provided on the back side of the region extending beyond the interconnecting layer; an isolation region is provided between the negative electrode and the interconnecting layer; One side of the interconnect layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of the extended perovskite region; an isolation region is provided between the positive electrode and the perovskite layer; A negative electrode is provided on the back of the TCO layer.

[0181] The preparation method of the above four-terminal crystalline silicon cell + narrow-bandgap perovskite cell includes the following steps: S1 Prepare a crystalline silicon cell: S1.1, Double-sided polishing of P-type silicon wafers.

[0182] Preferably, S1.1 includes: Selecting a P-type silicon wafer after wire saw cutting (the P-type silicon wafer can also be called a boron-doped silicon wafer). Double-sided polishing the silicon wafer, where the concentration of the KOH solution is 2.0 - 2.2 wt%, the temperature is 70 - 80 °C, and the time is 3 - 7 min.

[0183] S1.2, Backside phosphorus diffusion; converting the backside of the P-type silicon wafer from P-type to N-type.

[0184] Preferably, the conditions for the phosphorus diffusion are: phosphorus diffusion temperature 750 - 850 °C, diffusion time 10 - 50 min, POCl3 gas flow rate 100 - 300 sccm, O2 gas flow rate 500 - 3000 sccm; oxidation push temperature 850 - 950 °C, O2 gas flow rate 1000 - 20000 sccm, push time 20 - 60 min, and the thickness of the obtained PSG layer is 20 - 60 nm.

[0185] S1.3, Backside laser patterning to groove the PSG layer.

[0186] Preferably, the conditions for the laser patterning treatment are: laser wavelength 400 - 600 nm, frequency 500 - 700 KHz, marking speed 40000 - 50000 mm / s, power 10 - 50 W, and treatment time 1 - 5 s.

[0187] S1.4, Remove the PSG layer on the front and side. During the phosphorus diffusion process, it is inevitable that a diffusion layer appears on the front and side of the silicon wafer. To prevent edge leakage, this part needs to be removed.

[0188] Preferably, a chain machine is used to remove the PSG layer on the front and side of the silicon wafer, where the concentration of the HF solution in the chain machine is 20 - 80 wt%, and the belt speed is 0.5 - 5 m / min.

[0189] S1.5, Cleaning and texturing.

[0190] Preferably, the silicon wafer is placed in an alkaline texturing tank for integrated cleaning and texturing treatment; first, since the back PSG layer is laser-patterned and grooved in step S3, the phosphorus-doped layer at the bottom can be cleaned during the alkaline texturing process until the P-type silicon wafer is exposed. The non-laser-patterned area on the back is protected by the PSG layer, which can protect the phosphorus-doped layer at the bottom from being damaged. In addition, since there is no PSG layer on the front, the phosphorus-doped layer on the front can be corroded first during the alkaline texturing process, and then a pyramid-shaped textured surface is formed on the front P-type silicon wafer. The alkaline concentration is 1.5 - 2.2 wt%, the temperature is 75 - 85 °C, and the time is 6 - 8 minutes. S1.6. Deposit a passivation film on the front surface.

[0191] Preferably, S1.6 includes: in order to prevent the back of the silicon wafer from also depositing an insulating passivation film, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, a plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation films on the front surface (single side) of the silicon wafer in sequence. Among them, the thicknesses of the AlO x and SiN x passivation films are 5 - 10 nm and 70 - 90 nm respectively.

[0192] S1.7. Form the positive electrode and negative electrode on the back.

[0193] Preferably, S1.7 includes: using screen printing to print the paste (positive electrode) on the back of the P-type silicon wafer. Since most areas of the phosphorus-doped layer need to be connected to the subsequent perovskite cell, screen printing electrodes (negative electrodes) are only carried out on the left part of the phosphorus-doped layer, and then sintered at 700 - 800 °C to form an ohmic contact.

[0194] S2. Place the crystalline silicon cell with the back facing up, cover the non-interconnection layer design area with a mask, and deposit an interconnection layer on the exposed phosphorus-doped layer surface.

[0195] Preferably, S2 includes: using the crystalline silicon cell as a substrate, placing the back of the crystalline silicon cell facing up. First, use a mask (such as a high-temperature insulating tape) to block the non-interconnection layer area on the back of the crystalline silicon cell, so that this layer will not deposit the interconnection layer and the perovskite cell part subsequently. Then, use magnetron sputtering or other methods to deposit an interconnection layer (such as an ITO layer) on this basis, with a thickness of 50 - 200 nm and a refractive index of 1.5 - 2.5.

[0196] S3. Deposit a hole transport layer on the interconnection layer surface; cover the non-perovskite layer design area on the hole transport layer surface with a mask.

[0197] Preferably, S3 includes: preparing a precursor solution for the hole transport layer of the perovskite cell (such as nano-NiO xThe particulate ink is then coated on the back interconnect layer of the battery and annealed at 100-200 °C for 5-20 min to form a hole transport layer. Immediately afterwards, a mask is used to block the non-perovskite layer design area of the hole transport layer so that the perovskite layer, electron transport layer, etc. are not deposited in this area subsequently.

[0198] S4. Deposit a perovskite layer on the surface of the exposed hole transport layer.

[0199] Preferably, S4 includes: adjusting the perovskite composition or ratio according to the required bandgap width. Narrow-bandgap perovskites mainly use iodine, such as MAPbI3. The ionic radius of iodine is relatively large, and the energy band overlap is better, so the bandgap is relatively narrow. For narrow-bandgap perovskites, tin can be selected to replace part or all of lead to reduce the bandgap, such as MASnI3. Narrow-bandgap perovskites use large-radius cations, such as formamidine (FA), which can reduce the internal stress in the crystal and lower the bandgap. The crystal properties and bandgap width of narrow-bandgap perovskites can be adjusted by co-doping of Sn and Pb or co-doping of Cs and FA. After deposition, annealing crystallization is carried out at 100-200 °C to form a perovskite layer.

[0200] S5. Deposit an electron transport layer on the perovskite layer.

[0201] Preferably, S5 includes: dissolving tetrabutyl titanate in a suitable solvent (such as ethanol, isopropanol, etc.) to prepare a precursor solution for the electron transport layer. It is uniformly coated on the perovskite layer by doctor blade coating technology. After coating, annealing crystallization is carried out to remove the residual solvent at a temperature of 100-200 °C to form an electron transport layer.

[0202] S6. Deposit a TCO layer on the surface of the electron transport layer; remove the masks of S2 and S3.

[0203] Preferably, S6 includes: depositing a TCO layer (such as an ITO layer) on the basis of the semi-dry electron transport layer by magnetron sputtering or other methods, with a thickness of 50-200 nm and a refractive index of 1.5-2.5. Then remove the masks of S2 and S3.

[0204] S7. Deposit the positive electrode and negative electrode.

[0205] Preferably, S8 includes: depositing a low-temperature paste (positive electrode) on the hole transport surface of the perovskite battery by screen printing or other methods, depositing a low-temperature paste (negative electrode) on the surface of the TCO layer, and then forming a contact at 100-300 °C; since the positive electrode and negative electrode already exist in the crystalline silicon battery, the entire battery forms a final four-terminal (two positive electrodes, two negative electrodes) back-contact crystalline silicon battery + narrow-bandgap perovskite tandem battery structure.

[0206] Specific examples and comparative examples Example 1 A back-contact tandem solar cell, which is a two-terminal wide-bandgap perovskite cell + crystalline silicon cell: as Figure 1 shown, from the front to the back of the cell, it includes a TCO layer 1, a hole transport layer 2, a perovskite layer 3, an electron transport layer 4, an interconnect layer 5, a boron-doped layer 6, a phosphorus-doped layer 7, and a passivation film 8 stacked in sequence; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode 10 is provided on the back of the extended area, and there is an isolation area between the positive electrode and the perovskite layer; A negative electrode 9 penetrating the passivation film is provided on the back of the phosphorus-doped layer.

[0207] The preparation method of the above two-terminal wide-bandgap perovskite cell + crystalline silicon cell includes: S1. Prepare a crystalline silicon cell: S1.1. Texturize the front side of the N-type silicon wafer. As Figure 2 shown, select the N-type silicon wafer after wire sawing (the N-type silicon wafer can also be called a phosphorus-doped silicon wafer); subject the N-type silicon wafer to alkali texturing treatment to form a light-trapping pyramid texture 11 on its front side; the alkali texturing conditions are: the concentration of the KOH solution is 1.7 wt%, the temperature is 80 °C, and the time is 7 min.

[0208] S1.2. Boron diffusion, as Figure 3 shown, convert the surface of the N-type silicon wafer into a boron-doped layer 6 and a BSG layer 12, and the undoped part is a phosphorus-doped layer 7 (the N-type silicon wafer is a phosphorus-doped silicon). The boron diffusion conditions are: the diffusion temperature is 930 °C, the time is 20 min, the BCl3 flow rate is 50 sccm, and the O2 flow rate is 800 sccm; the oxidation push temperature is 1050 °C, the O2 flow rate is 7000 sccm, and the time is 60 min. The thickness of the obtained BSG layer is about 50 nm.

[0209] S1.3. As Figure 4 shown, use a chain machine to remove the BSG layer 12 on the back and side of the silicon wafer, where the concentration of the HF solution in the chain machine is 40 wt% and the belt speed is 3 m / min.

[0210] S1.4. As Figure 5 shown, alkali cleaning to remove the bypass plating: put the silicon wafer into an alkali polishing tank to remove the boron-doped layer 6 bypassed on the back and side of the silicon wafer. The alkali polishing conditions are: the concentration of the KOH solution is 2.0 wt%, the temperature is 75 °C, and the time is 5 min.

[0211] S1.5. As Figure 6 shown, deposit a passivation film 8 on the back: in order to prevent the insulating passivation film from being deposited on the front side of the silicon wafer, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, so a plate-type ALD and PECVD equipment can be selected to deposit AlO x and SiN xPassivation film. AlO x and SiN x The thicknesses of the passivation films are approximately 8 nm and 82 nm, respectively.

[0212] S1.6. As Figure 7 shown, the negative electrode paste is printed on the back of the silicon wafer by screen printing, and then sintered at 750 °C to form an ohmic contact, forming the negative electrode 9.

[0213] S2. Deposit the hole transport layer 2 on the back of the TCO layer 1: Select a quartz glass with a TCO layer (ITO) plated on the surface as the substrate, and then prepare a hole transport layer precursor solution (nano NiO x particle ink), coat it on the TCO layer, and anneal it at 180 °C for 12 min to form the final hole transport layer, as Figure 8 shown.

[0214] S3. By using the mask 13 (high-temperature insulating tape), the designed areas of the back perovskite layer and the isolation area are blocked, so that the perovskite layer, electron transport layer, etc. will not be deposited on this part subsequently, as Figure 9 shown.

[0215] S4. Subsequently, deposit a wide-bandgap perovskite layer on the hole transport layer. The preparation formula is: Select methylammonium bromide (MABr, CH3NH3Br), methylammonium chloride (MACl, CH3NH3Cl), lead bromide (PbBr2), and lead chloride (PbCl2). The solvent is N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO), which are fully mixed according to a volume ratio of 9:1. Dissolve 0.2 mmol MABr and 0.8 mmol MACl in 1 mL of DMF:DMSO (9:1), and stir well until transparent. Lead salt solution: Dissolve 0.2 mmol PbBr2 and 0.8 mmol PbCl2 in 1 mL of DMF:DMSO (9:1), and heat and stir at 60 °C until dissolved. Mix the two solutions in a volume ratio of 1:1 to obtain the precursor solution. Subsequently, use the doctor blade coating technique to uniformly apply the precursor solution on the surface of the hole transport layer. After that, in an environment isolated from water vapor and oxygen, first dry it at 65 °C for the first time, and then anneal it at 105 °C in an air environment with a humidity of 5% RH for the second time to form the final perovskite layer, with the chemical formula MAPb(Br 0.2 Cl 0.8 )3.

[0216] S5. Dissolve tetrabutyl titanate in an appropriate solvent (ethanol) to prepare an electron transport layer precursor solution. Then use the doctor blade coating technique to uniformly coat this solution on the perovskite layer. After coating, first perform low-temperature drying at a temperature of 60 °C to form a semi-dry electron transport layer 14 (solid content 35 wt%).

[0217] S6. As shown in Figure 10 , the interconnection layer 5 (ITO layer) is deposited on the semi-dry electron transport layer by magnetron sputtering. Its thickness is about 55 nm and the refractive index is 1.7. Then, the mask in S3 is removed so that this area is not covered with the perovskite layer, the electron transport layer, and the interconnection layer, as shown in Figure 11 .

[0218] S7. The natural oxide layer on the front of the silicon wafer of the crystalline silicon cell prepared in S1 is removed by a chain machine. The concentration of the HF solution in the chain machine is 30 wt%, and the belt speed is 4 m / min. Immediately afterwards, its front is covered and connected to the interconnection layer (the area not covered by the mask layer) (as shown in Figure 12 ), and then the whole sample is annealed and crystallized to remove the residual solvents in each layer, and the temperature is 160 °C.

[0219] S8. A low-temperature positive electrode paste is deposited on the surface of the hole transport layer (exposed part) of the stacked cell by screen printing, and then contact is formed at 200 °C; since the corresponding negative electrode already exists on the back of the crystalline silicon cell (N-type silicon substrate), the whole cell forms a final two-terminal (one positive electrode and one negative electrode) back-contact wide-bandgap perovskite cell + crystalline silicon stacked cell structure, as shown in Figure 13 .

[0220] Example 2 A back-contact stacked solar cell, which is a four-terminal wide-bandgap perovskite cell + crystalline silicon cell, as shown in Figure 14 , from the front to the back of the cell, it includes a TCO layer 1, a hole transport layer 2, a perovskite layer 3, an electron transport layer 4, an interconnection layer 5, a boron-doped layer 6, a phosphorus-doped layer 7, and a passivation film 8 stacked in sequence; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer. A positive electrode is provided on the back of the area where the hole transport layer extends beyond the perovskite layer, and there is an isolation area between the positive electrode 10 and the perovskite layer; One side of the perovskite layer and the electron transport layer extends beyond the interconnection layer. A negative electrode 11 is provided on the back of the area where the electron transport layer extends beyond the interconnection layer, and there is an isolation area between the negative electrode and the interconnection layer; One side of the interconnection layer and the boron-doped layer extends beyond the phosphorus-doped layer; a positive electrode is provided on the back of the area where the boron-doped layer extends beyond the phosphorus-doped layer, and there is an isolation area between the positive electrode and the phosphorus-doped layer; A negative electrode penetrating the passivation film is provided on the back of the phosphorus-doped layer.

[0221] The preparation method of the above four-terminal wide-bandgap perovskite cell + crystalline silicon cell includes: S1. Prepare a crystalline silicon cell: S1.1. Double-sided polishing of P-type silicon wafers: Select P-type silicon wafers after being cut by diamond wire (P-type silicon wafers can also be called boron-doped silicon wafers). Perform double-sided polishing on the silicon wafers, where the concentration of the KOH solution is 2.0 wt%, the temperature is 75 °C, and the time is 5 min.

[0222] S1.2. Phosphorus diffusion to convert the back side of the P-type silicon wafer from P-type to N-type, forming a phosphorus-doped layer and a PSG layer, while the front side remains P-type (i.e., a boron-doped layer). The conditions for phosphorus diffusion are: phosphorus diffusion temperature 790 °C, diffusion time 20 min, POCl3 gas flow rate 150 sccm, O2 gas flow rate 2000 sccm; oxidation push temperature 890 °C, O2 gas flow rate 7000 sccm, push time 40 min, and the thickness of the obtained PSG layer is about 38 nm.

[0223] S1.3. Laser patterning and grooving of the PSG layer on the back side. The conditions for laser patterning are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0224] S1.4. First, use a chain machine to remove the PSG layer on the front and side surfaces of the silicon wafer, where the concentration of the HF solution in the chain machine is 30 wt% and the belt speed is 4 m / min.

[0225] S1.5. Cleaning and texturing. Place the silicon wafer in an alkaline texturing tank for integrated cleaning and texturing treatment; first, since the PSG layer on the back side is laser-patterned and grooved in step S3, the phosphorus-doped layer at the bottom can be cleaned during the alkaline texturing process until the P-type silicon wafer is exposed, while the non-laser-patterned area on the back side can protect the phosphorus-doped layer at the bottom from being damaged due to the protection of the PSG layer. In addition, since there is no PSG layer on the front side, the phosphorus-doped layer on the front side can be etched first during the alkaline texturing process, and then a pyramid texture surface is formed on the front P-type silicon wafer. The alkaline concentration is 1.7 wt%, the temperature is 80 °C, and the time is 7 min.

[0226] S1.6. To prevent the deposition of an insulating passivation film on the front side of the silicon wafer, which affects the carrier transport between the subsequent perovskite battery and the crystalline silicon battery, a plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation and antireflection films on the back side (single side) of the silicon wafer. The thicknesses of the AlO x and SiN x passivation films are about 8 nm and 82 nm, respectively.

[0227] S1.7. Use screen printing to print the paste (positive electrode) on the P-type back side of the silicon wafer and print the paste (negative electrode) on the phosphorus-doped layer, and then sinter at 750 °C to form an ohmic contact. Finally, the back side of the semi-finished crystalline silicon battery has a positive and a negative electrode, with a two-terminal structure.

[0228] S2. Select quartz glass with a surface-coated TCO layer (ITO) as the substrate. Subsequently, prepare a hole transport layer precursor solution (nano NiO x particle ink), then coat it on the ITO glass substrate and anneal it at 180 °C for 12 min to form the final hole transport layer.

[0229] S3. Use a mask (high-temperature insulating tape) to block the designed areas of the perovskite layer and its adjacent isolation areas on the back of the hole transport layer, so that the perovskite layer, electron transport layer, etc. will not be deposited on this part subsequently.

[0230] S4. Subsequently, deposit a wide-bandgap perovskite layer on the hole transport layer. The preparation formula is as follows: Select methylammonium bromide (MABr, CH3NH3Br), methylammonium chloride (MACl, CH3NH3Cl), lead bromide (PbBr2), and lead chloride (PbCl2). The solvents are N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO), which are fully mixed according to a volume ratio of 9:1. Dissolve 0.2 mmol MABr and 0.8 mmol MACl in 1 mL of DMF:DMSO (9:1) and stir well until transparent. Lead salt solution: Dissolve 0.2 mmol PbBr2 and 0.8 mmol PbCl2 in 1 mL of DMF:DMSO (9:1) and heat and stir at 60 °C until dissolved. Mix the two solutions in a volume ratio of 1:1 to obtain the precursor solution. Subsequently, use the doctor blade coating technique to uniformly apply the precursor solution on the surface of the hole transport layer. Then, in an environment isolated from water vapor and oxygen, first dry it at 65 °C for the first time, and then anneal and crystallize it at 105 °C in an air environment with a humidity of 5% RH to form the final perovskite layer with the chemical formula MAPb(Br 0.2 Cl 0.8 )3.

[0231] S5. Dissolve tetrabutyl titanate in an appropriate solvent (ethanol) to prepare an electron transport layer precursor solution. Then use the doctor blade coating technique to uniformly coat this solution on the perovskite layer. After coating, first perform low-temperature drying at a temperature of 60 °C to make the electron transport layer in a semi-dry state with a solid content of 35 wt%.

[0232] S6. Deposit an interconnection layer (ITO layer) with a thickness of 55 nm and a refractive index of 1.7 on the semi-dry electron transport layer by magnetron sputtering. Then remove the masks in S3 and S5.

[0233] S7. Remove the natural oxide layer on the front side of the crystalline silicon cell through a chain machine, where the concentration of the HF solution in the chain machine is 30 wt%, and the belt speed is 4 m / min. Immediately connect its front side to the interconnection layer, and then anneal and crystallize the entire sample to remove the residual solvents in each layer at a temperature of 160 °C.

[0234] S8. Deposit low-temperature paste (positive electrode) on the surface of the exposed hole transport layer of the stacked cell and low-temperature paste (negative electrode) on the surface of the exposed electron transport layer by screen printing. Then form contacts at 200 °C; since there is already a positive and a negative electrode on the back side (N-type silicon wafer) of the crystalline silicon cell, the entire cell forms a final four-terminal (two positive electrodes, two negative electrodes) back-contact wide-bandgap perovskite cell + crystalline silicon stacked cell structure.

[0235] Example 3 A back-contact stacked solar cell: a two-terminal crystalline silicon cell + narrow-bandgap perovskite cell, as Figure 15 shown, including a passivation film 8, a boron-doped layer 6, a phosphorus-doped layer 7, an interconnection layer 5, a hole transport layer 2, a perovskite layer 3, an electron transport layer 4, and a TCO layer 1 stacked in sequence from the front side to the back side of the cell; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode 10 is provided on the back side of the area extending beyond the phosphorus-doped layer. There is an isolation area between the positive electrode and the phosphorus-doped layer; a negative electrode 9 is provided on the back side of the TCO layer.

[0236] The preparation method of the above two-terminal crystalline silicon cell + narrow-bandgap perovskite cell includes the following steps: S1. Prepare a crystalline silicon cell: S1.1. Double-sided polishing of the P-type silicon wafer: Select a P-type silicon wafer after diamond wire cutting (the P-type silicon wafer can also be called a boron-doped silicon wafer). Double-sided polish the silicon wafer with a KOH solution concentration of 2.0 wt%, a temperature of 75 °C, and a time of 5 min.

[0237] S1.2. Phosphorus diffusion on the back side to convert the back side of the P-type silicon wafer from P-type to N-type. The phosphorus diffusion temperature is 790 °C, the diffusion time is 20 min, the flow rate of POCl3 gas is 150 sccm, and the flow rate of O2 gas is 2000 sccm; the oxidation push temperature is 890 °C, the flow rate of O2 gas is 7000 sccm, and the push time is 40 min. The thickness of the obtained PSG layer is about 38 nm.

[0238] S1.3. Laser patterning and grooving of the PSG layer on the back side. The conditions for laser patterning are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0239] S1.4. Remove the PSG layer on the front and side of the silicon wafer using a chain machine, where the concentration of the HF solution in the chain machine is 30 wt%, and the belt speed is 4 m / min.

[0240] S1.5. Cleaning and texturing: Place the silicon wafer in an alkaline texturing tank for integrated cleaning and texturing treatment; First, since the back PSG layer is laser-patterned in step S3, the phosphorus-doped layer at the bottom can be cleaned during the alkaline texturing process until the P-type silicon wafer is exposed. The non-laser-patterned area on the back can protect the phosphorus-doped layer at the bottom from being damaged due to the protection of the PSG layer. In addition, since there is no PSG layer on the front, the phosphorus-doped layer on the front can be etched first during the alkaline texturing process, and then a pyramid-shaped textured surface is formed on the front P-type silicon wafer. The alkaline concentration is 1.7 wt%, the temperature is 80 °C, and the time is 7 min.

[0241] S1.6. To prevent the deposition of an insulating passivation film on the back of the silicon wafer, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, a plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation films on the front (single side) of the silicon wafer in sequence. The thicknesses of the AlO x and SiN x passivation films are approximately 8 nm and 82 nm respectively.

[0242] S1.7. Use screen printing to print the paste (positive electrode) on the back of the P-type silicon wafer. Since the phosphorus-doped layer area needs to be connected to the subsequent perovskite cell, there is no need to print the electrode, and then sinter at 750 °C to form an ohmic contact.

[0243] S2. With the crystalline silicon cell as the substrate, place the crystalline silicon cell with the back facing up. First, use a mask (high-temperature insulating tape) to cover the boron-doped layer area on the back of the crystalline silicon cell, so that this layer will not deposit the interconnection layer and the perovskite cell part subsequently. Then, use magnetron sputtering to deposit an interconnection layer (ITO layer) on this basis, with a thickness of 55 nm and a refractive index of 1.7.

[0244] S3. Prepare the precursor solution (nano-NiO x particle ink) for the hole transport layer of the perovskite cell, then coat it on the interconnection layer on the back of the cell, and anneal at 180 °C for 12 min to form the hole transport layer.

[0245] S4. Subsequently, a narrow-bandgap perovskite layer is deposited on the hole transport layer. The preparation formula is as follows: Select materials such as SnI2 (stannous iodide), MAI (methylammonium iodide, CH3NH3I), and HI (hydroiodic acid) for use. Then, N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO) are mixed in a volume ratio of 4:1 as the solvent. Subsequently, SnI2, MAI, and HI are added to the DMF / DMSO mixed solvent in a volume ratio of 1:1:2, sealed, and magnetically stirred (60 °C, 6 h) until the solution becomes clear and transparent. Then, the solution is coated on the hole transport layer by doctor blade coating, and after annealing treatment, it is annealed at 100 °C for 20 min to remove the residual solvent and form the final dense perovskite crystal phase with the chemical formula MASnI3.

[0246] S5. Dissolve tetrabutyl titanate in a suitable solvent (isopropanol) to prepare a precursor solution for the electron transport layer. Use the doctor blade coating technique to uniformly coat it on the perovskite layer. After coating, annealing crystallization is carried out to remove the residual solvent at a temperature of 160 °C to form the electron transport layer.

[0247] S6. Deposit a TCO layer (ITO layer) on the surface of the electron transport layer by magnetron sputtering, with a thickness of 55 nm and a refractive index of 1.7.

[0248] S7. Deposit a low-temperature paste (negative electrode) on the surface of the TCO layer of the stacked cell by screen printing, and then form a contact at 200 °C. Since the positive electrode already exists on the left side (P-type silicon wafer) of the crystalline silicon cell, the entire cell forms a final two-terminal (one positive electrode and one negative electrode) back-contact crystalline silicon cell + narrow-bandgap perovskite stacked cell structure.

[0249] Example 4 A back-contact stacked solar cell, which is a four-terminal crystalline silicon cell + narrow-bandgap perovskite cell, as Figure 16 shown, from the front to the back of the cell, it includes a passivation film 8, a boron-doped layer 6, a phosphorus-doped layer 7, an interconnect layer 5, a hole transport layer 2, a perovskite layer 3, an electron transport layer 4, and a TCO layer 1 stacked in sequence; One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode 10 is provided on the back of the region extending beyond the phosphorus-doped layer, and an isolation region is between the positive electrode and the phosphorus-doped layer; One side of the phosphorus-doped layer (the same side as the extended region of the boron-doped layer) extends beyond the interconnect layer, and a negative electrode 9 is provided on the back of the region extending beyond the interconnect layer; an isolation region is between the negative electrode and the interconnect layer; One side of the interconnect layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode 10 is provided on the back of the region extending beyond the perovskite region; an isolation region is between the positive electrode and the perovskite layer; A negative electrode 9 is provided on the back of the TCO layer.

[0250] The preparation method of the above four-terminal crystalline silicon cell + narrow-bandgap perovskite cell comprises the following steps: S1 Prepare a crystalline silicon cell: S1.1 Double-sided polishing of a P-type silicon wafer: Select a P-type silicon wafer after wire saw cutting (the P-type silicon wafer can also be called a boron-doped silicon wafer). Double-sided polish the silicon wafer, wherein the concentration of the KOH solution is 2.0 wt%, the temperature is 75 °C, and the time is 5 min.

[0251] S1.2 Backside phosphorus diffusion; convert the backside of the P-type silicon wafer from P-type to N-type. The conditions for phosphorus diffusion are: phosphorus diffusion temperature 790 °C, diffusion time 20 min, POCl3 gas flow rate 150 sccm, O2 gas flow rate 2000 sccm; oxidation push temperature 890 °C, O2 gas flow rate 7000 sccm, push time 40 min, and the thickness of the obtained PSG layer is about 38 nm.

[0252] S1.3 Backside laser patterning to groove the PSG layer. The conditions for laser patterning are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0253] S1.4 Use a chain machine to remove the PSG layer on the front and side surfaces of the silicon wafer, wherein the concentration of the HF solution in the chain machine is 30 wt%, and the belt speed is 4 m / min.

[0254] S1.5 Cleaning and texturing: Put the silicon wafer into an alkaline texturing tank for integrated cleaning and texturing treatment; First, since the backside PSG layer is grooved by laser patterning in step S3, the phosphorus-doped layer at the bottom can be cleaned during alkaline texturing until the P-type silicon wafer is exposed, while the non-laser-patterned area on the backside can protect the phosphorus-doped layer at the bottom from being damaged due to the protection of the PSG layer. In addition, since there is no PSG layer on the front side, the phosphorus-doped layer on the front side can be etched first during alkaline texturing, and then a pyramid-shaped textured surface is formed on the front side P-type silicon wafer. The alkaline concentration is 1.7 wt%, the temperature is 80 °C, and the time is 7 min.

[0255] S1.6 In order to prevent an insulating passivation film from being deposited on the backside of the silicon wafer, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, a plate-type ALD and PECVD equipment are selected to deposit AlO x and SiN x passivation films on the front side (single side) of the silicon wafer in sequence. The thicknesses of the AlO x and SiN x passivation films are 8 nm and 82 nm respectively.

[0256] S1.7. Use screen printing to print the paste (positive electrode) on the back of the P-type silicon wafer. Since most areas of the phosphorus-doped layer need to be connected to the subsequent perovskite battery, only screen-print the electrode (negative electrode) on the left part of the phosphorus-doped layer, and then sinter at 750 °C to form an ohmic contact.

[0257] S2. Using the crystalline silicon battery as the substrate, place the back of the crystalline silicon battery facing up. First, use a mask (high-temperature insulating tape) to cover the non-interconnect layer area on the back of the crystalline silicon battery, so that the subsequent interconnect layer and part of the perovskite battery are not deposited on this layer. Subsequently, deposit the interconnect layer (ITO layer) on this basis by magnetron sputtering or other methods, with a thickness of 55 nm and a refractive index of 1.7.

[0258] S3. Prepare the precursor solution of the hole transport layer of the perovskite battery (nano-NiO x particle ink), then coat it on the interconnect layer on the back of the battery, and anneal at 180 °C for 12 min to form the hole transport layer.

[0259] S4. Subsequently, deposit the narrow-bandgap perovskite layer on the basis of the hole transport layer. The preparation formula is as follows: Select materials such as SnI2 (tin(II) iodide), MAI (methylammonium iodide, CH3NH3I), and HI (hydroiodic acid) for use; then mix N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO) in a volume ratio of 4:1 as the solvent. Subsequently, add SnI2, MAI, and HI to the DMF / DMSO mixed solvent in a volume ratio of 1:1:2, seal it, and stir magnetically (60 °C, 6 h) until the solution is clear and transparent. Subsequently, cover the hole transport layer with the solution by blade coating, and then perform annealing treatment, annealing at 100 °C for 20 min to remove the residual solvent and form the final dense perovskite crystal phase with the chemical formula MASnI3.

[0260] S5. Dissolve tetrabutyl titanate in an appropriate solvent (isopropyl alcohol) to prepare the precursor solution of the electron transport layer. Use the blade coating technique to uniformly coat it on the perovskite layer. After coating, perform annealing crystallization to remove the residual solvent at a temperature of 160 °C to form the electron transport layer.

[0261] S6. Deposit the TCO layer (ITO layer) on the basis of the semi-dry electron transport layer by magnetron sputtering, with a thickness of 55 nm and a refractive index of 1.7. Then remove the masks in S2 and S3.

[0262] S7. Use screen printing to deposit the low-temperature paste (positive electrode) on the hole transport surface of the perovskite battery and deposit the low-temperature paste (negative electrode) on the surface of the TCO layer, and then form a contact at 200 °C; since the positive and negative electrodes already exist in the crystalline silicon battery, the entire battery forms the final four-terminal (two positive electrodes, two negative electrodes) back-contact crystalline silicon battery + narrow-bandgap perovskite stacked battery structure.

[0263] Comparative Example 1 (conventional stacked cell structure, non-back contact cell structure, taking the structure of Example 1 as an example) S1. Fabricate a crystalline silicon cell.

[0264] S1.1. Texturize the front surface of the N-type silicon wafer. Select the N-type silicon wafer after wire saw cutting (the N-type silicon wafer can also be called a phosphorus-doped silicon wafer); subject the N-type silicon wafer to alkaline texturing treatment to form a light-trapping pyramid texture on its front surface; the alkaline texturing conditions are: the concentration of the KOH solution is 1.7 wt%, the temperature is 80 °C, and the time is 7 min.

[0265] S1.2. Perform front boron diffusion to convert the front surface of the N-type silicon wafer into a boron-doped layer and a BSG layer, while the back surface is a phosphorus-doped layer (the N-type silicon wafer is a phosphorus-doped silicon). The boron diffusion conditions are: the diffusion temperature is 930 °C, the time is 20 min, the BCl3 flow rate is 50 sccm, and the O2 flow rate is 800 sccm; the oxidation and push temperature is 1050 °C, the O2 flow rate is 7000 sccm, and the time is 60 min. The thickness of the obtained BSG layer is about 50 nm.

[0266] S1.3. Use a chain machine to remove the BSG layer on the back and side surfaces of the silicon wafer, where the concentration of the HF solution in the chain machine is 40 wt% and the belt speed is 3 m / min.

[0267] S1.4. Alkaline cleaning to remove the boron-doped layer around the diffusion: Place the silicon wafer in an alkaline polishing tank to remove the boron-doped layer around the diffusion on the back and side surfaces of the silicon wafer. The alkaline polishing conditions are: the concentration of the KOH solution is 2.0 wt%, the temperature is 75 °C, and the time is 5 min.

[0268] S1.5. Deposit a passivation film on the back surface: In order to prevent the front surface of the silicon wafer from also depositing an insulating passivation film, which affects the carrier transport between the subsequent perovskite cell and the crystalline silicon cell, it is possible to select to use plate-type ALD and PECVD equipment to deposit AlO x and SiN x passivation films on the back surface (one side) of the silicon wafer in sequence. The thicknesses of the AlO x and SiN x passivation films are about 8 nm and 82 nm respectively.

[0269] S1.6. Use screen printing to print the negative electrode paste on the back surface of the silicon wafer, and then sinter it at 750 °C to form an ohmic contact to form the negative electrode.

[0270] S2. Using the crystalline silicon cell as a substrate, deposit an interconnection layer (ITO layer) on the front surface by means of magnetron sputtering, etc. Its thickness is 55 nm and the refractive index is 1.7.

[0271] S3. Dissolve tetrabutyl titanate in a suitable solvent (isopropanol) to prepare a precursor solution for the electron transport layer, and then use the blade coating technique to uniformly coat this solution onto the interconnection layer. After coating, anneal and crystallize the entire sample to remove the residual solvents in each layer at a temperature of 160 °C.

[0272] S4. Subsequently, deposit a wide-bandgap perovskite layer on the basis of the electron transport layer. The preparation formula is as follows: Select methylammonium bromide (MABr, CH3NH3Br), methylammonium chloride (MACl, CH3NH3Cl), lead bromide (PbBr2), and lead chloride (PbCl2). The solvents are N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO), which are fully mixed according to a volume ratio of 9:1. Dissolve 0.2 mmol of MABr and 0.8 mmol of MACl in 1 mL of DMF:DMSO (9:1), and stir well until transparent. Lead salt solution: Dissolve 0.2 mmol of PbBr2 and 0.8 mmol of PbCl2 in 1 mL of DMF:DMSO (9:1), and heat and stir at 60 °C until dissolved. Mix the two solutions according to a volume ratio of 1:1 to obtain a precursor solution. Subsequently, use the blade coating technique to uniformly apply the precursor solution onto the surface of the hole transport layer. Then, in an environment isolated from water vapor and oxygen, first dry it at 65 °C for the first time, and then perform the second annealing and crystallization at 105 °C in an air environment with a humidity of 5% RH to form the final perovskite layer, with the chemical formula MAPb(Br 0.2 Cl 0.8 )3.

[0273] S5. Immediately prepare a precursor solution for the hole transport layer (nano NiO x particle ink), then coat it on the perovskite layer, and anneal it at 180 °C for 12 min to form the hole transport layer.

[0274] S6. Deposit a transparent conductive film (ITO layer) on the basis of the hole transport layer by magnetron sputtering, with a thickness of 55 nm and a refractive index of 1.7.

[0275] S7. Deposit a low-temperature paste (positive electrode) on the front transparent conductive film of the perovskite solar cell by screen printing, and then form a contact at 200 °C; since the negative electrode already exists on the back of the crystalline silicon solar cell (N-type silicon wafer), the entire solar cell forms a conventional two-terminal perovskite solar cell + crystalline silicon tandem solar cell structure.

[0276] Comparative Example 2 (In Step S5 of Example 1, the electron transport layer is in a fully dried and crystallized state instead of a semi-dried state, and the remaining steps are the same as those in Example 1) S5. Dissolve tetrabutyl titanate in a suitable solvent (ethanol) to prepare a precursor solution for the electron transport layer. Then, use the blade coating technique to uniformly coat this solution onto the perovskite layer. After coating, anneal and crystallize the entire sample to remove the residual solvents in each layer at a temperature of 160 °C.

[0277] Performance Test Test the electrical performance of the solar cells obtained in each example and comparative example, and the results are shown in Table 1.

[0278] Table 1 Serial number η(%) v(V) <![CDATA[J (mA / cm 2 )]]> FF(%) Example 1 29.75 1.882 19.47 81.20 Example 2 29.92 1.884 19.55 81.25 Example 3 29.31 1.873 19.33 80.95 Example 4 29.53 1.880 19.37 81.08 Comparative example 1 28.30 1.867 18.79 80.65 Comparative example 2 25.17 1.763 17.88 79.85 First, for Example 1, since the back-contact two-terminal stacked cell structure is adopted, there is no light-shielding loss of the front electrode first, and the optical performance of the cell is better. Secondly, the wide-bandgap perovskite cell combined with the crystalline silicon cell can fully absorb the incident light in the entire wavelength band, and the corresponding cell voltage is also higher, and the performance is also better.

[0279] For Example 2, since the wide-bandgap perovskite cell combined with the crystalline silicon cell forms a four-terminal stacked cell structure, it can not only balance the current and voltage differences between the top cell and the bottom cell, but also is more conducive to the carrier collection performance. Therefore, the cell performance is the best and higher than that of Example 1.

[0280] For Example 3, since the positions of the crystalline silicon cell and the perovskite cell are opposite to those in Examples 1 and 2, and the absorption ability of the current narrow-bandgap perovskite cell for the medium and long wavelength bands is slightly worse than that of the wide-bandgap perovskite cell for the medium and short wavelength bands, the performance of this stacked cell is lower than that of Examples 1 and 2.

[0281] For Example 4, since the four-terminal structure is more conducive to the internal carrier transport of the crystalline silicon cell + narrow-bandgap perovskite stacked cell, the cell performance is higher than that of Example 3, but lower than that of Examples 1 and 2.

[0282] For Comparative Example 1, since it is a stacked cell structure of a conventional perovskite cell + crystalline silicon cell, and there is still the influence of electrode light shielding on the front side, the improvement of the optical performance is limited. And since it is a conventional two-terminal contact structure, the corresponding cell performance is lower than that of each example.

[0283] For Comparative Example 2, since the electron transport layer is directly annealed after deposition during the preparation of the perovskite cell, the electron transport layer is in a dry and crystalline state. When it is covered with the subsequent crystalline silicon cell, it is difficult to form a more effective and tight contact, resulting in more voids between the perovskite cell and the crystalline silicon cell, and the carrier transport is greatly affected, resulting in the lowest cell performance.

[0284] Unless otherwise specified, the raw materials and equipment used in the present invention are common raw materials and equipment in the art; unless otherwise specified, the methods used in the present invention are conventional methods in the art.

[0285] The above are only the preferred embodiments of the present invention and do not impose any limitations on the present invention. Any simple modifications, changes, and equivalent transformations made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A back-contact stacked solar cell, characterized in that: It is a two-terminal wide-bandgap perovskite cell + crystalline silicon cell, which includes a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnection layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence from the front to the back of the cell; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of the extended area. There is an isolation area between the positive electrode and the perovskite layer; A negative electrode is provided on the back of the phosphorus-doped layer.

2. A method for preparing the back-contact stacked solar cell according to claim 1, characterized in that It includes: S1. Prepare a crystalline silicon cell with a boron-doped layer, a phosphorus-doped layer, and a passivation film in sequence from the front to the back; S2. Deposit a hole transport layer on the back of the TCO layer; S3. Use a mask to cover the designed areas of the perovskite layer and the isolation area on the back of the hole transport layer; S4. Deposit a perovskite layer on the area of the hole transport layer without a mask on the back; S5. Deposit a semi-dry electron transport layer on the surface of the perovskite layer; S6. Deposit an interconnection layer on the surface of the semi-dry electron transport layer and remove the mask in S3; S7. Cover the front of the crystalline silicon cell on the surface of the interconnection layer and anneal for crystallization; S8. Deposit a positive electrode on the surface of the exposed hole transport layer.

3. The preparation method according to claim 2, wherein: S4 includes: coating a wide-bandgap perovskite precursor solution on the surface of the exposed hole transport layer, adding an anti-solvent to promote crystallization; first annealing at 60-80°C in an environment isolated from water vapor and oxygen, and then annealing at 90-110°C in an air environment with a humidity ≤ 30%RH for the second time to form a perovskite layer; S5 includes: coating an electron transport layer precursor solution on the surface of the perovskite layer and drying it to a semi-dry state with a solid content of 10-60 wt% of the electron transport layer; S7 includes: first removing the natural oxide layer on the front of the crystalline silicon cell, then covering its front on the surface of the interconnection layer, and annealing and crystallizing at 100-200°C to make the semi-dry electron transport layer fully formed.

4. A back-contact stacked solar cell, characterized in that: It is a four-terminal wide-bandgap perovskite cell + crystalline silicon cell, which includes a TCO layer, a hole transport layer, a perovskite layer, an electron transport layer, an interconnection layer, a boron-doped layer, a phosphorus-doped layer, and a passivation film stacked in sequence from the front to the back of the cell; One side of the TCO layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back of this area. There is an isolation area between the positive electrode and the perovskite layer; One side of the perovskite layer and the electron transport layer extends beyond the interconnection layer, and a negative electrode is provided on the back of this area. There is an isolation area between the negative electrode and the interconnection layer; One side of the interconnection layer and the boron-doped layer extends beyond the phosphorus-doped layer; a positive electrode is provided on the back of this area. There is an isolation area between the positive electrode and the phosphorus-doped layer; A negative electrode is provided on the back of the phosphorus-doped layer.

5. A method for manufacturing a back-contact stacked solar cell according to claim 4, characterized in that It includes: S1. Prepare a crystalline silicon cell with a boron-doped layer, a phosphorus-doped layer, and a passivation film in sequence from the front to the back; S2. Deposit a hole transport layer on the back of the TCO layer; S3. Use a mask to cover the designed areas of the perovskite layer and its adjacent isolation area on the back of the hole transport layer; S4. Deposit a perovskite layer on the surface of the exposed hole transport layer; S5. Deposit a semi-dry electron transport layer on the surface of the perovskite layer and use a mask to cover the designed areas of the negative electrode and the isolation area on the surface of the electron transport layer; S6. Deposit an interconnection layer on the surface of the semi-dry electron transport layer and remove the masks in S3 and S5; S7. Cover the front side of the crystalline silicon cell on the surface of the interconnection layer and anneal for crystallization. S8. Deposit the positive electrode and the negative electrode.

6. The preparation method according to claim 5, wherein: S4 includes: coating the wide-bandgap perovskite precursor solution on the surface of the exposed hole transport layer, dropping an antisolvent to promote crystallization; first annealing at 60 - 80 °C in an environment isolated from water vapor and oxygen, and then annealing at 90 - 110 °C in an air environment with a humidity ≤ 30%RH to form a perovskite layer. S5 includes: coating the electron transport layer precursor solution on the surface of the perovskite layer and drying until the electron transport layer is in a semi-dry state with a solid content of 10 - 60 wt%. S7 includes: first removing the natural oxide layer on the front side of the crystalline silicon cell, then covering its front side on the surface of the interconnection layer, and annealing and crystallizing at 100 - 200 °C to completely form the semi-dry electron transport layer.

7. A back-contact stacked solar cell, characterized in that: It is a two-terminal crystalline silicon cell + narrow-bandgap perovskite cell, which includes, from the front side to the back side of the cell, a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnection layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence. One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back side of the region extending beyond the phosphorus-doped layer. There is an isolation region between the positive electrode and the phosphorus-doped layer; a negative electrode is provided on the back side of the TCO layer.

8. A method for preparing the back-contact stacked solar cell according to claim 7, characterized in that It includes: S1. Prepare a crystalline silicon cell with a passivation film, a boron-doped layer, and a phosphorus-doped layer in sequence from the front side to the back side. S2. Use a mask to cover the boron-doped layer region on the back side of the crystalline silicon cell and deposit an interconnection layer on the surface of the phosphorus-doped layer. S3. Deposit a hole transport layer on the surface of the interconnection layer. S4. Deposit a perovskite layer on the surface of the hole transport layer. S5. Deposit an electron transport layer on the perovskite layer. S6. Deposit a TCO layer on the surface of the electron transport layer and remove the mask in S2. S7. Deposit a negative electrode.

9. A back-contact stacked solar cell, characterized in that: It is a four-terminal crystalline silicon cell + narrow-bandgap perovskite cell, which includes, from the front side to the back side of the cell, a passivation film, a boron-doped layer, a phosphorus-doped layer, an interconnection layer, a hole transport layer, a perovskite layer, an electron transport layer, and a TCO layer stacked in sequence. One side of the passivation film and the boron-doped layer extends beyond the phosphorus-doped layer, and a positive electrode is provided on the back side of the region extending beyond the phosphorus-doped layer. There is an isolation region between the positive electrode and the phosphorus-doped layer. One side of the phosphorus-doped layer extends beyond the interconnection layer, and a negative electrode is provided on the back side of the region extending beyond the interconnection layer. There is an isolation region between the negative electrode and the interconnection layer. One side of the interconnection layer and the hole transport layer extends beyond the perovskite layer, and a positive electrode is provided on the back side of the region extending beyond the perovskite layer. There is an isolation region between the positive electrode and the perovskite layer. A negative electrode is provided on the back side of the TCO layer.

10. A method for preparing the back-contact stacked solar cell according to claim 9, characterized in that It includes: S1. Prepare a crystalline silicon cell with a passivation film, a boron-doped layer, and a phosphorus-doped layer in sequence from the front side to the back side. S2. Use a mask to cover the non-interconnection layer design region and deposit an interconnection layer on the exposed surface of the phosphorus-doped layer. S3. Deposit a hole transport layer on the surface of the interconnection layer. Use a mask to cover the non-perovskite layer design region on the surface of the hole transport layer. S4. Deposit a perovskite layer on the exposed surface of the hole transport layer. S5. Deposit an electron transport layer on the perovskite layer. S6. Deposit a TCO layer on the surface of the electron transport layer; remove the masks in S2 and S3. S7. Deposit the positive electrode and the negative electrode.

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