Display device

Abstract

The present disclosure relates to a display device including: a display unit disposed over a substrate and including a first display area and a second display area, each of the first display area and the second display area including a plurality of pixel arrays, and the second display area further including a fillet portion; a first line extending in a first direction in a non-display area on one side of the display unit; a plurality of first wirings connected to a plurality of pixels, the plurality of first wirings being arranged in the first display area in the first direction and extending in a second direction crossing the first direction, extending to an area between the first display area and the first lines, and being connected to the first lines; and a plurality of second wirings connected to a plurality of pixels, the plurality of second wirings being arranged in the second display area in the first direction, the plurality of second wirings being disconnected from the first lines.

Description

[0001] This application is a divisional application of the patent application for invention with the application date of December 20, 2019, application number 201911322016.3, and invention title "display device".

[0002] This application claims the priority of and all rights derived from Korean Patent Application No. 10-2018-0167899, filed on December 21, 2018, the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device that implements a display area for displaying images of various shapes and at the same time includes a reduced dead space. Background Art

[0004] Recently, the uses of display devices are becoming more diverse. In addition, since display devices are substantially thin and light in weight, their range of use is being expanded.

[0005] As display devices are used in various ways, there is an increasing need for technologies to increase the ratio of the display area that provides images and reduce the non-display area that does not provide images when designing the shape of display devices. Summary of the Invention

[0006] One or more embodiments include a display device that implements a display area for displaying images of various shapes and at the same time includes a reduced dead space.

[0007] However, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not as a limitation of the present invention.

[0008] Additional embodiments will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the provided embodiments.

[0009] In one or more embodiments, a display device includes: a display unit disposed above a substrate and including a first display area and a second display area, each of the first display area and the second display area including a plurality of pixel arrays, and the second display area further including a rounded corner portion; a first driving voltage supply line extending in a first direction in a non-display area on one side of the display unit; a plurality of first driving voltage lines supplying driving voltage to the plurality of pixels, the plurality of first driving voltage lines being arranged in the first direction in the first display area and extending in a second direction intersecting the first direction, extending to an area between the first display area and the first driving voltage supply line, and connected to the first driving voltage supply line; and a plurality of second driving voltage lines supplying driving voltage to the plurality of pixels, the plurality of second driving voltage lines being arranged in the first direction in the second display area and disconnected from the first driving voltage supply line in an area between the second display area and the first driving voltage supply line.

[0010] In an embodiment, the plurality of first driving voltage lines and the plurality of second driving voltage lines may be electrically connected to a plurality of connection lines extending in the first direction.

[0011] In an embodiment, the plurality of connection lines may intersect the plurality of first driving voltage lines and the plurality of second driving voltage lines to form a grid shape.

[0012] In an embodiment, the plurality of second driving voltage lines may supply the driving voltage to the plurality of pixels disposed in the second display area through the plurality of connection lines.

[0013] In an embodiment, the display device may further include: a switch unit including a plurality of demultiplexers disposed in the non-display area, demultiplexing data signals, and supplying the demultiplexed data signals to a plurality of data lines; and a second driving voltage supply line disposed parallel to the first driving voltage supply line and connected to a terminal unit at an edge of the substrate, the switch unit being between the first driving voltage supply line and the second driving voltage supply line, wherein the display unit may include a plurality of scan lines and the plurality of data lines respectively connected to the plurality of pixels.

[0014] In an embodiment, the switching unit may include: a first switching unit that demultiplexes data signals supplied to the first display area; and a second switching unit that demultiplexes data signals supplied to the second display area, wherein a plurality of first demultiplexers included in the first switching unit may be arranged at a first pitch, and a plurality of second demultiplexers included in the second switching unit may be arranged at a second pitch smaller than the first pitch.

[0015] In an embodiment, the first driving voltage supply line and the second driving voltage supply line may be electrically connected to each other through a plurality of connection lines disposed between the plurality of first demultiplexers.

[0016] In an embodiment, pixels adjacent to an outer edge of the display unit among the plurality of pixels may be arranged in a stepped manner.

[0017] In an embodiment, the display unit may have one of a polygonal shape, a circular shape, and an oval shape.

[0018] In an embodiment, the display device may further include a substrate, on which the display unit is disposed, and the substrate includes a curved edge.

[0019] In an embodiment, lengths of the plurality of second driving voltage lines extending in the second direction may be smaller than lengths of the plurality of first driving voltage lines.

[0020] In one or more embodiments, a display device includes: a display unit in which a first display area and a second display area including corners are defined at an edge of the first display area, the display unit including a plurality of first pixels and a plurality of second pixels, the plurality of first pixels and the plurality of second pixels being respectively disposed in the first display area and the second display area and connected to a plurality of data lines and a plurality of driving voltage lines arranged in a first direction and a plurality of scan lines arranged in a second direction; a scan driver and a data driver, the scan driver and the data driver being disposed in a non-display area outside the display unit; a switch unit including a plurality of demultiplexers disposed in the non-display area, demultiplexing data signals output from the data driver and supplying the demultiplexed data signals to the plurality of data lines; and a driving voltage supply line disposed in the non-display area and connected to the plurality of driving voltage lines extending from the display unit, wherein the plurality of driving voltage lines include a first driving voltage line connected to the plurality of first pixels and a second driving voltage line connected to the plurality of second pixels, the first driving voltage line extends into the non-display area and is connected to the driving voltage supply line, and the second driving voltage line is disconnected from the driving voltage supply line in the non-display area.

[0021] In an embodiment, the corner may have a rounded shape.

[0022] In an embodiment, pixels of the plurality of first pixels and the plurality of second pixels adjacent to an outer edge of the display unit may be arranged in a stepped manner.

[0023] In an embodiment, the switch unit may further include: a first switch unit that demultiplexes data signals supplied to the plurality of first pixels; and a second switch unit that demultiplexes data signals supplied to the plurality of second pixels, and the plurality of demultiplexers included in the first switch unit may be arranged at a first pitch, and the plurality of demultiplexers included in the second switch unit may be arranged at a second pitch smaller than the first pitch.

[0024] In an embodiment, the driving voltage supplied to the plurality of driving voltage lines may be supplied along a grid path.

[0025] In an embodiment, the display unit may further include a plurality of connection lines extending in the first direction, and the plurality of connection lines are connected to the first driving voltage line and the second driving voltage line by contacting the first driving voltage line and the second driving voltage line.

[0026] In an embodiment, an insulating layer may be disposed between the plurality of connection lines and the first driving voltage line and the second driving voltage line, and the plurality of connection lines may be electrically connected to the first driving voltage line and the second driving voltage line through contact holes in the insulating layer.

[0027] In an embodiment, the driving voltage supply line may include a first driving voltage supply line and a second driving voltage supply line extending in the first direction. The switching unit is between the first driving voltage supply line and the second driving voltage supply line. The plurality of driving voltage lines may be connected to the first driving voltage supply line, and the second driving voltage supply line may be connected to the terminal unit.

[0028] In an embodiment, the driving voltage supply line may further include a plurality of connection lines connecting the first driving voltage supply line and the second driving voltage supply line, and the plurality of connection lines are disposed between the plurality of demultiplexers. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other embodiments will become apparent and more readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a plan view of an embodiment of a display device;

[0031] Figure 2 is an equivalent circuit diagram of an embodiment of a pixel;

[0032] Figure 3 and Figure 4 is a cross-sectional view of an embodiment of a pixel;

[0033] Figure 5 is an equivalent circuit diagram of another embodiment of a pixel;

[0034] Figure 6 and Figure 7 is Figure 1 an enlarged view of part A of

[0035] Figure 8 is a plan view of an embodiment of a pixel structure;

[0036] Figure 9 and Figure 10 are respectively Figure 6 and Figure 7 enlarged views of modified embodiments of

[0037] Figure 11 and Figure 12 is Figure 1 a plan view of a modified embodiment of ; and

[0038] Figure 13It is an enlarged plan view of an embodiment of a display device. Detailed Description of the Invention

[0039] Since the present invention contemplates various changes and many embodiments, the embodiments will be shown in the drawings and will be described in detail in the written description. When referring to the embodiments described with reference to the drawings, the effects and characteristics of the present invention and the methods for achieving these effects and characteristics will be apparent. However, the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0040] Hereinafter, the present invention will be described more fully with reference to the drawings in which embodiments of the present invention are shown. When describing with reference to the drawings, like reference numerals in the drawings denote like or corresponding elements, and repeated description thereof will be omitted.

[0041] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0042] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms.

[0043] It will also be understood that the terms "comprises / include" and / or "comprising / including" as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0044] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. That is, for example, there may be an intermediate layer, region or component.

[0045] For convenience of explanation, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0046] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0047] When a specific embodiment can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in a sequence opposite to the described sequence.

[0048] It will be understood that when a layer, region or component is referred to as being "connected" to another layer, region or component, the layer, region or component may be "directly connected" to the other layer, region or component, or may be "indirectly connected" to the other layer, region or component, with other layers, regions or components being interposed between the layer, region or component and the other layer, region or component. For example, it will be understood that when a layer, region or component is referred to as being "connected to or electrically connected" to another layer, region or component, the layer, region or component may be "directly electrically connected" to the other layer, region or component, or may be "indirectly connected or electrically connected" to the other layer, region or component, with other layers, regions or components being interposed between the layer, region or component and the other layer, region or component.

[0049] Figure 1 is a plan view of an embodiment of the display device 1.

[0050] Referring to Figure 1 , the display device 1 includes a display unit 10, a first scan driver 20, a second scan driver 30, a data driver 40, a terminal unit 50, a driving voltage supply line 60, a common voltage supply line 70, and a switching unit 80 disposed above a substrate 100.

[0051] The substrate 100 may include a material such as glass, metal, or an organic material, and the glass includes SiO2 as a main component. In an embodiment, the substrate 100 may include a flexible material. In an embodiment, although the substrate 100 may include a flexible plastic material such as polyimide, the present invention is not limited thereto. In another embodiment, for example, the plastic material may include at least one of polyethersulfone ("PES"), polyarylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyaryl compound, polyimide ("PI"), polycarbonate ("PC"), triacetyl cellulose ("TAC"), cellulose acetate propionate ("CAP"), cyclic olefin polymer, and cyclic olefin copolymer.

[0052] The display unit 10 includes pixels PX, and the pixels PX are connected to scan lines SL extending in a first direction, data lines DL extending in a second direction intersecting the first direction, and driving voltage lines PL. Each of the pixels PX in the pixels PX may emit, for example, red light, green light, blue light, or white light, and includes, for example, an organic light emitting diode. The display unit 10 provides a predetermined image by the light emitted from the pixels PX. A display area DA is defined by the pixels PX. In the specification, a non-display area NDA is an area where the pixels PX are not disposed and represents an area where no image is provided.

[0053] Although the display unit 10 has an approximately quadrilateral shape, in various embodiments, the display unit 10 may be provided in various shapes such as a polygonal shape, a circular shape, an oval shape, or a shape corresponding to a part of these shapes. In the illustrated embodiment, the display unit 10 has a quadrilateral shape as a whole and may include a rounded corner portion 10C in which each edge is curved. The substrate 100 provided above the display unit 10 may have a curved edge in at least a part of the outer edge region.

[0054] The first scan driver 20 and the second scan driver 30 are disposed in the non-display area NDA of the substrate 100, generate scan signals, and transmit the scan signals to each pixel PX through the scan lines SL. In an embodiment, the first scan driver 20 may be disposed on the left side of the display unit 10, and the second scan driver 30 may be disposed on the right side of the display unit 10.

[0055] The data driver 40 is disposed in the non-display area NDA of the substrate 100, generates data signals, and transmits the data signals to each pixel PX through the data lines DL. The data driver 40 may be disposed on one side of the display unit 10. For example, it may be disposed on the lower side of the display unit 10, where the terminal unit 50 is disposed below the display unit 10.

[0056] The terminal unit 50 is disposed at one end of the substrate 100 and includes a plurality of terminals 51, 52, 53, and 54. The terminal unit 50 is not covered by an insulating layer and is exposed, and may be electrically connected to a controller (not shown) such as a flexible printed circuit board or an integrated circuit (“IC”) chip. The controller changes a plurality of video signals transmitted from the outside into a plurality of video data signals, and transmits the changed video signals to the data driver 40 through the terminal 51. In addition, the controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate control signals for controlling the driving of the first scan driver 20, the second scan driver 30, and the data driver 40, and transmit the relevant control signals to the relevant components. The controller transmits the driving voltage ELVDD and the common voltage ELVSS to the driving voltage supply line 60 and the common voltage supply line 70 through the terminals 52 and 54, respectively.

[0057] The driving voltage supply line 60 is disposed in the non-display area NDA. In an embodiment, for example, the driving voltage supply line 60 may be disposed between the data driver 40 and the display unit 10. The driving voltage supply line 60 supplies the driving voltage ELVDD to the pixel PX. The driving voltage supply line 60 may extend in a first direction and may be connected to a plurality of driving voltage lines PL1 disposed in the first direction.

[0058] The common voltage supply line 70 is disposed in the non-display area NDA and supplies the common voltage ELVSS to the opposite electrode 223 of the organic light-emitting diode of the pixel PX (see Figure 3 ). In an embodiment, for example, the common voltage supply line 70 is provided as a loop having an opening defined on one side, and may extend along an edge of the substrate 100 except for the terminal unit 50.

[0059] The display unit 10 has an approximately quadrilateral shape and includes rounded corner portions 10C. The rounded corner portions 10C may be defined at each of the four edges of the display unit 10 and may be a part of a circle formed with a constant curvature.

[0060] The display unit 10 may be defined as a first display area DA1 and a second display area DA2 including the rounded corner portions 10C. The second display area DA2 may be disposed in a first direction, and the first display area DA1 is centered between the second display areas DA2. A plurality of first driving voltage lines PL1 are arranged to supply the driving voltage ELVDD to the pixels PX of the first display area DA1, and a plurality of second driving voltage lines PL2 are arranged to supply the driving voltage ELVDD to the pixels PX of the second display area DA2.

[0061] The lengths of the plurality of first driving voltage lines PL1 and the plurality of second driving voltage lines PL2 intercepted in the second direction may be different from each other. That is, the length of the plurality of first driving voltage lines PL1 in the second direction may be greater than the length of the plurality of second driving voltage lines PL2 in the second direction. This is because the plurality of first driving voltage lines PL1 extend into the non-display area NDA, but the plurality of second driving voltage lines PL2 do not extend into the non-display area NDA and are only arranged inside the second display area DA2.

[0062] The switching unit 80 is disposed in the non-display area NDA between the data driver 40 and the display unit 10, demultiplexes the data signal, and supplies the demultiplexed data signal to the plurality of data lines DL. The driving voltage supply line 60 may be disposed between the switching unit 80 and the data driver 40.

[0063] Figure 2 is an embodiment of the equivalent circuit diagram of the pixel PX, Figure 3 and Figure 4 is a cross-sectional view of an embodiment of the pixel PX, and Figure 5 is the equivalent circuit diagram of another embodiment of the pixel PX.

[0064] Referring to Figure 2, each pixel PX includes a pixel circuit PC connected to a scan line SL and a data line DL, and a light emitting diode connected to the pixel circuit PC, for example, an organic light emitting diode OLED.

[0065] The pixel circuit PC includes a driving thin film transistor (“TFT”) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving TFT T1 in response to a scan signal Sn input through the scan line SL.

[0066] The storage capacitor Cst is connected to the switching TFT T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching TFT T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

[0067] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light emitting diode OLED from the driving voltage line PL in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a predetermined brightness through the driving current.

[0068] Referring to Figure 3 , the pixel PX includes a pixel circuit PC disposed above the substrate 100 and an organic light emitting diode OLED connected to the pixel circuit PC. Hereinafter, for ease of description, the description is made according to the stacking order.

[0069] A buffer layer 101 may be disposed on the substrate 100, may reduce or block the penetration of foreign substances, moisture, or external air from below the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 101 may include an inorganic material such as an oxide or a nitride, or an organic material, or an organic / inorganic composite material. The buffer layer 101 may include a single layer or multiple layers of an inorganic material and an organic material.

[0070] The driving TFT (also referred to as “first TFT”) T1 includes a semiconductor layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1. The switching TFT (also referred to as “second TFT”) T2 includes a semiconductor layer A2, a gate electrode G2, a source electrode S2, and a drain electrode D2.

[0071] The semiconductor layers A1 and A2 may include amorphous silicon or polycrystalline silicon. In another embodiment, the semiconductor layers A1 and A2 may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn. Each of the semiconductor layers A1 and A2 may include a channel region and a source region and a drain region each doped with an impurity.

[0072] The gate electrodes G1 and G2 are respectively disposed above the semiconductor layers A1 and A2, and the gate insulating layer 103 is between the gate electrodes G1 and G2 and the semiconductor layers A1 and A2. The gate electrodes G1 and G2 may include one of Mo, Al, Cu, and Ti, and include a single layer or multiple layers. In an embodiment, for example, each of the gate electrodes G1 and G2 may include a single layer of Mo.

[0073] The gate insulating layer 103 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0074] The source electrodes S1 and S2 and the drain electrodes D1 and D2 are disposed on the interlayer insulating layer 107. The source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a conductive material containing Mo, Al, Cu, and Ti, and include a single layer or multiple layers containing the above materials. In an embodiment, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may have a multilayer structure of Ti / Al / Ti.

[0075] The interlayer insulating layer 107 may include SiO x , SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0076] The first electrode CE1 of the storage capacitor Cst may overlap with the first TFT T1. In an embodiment, for example, the gate electrode G1 of the first TFT T1 may also serve as the first electrode CE1 of the storage capacitor Cst.

[0077] The second electrode CE2 of the storage capacitor Cst overlaps with the first electrode CE1, and the dielectric layer 105 is between the second electrode CE2 and the first electrode CE1. The second electrode CE2 may include a conductive material containing Mo, Al, Cu, and Ti, and include a single layer or multiple layers containing the above materials. In an embodiment, the second electrode CE2 may include a single layer of Mo or a multilayer of Mo / Al / Mo.

[0078] The dielectric layer 105 may include an inorganic material, and the inorganic material includes an oxide or a nitride. In an embodiment, for example, the dielectric layer 105 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0079] The planarization layer 109 may be disposed on the source electrodes S1 and S2 and the drain electrodes D1 and D2. The organic light-emitting diode OLED may be disposed on the planarization layer 109. The planarization layer 109 may include a single layer or multiple layers, and the single layer or multiple layers include a layer of an organic material. The organic material may include common polymers such as polymethyl methacrylate (“PMMA”) or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, polyvinyl alcohol polymers, and blends thereof. Additionally, the planarization layer 109 may include a composite stack including an inorganic insulating layer and an organic insulating layer.

[0080] The organic light-emitting diode OLED includes a pixel electrode 221, an emission layer 222, and a counter electrode 223.

[0081] The pixel electrode 221 may include a reflective electrode. In an embodiment, for example, the pixel electrode 221 may include a reflective layer and a transparent or semi-transparent electrode layer disposed on the reflective layer, and the reflective layer includes one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and combinations thereof. In an embodiment, for example, the transparent or semi-transparent electrode layer may include at least one of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), and aluminum zinc oxide (“AZO”).

[0082] The pixel defining layer 112 is disposed on the pixel electrode 221. The pixel defining layer 112 may include at least one organic insulating material and may be provided by spin coating or the like, and the at least one organic insulating material includes polyimide, polyamide, acrylic resin, benzocyclobutene (“BCB”), and phenolic resin. The pixel defining layer 112 exposes the pixel electrode 221, and the emission layer 222 is disposed on the exposed area.

[0083] The emission layer 222 may include an organic material, and the organic material includes a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer 222 may include a low molecular weight or polymer organic material. Functional layers such as a hole transport layer (“HTL”), a hole injection layer (“HIL”), an electron transport layer (“ETL”), and an electron injection layer (“EIL”) may be selectively further disposed under the emission layer 222 and on the emission layer 222.

[0084] The counter electrode 223 may be a light-transmissive electrode. In an embodiment, for example, the counter electrode 223 may include a transparent or translucent electrode, and may include a metal thin film having a small work function and including one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and combinations thereof. Additionally, a transparent conductive oxide (“TCO”) layer such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film.

[0085] The thin film encapsulation layer 300 prevents the penetration of external moisture and oxygen. The thin film encapsulation layer 300 may include at least one organic layer 320 and at least one inorganic layer 310 and 330. The at least one organic layer 320 and the at least one inorganic layer 310 and 330 may be stacked in sequence. Although the thin film encapsulation layer 300 is shown in Figure 3 to include two inorganic layers 310 and 330 and one organic layer 320, the stacking order and the number of stacked layers are not limited to the embodiment shown in Figure 3 .

[0086] The touch film 400 may be disposed on the thin film encapsulation layer 300 to implement the touch screen function of the display device 1. The touch film 400 may include touch electrodes of various patterns and include a resistive layer type touch film or a capacitive touch film.

[0087] Referring to Figure 4 , the storage capacitor Cst of the pixel circuit PC may be disposed so as not to overlap with the driving TFT T1. The description of the pixel PX that is the same as the pixel PX in Figure 3 is omitted, and the differences will be mainly described below.

[0088] The first electrode CE1 of the storage capacitor Cst may be disposed in the same layer as the layer in which the gate electrodes G1 and G2 are disposed, and may include the same material as the gate electrodes G1 and G2. The second electrode CE2 may be disposed in the same layer as the layer in which the source electrodes S1 and S2 and the drain electrodes D1 and D2 are disposed, and may include the same material as the source electrodes S1 and S2 and the drain electrodes D1 and D2. The interlayer insulating layer 107 may be used as a dielectric.

[0089] Although the first TFT T1 and the second TFT T2 are shown as top-gate type TFTs in Figure 3 and Figure 4 , the present invention is not limited thereto. In the top-gate type TFT, the gate electrodes G1 and G2 are disposed above the semiconductor layers A1 and A2, and the gate insulating layer 103 is between the gate electrodes G1 and G2 and the semiconductor layers A1 and A2. In another embodiment, the first TFT T1 and the second TFT T2 may be bottom-gate type TFTs.

[0090] Although Figure 3 and Figure 4 describe a structure in which the first TFT T1 and the pixel electrode 221 are connected to each other through a through hole of the planarization layer 109, the present invention is not limited thereto.

[0091] Although Figure 2 describe a case where the pixel PX includes two TFTs and a storage capacitor, the present invention is not limited thereto.

[0092] Referring to Figure 5 , the pixel circuit PC may include not only the driving TFT T1 and the switching TFT T2, but also a compensation TFT T3, a first initialization TFT T4, a first emission control TFT T5, a second emission control TFT T6, and a second initialization TFT T7.

[0093] The drain electrode of the driving TFT T1 may be electrically connected to the organic light emitting diode OLED through the second emission control TFT T6. The driving TFT T1 may receive the data signal Dm and supply a driving current to the organic light emitting diode OLED in response to the switching operation of the switching TFT T2.

[0094] The gate electrode of the switching TFT T2 is connected to the first scan line SLn, and the source electrode of the switching TFT T2 is connected to the data line DL. The drain electrode of the switching TFT T2 may be connected to the source electrode of the driving TFT T1 and at the same time connected to the driving voltage line PL through the first emission control TFT T5.

[0095] The switching TFT T2 performs such a switching operation: it turns on in response to the first scan signal Sn transmitted through the first scan line SLn and transmits the data signal Dm transmitted through the data line DL to the source electrode of the driving TFT T1.

[0096] The gate electrode of the compensation TFT T3 may be connected to the first scan line SLn. The source electrode of the compensation TFT T3 may be connected to the drain electrode of the driving TFT T1 and at the same time connected to the pixel electrode of the organic light emitting diode OLED through the second emission control TFT T6. The drain electrode of the compensation TFT T3 may be connected to one of the electrodes of the storage capacitor Cst, the source electrode of the first initialization TFT T4, and the gate electrode of the driving TFT T1 at the same time. The compensation TFT T3 turns on in response to the first scan signal Sn transmitted through the first scan line SLn and connects the gate electrode and the drain electrode of the driving TFT T1 to each other to connect the driving TFT T1 in a diode manner.

[0097] The gate electrode of the first initialization TFT T4 can be connected to the second scan line SLn-1. The drain electrode of the first initialization TFT T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization TFT T4 can be connected to one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation TFT T3, and the gate electrode of the driving TFT T1 at the same time. The first initialization TFT T4 can perform such an initialization operation: turn on in response to the second scan signal Sn-1 transmitted through the second scan line SLn-1 and initialize the voltage of the gate electrode of the driving TFT T1 by transmitting the initialization voltage VINT to the gate electrode of the driving TFT T1.

[0098] The gate electrode of the first emission control TFT T5 can be connected to the emission control line EL. The source electrode of the first emission control TFT T5 can be connected to the driving voltage line PL. The drain electrode of the first emission control TFT T5 can be connected to the source electrode of the driving TFT T1 and the drain electrode of the switch TFT T2 at the same time.

[0099] The gate electrode of the second emission control TFT T6 can be connected to the emission control line EL. The source electrode of the second emission control TFT T6 can be connected to the drain electrode of the driving TFT T1 and the source electrode of the compensation TFT T3. The drain electrode of the second emission control TFT T6 can be electrically connected to the pixel electrode of the organic light-emitting diode OLED. When the first emission control TFT T5 and the second emission control TFT T6 are turned on simultaneously in response to the emission control signal En transmitted through the emission control line EL, the driving voltage ELVDD is transmitted to the organic light-emitting diode OLED, and a driving current flows through the organic light-emitting diode OLED.

[0100] The gate electrode of the second initialization TFT T7 can be connected to the third scan line SLn+1. The source electrode of the second initialization TFT T7 can be connected to the pixel electrode of the organic light-emitting diode OLED. The drain electrode of the second initialization TFT T7 can be connected to the initialization voltage line VL. The second initialization TFT T7 can be turned on in response to the third scan signal Sn+1 transmitted through the third scan line SLn+1, and can initialize the pixel electrode of the organic light-emitting diode OLED.

[0101] The other electrode of the storage capacitor Cst can be connected to the driving voltage line PL. One electrode of the storage capacitor Cst can be connected to the gate electrode of the driving TFT T1, the drain electrode of the compensation TFT T3, and the source electrode of the first initialization TFT T4 at the same time.

[0102] The opposite electrode of the organic light-emitting diode OLED is connected to a common voltage (also referred to as "common power supply voltage") ELVSS. The organic light-emitting diode OLED emits light by receiving a driving current from the driving TFT T1.

[0103] Figure 6 is Figure 1 a plan view of part A of Figure 7 is Figure 6 an enlarged view of a part of Figure 6 and Figure 7 are enlarged and show Figure 1 the rounded corner portion 10C of the display unit 10 of

[0104] Referring to Figure 1 、 Figure 6 and Figure 7 In the embodiment, the display device 1 includes a display unit 10 with rounded edges. The display unit 10 includes a first display area DA1 and a second display area DA2. Each of the first display area DA1 and the second display area DA2 includes an array of a plurality of pixels PX and extends in a second direction. The second display area DA2 includes a rounded corner portion 10C, and the first display area DA1 is arranged between the second display areas DA2.

[0105] Since the pixels PX arranged in the rounded corner portion 10C are arranged substantially stepwise, the boundary between the first display area DA1 and the second display area DA2 can be the portion where the first stepwise arrangement of the pixels PX starts. Therefore, the first display area DA1 includes a straight pixel arrangement over the entire area, and the second display area DA2 includes a stepwise pixel arrangement at the rounded corner portion 10C.

[0106] The driving voltage supply line 60 and the switching unit 80 can be provided in the non-display area NDA on one side of the display unit 10. Although in the embodiment, the switching unit 80 is shown to be arranged between the driving voltage supply line 60 and the display unit 10, in another embodiment, as shown in Figure 9 , the first driving voltage supply line 61 and the second driving voltage supply line 62 can be arranged such that the switching unit 80 is between the first driving voltage supply line 61 and the second driving voltage supply line 62, which will be described in detail with reference to Figure 8 and Figure 9 this will be described in detail.

[0107] The switching unit 80 includes a plurality of demultiplexers DMX, which demultiplex data signals and supply the demultiplexed data signals to a plurality of data lines DL. Although not shown, each of the plurality of demultiplexers DMX may include a control TFT and a switching TFT. Although in Figure 7The demultiplexer DMX is shown connected to two data lines DL, but the demultiplexer DMX can be connected to three or more data lines DL.

[0108] The demultiplexer DMX is connected to the data driver 40 through the multiplexed data line MDL. The data driver 40 generates a multiplexed data signal under the control of a controller (not shown) and supplies the generated multiplexed data signal to the multiplexed data line MDL. That is, through the demultiplexer DMX, the data driver 40 can supply signals to two or more data lines DL through one multiplexed data line MDL. By this, the number of output lines connected to the data driver 40 can be effectively reduced at high resolution.

[0109] The switch unit 80 includes a first switch unit 81 and a second switch unit 82 separated near the boundary between the first display area DA1 and the second display area DA2. The first switch unit 81 can correspond to the first display area DA1, and the second switch unit 82 can correspond to the second display area DA2.

[0110] The first switch unit 81 and the second switch unit 82 can respectively include a plurality of first demultiplexers DMX1 and a plurality of second demultiplexers DMX2. In the illustrated embodiment, the plurality of first demultiplexers DMX1 are arranged at a first pitch P1, and the plurality of second demultiplexers DMX2 are arranged at a second pitch P2. In this case, the second pitch P2 can be smaller than the first pitch P1.

[0111] A plurality of first driving voltage lines PL1 are provided in the first display area DA1, the plurality of first driving voltage lines PL1 are arranged in a first direction and extend in a second direction, and supply a driving voltage to a plurality of first pixels PX1. A plurality of second driving voltage lines PL2 are provided in the second display area DA2, the plurality of second driving voltage lines PL2 are arranged in a first direction and extend in a second direction, and supply a driving voltage to a plurality of second pixels PX2. The plurality of first driving voltage lines PL1 are connected to the driving voltage supply line 60 through the first switch unit 81. In contrast, the plurality of second driving voltage lines PL2 are not connected to the driving voltage supply line 60. That is, the plurality of first driving voltage lines PL1 extend to the area between the first display area DA1 and the driving voltage supply line 60 and are connected to the driving voltage supply line 60. In contrast, the plurality of second driving voltage lines PL2 do not extend to the area between the second display area DA2 and the driving voltage supply line 60, and thus are disconnected from the driving voltage supply line 60.

[0112] All of the plurality of pixels PX arranged in the display unit 10 are connected to data lines DL arranged in a first direction and extending in a second direction and driving voltage lines PL. The data lines DL and the driving voltage lines PL extend from the display area DA to the non-display area NDA and are electrically connected to a controller (not shown). In this case, compared with a first display area DA1 in which the outer edge of the display unit 10 is set in a straight line, a second display area DA2 in which the outer edge of the display unit 10 is set in a rounded shape includes a limited space in the non-display area NDA where the data lines DL and the driving voltage lines PL are connected to all the pixels PX in the second display area DA2. When a high resolution is achieved and the curvature of the rounded corner portion 10C becomes small, this space is further limited.

[0113] Therefore, in the display device 1 in the embodiment, a plurality of second driving voltage lines PL2 arranged in the second display area DA2 do not extend to the area between the second display area DA2 and the driving voltage supply line 60 and are disconnected from the driving voltage supply line 60. With this configuration, a space in the area where the data lines DL are arranged between the second display area DA2 and the driving voltage supply line 60 can be effectively ensured.

[0114] Figure 8 is a plan view of an embodiment of a pixel structure.

[0115] Referring to Figure 8 and Figure 6 , all of the data lines DL and a plurality of first driving voltage lines PL1 connected to the first pixel PX1 in the first display area DA1 extend to the non-display area NDA. In contrast, the data lines DL connected to the second pixel PX2 in the second display area DA2 extend to the non-display area NDA, but a plurality of second driving voltage lines PL2 do not extend to the non-display area NDA and are disconnected from the outer edge of the second display area DA2.

[0116] As described above, since the plurality of second driving voltage lines PL2 do not extend to the non-display area NDA, the plurality of second driving voltage lines PL2 are not directly connected to the driving voltage supply line 60 arranged in the non-display area NDA. Therefore, the plurality of second driving voltage lines PL2 can be electrically connected to each other through a plurality of connection lines CL extending in the first direction to receive a driving voltage. The plurality of connection lines CL can cross the plurality of first driving voltage lines PL1 and the plurality of second driving voltage lines PL2 to form a grid shape. The plurality of second driving voltage lines PL2 can supply the driving voltage ELVDD to the pixels PX2 arranged in the second display area DA2 through the plurality of connection lines CL. The first pixel PX1 and the second pixel PX2 arranged in the same row can be connected through the same connection line CL.

[0117] A plurality of connection lines CL can be electrically connected through contact holes CNT defined in an insulating layer (not shown), and the insulating layer is disposed between the plurality of second driving voltage lines PL2 and the plurality of connection lines CL. In an embodiment, the plurality of connection lines CL can be disposed in the same layer as the second electrode CE2 of the storage capacitor Cst in which Figure 3 is disposed, and the plurality of second driving voltage lines PL2 can be disposed in the same layer as the data line DL in which Figure 3 is disposed. Therefore, with this structure, the driving voltage ELVDD supplied to the driving voltage line PL provided in the display area DA can include a grid path.

[0118] Figure 9 and Figure 10 are plan views of another embodiment of the display device 1. Figure 9 and Figure 10 show Figure 6 and Figure 7 modified embodiments.

[0119] Referring to Figure 9 and Figure 10 , the display device 1 according to an embodiment includes a first driving voltage supply line 61, a second driving voltage supply line 62, and a plurality of connection lines 63 connecting the first driving voltage supply line 61 and the second driving voltage supply line 62. The first driving voltage supply line 61 and the second driving voltage supply line 62 can be disposed in a second direction, and the plurality of connection lines 63 can be disposed in a first direction intersecting the second direction.

[0120] The first driving voltage supply line 61 can be directly connected to the first driving voltage line PL1 extending from the first display area DA1, and the second driving voltage supply line 62 can be directly connected to the terminal 52 (refer to Figure 1 ). With this dual wiring structure, the resistance of the wiring itself can be reduced, and thus, the driving voltage ELVDD can be effectively supplied to the display area DA at a high resolution.

[0121] A switch unit 80 is disposed between the first driving voltage supply line 61 and the second driving voltage supply line 62. As in the previous embodiment, the switch unit 80 includes a first switch unit 81 and a second switch unit 82 separated near the boundary between the first display area DA1 and the second display area DA2. The first switch unit 81 corresponds to the first display area DA1, and the second switch unit 82 corresponds to the second display area DA2.

[0122] The first switch unit 81 and the second switch unit 82 may each include a plurality of first demultiplexers DMX1 and a plurality of second demultiplexers DMX2. In the illustrated embodiment, the plurality of first demultiplexers DMX1 are arranged at a first pitch P1, and the plurality of second demultiplexers DMX2 are arranged at a second pitch P2. In this case, the second pitch P2 may be smaller than the first pitch P1. Referring to Figure 10 , a connection line 63 may be provided between the plurality of first demultiplexers DMX1.

[0123] Figure 11 is a plan view of a display device 2 according to another embodiment. Figure 11 The display device 2 of Figure 1 differs from the display device 1 of

[0124] in the shape of the display unit 10. Therefore, repeated descriptions are omitted, and the differences will be mainly described below. Figure 11 , the display device 2 according to the illustrated embodiment may include a display unit 10 having various shapes. The display unit 10 may include a recessed portion 10R that is indented inward on one side of the display unit 10. A through portion TH may be provided in a non-display area NDA in which the recessed portion 10R is provided. In an embodiment, for example, the through portion TH is a hole passing through the display device 2. Various electronic components such as a camera, a sensor, a speaker, a microphone, etc. may be provided (e.g., mounted) on the through portion TH. In an alternative embodiment, the through portion TH may include a space for a separate component for the function of the display device 2 or a separate component that can add a new function to the display device 2.

[0125] Figure 12 is a plan view of another embodiment of a display device 3. Figure 12 The display device 3 of Figure 1 differs from the display device 1 of

[0126] in the structure of the driving voltage supply line. Therefore, repeated descriptions are omitted, and the differences will be mainly described below. Figure 12 , the display device 3 in the illustrated embodiment may include a first driving voltage supply line 61 on one side of the display unit 10 and a second driving voltage supply line 62 on the other side of the display unit 10. One side of the first driving voltage line PL1 provided in the first display area DA1 may be connected to the first driving voltage supply line 61 in a second direction, and the other side of the first driving voltage line PL1 may be connected to the second driving voltage supply line 62 in the second direction.

[0127] The second driving voltage line PL2 disposed in the second display area DA2 does not extend toward the first driving voltage supply line 61 and the second driving voltage supply line 62, and is not connected to the first driving voltage supply line 61 and the second driving voltage supply line 62 in the second direction. The second driving voltage line PL2 is not directly connected to the first driving voltage supply line 61 and the second driving voltage supply line 62 in the second direction. The second driving voltage line PL2 is removed in the non-display area NDA between the second display area DA2 and the first driving voltage supply line 61 and in the non-display area NDA between the second display area DA2 and the second driving voltage supply line 62. Thus, in the non-display area NDA, the second driving voltage line PL2 is disconnected from the first driving voltage supply line 61 and the second driving voltage supply line 62. As described above, the second driving voltage line PL2 can receive a driving voltage by being electrically connected to a plurality of connection lines CL (refer to Figure 8 ) and having a mesh shape.

[0128] Figure 13 is an enlarged plan view of a part of the display device 1 in the embodiment. Figure 13 can correspond to Figure 1 the lower right end of the display device 1. Figure 13 can be understood as a region symmetric to part A of Figure 1 .

[0129] Refer to Figure 13 , one side with reference to the reference line RX can be defined as the first display area DA1, and the other side with reference to the reference line RX can be defined as the second display area DA2. The second display area DA2 includes a region containing the rounded corner portion 10C, and the reference line RX can be understood as the point from which the rounded corner portion 10C starts. The edge of the substrate 100 adjacent to the second display area DA2 can be provided in a rounded shape corresponding to the shape of the rounded corner portion 10C.

[0130] The first driving circuit area DCA1 can be provided in the non-display area NDA adjacent to the second display area DA2 in the first direction. Driving circuits such as a transmission control driver (not shown) and Figure 1 the second scanning driver 30 can be arranged in the first driving circuit area DCA1.

[0131] The first switch area SWA1 and the second switch area SWA2 can be arranged in the non-display area NDA adjacent to the first display area DA1 and the second display area DA2 in the second direction. Figure 6 The first switch unit 81 and the second switch unit 82 of Figure 7 can be arranged in the first switch area SWA1 and the second switch area SWA2, and can include the first demultiplexer DMX1 and the second demultiplexer DMX2 as shown in

[0132] The second driving circuit area DCA2 may be provided in the edge of the substrate 100. Figure 1 The data driver 40 may be provided in the second driving circuit area DCA2. Although not shown, film on glass ("FOG"), chip on film ("COG"), etc. may be arranged in the relevant areas.

[0133] The first fan-out area FOA1 may be provided between the first switching area SWA1 and the second switching area SWA2 and the second driving circuit area DCA2. Additionally, the second fan-out area FOA2 may be provided between the second display area DA2 and the second switching area SWA2. The multiplexed data line MDL (refer to Figure 7 ) may be arranged in the first fan-out area FOA1. The data line DL (refer to Figure 7 ) may be arranged in the second fan-out area FOA2.

[0134] Refer to Figure 13 and Figure 7 (or Figure 9 ), compared with the first display area DA1 in which the outer edge of the display unit 10 is set in a straight line, the second display area DA2 in which the outer edge of the display unit 10 is set in a rounded shape includes a limited space of the non-display area NDA where the data line DL and the driving voltage line PL are connected to all the pixels PX in the second display area DA2, that is, the second fan-out area FOA2. When high resolution is achieved and the curvature of the rounded corner portion 10C becomes small, this space is further limited.

[0135] A plurality of second driving voltage lines PL2 arranged in the second display area DA2 are disconnected from the driving voltage supply line 60 and receive electrical signals through a mesh shape as shown in Figure 8 . Through this structure, the space in the second fan-out area FOA2 where the data line DL is arranged between the second display area DA2 and the second switching area SWA2 can be effectively ensured.

[0136] The embodiments may implement such a display device: the display device realizes display areas of various shapes for displaying images and includes a reduced dead zone at the same time. However, the scope of the present invention is not limited by this effect.

[0137] Although the present invention has been described with reference to the embodiments shown in the drawings, this is only provided as an example, and those of ordinary skill in the art will understand that various changes in form and details and their equivalents may be made therein without departing from the spirit and scope of the present invention defined by the present disclosure.

Claims

1. A display device, wherein, The display device includes: a display unit disposed above a substrate and including a first display area and a second display area, each of the first display area and the second display area including a plurality of pixel arrays, and the second display area further including a rounded corner portion; a first line extending in a first direction in a non-display area on one side of the display unit; a plurality of first wirings connected to a plurality of pixels, the plurality of first wirings being arranged in the first direction in the first display area and extending in a second direction intersecting the first direction, extending to an area between the first display area and the first line, and connected to the first line; and a plurality of second wirings connected to a plurality of pixels, the plurality of second wirings being arranged in the first direction in the second display area and being disconnected from the first line in an area between the second display area and the first line.

2. The display device according to claim 1, wherein, The plurality of first wirings and the plurality of wirings are electrically connected to a plurality of connection lines extending in the first direction.

3. The display device according to claim 2, wherein, The plurality of connection lines intersect the plurality of first wirings and the plurality of second wirings to form a grid shape.

4. The display device according to claim 2, wherein, The plurality of first wirings supply a driving voltage to the plurality of pixels provided in the first display area through the plurality of connection lines, and wherein the plurality of second wirings supply the driving voltage to the plurality of pixels provided in the second display area through the plurality of connection lines.

5. The display device according to claim 1, wherein, The display device further includes: a switch unit including a plurality of demultiplexers arranged in the non-display area, demultiplexing data signals, and supplying the demultiplexed data signals to a plurality of data lines; and a second line arranged in parallel with the first line and connected to a terminal unit at an edge of the substrate, the switch unit being between the first line and the second line, wherein the display unit includes a plurality of scan lines and the plurality of data lines respectively connected to the plurality of pixels.

6. The display device according to claim 5, wherein, The switch unit includes: a first switch unit demultiplexing data signals supplied to the first display area; and a second switch unit demultiplexing data signals supplied to the second display area, wherein a plurality of first demultiplexers included in the first switch unit are arranged at a first pitch, and a plurality of second demultiplexers included in the second switch unit are arranged at a second pitch smaller than the first pitch.

7. The display device according to claim 6, wherein, The first line and the second line are electrically connected to each other through a plurality of connection lines arranged between the plurality of first demultiplexers.

8. The display device according to claim 1, wherein, Pixels adjacent to an outer edge of the display unit among the plurality of pixels are arranged stepwise.

9. The display device according to claim 1, wherein, The display unit has one of a polygonal shape, a circular shape, and an oval shape.

10. The display device according to claim 1, wherein, The display device further includes a substrate, the display unit being disposed above the substrate, and the substrate including a curved edge.

11. The display device according to claim 1, wherein, The length of the plurality of second wirings extending in the second direction is less than the length of the plurality of first wirings.

12. A display device, wherein, The display device includes: A display unit in which a first display area and a second display area including corners are defined at an edge of the first display area. The display unit includes a plurality of first pixels and a plurality of second pixels. The plurality of first pixels and the plurality of second pixels are respectively arranged in the first display area and the second display area, and are connected to a plurality of first extension lines and a plurality of wirings extending in a second direction and a plurality of second extension lines extending in a first direction intersecting the second direction; A second driver and a first driver, the second driver and the first driver are arranged in a non-display area outside the display unit; A switch unit, the switch unit includes a plurality of demultiplexers arranged in the non-display area, demultiplexes a first signal output from the first driver, and supplies the demultiplexed first signal to the first extension line; and A conductive wire, the conductive wire is arranged in the non-display area and is connected to the plurality of wirings extending from the display unit, Wherein, the plurality of wirings include a first wiring connected to the plurality of first pixels and a second wiring connected to the plurality of second pixels. The first wiring extends into the non-display area and is connected to the conductive wire, and the second wiring is disconnected from the conductive wire in the non-display area.

13. The display device according to claim 12, wherein, The corner has a rounded shape.

14. The display device according to claim 12, wherein, Pixels adjacent to the outer edge of the display unit among the plurality of first pixels and the plurality of second pixels are arranged stepwise.

15. The display device according to claim 12, wherein, The switch unit further includes: A first switch unit that demultiplexes the first signal supplied to the plurality of first pixels; and A second switch unit that demultiplexes the first signal supplied to the plurality of second pixels, Wherein, the plurality of demultiplexers included in the first switch unit are arranged at a first pitch, and the plurality of demultiplexers included in the second switch unit are arranged at a second pitch smaller than the first pitch.

16. The display device according to claim 12, wherein, The driving voltage supplied to the plurality of wirings is supplied along a grid path.

17. The display device according to claim 12, wherein, The display device further includes a plurality of connection lines extending in the first direction. The plurality of connection lines are connected to the first wiring and the second wiring by contacting the first wiring and the second wiring.

18. The display device according to claim 17, wherein An insulating layer is arranged between the plurality of connection lines and the first wiring and the second wiring, and the plurality of connection lines are electrically connected to the first wiring and the second wiring through contact holes in the insulating layer.

19. The display device according to claim 12, wherein, The conductive wire includes a first line and a second line extending in the first direction. The switch unit is between the first line and the second line. The plurality of wirings are connected to the first line, and the second line is connected to a terminal unit.

20. The display device according to claim 19, wherein The conductive wire further includes a plurality of connection lines connecting the first line and the second line. The plurality of connection lines are arranged between the plurality of demultiplexers.

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