Display panel and display device

Abstract

The invention provides a display device and a display panel thereof. The display panel is provided with a display area and a fan-out area located on one side of the display area. The display panel comprises fan-out wires arranged in a fan-out area, and the area where the fan-out wires are distributed in the fan-out area comprises a first wiring area, a second wiring area and a third wiring area which are sequentially arranged in the direction away from the display area and adjacent to the side edge of the fan-out area. The maximum length of the second wiring area in the direction parallel to the side edge is smaller than or equal to the minimum length of the first wiring area and the third wiring area in the direction parallel to the side edge; in addition, the length of the first wiring area in the direction parallel to the side edge is decreased progressively in the direction away from the side edge, adjacent to the fan-out area, of the display area, and the length of the third wiring area in the direction parallel to the side edge is increased progressively in the direction away from the side edge, adjacent to the fan-out area, of the display area. The distribution density of the fan-out wires in the second wiring area is larger than the distribution density of the fan-out wires in the first wiring area and the third wiring area.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Currently, a fanout area is usually designed in the lower border area of a display panel for transmitting signals of a driving IC to a display area (AA area). In addition, in order to perform defect detection during the panel manufacturing process, a test structure, such as an electrical test pad (ET Pad), is usually further provided within the lower border. The lateral dimension of a conventionally designed display area is generally larger than the lateral dimension of an integrated circuit. After routing, the fanout traces will overall present a fan-shaped distribution, leaving sufficient space on both sides of the integrated circuit. Therefore, test structures can be placed in the non-fanout area within the lower border to meet the detection requirements.

[0003] However, with the miniaturization of display panels, the lateral dimension of the display area gradually approaches the lateral dimension of the integrated circuit. In this case, adopting the conventional fanout trace routing method will cause the space within the lower border to be completely occupied by the fanout traces, and insufficient placement area cannot be provided for the test structures. In the absence of test structures, the defect detection function during the manufacturing process cannot be realized, resulting in defective products not being effectively intercepted, and affecting the yield and reliability of the products. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a display panel and a display device, which can leave sufficient space in the fanout area to arrange other devices by setting multiple trace areas with different widths in the fanout area.

[0005] To achieve the above object, an embodiment of the present disclosure provides a display panel having a display area and a fanout area located on one side of the display area. The display panel includes fanout traces provided in the fanout area. The area where the fanout traces are distributed in the fanout area includes a first trace area, a second trace area, and a third trace area sequentially arranged along a direction away from the side adjacent to the fanout area of the display area. Among them,

[0006] the maximum length of the second trace area in a direction parallel to the side is less than or equal to the minimum length of the first trace area and the third trace area in a direction parallel to the side; and the length of the first trace area in a direction parallel to the side decreases along a direction away from the side adjacent to the fanout area of the display area, and the length of the third trace area in a direction parallel to the side increases along a direction away from the side adjacent to the fanout area of the display area;

[0007] The distribution density of the fan-out traces in the second trace area is greater than that in the first trace area and the third trace area.

[0008] Optionally, the fan-out traces include at least two trace groups, each trace group includes at least one trace; the traces in at least two of the trace groups are distributed on at least two wiring layers in the first trace area and the third trace area.

[0009] Optionally, at least one trace in the fan-out traces has a first sub-trace segment and a second sub-trace segment in the first trace area and / or the third trace area, the first sub-trace segment and the second sub-trace segment are respectively distributed on two wiring layers of the multi-layer wiring layer, and are electrically connected through a jump structure; the resistances of different wiring layers are different.

[0010] Optionally, the fan-out traces include multiple traces of different lengths, and the multiple traces of different lengths are divided into multiple trace clusters according to the trace length, each trace cluster includes at least one trace; the multiple trace clusters include a first trace cluster, the length of the traces in which is in a first length range, wherein the minimum value of the first length range is greater than or equal to a preset length threshold, and the first sub-trace segment and the second sub-trace segment of the traces in the first trace cluster are respectively distributed on two wiring layers of the multi-layer wiring layer, and are electrically connected through a jump structure.

[0011] Optionally, the fan-out traces include at least one single-layer wiring trace group, each single-layer wiring trace group includes at least one trace; the traces in at least one of the single-layer wiring trace groups are distributed on the same wiring layer in the multi-layer wiring layer in the first trace area and the third trace area; the same wiring layer is different from the wiring layer where the first sub-trace segment or the second sub-trace segment is located.

[0012] Optionally, the orthographic projections of the trace segments of the fan-out traces on different wiring layers on the substrate of the display panel at least partially overlap.

[0013] Optionally, the signal polarities of two trace segments of the fan-out traces on adjacent wiring layers and with at least partially overlapping orthographic projections are opposite.

[0014] Optionally, the orthographic projections of two trace segments of the fan-out traces on adjacent wiring layers and with opposite signal polarities on the substrate of the display panel completely overlap.

[0015] Optionally, in the adjacent wiring layers, the line width of the trace segment in one of the wiring layers is greater than the line width of the trace segment in the other wiring layer;

[0016] Among them, the orthographic projection of the trace segment in one of the wiring layers on the substrate overlaps with the orthographic projections of two adjacent trace segments in the other wiring layer at the same time.

[0017] Optionally, test structures are provided on one or both sides of the second trace region in a direction parallel to the side edge.

[0018] On the other hand, the present disclosure provides a display device including the above-mentioned display panel.

[0019] The present disclosure has the following beneficial effects:

[0020] The display panel provided by the present disclosure has a display area and a fan-out area located on one side of the display area. The display panel includes fan-out traces provided in the fan-out area. The area where the fan-out traces are distributed in the fan-out area includes a first trace region, a second trace region, and a third trace region that are sequentially arranged in a direction away from the side edge adjacent to the fan-out area of the display area. The maximum length of the second trace region in a direction parallel to the side edge is less than or equal to the minimum lengths of the first trace region and the third trace region in a direction parallel to the side edge. The length of the first trace region in a direction parallel to the side edge decreases in a direction away from the side edge adjacent to the fan-out area of the display area, and the length of the third trace region in a direction parallel to the side edge increases in a direction away from the side edge adjacent to the fan-out area of the display area. The distribution density of the fan-out traces in the second trace region is greater than their distribution densities in the first trace region and the third trace region. Thus, the display panel provided by the present disclosure forms two fan-shaped trace regions and a densely arranged trace region through the above-mentioned first trace region, second trace region, and third trace region, leaving sufficient space near the densely arranged trace region for placing various devices. Description of the Drawings

[0021] Figure 1 Schematic diagram of the display panel provided in some embodiments of the present disclosure;

[0022] Figure 2 Schematic diagram of the fan-out traces of the display panel provided in some embodiments of the present disclosure in the fan-out area;

[0023] Figure 3 Cross-sectional view of the trace segments of the fan-out traces of the display panel provided in some embodiments of the present disclosure in the first trace region and the third trace region;

[0024] Figure 4 Cross-sectional view of the trace segments of the fan-out traces of the display panel provided in some embodiments of the present disclosure in the first trace region and the third trace region;

[0025] Figure 5 Cross-sectional view of the trace segments of the fan-out traces of the display panel provided in some embodiments of the present disclosure in the first trace region and the third trace region;

[0026] Figure 6 Schematic diagram of a display panel provided in some embodiments of the present disclosure;

[0027] Figure 7 Cross-sectional view of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in the first routing area and the third routing area;

[0028] Figure 8 Cross-sectional view of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in the first routing area and the third routing area;

[0029] Figure 9 Cross-sectional view of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in the first routing area and the third routing area;

[0030] Figure 10 Schematic diagram of partial overlap of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in different wiring layers;

[0031] Figure 11 Schematic diagram of complete overlap of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in different wiring layers;

[0032] Figure 12 Schematic diagram of overlap of the fan-out routing segments of the display panel provided in some embodiments of the present disclosure in different wiring layers;

[0033] Figure 13 Schematic diagram of a display panel provided in some embodiments of the present disclosure;

[0034] Figure 14 Schematic diagram of a display device provided in some embodiments of the present disclosure. Detailed Description of the Embodiments

[0035] The following provides a detailed description of the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present disclosure, and are not intended to limit the present disclosure.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure. Without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" do not necessarily limit to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left" and "right" are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationships may also change accordingly.

[0038] As used herein, "parallel" and "perpendicular" include the stated situations and situations similar to the stated situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5° deviation.

[0039] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0040] In the embodiments of the present disclosure, the first direction, the second direction and the third direction intersect pairwise. In the present disclosure, taking the first direction and the second direction being perpendicular to each other in the plane of the substrate, the first direction being the horizontal direction, the second direction being the vertical direction, and the third direction being the perpendicular direction perpendicular to the plane of the substrate as an example for illustration, it does not constitute a limitation to the present disclosure.

[0041] In the embodiments of the present disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then forming the layer structure by using the same mask through a single patterning process. Depending on the different specific patterns, the patterning process may include multiple exposure, development, or etching processes in sequence, and the specific patterns formed in the same layer may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0042] As Figure 1 shown, an embodiment of the present disclosure provides a display panel 1. The display panel 1 can be applied to a display device D1 and is used to connect to an integrated circuit (e.g., a driving IC) in the display device D1.

[0043] In this embodiment, as Figure 1As shown, the display panel 1 has a display area AA and a fan-out area FO located on one side of the display area AA. The display panel 1 includes fan-out traces 100 disposed in the fan-out area FO. The area where the fan-out traces 100 are distributed in the fan-out area FO includes a first trace area 10, a second trace area 20, and a third trace area 30. The first trace area 10, the second trace area 20, and the third trace area 30 are sequentially arranged along the direction away from the side S of the fan-out area FO adjacent to the display area AA. In other words, the side S of the display area AA extends in a first direction, and the first trace area 10, the second trace area 20, and the third trace area 30 extend away from the side S of the display area AA in a second direction. The maximum length of the second trace area 20 in the direction parallel to the side S is less than or equal to the minimum length of the first trace area 10 and the third trace area 30 in the direction parallel to the side S. In other words, the maximum length L2 of the second trace area 20 in the first direction is less than or equal to the minimum length L1 of the first trace area 10 in the first direction and less than or equal to the minimum length L3 of the third trace area 30 in the first direction. The length of the first trace area 10 in the direction parallel to the side S decreases along the direction away from the side S of the fan-out area FO adjacent to the display area AA. The length of the third trace area 30 in the direction parallel to the side S increases along the direction away from the side S of the fan-out area FO adjacent to the display area AA. In other words, the length of the first trace area 10 in the first direction decreases along the second direction away from the side S. The length of the third trace area 30 in the first direction increases along the second direction away from the side S. The distribution density of the fan-out traces 100 in the second trace area 20 is greater than that in the first trace area 10 and the third trace area 30. Thus, the display panel 1 of the present embodiment forms two fan-shaped trace areas (i.e., the first trace area 10 and the third trace area 30) and a densely arranged trace area (i.e., the second trace area 20) through the above-mentioned first trace area 10, second trace area 20, and third trace area 30, leaving sufficient space near the densely arranged trace area for placing various devices, such as measuring devices (e.g., electrical test pads ET-PAD for defect detection in the manufacturing process).

[0044] On this basis, when the display panel 1 in this embodiment is a small-sized display panel, the size of its display area AA in the first direction (horizontal direction) can be the same as or similar to the size of the driving IC in the first direction, enabling the display panel 1 as a small-sized display panel to provide sufficient placement space for the test structure, thereby meeting the requirement of providing the test structure while ensuring the small-sized design. In some embodiments, the ratio of the size of the display area AA in the first direction to the size of the driving IC of the display device D1 in the first direction can be in the range of 5:4 to 1:1. In some embodiments, the size of the display area AA in the first direction can be the same as the size of the driving IC of the display device D1 in the first direction.

[0045] In some embodiments, the third routing area 30 can be used to connect to other devices. For example, a driving IC.

[0046] In some embodiments, as Figure 2 shown, the routing segments of the fan-out routing 100 in the first routing area 10 and the third routing area 30 can be distributed on a single wiring layer. By distributing the routing on a single wiring layer in the display panel 1 of this embodiment, the parasitic capacitance of the interlayer interconnection is reduced, thereby reducing the overall load of the fan-out routing 100. In addition, single-layer wiring can also avoid the alignment deviation and the risk of interlayer short circuit between multi-layer routings, improving the process tolerance of the routing.

[0047] In some embodiments, as Figure 3 and Figure 4 shown, the fan-out routing 100 can include at least two groups of routing groups, and each group of routing groups includes at least one routing. The routing segments of the routings in at least two groups of routing groups in the first routing area 10 and the third routing area 30 are respectively distributed on at least two wiring layers 200. Specifically, the wiring layers are stacked in the third direction. By multi-layer wiring in the display panel 1 of this embodiment, the fan-out routing 100 adopts a hierarchical layout, reducing the density of single-layer routing, thereby leaving more space on both sides of the routing. In addition, compared with single-layer routing, multi-layer routing reduces the occupied space of the fan-out routing 100 in the longitudinal direction (the second direction) through vertical stacking (the third direction), thereby compressing the lower border width to achieve a narrower border design and improving the screen-to-body ratio.

[0048] In some embodiments, as Figure 3 shown, the fan-out routing 100 can include a first group of routings 110 and a second group of routings 120. The routing segments of the routings in the first group of routings 110 in the first routing area 10 and the third routing area 30 are distributed on the first wiring layer 210. The routing segments of the routings in the second group of routings 120 in the first routing area 10 and the third routing area 30 are distributed on the second wiring layer 220.

[0049] In some embodiments, as Figure 4 shown, the fan-out routing 100 can include a first group of routings 110, a second group of routings 120 and a third group of routings 130. The routing segments of the routings in the first group of routings 110 in the first routing area 10 and the third routing area 30 are distributed on the first wiring layer 210. The routing segments of the routings in the second group of routings 120 in the first routing area 10 and the third routing area 30 are distributed on the second wiring layer 220. The routing segments of the routings in the third group of routings 130 in the first routing area 10 and the third routing area 30 are distributed on the third wiring layer 230.

[0050] In some embodiments, as Figure 5As shown, at least one trace in the fan-out trace 100 may include a first sub-trace segment 101 and a second sub-trace segment 102 in the first trace region 10 and / or the third trace region 30. The first sub-trace segment 101 and the second sub-trace segment 102 are respectively distributed on two wiring layers in the multi-layer wiring layer 200 and are electrically connected through a jump structure V. For example, the jump structure may be a via. The resistances of different wiring layers 200 are different. Through the above settings, the display panel 1 of this embodiment can divide a single trace into a first sub-trace segment 101 and a second sub-trace segment 102 distributed on different wiring layers and use the jump structure to achieve electrical connection, so that the first sub-trace segment 101 and the second sub-trace segment 102 of a part of the traces adopt wiring layers with different resistances, effectively reducing the line resistance difference between the traces.

[0051] In some embodiments, as Figure 6 and Figure 7 shown, the fan-out trace 100 may include multiple traces of different lengths. The multiple traces of different lengths are divided into multiple trace clusters according to the trace length, and each trace cluster includes at least one trace. The multiple trace clusters include a first trace cluster 140. The length of the traces in the first trace cluster 140 is within a first length range LR1. The minimum value of the first length range LR1 is greater than or equal to a preset length threshold. The first sub-trace segment 141 and the second sub-trace segment 142 of the traces in the first trace cluster 140 are respectively distributed on two wiring layers in the multi-layer wiring layer 200 and are electrically connected through a jump structure V. Therefore, to ensure more uniformity of the line group, the display panel 1 of this embodiment utilizes the characteristic that the materials of the multi-layer wiring layer 200 can be different, so that the resistances are different, and the longer edge traces (i.e., the above-mentioned first trace cluster 140) are distributed on different wiring layers with different resistances in different sections according to requirements, thereby achieving a uniform effect. For example, the multiple trace clusters include a first trace cluster 140 and a second trace cluster 150. The length of the traces in the first trace cluster 140 is within a first length range LR1. The first sub-trace segment 141 of the traces in the first trace cluster 140 is located on the first wiring layer 210, and the second sub-trace segment 142 is located on the second wiring layer 220. The resistance of the first wiring layer 210 is lower than that of the second wiring layer 220. In some embodiments, the position of the trace jump of the traces in the first trace cluster 140 is determined according to the length of the trace.

[0052] In some embodiments, as Figure 6 and Figure 8As shown, multiple routing clusters may include a second routing cluster 150, where the lengths of the routes are within a second length range LR2. The first sub-route segment 151 of the routes in the second routing cluster 150 is located on the second wiring layer 220, and the second sub-route segment 152 is located on the first wiring layer 210. The minimum value of the first length range LR1 is greater than the maximum value of the second length range LR2. Thus, in the case where the second sub-route segment 142 of the first routing cluster 140 is located on the second wiring layer 220, the second sub-route segment 152 of the central route with a smaller length (i.e., the above-mentioned second routing cluster 150) is distributed on the first wiring layer 210 to reduce the routing density of the second wiring layer. In some embodiments, the route segments of the routes in the second routing cluster 150 in the first routing area 10 and the third routing area 30 may be distributed on a single wiring layer (e.g., the second wiring layer 220).

[0053] In some embodiments, as Figure 9 shown, the fan-out route 100 may include at least one single-layer wiring route group 160, and each group of single-layer wiring route groups 160 includes at least one route. The route segments of the routes in at least one group of single-layer wiring route groups in the first routing area 10 and the third routing area 30 are distributed on the same wiring layer in the multi-layer wiring layer 200. The same wiring layer is different from the wiring layer where the above-mentioned first sub-route segment or second sub-route segment is located. In other words, the route segments of the routes in the single-layer wiring route group 160 in the first routing area 10 and the third routing area 30 may be distributed on a single wiring layer. For example, the routes in the single-layer wiring route group 160 may be distributed on the third wiring layer 230. Through the above-mentioned method of combining single-layer wiring with multi-layer jump wiring, the display panel 1 of this embodiment can transmit important signals through single-layer wiring and transmit the remaining signals through multi-layer jump wiring, maintaining the simplicity of the wiring structure, making the single-layer wiring and the multi-layer jump wiring complementary, so as to reduce the bezel width while maintaining the signal transmission quality.

[0054] In some embodiments, as Figure 10 shown, the orthographic projections of the route segments of the fan-out route 100 located on different wiring layers on the substrate of the display panel 1 may at least partially overlap, so as to improve the utilization rate of the routing space and the curing efficiency of the sealant on the premise of ensuring signal quality. For example, the orthographic projections of the route segment 171 and the route segment 172 in the adjacent wiring layer (the wiring layer is omitted in the figure) in the third direction at least partially overlap.

[0055] In some embodiments, the signals carried by two route segments of the fan-out route 100 that are on adjacent wiring layers and whose orthographic projections at least partially overlap may have opposite polarities, and the electromagnetic fields generated by the opposite-polarity signals cancel each other out to solve the signal interference problem in the narrow bezel design.

[0056] In some embodiments, the signals carried by two wire segments in the fan-out trace 100 that are on adjacent wiring layers and whose orthographic projections at least partially overlap may have the same polarity to reduce the coupling capacitance between the traces.

[0057] In some embodiments, as Figure 11 shown, for two wire segments in the fan-out trace 100 that are on adjacent wiring layers and have opposite signal polarities, their orthographic projections on the substrate of the display panel 1 may completely overlap. For example, the orthographic projections of wire segment 171 and wire segment 172 in an adjacent wiring layer (the wiring layer is omitted in the figure) in the third direction completely overlap.

[0058] In some embodiments, as Figure 12 shown, in adjacent wiring layers, the line width of the wire segment in one of the wiring layers is greater than that of the wire segment in the other wiring layer. The orthographic projection of the wire segment in this one wiring layer on the substrate overlaps with the orthographic projections of two adjacent wire segments in the other wiring layer at the same time. For example, the orthographic projections of two wire segments 181 and 182 in the third direction overlap.

[0059] In some embodiments, as Figure 13 shown, a test structure 40 is provided on one side or both sides of the second trace region 20 in a direction parallel to the side S.

[0060] In some embodiments, the width of the wire segments of the fan-out trace 100 located in different wiring layers 200 is proportional to the wiring layer 200.

[0061] In some embodiments, an isolation layer may be provided between adjacent wiring layers.

[0062] As Figure 14 shown, an embodiment of the present disclosure also provides a display device D1. The display device D1 includes the above-mentioned display panel 1. Thus, by providing the above-mentioned first trace region 10, second trace region 20, and third trace region 30, the display device D1 of this embodiment forms two fan-shaped trace regions (i.e., the first trace region 10 and the third trace region 30) and a densely arranged trace region (i.e., the second trace region 20), leaving sufficient space near the densely arranged trace region for placing various devices, such as a measuring device (e.g., an electrical test pad ET-PAD for defect detection in the manufacturing process).

[0063] As Figure 14 shown, the display device D1 may include a driving IC. Actually, when performing display, it is necessary to combine the driving of the source driving circuit and the gate driving circuit for display.

[0064] Accordingly, a display panel 1 and a display device D1 proposed by embodiments of the present disclosure can set a plurality of routing areas with different widths in the fan-out region FO, leaving sufficient space in the fan-out region to arrange other devices. On this basis, through various embodiments, while achieving the above technical effects, the requirement for the border width is reduced and the signal quality is maintained.

[0065] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the disclosure herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0066] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A display panel having a display area and a fan-out area located on one side of the display area, characterized in that, The display panel includes fan-out traces disposed in the fan-out region. The region where the fan-out traces are distributed in the fan-out region includes a first trace region, a second trace region, and a third trace region that are sequentially arranged along a direction away from the side adjacent to the fan-out region of the display region. Among them, the maximum length of the second trace region in the direction parallel to the side is less than or equal to the minimum length of the first trace region and the third trace region in the direction parallel to the side; and, the length of the first trace region in the direction parallel to the side decreases along the direction away from the side adjacent to the fan-out region of the display region, and the length of the third trace region in the direction parallel to the side increases along the direction away from the side adjacent to the fan-out region of the display region; the distribution density of the fan-out traces in the second trace region is greater than their distribution density in the first trace region and the third trace region.

2. The display panel according to claim 1, wherein The fan-out traces include at least two sets of trace groups, and each set of the trace groups includes at least one trace; the trace segments of the traces in at least two sets of the trace groups in the first trace region and the third trace region are respectively distributed on at least two wiring layers.

3. The display panel according to claim 1, wherein At least one trace segment of the fan-out traces in the first trace region and / or the third trace region includes a first sub-trace segment and a second sub-trace segment. The first sub-trace segment and the second sub-trace segment are respectively distributed on two wiring layers of the multi-layer wiring layer and are electrically connected through a jump structure; the resistances of different wiring layers are different.

4. The display panel according to claim 3, wherein, The fan-out traces include multiple traces of different lengths, and the multiple traces of different lengths are divided into multiple trace clusters according to the trace length. Each trace cluster includes at least one trace; the multiple trace clusters include a first trace cluster, and the lengths of the traces therein are within a first length range, where the minimum value of the first length range is greater than or equal to a preset length threshold, and the first sub-trace segment and the second sub-trace segment of the traces in the first trace cluster are respectively distributed on two wiring layers of the multi-layer wiring layer and are electrically connected through a jump structure.

5. The display panel according to claim 3, characterized in that The fan-out traces include at least one single-layer wiring trace group, and each set of the single-layer wiring trace groups includes at least one trace; the trace segments of the traces in at least one set of the single-layer wiring trace groups in the first trace region and the third trace region are distributed on the same wiring layer of the multi-layer wiring layer; the same wiring layer is different from the wiring layer where the first sub-trace segment or the second sub-trace segment is located.

6. The display panel according to any one of claims 2 to 5, wherein the orthographic projections of the trace segments of the fan-out traces located in different wiring layers on the substrate of the display panel at least partially overlap.

7. The display panel according to claim 6, wherein The signal polarities of two trace segments of the fan-out traces that are on adjacent wiring layers and whose orthographic projections at least partially overlap are opposite.

8. The display panel according to claim 7, characterized in that, The orthographic projections of two trace segments of the fan-out traces that are on the adjacent wiring layers and have opposite signal polarities completely overlap on the substrate of the display panel.

9. The display panel according to claim 7, wherein Among the adjacent wiring layers, the line width of the trace segment in one wiring layer is greater than the line width of the trace segment in the other wiring layer; Among them, the orthographic projection of the trace segment in one of the wiring layers on the substrate overlaps the orthographic projections of two adjacent trace segments in the other wiring layer at the same time.

10. The display panel according to any one of claims 2 to 5, characterized in that, The second trace region is provided with a test structure on one side or both sides in the direction parallel to the side edge.

11. A display device, characterized in that, It includes a display panel according to any one of claims 1 to 10.

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