Preparation method of packaging structure of Hall sensor

Abstract

The embodiment of the invention discloses a preparation method of a packaging structure of a Hall sensor. The preparation method comprises the following steps: providing a target integrated chip, a frame and an isolation gasket; the target integrated chip comprises a substrate and a circuit layer which are laminated; the circuit layer comprises a Hall sensor and a functional bonding pad; the frame comprises a primary frame and a secondary frame; performing film turning on the target integrated chip to enable the circuit layer to face downwards and the substrate to face upwards; the frame is turned over, so that the silver-plated surfaces of the pins face downwards; one side of the isolation gasket is attached to the primary side frame; attaching the circuit layer to the other side of the isolation gasket to obtain a chip mounting structure; the target integrated chip is bonded with the secondary frame, and the functional bonding pad is welded with the silver-plated surface of the pin to obtain the packaging structure, so that the Hall sensor can be ensured to be located on one side, close to the primary frame, of the integrated chip, the distance between the Hall sensor and the primary frame is reduced, the magnetic flux sensed by the Hall sensor is improved, and the reliability of the Hall sensor is improved. And the product sensitivity is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a packaging structure of a Hall sensor. Background Art

[0002] Hall effect current sensors are widely used in various fields that require current detection, such as photovoltaic and frequency converters.

[0003] Figure 1 As a schematic diagram of a packaging structure of a Hall sensor in the prior art, as Figure 1 shown, the magnetic field generated by the energization of the primary frame 10' vertically penetrates the Hall sensor 301'. In the prior art, the side of the target integrated chip 30' where the Hall sensor 301' is disposed is far from the primary frame 10'. The distance between the Hall sensor 301' and the primary frame 10' is at least the sum of the thickness of the target integrated chip 30' and the thickness of the isolation gasket 40'. The distance between the Hall sensor 301' and the primary frame 10' is at least 200μm - 250μm. Since the distance between the Hall sensor and the primary frame is relatively far, the magnetic flux sensed by the Hall sensor is less, which will affect the sensitivity of the packaging structure. Summary of the Invention

[0004] An embodiment of the present invention provides a method for preparing a packaging structure of a Hall sensor, so that the Hall sensor is located on the side of the integrated chip close to the primary frame, thereby reducing the distance between the Hall sensor and the primary frame, increasing the magnetic flux sensed by the Hall sensor, and improving the sensitivity of the product.

[0005] An embodiment of the present invention provides a method for preparing a packaging structure of a Hall sensor, including:

[0006] Providing a target integrated chip, a frame, and an isolation gasket; the target integrated chip includes a substrate and a circuit layer stacked; the circuit layer includes a Hall sensor and a functional pad; the frame includes a primary frame and a secondary frame, and the secondary frame includes a pin silver-plated surface;

[0007] Turning over the target integrated chip so that the circuit layer faces downward and the substrate faces upward;

[0008] Turning over the frame so that the pin silver-plated surface faces downward;

[0009] Attaching one side of the isolation gasket to the primary frame;

[0010] Attaching the circuit layer to the other side of the isolation gasket to obtain a chip mounting structure;

[0011] Bond the target integrated chip to the secondary side frame, and weld the functional pads to the silver-plated surfaces of the pins to obtain a packaged structure.

[0012] Optionally, after attaching the circuit layer to the other side of the isolation gasket to obtain a die-attached structure, the method further includes:

[0013] Flip the die-attached structure to expose the silver-plated surfaces of the pins and the functional pads.

[0014] Optionally, after bonding the target integrated chip to the secondary side frame and welding the functional pads to the silver-plated surfaces of the pins to obtain a packaged structure, the method further includes:

[0015] Encapsulate and cure the packaged structure with a molding compound.

[0016] Optionally, attaching the circuit layer to the other side of the isolation gasket to obtain a die-attached structure includes:

[0017] Attach the circuit layer to the other side of the isolation gasket with glue;

[0018] Bake and cure the glue to obtain a die-attached structure.

[0019] Optionally, attaching one side of the isolation gasket to the primary side frame includes:

[0020] Attach one side of the isolation gasket to the primary side frame through a die attach film, and bake and cure the die attach film.

[0021] Optionally, after flipping the target integrated chip so that the circuit layer faces down and the substrate faces up, the method further includes:

[0022] Place the circuit layer on a carrier film to support the target integrated chip.

[0023] Optionally, providing a target integrated chip includes:

[0024] Provide a wafer;

[0025] Thin and dice the wafer to obtain a target integrated chip.

[0026] Optionally, before bonding the target integrated chip to the secondary side frame and welding the functional pads to the silver-plated surfaces of the pins to obtain a packaged structure, the method further includes:

[0027] Ion clean the target integrated chip.

[0028] Optionally, the thickness H1 of the target integrated chip satisfies: H1 ≥ 100 μm.

[0029] Optionally, the distance H2 between the Hall sensor and the primary side frame satisfies: 50 μm ≤ H2 ≤ 100 μm.

[0030] The technical solution provided by the embodiment of the present invention flips the target integrated chip so that the circuit layer faces downward and the substrate faces upward, so as to paste the circuit layer with the isolation gasket and ensure that the Hall chip is located on the side close to the primary side frame. The frame is flipped so that the silver-plated surface of the pin faces downward, so that the functional pads on the subsequent integrated chip have the same orientation as the silver-plated surface of the pin, facilitating welding between the two. In this way, the target integrated chip, the isolation gasket, and the frame arranged in a stacked manner can be obtained, and the distance between the Hall sensor and the primary side frame is relatively close. When a current passes through the primary side frame to generate a magnetic field, the magnetic flux sensed by the Hall sensor can be increased, improving the sensitivity of the packaging structure. Description of the Drawings

[0031] Figure 1 Schematic diagram of a packaging structure of a Hall sensor in the prior art;

[0032] Figure 2 Schematic flow chart of a preparation method for a packaging structure of a first Hall sensor provided by an embodiment of the present invention;

[0033] Figure 3 Schematic diagram of a packaging structure of a Hall sensor provided by an embodiment of the present invention;

[0034] Figure 4 Schematic diagram of a structure of a target integrated chip provided by an embodiment of the present invention;

[0035] Figure 5 Schematic diagram of a structure before flipping of a frame provided by an embodiment of the present invention;

[0036] Figure 6 Schematic diagram of a structure after flipping of a frame provided by an embodiment of the present invention;

[0037] Figure 7 Schematic diagram of the attachment of an isolation gasket to a primary side frame provided by an embodiment of the present invention;

[0038] Figure 8 Schematic diagram of the attachment of a circuit layer to an isolation gasket provided by an embodiment of the present invention;

[0039] Figure 9 Schematic flow chart of a preparation method for a packaging structure of a second Hall sensor provided by an embodiment of the present invention;

[0040] Figure 10 Schematic diagram of a structure before flipping of a chip mounting structure provided by an embodiment of the present invention;

[0041] Figure 11 Schematic diagram of the structure after flipping the chip mounting structure provided by an embodiment of the present invention;

[0042] Figure 12 Schematic flow chart of the preparation method of the third packaging structure of the Hall sensor provided by an embodiment of the present invention;

[0043] Figure 13 Schematic flow chart of the preparation method of the fourth packaging structure of the Hall sensor provided by an embodiment of the present invention. Detailed implementation manners

[0044] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that only the parts related to the present invention rather than all the structures are shown in the drawings for the convenience of description.

[0045] Figure 2 Schematic flow chart of the preparation method of the first packaging structure of the Hall sensor provided by an embodiment of the present invention, as Figure 2 shown, the preparation method of the packaging structure includes:

[0046] S101. Provide a target integrated chip, a frame, and an isolation gasket; the target integrated chip includes a substrate and a circuit layer stacked; the circuit layer includes a Hall sensor and functional pads; the frame includes a primary frame and a secondary frame, and the secondary frame includes a silver-plated surface of the pin.

[0047] Specifically, Figure 3 Schematic diagram of a packaging structure of a Hall sensor provided by an embodiment of the present invention, Figure 4 Schematic diagram of a target integrated chip provided by an embodiment of the present invention, as Figure 3 and Figure 4 shown, the target integrated chip 30 may be an Application Specific Integrated Circuit (ASIC). The substrate can be understood as the silicon dioxide layer of the target integrated chip, and the circuit layer can be understood as the film layer in the integrated chip where the Hall sensor 301 and the functional pads 302 are provided. Exemplarily, the number of Hall sensors may be multiple.

[0048] Specifically, continue to refer to Figure 3, the frame 100 includes a primary side frame 10 and a secondary side frame 20. The primary side frame 10 can be a copper frame. When current is introduced into the primary side pin distribution part 101 of the primary side frame 10, a magnetic field will be generated in the primary side frame 10. The Hall sensor 301 located on one side of the primary side frame 10 can sense the magnetic field in the vertical direction and convert the magnetic signal into an electrical signal, thereby realizing the measurement and detection of current. The functional pad 302 is generally located at the edge position on one side of the target integrated chip 30. The functional pad 302 can be electrically connected to the silver-plated surface 201 of the pin of the secondary side frame 20 through a lead, so that signal transmission can be carried out, and it is convenient to detect signals through the pins with silver-plated surfaces.

[0049] S102. Flip the target integrated chip so that the circuit layer faces down and the substrate faces up.

[0050] Specifically, as a comparative example, in the preparation process of the packaging structure of the Hall sensor in the prior art, it is not necessary to flip the target integrated chip. That is, the conventional way of laminating the target integrated chip is to have the circuit layer facing up and the substrate facing down. After the packaging structure is prepared in this way, the Hall sensor is located on the side of the target integrated chip away from the primary side frame. However, in the technical solution provided by the embodiments of the present invention, the target integrated chip is flipped, that is, the target integrated chip is flipped by 180°, so that the circuit layer faces down and the substrate faces up, so as to subsequently arrange the Hall sensor on the side close to the primary side frame, thereby reducing the distance between the Hall sensor and the primary side frame.

[0051] S103. Flip the frame so that the silver-plated surface of the pin faces down.

[0052] Specifically, Figure 5 is a schematic structural diagram of the frame before flipping provided by the embodiments of the present invention. Figure 6 is a schematic structural diagram of the frame after flipping provided by the embodiments of the present invention. As shown in Figure 5 and Figure 6 shown, flipping the frame by 180° so that the silver-plated surface of the pin faces down is beneficial for subsequent welding of the functional pad and the silver-plated surface of the pin.

[0053] S104. Attach one side of the isolation gasket to the primary side frame.

[0054] Specifically, Figure 7 is an attachment schematic diagram of the isolation gasket and the primary side frame provided by the embodiments of the present invention. As shown in Figure 7 shown, attach one side of the isolation gasket 40 to the primary side frame 10 to realize the fixation of the two. It should be noted that the loading direction of the isolation gasket 40 is perpendicular to the primary side frame and falls on the primary side frame.

[0055] Exemplarily, the thickness of the isolation gasket 40 is about 50 μm.

[0056] S105. Attach the circuit layer to the other side of the isolation spacer to obtain a chip mounting structure.

[0057] Specifically, Figure 8 is a schematic diagram of the attachment of the circuit layer and the isolation spacer provided by the embodiment of the present invention. As Figure 8 shown, attach the circuit layer to the other side of the isolation spacer. That is to say, attach the side of the target integrated chip containing the circuit layer to the isolation spacer, so that the Hall sensor can be located on the side close to the primary frame, and then the bonding between the primary frame, the isolation spacer and the target integrated chip can be realized to obtain a chip mounting structure.

[0058] S106. Bond the target integrated chip to the secondary frame, and weld the functional pads to the silver-plated surface of the pins to obtain a packaged structure.

[0059] Specifically, continue to refer to Figure 3 , and gold wire or copper wire can be used to weld the functional pads 302 to the silver-plated surface 201 of the pins by ultrasonic welding to obtain a chip mounting structure, so that the signal transmission between the target integrated chip and the secondary frame can be realized.

[0060] Optionally, the distance H2 between the Hall sensor and the primary frame satisfies: 50 μm ≤ H2 ≤ 100 μm.

[0061] As a comparative example, in the prior art, the Hall sensor is located on the side far from the primary frame, and the distance between the Hall sensor and the primary frame is at least 200 μm - 250 μm. In the embodiment of the present invention, by arranging the Hall sensor on the side of the integrated chip facing the primary frame, the distance between the Hall sensor and the primary frame is independent of the thickness of the target integrated chip, and the distance between the Hall sensor and the primary frame can be directly reduced. The distance H2 between the Hall sensor and the primary frame satisfies: 50 μm ≤ H2 ≤ 100 μm. Exemplarily, the distance H2 between the Hall sensor and the primary frame is 75 μm. In this way, the distance between the primary frame and the Hall sensor can be reduced, and then the distance between the Hall sensor and the magnetic field can be reduced, the magnetic flux sensed by the Hall sensor can be increased, and the sensitivity of the packaged structure of the Hall sensor can be improved.

[0062] The preparation method of the packaging structure of the Hall sensor provided by the embodiment of the present invention flips the target integrated chip so that the circuit layer faces downward and the substrate faces upward, so as to paste the circuit layer with the isolation gasket, ensuring that the Hall chip is located on the side close to the primary frame. Flip the frame so that the silver-plated surface of the pin faces downward, so that the functional pads on the subsequent integrated chip have the same orientation as the silver-plated surface of the pin, facilitating welding between the two. In this way, the target integrated chip, the isolation gasket, and the frame can be obtained in a stacked arrangement, and the distance between the Hall sensor and the primary frame is relatively close. When a current passes through the primary frame to generate a magnetic field, the magnetic flux sensed by the Hall sensor can be increased, improving the sensitivity of the packaging structure.

[0063] Optionally, Figure 9 It is a schematic flowchart of the preparation method of the second packaging structure of the Hall sensor provided by the embodiment of the present invention. Figure 9 On the basis of the above embodiment, the operations after attaching the circuit layer to the other side of the isolation gasket to obtain the chip mounting structure and the operations after bonding the target integrated chip to the secondary frame and welding the functional pads to the silver-plated surface of the pins to obtain the packaging structure are elaborated in detail. As Figure 9 shown, the preparation method of this packaging structure includes:

[0064] S201. Provide a target integrated chip, a frame, and an isolation gasket; the target integrated chip includes a substrate and a circuit layer arranged in a stacked manner; the circuit layer includes a Hall sensor and functional pads; the frame includes a primary frame and a secondary frame, and the secondary frame includes a silver-plated surface of the pin.

[0065] S202. Flip the target integrated chip so that the circuit layer faces downward and the substrate faces upward.

[0066] S203. Flip the frame so that the silver-plated surface of the pin faces downward.

[0067] S204. Attach one side of the isolation gasket to the primary frame.

[0068] S205. Attach the circuit layer to the other side of the isolation gasket to obtain a chip mounting structure.

[0069] S206. Flip the chip mounting structure to expose the silver-plated surface of the pin and the functional pads.

[0070] Specifically, Figure 10 It is a schematic diagram of the structure before flipping of a chip mounting structure provided by the embodiment of the present invention. Figure 11 It is a schematic diagram of the structure after flipping of a chip mounting structure provided by the embodiment of the present invention. As Figure 10 and Figure 11As shown, the rotating piece structure is flipped by 180°, making the silver-plated surface of the pins and the functional pads face upward, facilitating the soldering of the silver-plated surface of the pins and the functional pads through leads.

[0071] S207. Bond the target integrated chip to the secondary side frame, solder the functional pads to the silver-plated surfaces of the pins, and obtain a packaged structure.

[0072] S208. Encapsulate and cure the packaged structure with an encapsulation material.

[0073] Specifically, encapsulating the packaged structure with an encapsulation material means using the encapsulation material to wrap the packaged structure, which plays roles of protection, isolation, and insulation. In addition, the encapsulated structure is baked in an oven at a temperature of 170°C - 180°C to completely cure the encapsulation material and release internal stress.

[0074] Exemplarily, the encapsulation material can be a thermosetting resin.

[0075] It should be noted that after encapsulating and curing the packaged structure with an encapsulation material, it also includes steps such as an electroplating process, laser printing, lead cutting and forming, appearance inspection, and packaging.

[0076] Specifically, the electroplating process can be understood as electroplating tin on the external pins of the frame, which is beneficial for the subsequent packaged finished product to be soldered onto the circuit board by means of reflow soldering and surface mounting. Laser printing can print information such as required numbers, letters, or company symbols on the front of the product through laser engraving or other means. Lead cutting and forming can cut the positions that do not need to be connected between the pins through equipment fixtures, cut the whole row of products into single products, and bend the product pins into the required dimensions and angles according to requirements. Appearance inspection mainly conducts appearance inspection on the packaged finished product by means of manual visual inspection and sampling inspection, rejects the non-conforming defective products, and retains the qualified products for shipment. Packaging mainly puts the packaged finished product into a paper box and affixes a product label according to requirements to facilitate the product not being damaged during the subsequent transportation process.

[0077] In the preparation method of the packaged structure of the Hall sensor provided by the embodiment of the present invention, the rotating piece structure is flipped by 180°, making the silver-plated surface of the pins and the functional pads face upward, facilitating the soldering of the silver-plated surface of the pins and the functional pads through leads. In addition, encapsulating and curing the packaged structure with an encapsulation material can play roles of protecting, isolating, insulating, and releasing stress on the packaged structure.

[0078] Optionally, Figure 12 is a schematic flow chart of the preparation method of the third packaged structure of the Hall sensor provided by the embodiment of the present invention. Figure 12Based on the above embodiments, the operations of attaching the circuit layer to the other side of the isolation gasket to obtain the chip mounting structure and attaching one side of the isolation gasket to the primary side frame are elaborated in detail. As Figure 12 shown, the preparation method of the packaging structure includes:

[0079] S301. Provide a target integrated chip, a frame, and an isolation gasket; the target integrated chip includes a substrate and a circuit layer arranged in a stacked manner; the circuit layer includes a Hall sensor and functional pads; the frame includes a primary side frame and a secondary side frame, and the secondary side frame includes a silver-plated pin surface.

[0080] S302. Flip the target integrated chip so that the circuit layer faces down and the substrate faces up.

[0081] S303. Flip the frame so that the silver-plated pin surface faces down.

[0082] S304. Attach one side of the isolation gasket to the primary side frame through a die attach film, and bake and cure the die attach film.

[0083] As a comparative example, in the prior art, glue is used to bond the isolation gasket and the primary side frame. Due to the large fluidity of the glue, during the bonding process of the isolation gasket and the primary side frame, the glue will overflow at the edge contour position of the primary side frame, and then foreign matter contamination will occur, resulting in insufficient creepage distance and weakening the isolation withstand voltage ability.

[0084] Specifically, in the embodiment of the present invention, the die attach film (DAF) is attached to one side of the isolation gasket, and the bonding between the isolation gasket and the primary side frame is realized through the die attach film, which can avoid the problem of insufficient creepage distance caused by foreign matter contamination due to glue overflow during the bonding process of the isolation gasket and the primary side frame. Furthermore, it can reduce the risk of withstand voltage failure, improve the isolation withstand voltage requirement, meet the isolation withstand voltage condition of applying a voltage of 6 kV, an alternating current frequency of 50 Hz, and an applied voltage time of 60 s, and improve the product yield.

[0085] Specifically, using an oven, by setting the temperature in the oven to 130 °C and the baking time to 1 hour, the curing of the die attach film is completed.

[0086] S305. Attach the circuit layer to the other side of the isolation gasket through glue.

[0087] Specifically, the glue can be a photoresist, and the main material of the photoresist can be a polyimide material. During the preparation process of the packaging structure of the Hall sensor, a layer of photoresist is coated on the side of the integrated chip where the Hall sensor is provided by using semiconductor processing technology. The photoresist serves as an isolation protection between the surface circuit of the chip and the external bonding material, playing an additional role in strengthening insulation isolation.

[0088] S306. Bake and cure the glue to obtain a chip mounting structure.

[0089] Specifically, cure the glue. The cured glue acts as a medium between the chip and the isolation gasket. The excellent stress absorption and buffering can be achieved by using the glue, and part of the stress applied to the chip from the frame and the gasket can be eliminated.

[0090] Specifically, cure the glue by setting the temperature in the oven to 125 °C and the baking time to 26 minutes to turn the liquid glue into a solid state.

[0091] S307. Bond the target integrated chip to the secondary side frame, and weld the functional pads to the silver-plated surface of the pins to obtain a package structure.

[0092] In the method for preparing the package structure of the Hall sensor provided by the embodiment of the present invention, the bonding between the target integrated chip and the isolation gasket is realized by using a photoresist, and the bonding between the isolation gasket and the primary side frame is realized by using a mounting film. On the one hand, the bonding effect can be guaranteed, on the other hand, the thinning setting of the package structure can be realized, and the stability and reliability of the package structure can be improved.

[0093] Optionally, Figure 13 is a schematic flowchart of the method for preparing the package structure of the fourth Hall sensor provided by the embodiment of the present invention. Figure 13 Based on the above embodiments, the operations after turning over the target integrated chip so that the circuit layer faces down and the substrate faces up, the operation of providing the target integrated chip, and the operations before bonding the target integrated chip to the secondary side frame and welding the functional pads to the silver-plated surface of the pins to obtain a package structure are elaborated in detail. As Figure 13 shown, the method for preparing the package structure includes:

[0094] S401. Provide a wafer, a frame, and an isolation gasket; the target integrated chip includes a substrate and a circuit layer stacked; the circuit layer includes a Hall sensor and functional pads; the frame includes a primary side frame and a secondary side frame, and the secondary side frame includes a silver-plated surface of the pins.

[0095] Specifically, the wafer may include multiple target integrated chips. Exemplarily, the size of the wafer may be 6 inches, 8 inches, or 12 inches.

[0096] S402. Thin and slice the wafer to obtain the target integrated chip.

[0097] Specifically, the thickness of a general wafer is 725 μm. Exemplarily, the wafer thickness can be thinned to 150 μm, 200 μm, etc. The embodiments of the present invention do not specifically limit the thickness of the wafer after thinning, and can be thinned according to actual needs.

[0098] As a comparative example, in the prior art, the Hall sensor is located on the side of the integrated chip away from the primary side frame. By thinning the thickness of the integrated chip, the distance between the Hall sensor and the primary side frame can be reduced. However, when the thickness of the integrated chip is relatively thin, there is a risk of fragmentation, which affects the stability and reliability of the packaging structure. It should be noted that the target integrated chip thickness H1≥100 μm after wafer thinning is beneficial to ensure the stability of the integrated chip and prevent the risk of fragmentation due to the relatively thin thickness of the integrated chip.

[0099] S403. Flip the target integrated chip so that the circuit layer faces down and the substrate faces up.

[0100] S404. Place the circuit layer on the carrier film to support the target integrated chip.

[0101] Specifically, attach the side of the target integrated chip with the circuit layer to the blue film, with the circuit layer facing down and the substrate facing up, to prepare for bonding the circuit layer to the isolation gasket later. The carrier film can play a role in supporting the target integrated chip. All the chips on the entire wafer are carried by the carrier film during the transfer and operation in the previous process.

[0102] Exemplarily, the carrier film can be a blue film.

[0103] S405. Flip the frame so that the silver-plated surface of the pin faces down.

[0104] S406. Attach one side of the isolation gasket to the primary side frame.

[0105] S407. Attach the circuit layer to the other side of the isolation gasket to obtain a chip mounting structure.

[0106] S408. Perform ion cleaning on the target integrated chip.

[0107] Specifically, mainly using argon, hydrogen or oxygen, after excitation, dissociation and ionization, functional substances, ions and free radicals will be generated. These substances help to remove the contamination on the surface of the target chip before bonding, strengthen the bonding ability between the subsequent plastic packaging material and the target chip and the frame, reduce product delamination, and also improve the operability of bonding.

[0108] S409. Bond the target integrated chip to the secondary side frame, and weld the functional pads to the silver-plated surface of the pins to obtain a packaging structure.

[0109] The preparation method of the packaging structure of the Hall sensor provided by the embodiment of the present invention thins the wafer before obtaining the target integrated chip to ensure that the thickness of the target integrated chip is appropriate, thereby ensuring the performance of the target integrated chip. In addition, after ion cleaning the target integrated chip and then bonding, the bonding effect between the target integrated chip and the secondary side frame can be ensured, thereby ensuring the stability and reliability of the product.

[0110] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A preparation method of a packaging structure of a Hall sensor, characterized in that, Including: Providing a target integrated chip, a frame, and an isolation spacer; the target integrated chip includes a substrate and a circuit layer arranged in a stack; the circuit layer includes a Hall sensor and functional pads; the frame includes a primary-side frame and a secondary-side frame, and the secondary-side frame includes a silver-plated pin surface; Turning over the target integrated chip so that the circuit layer faces down and the substrate faces up; Turning over the frame so that the silver-plated pin surface faces down; Attaching one side of the isolation spacer to the primary-side frame; Attaching the circuit layer to the other side of the isolation spacer to obtain a chip mounting structure; Bonding the target integrated chip to the secondary-side frame and soldering the functional pads to the silver-plated pin surface to obtain a packaged structure.

2. The manufacturing method of the encapsulation structure according to claim 1, characterized in that After attaching the circuit layer to the other side of the isolation spacer to obtain a chip mounting structure, it further includes: Turning over the chip mounting structure to expose the silver-plated pin surface and the functional pads.

3. The manufacturing method of the encapsulation structure according to claim 1, characterized in that, After bonding the target integrated chip to the secondary-side frame and soldering the functional pads to the silver-plated pin surface to obtain a packaged structure, it further includes: Encapsulating and curing the packaged structure with a molding material.

4. The preparation method of the encapsulation structure according to claim 1, wherein, Attaching the circuit layer to the other side of the isolation spacer to obtain a chip mounting structure, including: Attaching the circuit layer to the other side of the isolation spacer with glue; Baking and curing the glue to obtain a chip mounting structure.

5. The manufacturing method of the encapsulation structure according to claim 1, characterized in that, Attaching one side of the isolation spacer to the primary-side frame, including: Attaching one side of the isolation spacer to the primary-side frame through a chip mounting film and baking and curing the chip mounting film.

6. The preparation method of the encapsulation structure according to claim 1, wherein After turning over the target integrated chip so that the circuit layer faces down and the substrate faces up, it further includes: Placing the circuit layer on a carrier film to support the target integrated chip.

7. The manufacturing method of the encapsulation structure according to claim 1, characterized in that, Providing a target integrated chip, including: Providing a wafer; Thinning and dicing the wafer to obtain a target integrated chip.

8. The manufacturing method of the encapsulation structure according to claim 1, characterized in that, Before bonding the target integrated chip to the secondary-side frame and soldering the functional pads to the silver-plated pin surface to obtain a packaged structure, it further includes: Performing ion cleaning on the target integrated chip.

9. The manufacturing method of the encapsulation structure according to claim 1, characterized in that, The thickness H1 of the target integrated chip satisfies: H1≥100μm.

10. The manufacturing method of the encapsulation structure according to claim 1, wherein, The distance H2 between the Hall sensor and the primary-side frame satisfies: 50μm≤H2≤100μm.

Images