Semiconductor device, display device, and electronic apparatus

Abstract

Provided is a semiconductor device that operates stably. The semiconductor device includes first to fourth transistors. The first to fourth transistors include a first insulator. The first and second transistors each include a first gate insulating film, and the third and fourth transistors each include a second gate insulating film. The first and second transistors each include a first channel formation region along a side surface of a first opening formed in the first insulator, and the third and fourth transistors each include a second channel formation region along a side surface of a second opening formed in the first insulator. The first gate insulating film is over the first channel formation region, and the second gate insulating film is over the second channel formation region. The first gate insulating film is thicker than the second gate insulating film. The first and second transistors are electrically connected in series, and the third and fourth transistors are electrically connected in series.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification can include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods. Background Art

[0003] In recent years, for example, various improvements have been made to display devices in electronic devices for VR (Virtual Reality), AR (Augmented Reality), etc., such as XR (Extended Reality or Cross Reality), mobile phones (e.g., smartphones), tablet-type information terminals, notebook PCs (Personal Computers), etc. For example, display devices have been developed to improve resolution, improve color reproducibility (NTSC ratio), reduce drive circuits, or reduce power consumption, etc.

[0004] For example, in order to improve the display quality of a display device, circuits that can reduce the non-uniformity of the characteristics of drive transistors in pixels are actively researched and developed. In particular, Patent Document 1 discloses an invention of a pixel circuit including a circuit that can correct the threshold voltage of a drive transistor.

[0005] In addition, as an example of a switching element included in a pixel circuit in a display device, a technique of using a transistor in which an oxide semiconductor is used for a semiconductor thin film can be cited.

[0006] As a semiconductor thin film that can be used for a transistor, silicon-based semiconductor materials are known. In addition, as materials other than silicon-based semiconductor materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, in addition to oxides of single-element metals such as indium oxide and zinc oxide, multi-element metal oxides are also known. Among multi-element metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0007] It has been reported that transistors using IGZO for the active layer have an extremely low off-state current (refer to Non-Patent Document 1); and LSIs (Large Scale Integration) and display devices that utilize this characteristic (refer to Non-Patent Documents 2 and 3). In addition, Patent Document 2 discloses an invention in which a transistor containing IGZO in the active layer is used for a pixel circuit of a display device. [Prior Art Documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-10000 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-156963 [Non-Patent Documents]

[0009] [Non-Patent Document 1] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1 - 021201-7 [Non-Patent Document 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216 - T217 [Non-Patent Document 3] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626 - 629 Summary of the Invention Technical Problem to be Solved by the Invention

[0010] Generally, a driving circuit is provided in a display device, and various circuits are provided in the driving circuit. For example, a shift register circuit, a latch circuit, a source follower circuit, etc. are provided in a driving circuit serving as a source driver.

[0011] When it is desired to increase the frame frequency of a display device, it is preferable to provide a transistor with a high driving frequency in the shift register circuit. By forming a gate insulating film between the gate and the semiconductor layer including the channel formation region thin, a transistor with a high driving frequency can be manufactured. On the other hand, a transistor for the source follower circuit is preferably a transistor with high voltage tolerance. By increasing the thickness of the gate insulating film, a transistor with high voltage tolerance can be manufactured.

[0012] From the viewpoints of the cost aspect, the number of processes, etc., when manufacturing a driving circuit, it is preferable to manufacture a shift register circuit and a source follower circuit simultaneously. However, as described above, since the most suitable thicknesses of the gate insulating films of the transistors for each of the shift register circuit and the source follower circuit are different from each other, in the case of manufacturing the shift register circuit and the source follower circuit simultaneously, it is necessary to consider the processes of forming transistors having different thicknesses of gate insulating films separately. Note that when forming transistors separately, in addition to the transistors in the driving circuit, the transistors included in the pixel circuit can also be targeted.

[0013] One of the objects of one aspect of the present invention is to provide a semiconductor device that operates stably. One of the objects of one aspect of the present invention is to provide a semiconductor device with a high driving frequency. One of the objects of one aspect of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objects of one aspect of the present invention is to provide a display device including the above semiconductor device. In addition, one of the objects of one aspect of the present invention is to provide an electronic device including the above display device. In addition, one of the objects of one aspect of the present invention is to provide a novel semiconductor device, a novel display device, or a novel electronic device.

[0014] Note that the object of one aspect of the present invention is not limited to the above objects. The above-listed objects do not prevent the existence of other objects. In addition, other objects are objects that are not mentioned above and will be described in the following description. Those skilled in the art can derive and appropriately extract objects not mentioned above from the description of the specification, drawings, etc. In addition, one aspect of the present invention achieves at least one of the above-listed objects and other objects. Therefore, one aspect of the present invention does not need to achieve all of the above objects and other objects. Means for Solving Technical Problems

[0015] One aspect of the present invention is a semiconductor device in view of the above object, the semiconductor device including a transistor in which a gate electrode and a channel formation region are provided along a height direction. In addition, since the channel formation region is along the height direction, the source electrode and the drain electrode are located at different heights.

[0016] In addition, in each of a plurality of such transistors, the thickness of the gate insulating film can be made different. For example, in each of a plurality of such transistors, a first insulating film and a second insulating film that will become part of the gate insulating film are stacked. In addition, an etching process is performed on the transistor in which the gate insulating film becomes a thin film to remove the second insulating film in the region that will become the gate insulating film. On the other hand, in the region that will become the gate insulating film of the transistor with a thick gate insulating film, the second insulating film remains through this etching process. Thereby, transistors having different thicknesses of gate insulating films can be manufactured separately.

[0017] Hereinafter, a typical structural example of a processing device according to one embodiment of the present invention will be described. (1) One embodiment of the present invention is a semiconductor device including: a shift register; and a source follower circuit. The shift register includes a first transistor, and the source follower circuit includes a second transistor. The first transistor and the second transistor include a first insulator. The first transistor includes a first gate insulating film, and the second transistor includes a second gate insulating film. The first transistor includes a first channel formation region along a side surface of a first opening formed in the first insulator, and the second transistor includes a second channel formation region along a side surface of a second opening formed in the first insulator. The first gate insulating film is located above the first channel formation region when viewed in plan, and the second gate insulating film is located above the second channel formation region when viewed in plan. The thickness of the second gate insulating film is thicker than the thickness of the first gate insulating film. (2) In the above (1), one embodiment of the present invention may also have a structure in which the first gate insulating film includes a second insulator, and the second gate insulating film includes a second insulator and a third insulator. The third insulator is preferably located on the second insulator. (3) In the above (2), one embodiment of the present invention may also further include a latch circuit. In particular, the latch circuit preferably includes a third transistor, and the third transistor preferably includes a third gate insulating film. The third transistor preferably has a third channel formation region along a side surface of a third opening formed in the first insulator. The third gate insulating film is preferably located above the third channel formation region when viewed in plan. The third gate insulating film preferably includes a second insulator. (4) In the above (3), one embodiment of the present invention may also further include a level converter circuit. In particular, the level converter circuit preferably includes a fourth transistor, and the fourth transistor preferably includes a fourth gate insulating film. The fourth transistor preferably has a fourth channel formation region along a side surface of a fourth opening formed in the first insulator. The fourth gate insulating film is preferably located above the fourth channel formation region when viewed in plan. The fourth gate insulating film preferably includes a second insulator and a third insulator. (5) In the above (4), one embodiment of the present invention may also have a structure in which the first to fourth channel formation regions each contain one or more selected from indium, zinc, and element M.

[0023] Element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (6) In (5) above, one aspect of the present invention may also have a structure in which the taper angles of the respective side surfaces of the first opening to the fourth opening are 70° or more and 110° or less. (7) One aspect of the present invention is a display device including: the semiconductor device in (6) above; and a pixel circuit. The pixel circuit includes a driving transistor, and the driving transistor includes a fifth gate insulating film. The driving transistor has a fifth channel formation region above the first insulator. The fifth gate insulating film is located above the fifth channel formation region when viewed in plan. The fifth gate insulating film includes a second insulator and a third insulator. (8) In (7) above, one aspect of the present invention may also have a structure in which the fifth channel formation region contains one or more selected from indium, zinc, and element M. (9) In (8) above, one aspect of the present invention may also have a structure in which the pixel circuit includes a light-emitting device containing an organic EL material. (10) One aspect of the present invention is an electronic device including the display device in (9) above and a housing. (11) One aspect of the present invention is a semiconductor device including: a first transistor; a second transistor; a third transistor; and a fourth transistor.

[0030] Each of the first transistor to the fourth transistor includes a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with side surfaces of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first transistor and the second transistor are both thicker than the gate insulating films of the third transistor and the fourth transistor.

[0031] One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor. One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor. (12) In (11) above, one aspect of the present invention may also have a structure in which the gate insulating films of the first transistor and the second transistor both include a second insulator, and the gate insulating films of the third transistor and the fourth transistor both include a second insulator and a third insulator. In particular, the third insulator is preferably located on the second insulator. (13) In the above (12), one aspect of the present invention may further include a first circuit. In particular, the first circuit preferably includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal is preferably electrically connected to the gate electrode of the first transistor, the second terminal is preferably electrically connected to the gate electrode of the second transistor, the third terminal is preferably electrically connected to the gate electrode of the third transistor, and the fourth terminal is preferably electrically connected to the gate electrode of the fourth transistor. The first circuit preferably has a function of outputting one of a high-level potential and a low-level potential to each of the first terminal and the third terminal, and a function of outputting the other of a high-level potential and a low-level potential to each of the second terminal and the fourth terminal. (14) One aspect of the present invention is a semiconductor device including: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first capacitor; and a second capacitor.

[0035] Each of the first to sixth transistors includes a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of a source and a drain, a semiconductor in contact with the side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first, second, and fifth transistors are thicker than the gate insulating films of the third, fourth, and sixth transistors.

[0036] One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor. The gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor and the other of a pair of terminals of the first capacitor. One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor. The gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor and the other of a pair of terminals of the second capacitor. The other of the first conductor and the second conductor of the fifth transistor is electrically connected to the other of the first conductor and the second conductor of the sixth transistor. The gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor. (15) In the above (14), one embodiment of the present invention may also have a structure in which the gate insulating films of the first transistor, the second transistor, and the fifth transistor all include a second insulator, and the gate insulating films of the third transistor, the fourth transistor, and the sixth transistor all include a second insulator and a third insulator. In particular, the third insulator is preferably located on the second insulator. (16) In the above (15), one embodiment of the present invention may also further include a first circuit. In particular, the first circuit preferably includes a first terminal and a second terminal. The first terminal is preferably electrically connected to the other of the first conductor and the second conductor of the fifth transistor and the other of the first conductor and the second conductor of the sixth transistor. The second terminal is preferably electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. The first circuit preferably has a function of outputting one of a high-level potential and a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal. (17) One embodiment of the present invention is a semiconductor device, including: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a first capacitor; and a second capacitor.

[0040] The first transistor to the eighth transistor all include a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with the side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first transistor, the second transistor, the fifth transistor, and the seventh transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor.

[0041] One of the first and second conductors of the first transistor is electrically connected to one of the first and second conductors of the second transistor and one of the pair of terminals of the first capacitor, and the gate electrode of the first transistor is electrically connected to one of the first and second conductors of the fifth transistor, the other of the pair of terminals of the first capacitor, and one of the first and second conductors of the seventh transistor. One of the first and second conductors of the third transistor is electrically connected to one of the first and second conductors of the fourth transistor and one of the pair of terminals of the second capacitor, and the gate electrode of the third transistor is electrically connected to one of the first and second conductors of the sixth transistor, the other of the pair of terminals of the second capacitor, and one of the first and second conductors of the eighth transistor. The other of the first and second conductors of the fifth transistor is electrically connected to the gate electrode of the fifth transistor, the other of the first and second conductors of the sixth transistor, and the gate electrode of the sixth transistor. The gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor. (18) In the above (17), one aspect of the present invention may also have a structure in which the gate insulating films of the first, second, fifth, and seventh transistors all include a second insulator, and the gate insulating films of the third, fourth, sixth, and eighth transistors all include a second insulator and a third insulator. In particular, the third insulator is preferably located on the second insulator. (19) In the above (18), one aspect of the present invention may also further include a first circuit. In particular, the first circuit preferably includes a first terminal and a second terminal. The first terminal is preferably electrically connected to the other of the first and second conductors of the fifth transistor and the other of the first and second conductors of the sixth transistor, and the second terminal is preferably electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. The first circuit preferably has a function of outputting one of a high-level potential and a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal. (20) One aspect of the present invention is a semiconductor device including: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a ninth transistor; a first capacitor; and a second capacitor.

[0045] The first transistor to the sixth transistor and the ninth transistor each include a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first transistor, the second transistor, the fifth transistor, and the ninth transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, and the sixth transistor.

[0046] One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor. The gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitor, and the gate electrode of the ninth transistor. One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor. The gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor and the other of the pair of terminals of the second capacitor. The other of the first conductor and the second conductor of the fifth transistor is electrically connected to the other of the first conductor and the second conductor of the sixth transistor and one of the first conductor and the second conductor of the ninth transistor. The gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor. (21) In the above (20), one aspect of the present invention may also have a structure in which the gate insulating films of the first transistor, the second transistor, the fifth transistor, and the ninth transistor each include a second insulator, and the gate insulating films of the third transistor, the fourth transistor, and the sixth transistor each include a second insulator and a third insulator. In particular, the third insulator is preferably located on the second insulator. (22) In the above (21), one aspect of the present invention may also further include a first circuit. In particular, the first circuit preferably includes a first terminal and a second terminal. The first terminal is preferably electrically connected to the other of the first conductor and the second conductor of the fifth transistor and the other of the first conductor and the second conductor of the sixth transistor. The second terminal is preferably electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. The first circuit preferably has a function of outputting one of a high-level potential and a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal. (23) One aspect of the present invention is a semiconductor device including: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a first capacitor; and a second capacitor, and having a structure different from the above (7).

[0050] The first to eighth transistors each include a first conductor located below a first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first and second conductors, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first, second, fifth, and seventh transistors are thicker than the gate insulating films of the third, fourth, sixth, and eighth transistors.

[0051] One of the first and second conductors of the first transistor is electrically connected to one of the first and second conductors of the second transistor and one of a pair of terminals of the first capacitor. The gate electrode of the first transistor is electrically connected to one of the first and second conductors of the fifth transistor, the other of the pair of terminals of the first capacitor, and one of the first and second conductors of the seventh transistor. One of the first and second conductors of the third transistor is electrically connected to one of the first and second conductors of the fourth transistor and one of a pair of terminals of the second capacitor. The gate electrode of the third transistor is electrically connected to one of the first and second conductors of the sixth transistor, the other of the pair of terminals of the second capacitor, and one of the first and second conductors of the eighth transistor. The gate electrode of the fifth transistor is electrically connected to the gate electrode of the sixth transistor. The gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor. (24) In the above (23), one aspect of the present invention may also have a structure in which the gate insulating films of the first, second, fifth, and seventh transistors each include a second insulator, and the gate insulating films of the third, fourth, sixth, and eighth transistors each include a second insulator and a third insulator. In particular, the third insulator is preferably located on the second insulator. (25) In the above (24), one embodiment of the present invention may further include a first circuit. In particular, the first circuit preferably includes a first terminal and a second terminal. The first terminal is preferably electrically connected to the gate electrodes of the fifth transistor and the sixth transistor, and the second terminal is preferably electrically connected to the gate electrodes of the second transistor and the fourth transistor. The first circuit preferably has a function of outputting either a high-level potential or a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal. (26) In any one of the above (11) to (25), one embodiment of the present invention may have a structure in which the taper angle of each side of each opening is 70° or more and 110° or less. (27) In the above (26), one embodiment of the present invention may have a structure in which the channel formation region included in each semiconductor contains one or more selected from indium, zinc, and element M.

[0056] Element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (28) One embodiment of the present invention is a display device including a driving circuit having the semiconductor device in the above (27) and a display device. (29) In the above (29), one embodiment of the present invention may have a structure in which the display unit includes a pixel circuit having any one of a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode. (30) One embodiment of the present invention is an electronic device including the display device in the above (29) and a housing. Advantages of the Invention

[0060] In the above embodiments, transistors having different gate insulating films can be provided in the same circuit or the same device. Thus, transistors with a high driving frequency and transistors with high voltage tolerance can be provided in the same circuit or the same device.

[0061] According to one aspect of the present invention, a semiconductor device that operates stably can be provided. One of the objectives of one aspect of the present invention is to provide a semiconductor device with a high driving frequency. According to one aspect of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one aspect of the present invention, a display device including the above semiconductor device can be provided. In addition, according to one aspect of the present invention, an electronic device including the above display device can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0062] Note that the effects of one aspect of the present invention are not limited to the above effects. The above-listed effects do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned above and will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. In addition, one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may sometimes not have the above-listed effects depending on the circumstances. Brief Description of the Drawings

[0063] Figure 1 is a block diagram showing an example of a display device. Figure 2A is a plan view showing an example of a semiconductor device, Figures 2B to 2D is a cross-sectional view showing an example of a semiconductor device. Figure 3 is a block diagram showing an example of a semiconductor device. Figure 4 is a block diagram showing an example of a semiconductor device. Figure 5A and Figure 5B is a block diagram showing an example of a semiconductor device. Figure 6A and Figure 6B is a circuit diagram showing an example of the structure of a semiconductor device. Figure 7 is a layout diagram showing an example of the structure of a semiconductor device. Figure 8A and Figure 8B is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 9A and Figure 9B is a circuit diagram showing an example of the structure of a semiconductor device. Figure 10 is a circuit diagram showing an example of the structure of a semiconductor device. Figure 11A and Figure 11BIt is a circuit diagram showing a structural example of a semiconductor device. Figure 12A and Figure 12B It is a circuit diagram showing a structural example of a semiconductor device. Figure 13 It is a circuit diagram showing a structural example of a semiconductor device. Figure 14A and Figure 14B It is a circuit diagram showing a structural example of a semiconductor device. Figure 15A and Figure 15B It is a circuit diagram showing a structural example of a semiconductor device. Figure 16 It is a circuit diagram showing a structural example of a semiconductor device. Figure 17A and Figure 17B It is a circuit diagram showing a structural example of a semiconductor device. Figure 18A and Figure 18B It is a circuit diagram showing a structural example of a semiconductor device. Figure 19A and Figure 19B It is a circuit diagram showing a structural example of a semiconductor device. Figure 20A and Figure 20B It is a circuit diagram showing a structural example of a semiconductor device. Figure 21A and Figure 21B It is a circuit diagram showing a structural example of a semiconductor device. Figure 22A and Figure 22B It is a circuit diagram showing a structural example of a semiconductor device. Figure 23 It is a circuit diagram showing a structural example of a semiconductor device. Figure 24 It is a circuit diagram showing a structural example of a semiconductor device. Figures 25A to 25E It is a circuit diagram showing a structural example of a semiconductor device. Figures 26A to 26C It is a circuit diagram showing a structural example of a semiconductor device. Figure 27A It is a circuit diagram showing a structural example of a semiconductor device, Figure 27B and it is a timing diagram showing an operating example of the semiconductor device. Figure 28 It is a circuit diagram showing a structural example of a semiconductor device. Figure 29A It is a circuit diagram showing a structural example of a semiconductor device, Figure 29B and it is a timing diagram showing an operating example of the semiconductor device. Figures 30A to 30D It is a circuit diagram showing an example of the structure of a pixel circuit. Figure 31A and Figure 31B It is a circuit diagram showing an example of the structure of a pixel circuit. Figure 32A and Figure 32B It is a circuit diagram showing an example of the structure of a pixel circuit. Figure 33 It is a circuit diagram showing an example of the structure of a pixel circuit. Figure 34 It is a circuit diagram showing an example of the structure of a pixel circuit. Figure 35A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 35B to 35D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 36A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 36B to 36D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 37A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 37B to 37D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 38A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 38B to 38D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 39A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 39B to 39D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 40A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 40B to 40D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 41A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 41B to 41D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 42A It is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 42B to 42D and it is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figure 43AIt is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 43B to 43D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 44A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 44B to 44D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 45A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 45B to 45D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 46A It is a plan view showing an example of a semiconductor device. Figures 46B to 46D It is a cross-sectional view showing an example of a semiconductor device. Figure 47A It is a plan view showing an example of a semiconductor device. Figures 47B to 47D It is a cross-sectional view showing an example of a semiconductor device. Figure 48A It is a plan view showing an example of a semiconductor device. Figure 48B and Figure 48C It is a cross-sectional view showing an example of a semiconductor device. Figure 49A It is a plan view showing an example of a semiconductor device. Figures 49B to 49D It is a cross-sectional view showing an example of a semiconductor device. Figure 50A It is a plan view showing an example of a semiconductor device. Figures 50B to 50D It is a cross-sectional view showing an example of a semiconductor device. Figure 51A It is a plan view showing an example of a semiconductor device. Figures 51B to 51D It is a cross-sectional view showing an example of a semiconductor device. Figure 52A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 52B to 52D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 53A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 53B to 53D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 54A It is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 54B to 54D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 55A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 55B to 55D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 56A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 56B to 56D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 57A is a plan view showing an example of a semiconductor device, Figures 57B to 57D is a cross-sectional view showing an example of a semiconductor device. Figure 58A is a plan view showing an example of a semiconductor device, Figures 58B to 58D is a cross-sectional view showing an example of a semiconductor device. Figure 59A is a plan view showing an example of a semiconductor device, Figures 59B to 59D is a cross-sectional view showing an example of a semiconductor device. Figure 60A is a plan view showing an example of a semiconductor device, Figures 60B to 60D is a cross-sectional view showing an example of a semiconductor device. Figure 61A is a plan view showing an example of a semiconductor device, Figures 61B to 61D is a cross-sectional view showing an example of a semiconductor device. Figure 62A is a plan view showing an example of a semiconductor device, Figures 62B to 62D is a cross-sectional view showing an example of a semiconductor device. Figure 63A is a plan view showing an example of a semiconductor device, Figures 63B to 63D is a cross-sectional view showing an example of a semiconductor device. Figure 64A is a plan view showing an example of a semiconductor device, Figures 64B to 64D is a cross-sectional view showing an example of a semiconductor device. Figure 65A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 65B to 65D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 66A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 66B to 66D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 67A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 67B to 67D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 68A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 68B to 68D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 69A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 69B to 69D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 70A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 70B to 70D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 71A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 71B to 71D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 72A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 72B to 72D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 73A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 73B to 73D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 74A is a plan view showing an example of a semiconductor device, Figures 74B to 74D is a cross-sectional view showing an example of a semiconductor device. Figure 75A and Figure 75B is a perspective view showing a structural example of a display device. Figure 76 is a block diagram showing a structural example of a display device. Figure 77 is a cross-sectional view showing a structural example of a display device. Figures 78A to 78C is a cross-sectional view showing a structural example of a display device. Figure 79 is a cross-sectional view showing a structural example of a display device. Figure 80 is a cross-sectional view showing a structural example of a display device. Figure 81It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 82 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 83 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 84 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 85 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 86 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 87 It is a cross-sectional schematic diagram showing an example of the structure of a display device. Figure 88A And Figure 88B It is a diagram showing an example of the structure of a display module. Figures 89A to 89I It is a perspective view showing an example of an electronic device. Figure 90A It is a perspective schematic diagram illustrating an example of the structure of a storage device, Figure 90B It is a block diagram illustrating an example of the structure of a semiconductor device. Figure 91 It is a block diagram illustrating an example of the structure of a storage device. Figure 92A And Figure 92B It is a diagram showing an example of an electronic component. Figure 93A And Figure 93B It is a diagram showing an example of an electronic device, Figures 93C to 93E It is a diagram showing an example of a mainframe computer. Figure 94 It is a diagram showing an example of a space device. Figure 95 It is a diagram showing an example of a storage system applicable to a data center. Modes for Implementing the Invention

[0064] In the present specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including semiconductor elements (e.g., transistors, diodes, photodiodes), and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. As an example of a semiconductor device, an integrated circuit can be cited. In addition, as an example of a semiconductor device, a chip having an integrated circuit can also be cited. In addition, as an example of a semiconductor device, an electronic component in which a chip is housed in a package can also be cited. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device may sometimes be a semiconductor device itself, or may sometimes include a semiconductor device.

[0065] In addition, in the present specification and the like, when it is described that "X is connected to Y", it means that the following cases are disclosed in the present specification and the like: the case where X is electrically connected to Y; the case where X is functionally connected to Y; and the case where X is directly connected to Y. Therefore, it is not limited to a specified connection relationship such as the connection relationship shown in the drawings or the text, and a connection relationship other than the connection relationship shown in the drawings or the text is also considered to be described in the drawings or the text. X and Y are each an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film or layer).

[0066] As an example of the case where X is electrically connected to Y, one or more elements capable of electrically connecting X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display device, a light-emitting device, a load, etc.) can be connected between X and Y. In addition, the switch has a function of controlling on or off. In other words, whether to allow current to flow is controlled by making the switch in a conductive state (on state) or a non-conductive state (off state).

[0067] In addition, when both a component and a power supply line (e.g., VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring for applying a desired potential) are disposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, when only a power supply line is disposed between X and Y, there is no other component between X and Y, and thus it can be said that X and Y are directly connected. Therefore, when only a power supply line is disposed between X and Y, it can also be said that "X and Y are electrically connected". However, when both a component and a power supply line are disposed between X and Y, it can be said that X is electrically connected to the power supply line (through the component) and Y is electrically connected to the power supply line, but it cannot be said that X and Y are electrically connected. In addition, when the gate and source of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, when the gate and drain of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. That is, regarding a transistor, when the drain and source of the transistor are interposed between X and Y, it can be said that X and Y are electrically connected. In addition, when a capacitor is disposed between X and Y, sometimes it can be said that X and Y are electrically connected, and sometimes it cannot be said that X and Y are electrically connected. For example, in the structure of a digital circuit or a logic circuit, when a capacitor is disposed between X and Y, sometimes it cannot be said that X and Y are electrically connected. On the other hand, for example, in the structure of an analog circuit, when a capacitor is disposed between X and Y, sometimes it can be said that X and Y are electrically connected.

[0068] As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (e.g., a logic circuit (e.g., an inverter, a NAND circuit, a NOR circuit), a signal conversion circuit (e.g., a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, a gamma correction circuit), a potential level conversion circuit (e.g., a power supply circuit such as a boost circuit or a buck circuit and a level shift circuit for changing the potential level of a signal), a voltage source, a current source, a switching circuit, an amplification circuit (e.g., a circuit capable of increasing the signal amplitude or current amount, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit), a signal generation circuit, a storage circuit, a control circuit, etc.) can be connected between X and Y. Note that, for example, even when other circuits are interposed between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

[0069] In addition, for example, it can be expressed as "X, the source of the transistor (sometimes alternatively referred to as one of the first and second terminals) and the drain of the transistor (sometimes alternatively referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Or, it can be expressed as "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". In addition, it can be expressed as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are arranged to be connected to each other in sequence". By using the same representation method as these examples to specify the connection order in the circuit structure, the source and drain of the transistor can be distinguished and the technical scope can be determined. Note that this representation method is an example and is not limited to the above representation method. Here, X and Y are objects (for example, devices, components, circuits, wirings, electrodes, terminals, conductive films or layers).

[0070] In addition, even when independent components on a circuit diagram are electrically connected to each other, sometimes one component has the functions of multiple components. For example, when a part of a wiring is used as an electrode, one conductive film has the two functions of a wiring and an electrode. Therefore, the scope of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0071] In this specification and the like, a "resistor" can be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistor" includes a wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, or a coil. Therefore, a "resistor" can sometimes be alternatively referred to as "resistance", "load", or "region having a resistance value". In contrast, "resistance", "load", or "region having a resistance value" can sometimes be alternatively referred to as "resistor". As the resistance value, for example, it is preferably 1 mΩ or more and 10Ω or less, more preferably 5 mΩ or more and 5Ω or less, and further preferably 10 mΩ or more and 1Ω or less. In addition, for example, it can also be 1Ω or more and 1×10 9 Ω or less.

[0072] In this specification and the like, a "capacitor" can be, for example, a circuit element having an electrostatic capacitance value higher than 0 F, a region of a wiring having an electrostatic capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, a "capacitor", a "parasitic capacitance", or a "gate capacitance" can sometimes be interchangeably referred to as a "capacitance". In contrast, a "capacitance" can sometimes be interchangeably referred to as a "capacitor", a "parasitic capacitance", or a "gate capacitance". Furthermore, a "capacitor" (including a "capacitor" having three or more terminals) has a structure including an insulator and a pair of conductors sandwiching the insulator. Thus, the "pair of conductors" of a "capacitor" can be interchangeably referred to as a "pair of electrodes", a "pair of conductive regions", a "pair of regions", or a "pair of terminals". In addition, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. The electrostatic capacitance value can be, for example, 0.05 fF or more and 10 pF or less. In addition, for example, it can also be 1 pF or more and 10 μF or less.

[0073] In this specification and the like, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal for controlling the conduction state of the transistor. The two terminals used as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (e.g., n-channel type, p-channel type) and the magnitudes of the potentials applied to the three terminals of the transistor, one of the two input / output terminals is used as the source and the other is used as the drain. Therefore, in this specification and the like, the source and the drain can be interchanged with each other. In this specification and the like, when explaining the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, sometimes in addition to the above three terminals, it also includes a back gate. In this case, in this specification and the like, sometimes one of the gate and the back gate of the transistor is referred to as a first gate, and the other of the gate and the back gate of the transistor is referred to as a second gate. And in the same transistor, sometimes the "gate" and the "back gate" can be interchanged with each other. Furthermore, when a transistor includes three or more gates, in this specification and the like, sometimes each gate is referred to as a first gate, a second gate, a third gate, etc.

[0074] For example, in this specification and the like, as an example of a transistor, a multi-gate structure transistor having two or more gate electrodes can be adopted. When the multi-gate structure is adopted, since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is formed. Therefore, by adopting the multi-gate structure, the off-state current can be reduced, and the breakdown voltage of the transistor (reliability improvement) can be increased. Alternatively, by using the multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not very large, so that a voltage-current characteristic with a flat slope angle can be obtained. When using the voltage-current characteristic with a flat slope angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0075] In addition, a circuit diagram showing a case of one circuit element sometimes includes a case where the circuit element has a plurality of circuit elements. For example, a circuit diagram showing a case of one resistor includes a case where two or more resistors are connected in series electrically. In addition, for example, a circuit diagram showing a case of one capacitor includes a case where two or more capacitors are connected in parallel electrically. In addition, for example, a circuit diagram showing a case of one transistor includes a case where two or more transistors are connected in series electrically and the gates of the respective transistors are electrically connected to each other. Similarly, for example, a circuit diagram showing a case of one switch includes a case where the switch has two or more transistors, two or more transistors are connected in series electrically or in parallel electrically and the gates of the respective transistors are electrically connected to each other.

[0076] In addition, in this specification and the like, a node can also be renamed as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region according to the circuit structure and the device structure. In addition, a terminal, a wiring, etc. can also be renamed as a node.

[0077] In addition, in this specification and the like, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is the ground potential (grounded potential), "voltage" can also be renamed as "potential". The ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential applied to a wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change according to the change of the reference potential.

[0078] In addition, in this specification and the like, "high-level potential" and "low-level potential" do not mean specific potentials. For example, in a case where two wirings are both described as "a wiring for supplying a high-level potential", the high-level potentials applied to the two wirings can also be different from each other. Similarly, in a case where two wirings are both described as "a wiring for supplying a low-level potential", the low-level potentials applied to the two wirings can also be different from each other.

[0079] In addition, "electric current" refers to the phenomenon of the movement of electric charges (electric conduction). For example, the description "electric conduction of a positively charged object occurs" can be replaced with the description "electric conduction of a negatively charged object occurs in the opposite direction". Therefore, in this specification and the like, without special instructions, "electric current" refers to the phenomenon of the movement of electric charges (electric conduction) when carriers move. Here, examples of carriers include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of the electric current" in wirings, etc. is the direction in which the positively charged carriers move, and is described by the positive electric current amount. In other words, the direction in which the negatively charged carriers move is opposite to the direction of the electric current, and is described by the negative electric current amount. Therefore, in this specification and the like, without special instructions, regarding the positive and negative of the electric current (or the direction of the electric current), the description "an electric current flows from element A to element B" can be replaced with the description "an electric current flows from element B to element A". In addition, the description "an electric current is input to element A" can be replaced with the description "an electric current is output from element A".

[0080] In addition, in this specification and the like, ordinal numbers such as "first", "second", "third", etc. are added to avoid confusion of the components. Therefore, this ordinal number does not limit the number of components. In addition, this ordinal number does not limit the order of the components. For example, in one of the embodiments of this specification and the like, the component with "first" attached may have "second" attached in other embodiments or claims. In addition, for example, in this specification and the like, the component referred to as "first" in one embodiment may be omitted in other embodiments or claims.

[0081] In this specification and the like, for convenience, phrases such as "above" and "below" indicating the arrangement are sometimes used to describe the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction of describing each structure. Therefore, without being limited to the phrases described in the specification and the like, the phrases can be appropriately changed according to the situation. For example, in the expression "the insulator located on the top surface of the conductor", by rotating the direction of the shown drawing by 180 degrees, it can also be referred to as "the insulator located below the conductor".

[0082] In addition, expressions such as "above" or "below" are not limited to the case where the positional relationship of the constituent elements is "directly above" or "directly below" and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessarily required that electrode B is formed in direct contact on insulating layer A, and it may also include cases where other constituent elements are included between insulating layer A and electrode B. Similarly, for example, in the expression "electrode B above insulating layer A", it is not necessarily required that electrode B is formed in direct contact on insulating layer A, and it may also include cases where other constituent elements are included between insulating layer A and electrode B. Similarly, for example, in the expression "electrode B below insulating layer A", it is not necessarily required that electrode B is formed in direct contact below insulating layer A, and it may also include cases where other constituent elements are included between insulating layer A and electrode B.

[0083] In addition, in this specification and the like, expressions such as "row" and "column" are sometimes used to describe the constituent elements configured in a matrix and their positional relationships. In addition, the positional relationships of the constituent elements are appropriately changed according to the directions for describing each structure. Therefore, it is not limited to the expressions described in the specification and the like, and the expressions can be appropriately changed according to the situation. For example, in the expression "row direction", by rotating the direction of the shown drawing by 90 degrees, it may sometimes be referred to as the "column direction".

[0084] In addition, in this specification and the like, depending on the situation, expressions such as "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be interchanged with "conductive film". In addition, sometimes "insulating film" can be changed to "insulating layer". Additionally, depending on the situation or circumstances, other expressions can be used instead of "film" and "layer" and the like. For example, sometimes "conductive layer" or "conductive film" can be changed to "conductor". In addition, for example, sometimes "insulating layer" or "insulating film" can be changed to "insulator".

[0085] Note that in this specification and the like, the expressions "electrode", "wiring", and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring", and vice versa. Furthermore, expressions such as "electrode" or "wiring" also include cases where multiple "electrodes" or "wirings" are formed integrally. In addition, for example, sometimes "terminal" is used as part of "wiring" or "electrode", and vice versa. Furthermore, the expression "terminal" also includes cases where one or more selected from "electrode", "wiring", and "terminal" are formed integrally. Therefore, for example, "electrode" can be part of "wiring" or "terminal", and for example, "terminal" can be part of "wiring" or "electrode". In addition, the expressions such as "electrode", "wiring", or "terminal" are sometimes replaced with expressions such as "region" according to the situation.

[0086] In this specification and the like, depending on the situation or condition, terms such as "wiring", "signal line", or "power supply line" may be interchanged with each other. For example, sometimes "wiring" may be changed to "signal line". In addition, for example, sometimes "wiring" may be changed to "power supply line" or the like. Conversely, sometimes "signal line" or "power supply line" or the like may be changed to "wiring". Sometimes "power supply line" or the like may be changed to "signal line". Conversely, sometimes "signal line" or the like may be changed to "power supply line". In addition, depending on the situation or condition, sometimes the "potential" applied to the wiring may be interchanged with "signal". Conversely, sometimes "signal" may be changed to "potential".

[0087] In addition, in this specification and the like, sometimes the operation method of the semiconductor device is described with reference to a timing chart. In addition, the timing chart used in this specification and the like shows an ideal operation example, and without special explanation, it is not limited to the period, the magnitude of the signal (e.g., potential or current), and the timing shown in the timing chart. In the timing chart of this specification and the like, the magnitude and timing of the signal (e.g., potential or current) input to each wiring (including nodes) in the timing chart can be changed according to the situation. For example, even if two periods with equal intervals are shown in the timing chart, the lengths of the two periods are sometimes not the same. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods are sometimes the same, or sometimes one of the two periods can be made short and the other long.

[0088] In this specification and the like, metal oxide refers to the oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which can also be abbreviated as OS), etc. For example, when a metal oxide is included in the channel formation region of a transistor, sometimes the metal oxide is referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor having at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be alternatively referred to as a transistor including a metal oxide or an oxide semiconductor.

[0089] In addition, in this specification and the like, sometimes a metal oxide containing nitrogen is also referred to as a metal oxide (metaloxide). In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride.

[0090] In addition, in this specification and the like, an impurity in a semiconductor refers to a substance other than the main component constituting the semiconductor layer. For example, an element with a concentration lower than 0.1 atomic% is an impurity. When an impurity is included, one or more of an increase in the density of defect states in the semiconductor, a decrease in the carrier mobility, and a decrease in crystallinity sometimes occur. When the semiconductor is an oxide semiconductor, examples of impurities that change the semiconductor characteristics include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main component. In particular, for example, there are hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0091] In this specification and the like, a switch refers to an element that has a function of controlling whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching current paths. Therefore, a switch sometimes includes two or more current-carrying terminals in addition to the control terminal. As an example of a switch, an electrical switch or a mechanical switch or the like can be used. In other words, as long as a switch can control current, it is not limited to a specific element.

[0092] Examples of electrical switches include transistors (such as bipolar transistors, MOS transistors, etc.), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits that combine these elements. When a transistor is used as a switch, the "conducting state" of the transistor, for example, refers to a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When only a transistor is used as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

[0093] As an example of a mechanical switch, a switch using MEMS (microelectromechanical systems) technology can be cited. This switch has an electrode that can move mechanically, and operates by moving this electrode to control conduction and non-conduction.

[0094] In addition, in this specification and the like, a device manufactured using a metal mask or an FMM (Fine Metal Mask, high-precision metal mask) is sometimes referred to as a device having an MM (Metal Mask) structure. In addition, in this specification and the like, a device not manufactured using a metal mask or an FMM is sometimes referred to as a device having an MML (MetalMask Less) structure.

[0095] Note that in this specification and the like, a structure in which a light-emitting layer is separately formed or separately coated in each of the light-emitting devices of each color (here, blue (B), green (G), and red (R)) is sometimes referred to as an SBS (Side By Side) structure. In addition, in this specification and the like, a light-emitting device that can emit white light is sometimes referred to as a white light-emitting device. A display device that can achieve full-color display can be realized by combining a white light-emitting device with a coloring layer (for example, a color filter).

[0096] In addition, light-emitting devices can be roughly classified into a single structure and a tandem structure. A device with a single structure preferably has the following structure: a single light-emitting unit is included between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. In the case of obtaining white light using two light-emitting layers, the light-emitting layers can be selected such that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer be in a complementary color relationship, a structure in which the entire light-emitting device emits white light can be obtained. In addition, in the case of obtaining white light using three or more light-emitting layers, a structure in which the light-emitting colors of the three or more light-emitting layers are combined to obtain white light in the entire light-emitting device can be used.

[0097] A device with a tandem structure preferably has the following structure: two or more light-emitting units are included between a pair of electrodes, and each light-emitting unit includes one or more light-emitting layers. In order to obtain white light, a structure in which light emitted from the light-emitting layers of the plurality of light-emitting units is combined to obtain white light can be used. Note that the structure for obtaining white light is the same as the structure in the single structure. In addition, in a device with a tandem structure, it is preferable to provide an intermediate layer such as a charge generation layer between the plurality of light-emitting units.

[0098] In addition, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) and the light-emitting device with an SBS structure, the power consumption of the light-emitting device with an SBS structure can be made lower than that of the white light-emitting device. A device that wants to reduce power consumption preferably uses a light-emitting device with an SBS structure. On the other hand, the manufacturing process of the white light-emitting device is simpler than that of the light-emitting device with an SBS structure, so the manufacturing cost can be reduced or the manufacturing yield can be increased, which is therefore preferable.

[0099] In this specification, "parallel" means a state in which the angle formed by two straight lines is more than -10° and less than 10°. Therefore, it also includes the state in which the angle is more than -5° and less than 5°. "Substantially parallel" means a state in which the angle formed by two straight lines is more than -20° and less than 20°. In addition, "perpendicular" means a state in which the angle formed by two straight lines is more than 80° and less than 100°. Therefore, it also includes the state in which the angle is more than 85° and less than 95°. "Substantially perpendicular" means a state in which the angle formed by two straight lines is more than 70° and less than 110°.

[0100] In addition, in this specification and the like, the structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to form one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0101] In addition, the content (or a part thereof) described in a certain embodiment can be applied / combined / replaced with at least one of the content (or a part thereof) described in other content (or a part thereof) described in the same embodiment and the content (or a part thereof) described in another or multiple other embodiments.

[0102] Note that the content described in the embodiments refers to the content described by using various drawings in each embodiment or the content described by using the articles recorded in the specification.

[0103] In addition, by combining the drawing (or a part thereof) shown in a certain embodiment with at least one of the other parts of the drawing, the other drawings (or a part thereof) shown in the same embodiment, and the drawings (or a part thereof) shown in another or multiple other embodiments, more drawings can be formed.

[0104] The embodiments described in this specification are described with reference to the drawings. However, those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in multiple different forms, and the ways and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts having the same functions, and repeated descriptions are omitted. In a perspective view or the like, for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0105] In addition, in this specification and the like, when the same symbol is used for a plurality of elements and it is necessary to distinguish them, sometimes a symbol for identification such as "_1", "[n]", "[m, n]" is attached to the symbol. Further, in the drawings and the like, in the case where a symbol for identification such as "_1", "[n]", "[m, n]" is attached to the symbol, if it is not necessary to distinguish them in this specification and the like, sometimes the symbol for identification is not attached.

[0106] In the drawings of this specification, for the sake of clear illustration, sometimes the size, the thickness of a layer, or a region is exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings. Further, in the drawings, ideal examples are schematically shown, and are not limited to the shapes or values shown in the drawings. For example, it may include unevenness of signals, voltages, or currents caused by noise or timing deviation or the like.

[0107] (Embodiment 1) In this embodiment, a display device according to one aspect of the present invention will be described.

[0108] <Structural example of the display device> Figure 1 It is a schematic diagram showing an example of a display device DSP according to one aspect of the present invention. As an example, the display device DSP has a structure in which a pixel array PXA, a driving circuit GD, a driving circuit SD, a protection circuit PRT, and a driving circuit TSD are provided on a substrate BS.

[0109] As an example, the substrate BS is used as a support for setting the pixel array PXA, the driving circuit GD, the driving circuit SD, the protection circuit PRT, and the driving circuit TSD. In addition, part or all of the above-listed circuits may be directly formed on the substrate BS, or may be mounted on the substrate BS by a method such as COG (Chip On Glass). Further, part or all of the above-listed circuits may also be mounted on an FPC (Flexible Printed Circuits) electrically connected to the substrate BS by a method such as COF (Chip On Film).

[0110] As the substrate BS, for example, a semiconductor substrate (e.g., a semiconductor substrate made of silicon or germanium) can be used. In addition, as the substrate BS, in addition to the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a laminated film, a paper or a base film including a fibrous material, etc. can be cited. As the glass substrate, for example, barium borosilicate glass, aluminosilicate glass, or soda-lime glass can be cited. As the flexible substrate, the laminated film, or the base film, etc., for example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. In addition, as another example, synthetic resins such as acrylic resins can be cited. In addition, as another example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be cited. In addition, as another example, polyamide, polyimide, aramid, epoxy resin, an inorganic vapor deposition film, or paper can be cited. In the case where the manufacturing process of the display device DSP includes heat treatment, a material with high heat resistance is preferably selected as the substrate BS.

[0111] As an example, the pixel array PXA includes a plurality of pixel circuits PX. The plurality of pixel circuits PX are arranged in a matrix in the pixel array PXA. For example, in the pixel array PXA, the plurality of pixel circuits PX are arranged in any one of a matrix arrangement, a stripe arrangement, an S stripe arrangement, a Delta arrangement, a Bayer arrangement, a Pentile arrangement, etc. In Figure 1 this case, the pixel circuit PX located in the i-th row and the j-th column (i is an integer of 1 or more, and j is an integer of 1 or more) among the plurality of pixel circuits PX is represented as the pixel circuit PX[i, j]. Note that the pixel array PXA may also have a structure having only one pixel circuit PX and not having a plurality of pixel circuits PX.

[0112] The plurality of pixel circuits PX, for example, have a function of acquiring an image signal transmitted from a driving circuit SD described later and emitting light corresponding to the intensity of the image signal. One pixel circuit PX may also include two or more sub-pixel circuits. For example, the number of sub-pixel circuits included in one pixel circuit PX and the emission color may be set such that the combination of light emitted from each of the plurality of sub-pixel circuits presents white. For example, by setting the emission colors of the plurality of sub-pixel circuits included in the pixel circuit PX to red (R), green (G), and blue (B), the pixel circuit PX as a whole can become a circuit capable of emitting white light.

[0113] In addition, the screen resolution of the display device DSP is determined according to the number of pixel circuits PX included in the pixel array PXA. For example, when the screen resolution of the display device DSP is 8K4K, the number of pixel circuits PX included in the pixel array PXA is 7,680 × 4,320. Furthermore, when the pixel circuit PX includes, for example, three sub-pixel circuits of red (R), green (G), and blue (B), the total number of the sub-pixel circuits included in the pixel array PXA is 7,680 × 4,320 × 3. In addition, the screen resolution of the display device DSP can be SD (the number of pixel circuits PX is 720 × 480), can be HD (the number of pixel circuits PX is 1,280 × 720), can be FHD (the number of pixel circuits PX is 1,920 × 1,080), or can be 4K2K (the number of pixel circuits PX is 3,840 × 2,160). In addition, the screen resolution of the display device DSP is not limited to the above resolutions and can also be arbitrarily determined in the design stage of the display device DSP.

[0114] In addition, the diagonal size of the display area (for example, the pixel array PXA) of the display device DSP can be determined according to the electronic device equipped with the display device DSP. For example, in the use of a large display such as a television device, the diagonal size of this display area can be 20 inches or more, 30 inches or more, 60 inches or more, or 100 inches or more. In addition, for example, in the use of a medium or small display such as a tablet information terminal or a portable information terminal, the diagonal size of this display area can be 3 inches or more and 13 inches or less. Additionally, for example, in the use of a small display such as an XR device or a wearable information terminal, as an example, it can be 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less.

[0115] In addition, the clarity (sometimes referred to as pixel density) of the display area of the display device DSP is determined according to the above screen resolution and diagonal size. For example, when the display device DSP is used for a large display, the clarity of the display area of the display device DSP is preferably 50 ppi or more, more preferably 100 ppi or more, and further preferably 150 ppi or more. In addition, when the display device DSP is used for a medium or small display, the clarity of the display area of the display device DSP is preferably 200 ppi or more, more preferably 400 ppi or more, and further preferably 800 ppi or more. In addition, when the display device DSP is used for a small display, the clarity of the display area of the display device DSP is preferably 1,000 ppi or more, more preferably 2,000 ppi or more, and further preferably 4,000 ppi or more.

[0116] In addition, there is no particular limitation on the screen ratio (aspect ratio) of the display area (e.g., pixel array PXA) of the display device DSP. For example, the display area can correspond to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0117] As an example, the driving circuit GD is used as the gate driver circuit of the pixel circuit PX included in the pixel array PXA for selecting the pixels to which the image signal is to be written.

[0118] As an example, the driving circuit SD is used as the source driver circuit for sending the image signal to the pixel circuit PX included in the pixel array PXA.

[0119] As an example, the pixel circuit PX[i, j] is electrically connected to the driving circuit GD through the wiring GLS[i]. In addition, as an example, the pixel circuit PX[i, j] is electrically connected to the driving circuit SD through the wiring SLS[j].

[0120] As an example, the wiring GLS[i] is used as the wiring for sending the selection signal for driving the pixel circuit PX[i, j] from the driving circuit GD to the pixel circuit PX[i, j].

[0121] As an example, the wiring SLS[j] is used as the wiring for sending the image signal for displaying the image on the pixel circuit PX[i, j] from the driving circuit SD to the pixel circuit PX[i, j].

[0122] Note that the wiring GLS[i] can be a single wiring or a wiring group composed of multiple wirings. Similarly, the wiring SLS[j] can be a single wiring or a wiring group composed of multiple wirings.

[0123] As an example, the driving circuit TSD is used as the circuit for driving the touch sensor provided in the region overlapping the pixel array PXA when viewed from the plane. Note that when there is no touch sensor provided in this region, the driving circuit TSD can also be not provided in the display device DSP.

[0124] As an example, the protection circuit PRT is electrically connected to the wiring GLS[i] and other wirings. The protection circuit PRT has, for example, the following function: when a potential outside the specified range is supplied to the wiring GLS[i], it makes the wiring GLS[i] in a conducting state with the other wiring, and keeps the potential of the wiring GLS[i] within the specified range.

[0125] In addition, similarly, as an example, the protection circuit PRT can also be electrically connected to the wiring SLS[j] and other wirings. At this time, the protection circuit PRT preferably has the following functions, for example: when a potential outside the specified range is supplied to the wiring SLS[j], it makes the wiring SLS[j] in a conducting state with the other wiring, and makes the potential of the wiring SLS[j] within the specified range.

[0126] As an example, the pixel array PXA, the driving circuit GD, the driving circuit SD, the protection circuit PRT, and the driving circuit TSD included in the above display device DSP all include transistors. The various characteristics of the transistors depend on the thickness and materials of the semiconductor having the channel formation region, the gate insulator, the source electrode or the drain electrode, the gate electrode, etc. Therefore, it is preferable to set transistors having the most suitable structure according to the arrangement position of the transistors. For example, since a level shifter or the like included in the driving circuit SD or the driving circuit GD processes a high voltage, it is preferable to use a transistor having high tolerance to a high voltage (high gate potential, high source potential, or high drain potential). In addition, when the frame frequency of the display device DSP is high, a shift register or the like included in the driving circuit SD or the driving circuit GD preferably uses a transistor having a high driving frequency. In addition, when it is desired to hold data corresponding to an image signal in the pixel circuit PX for a long time, as the writing transistor included in the pixel circuit PX, it is preferable to use a transistor having a low off-state current characteristic.

[0127] On the other hand, when transistors having different structures are formed on the same substrate (for example, on the substrate BS in the display device of Figure 1 ), the more types of transistors there are, the more manufacturing processes there are, which sometimes leads to an increase in cost, a decrease in yield, etc.

[0128] One aspect of the present invention is a display device in view of the above, including a transistor having high tolerance to a high voltage and a transistor having a high driving frequency. In addition, one aspect of the present invention is a display device in which a transistor having high tolerance to a high voltage and a transistor having a high driving frequency are formed without increasing the number of manufacturing processes. In addition, one aspect of the present invention may also be a display device including a transistor having a low off-state current characteristic. Note that the transistor having high tolerance to a high voltage and the transistor having a high driving frequency may also have a low off-state current characteristic.

[0129] <Examples of transistor structures> Figures 2A to 2D An example of a semiconductor device (for example, a pixel circuit or a driving circuit) including a transistor MTCK having high tolerance to a high voltage and a transistor MTHN having a high driving frequency is shown. Specifically, Figure 2AA plan view showing transistor MTCK and transistor MTHN is presented. Additionally, Figure 2B is a cross-sectional view of a portion along the Figure 2A indicated dash-dotted line A1 - A2, and is also a cross-sectional view of transistor MTCK and transistor MTHN. Additionally, Figure 2C is a cross-sectional view of a portion along the Figure 2A indicated dash-dotted line A3 - A4, and is also a cross-sectional view of transistor MTCK. Additionally, Figure 2D is a cross-sectional view of a portion along the Figure 2A indicated dash-dotted line A5 - A6, and is also a cross-sectional view of transistor MTHN.

[0130] In Figures 2A to 2D , the direction of dash-dotted line A1 - A2 is regarded as the X direction, and the direction of dash-dotted line A3 - A4 or dash-dotted line A5 - A6 is regarded as the Y direction. Additionally, the direction perpendicular to the X direction and the Y direction is the Z direction. The X direction and the Y direction can be perpendicular to each other. In subsequent figures, the definitions of the X direction, the Y direction, and the Z direction are sometimes the same as above and sometimes different. Additionally, in the description of plan views such as Figure 2A , sometimes the right side is called the X direction, the left side is called the -X direction, the upper side is called the Y direction, and the lower side is called the -Y direction. Additionally, in the description of cross-sectional views such as Figure 2B , sometimes the right side is called the X direction, the left side is called the -X direction, the upper side is called the Z direction, and the lower side is called the -Z direction. Additionally, in the description of cross-sectional views such as Figure 2C and Figure 2D , sometimes the right side is called the -Y direction, the left side is called the +Y direction, the upper side is called the Z direction, and the lower side is called the -Z direction.

[0131] Figures 2A to 2D The transistor MTCK and transistor MTHN of

[0132] include insulators IS1 to IS3, insulators GI1, GI2, conductors ME1 to ME3, and semiconductor SC1.

[0133] As an example, insulator IS1 is used as a base film for disposing the source, drain, drain, and channel formation regions of each of transistor MTCK and transistor MTHN above insulator IS1.

[0133] Conductor ME1 is a conductor (sometimes also called a terminal, wiring, etc.) used as one of the source and drain in each of transistor MTCK and transistor MTHN. Additionally, conductor ME2 is a conductor (sometimes also called a terminal, wiring, etc.) used as the other of the source and drain in each of transistor MTCK and transistor MTHN.

[0134] In Figures 2A to 2DAmong them, as an example, the conductor ME1 extends as a wiring in the Y direction. In addition, as an example, the conductor ME2 extends as a wiring in the X direction.

[0135] In addition, as an example, the insulator IS2 is used as an interlayer film that separates the source and drain in the transistors MTCK and MTHN.

[0136] In addition, an opening KK1 whose side is substantially perpendicular to the X-Y plane (the cone angle is 70° or more and 110° or less) is formed in the region of the insulator IS2 where the transistor MTCK is provided. Further, the semiconductor SC1 having the channel formation region of the transistor MTCK is arranged so as to be in contact with the conductor ME1 and the conductor ME2 through the opening KK1. Similarly, an opening KK2 whose side is substantially perpendicular to the X-Y plane is formed in the region of the insulator IS2 where the transistor MTHN is provided. In addition, the semiconductor SC1 having the channel formation region of the transistor MTHN is arranged so as to be in contact with the conductor ME1 and the conductor ME2 through the opening KK2.

[0137] In addition, in each of the transistors MTCK and MTHN, an insulator GI1 is provided on the semiconductor SC1. Specifically, when viewed from a plane, the insulator GI1 overlaps with the channel formation region of the semiconductor SC1 and is located above it. Furthermore, in the transistor MTCK, an insulator GI2 is provided on the insulator GI1. Therefore, the insulator GI1 and the insulator GI2 are used as gate insulating films in the transistor MTCK, and the insulator GI1 is used as a gate insulating film in the transistor MTHN.

[0138] In addition, in the transistor MTCK, the conductor ME3 is provided on the insulator GI2 so as to fill the opening KK1. In addition, in the transistor MTHN, the conductor ME3 is provided on the insulator GI1 so as to fill the opening KK2. The conductor ME3 is a conductor (sometimes also referred to as a terminal, wiring, etc.) that serves as a gate in each of the transistors MTCK and MTHN.

[0139] In addition, in Figures 2A to 2D Among them, as an example, the conductor ME3 extends as a wiring in the Y direction.

[0140] As described above, in Figures 2A to 2D In the transistors MTCK and MTHN shown, the conductor ME1 serving as one of the source and drain is located below the insulator IS2 serving as an interlayer film, and the conductor ME2 serving as the other of the source and drain is located above the insulator IS2. Therefore, each channel formation region of the transistors MTCK and MTHN is provided along the opening of the first insulator.

[0141] Thus, the transistor MTCK and the transistor MTHN have a structure in which the source electrode and the drain electrode are at different heights and the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction can be said to have a component in the height direction (vertical direction), so the transistor MTCK and the transistor MTHN can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, etc.

[0142] As Figures 2A to 2D shown, by arranging the channel formation region of the transistor along the side surface of the opening of the insulator used as the interlayer film, the formation area of the transistor can be reduced compared with the case where the channel formation region of the transistor is arranged along the X-Y plane. In the transistor MTCK and the transistor MTHN, the source electrode, the semiconductor layer, and the drain electrode can be arranged in an overlapping manner, so the occupied area can be greatly reduced compared with the so-called planar transistor in which the semiconductor is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistor MTCK and the transistor MTHN, the area of the circuit can be reduced. In addition, as a result, miniaturization of a semiconductor device including the circuit or a display device including the circuit can be achieved.

[0143] As an example, the channel length of the transistor MTCK is Figure 2B and Figure 2C shown as the channel length LCK, and as an example, the channel length of the transistor MTHN is Figure 2B and Figure 2D shown as the channel length LHN. The channel length LCK and the channel length LHN can be said to be the shortest distance between the portion in contact with the conductor ME1 and the portion in contact with the conductor ME2 in the semiconductor SC1 when viewed from the cross section. In addition, the channel length can refer to the length between the source and the drain of the channel formation region.

[0144] The channel length LCK of the transistor MTCK corresponds to the length in the height direction of the opening KK1 of the insulator IS2 when viewed in cross-section. Similarly, the channel length LHN of the transistor MTHN corresponds to the length in the height direction of the opening KK2 of the insulator IS2 when viewed in cross-section. That is, the channel length LCK and the channel length LHN are determined according to the thickness of the insulator IS2. In addition, when the opening KK1 has a tapered shape, the channel length LCK also depends on the angle formed by the opening KK1 and the formed surface (here, the top surface of the conductor ME2), and the channel length LHN also depends on the angle formed by the opening KK2 and the formed surface (here, the top surface of the conductor ME2). Therefore, for example, the channel length LCK and the channel length LHN can be set to values smaller than the limit resolution of the exposure apparatus, and fine transistors can be realized. Specifically, transistors with an extremely small channel length that cannot be realized in the exposure apparatus used in the mass production of existing flat panel displays (for example, the minimum line width is about 2 μm or 1.5 μm) can be realized. In addition, transistors with a channel length of less than 10 nm can be realized without using the very expensive exposure apparatus used in the most advanced LSI technology.

[0145] The channel length LCK and the channel length LHN can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length LCK and the channel length LHN can also be 100 nm or more and 1 μm or less.

[0146] By shortening the channel length LCK and the channel length LHN, the on-state current of the transistor MTCK and the transistor MTHN can be increased. In other words, it is not necessary to increase the gate-source voltage in order to increase the on-state current. Therefore, for example, by using the transistor MTCK and the transistor MTHN in the drive circuit of a large display device or the drive circuit of a high-definition display device, the power consumption required for the gate-source voltage of these drive circuits can be reduced. In addition, when the transistor MTCK and the transistor MTHN are applied to a large display device or a high-definition display device, even if the number of wirings increases, the signal delay in each wiring can be reduced, and display unevenness can be suppressed. In addition, since the occupied area of the circuit can be reduced, the bezel of the display device can be reduced.

[0147] In addition, since the gate insulating film of the transistor MTCK includes the insulator GI2, the thickness of the gate insulating film of the transistor MTCK is thicker than that of the gate insulating film of the transistor MTHN. When the gate insulating film of a transistor is formed thick, the voltage gradient between the gate of the transistor and the channel formation region of the semiconductor can be made slow, so the tolerance of the transistor to the gate potential can be improved. On the other hand, when the gate insulating film of a transistor is formed thin, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes fast, so the driving frequency of the transistor can be increased.

[0148] That is, the transistor MTCK is used as a transistor having high tolerance to a high gate potential (in other words, sometimes referred to as a high gate-source voltage or a high gate-drain voltage), and the transistor MTHN is used as a transistor having a high driving frequency. Note that the transistor MTCK is sometimes used as a transistor having high tolerance to the source potential or the drain potential.

[0149] The difference between the transistor MTCK and the transistor MTHN lies in the thickness of the gate insulating film. By forming the insulator GI2 on the insulator GI1 in the region where the transistor MTCK is formed after forming the insulator GI1, the transistor MTCK with a thick gate insulating film and the transistor MTHN with a thin gate insulating film can be simply formed separately.

[0150] In addition, the thickness of the insulator GI2 formed after setting the insulator GI1 can be determined at the stage of the deposition process of the insulator GI2. That is, sometimes the thickness of the gate insulating film of the transistor MTCK can also be adjusted after setting the insulator GI1.

[0151] Note that although two transistors, the transistor MTCK and the transistor MTHN, are shown as an example in Figures 2A to 2D , one embodiment of the present invention is not limited thereto. For example, the transistor MTCK has a structure of two films including the insulator GI1 and the insulator GI2 in the gate insulating film, but the gate insulating film of the transistor MTCK may also be an insulating film in which three or more insulators are stacked. In addition, for example, a display device may also include three or more transistors having different thicknesses of the gate insulating film.

[0152] <Structural Example of Driving Circuit> Next, the driving circuit SD, the driving circuit GD, the driving circuit TSD, and the protection circuit PRT of the display device DSP in Figure 1 will be described.

[0153] <<Driving Circuit SD>> Figure 3 Shows what can be included in Figure 1An example of the structure of the driving circuit SD in the display device DSP. As an example, Figure 3 The driving circuit SD1 includes a shift register SR, a holding circuit LTC1, a holding circuit LTC2, an amplifying circuit SF, and a conversion circuit CVT.

[0154] As an example, the shift register SR includes a plurality of storage circuits RES (e.g., flip-flop circuits or register circuits) connected in a column. Specifically, in adjacent storage circuits RES, the first output terminal of the previous-stage storage circuit RES is electrically connected to the first input terminal of the subsequent-stage storage circuit RES. In addition, the first input terminal of the head storage circuit RES[1] (corresponding to the terminal IT of the storage circuit RESA shown in Figure 6A etc.) is electrically connected to the wiring SP. In addition, each of the second input terminals of the plurality of storage circuits RES (corresponding to the terminals CLK1, CLK2, terminal PWC, etc. of the storage circuit RESA shown in Figure 6A etc.) is electrically connected to the wiring CLS. Note that in Figure 3 the storage circuits RES[1] to RES[5] are shown as an abstract of the storage circuit RES.

[0155] As an example, the wiring SP is used as a wiring for supplying a variable potential (sometimes also referred to as a pulse potential, pulse voltage, or pulse signal) to the shift register SR. In addition, the wiring SP can be used, for example, as a wiring for supplying a fixed potential (e.g., high-level potential, low-level potential, ground potential, negative potential, etc.). Note that the wiring SP can be one wiring or multiple wirings. In addition, in the present embodiment, the wiring SP is used as a wiring for supplying a start pulse signal to the shift register SR.

[0156] As an example, the wiring CLS is used as a wiring for supplying a clock signal to the shift register SR. In addition, the wiring CLS can be used, for example, as a wiring for supplying a fixed potential (e.g., high-level potential, low-level potential, ground potential, negative potential, etc.) or a variable potential. Note that the wiring SP can be one wiring or multiple wirings.

[0157] When the start pulse signal is input from the wiring SP to the first input terminal of the storage circuit RES[1], the start pulse signal is supplied to the storage circuit RES[1], and the storage circuit RES[1] stores the information of the start pulse signal. In addition, at this time, when the clock signal is input from the wiring CLS to the second input terminals of the plurality of storage circuits RES, a signal corresponding to the information is output from the first output terminal of the storage circuit RES[1] (e.g., corresponding to the Figure 6AThe information is sent from the output terminal OT of the storage circuit RESA to the first input terminal of the adjacent storage circuit RES[2], and the storage circuit RES[2] stores the information. In other words, the shift register SR has the function of moving the information held in the previous-stage storage circuit RES to the next-stage storage circuit RES by receiving a clock signal.

[0158] In addition, the storage circuit RES also has the following function: when a clock signal is input from the wiring CLS to the second input terminal of the storage circuit RES that stores the start pulse signal information, a high-level potential is output to the second output terminal of the storage circuit RES.

[0159] As an example, the holding circuit LTC1 includes a plurality of first latch circuits LA. Each of the input terminals D of the plurality of first latch circuits LA is electrically connected to the wiring VIS. In addition, each of the second output terminals of the plurality of storage circuits RES included in the shift register SR (for example, corresponding to the terminal GT of the storage circuit RESA described later) is electrically connected to the enable input terminal E (clock input terminal) of the plurality of first latch circuits LA in a one-to-one manner. In addition, Figure 6A in, the first latch circuits LA[1] to LA[5] are shown as an abstract of the first latch circuit LA. Figure 3

[0160] As an example, the wiring VIS is used as a wiring for supplying an image signal (sometimes also referred to as a video signal or a display signal) as digital data to the holding circuit LTC1. In addition, as an example, the wiring VIS can be used as a wiring for supplying a fixed potential (for example, a high-level potential, a low-level potential, a ground potential, a negative potential, etc.). In addition, in the present embodiment, since an image signal as digital data is transmitted, the wiring VIS is a plurality of wirings.

[0161] The first latch circuit has the following functions: when a high-level potential is input from the second output terminal of the storage circuit RES to the enable input terminal E of the first latch circuit LA, the first latch circuit LA stores the image signal from the wiring VIS input to the input terminal of the first latch circuit LA. In addition, the first latch circuit has the following function: as long as the image signal is not rewritten after storing the image signal, the image signal is output to the output terminal of the first latch circuit.

[0162] ​That is to say, by inputting a start pulse signal from a wiring SP into a shift register SR and sequentially inputting a clock signal from a wiring CLS into the shift register SR, high-level potentials are sequentially input to the enable input terminals E of a plurality of first latch circuits respectively. Therefore, by changing the image signal of the wiring VIS according to the clock signal input from the wiring CLS into the shift register SR, each of the plurality of first latch circuits can store the image signal corresponding to each column.

[0163] As an example, a holding circuit LTC2 includes a plurality of second latch circuits LB. Each of the input terminals D of the plurality of second latch circuits LB is electrically connected to each of the output terminals of the plurality of first latch circuits LA in a one-to-one manner. In addition, the enable input terminals E of the plurality of second latch circuits LB are respectively electrically connected to a wiring DAT. Note that in Figure 3 Second latch circuits LB[1] to LB[5] are schematically shown as the second latch circuit LB.

[0164] As an example, the wiring DAT is used as a wiring for supplying a variable potential. In addition, the wiring DAT can also be used as a wiring for supplying a fixed potential (high-level potential, low-level potential, ground potential, negative potential, etc.) for example. Note that in this embodiment, the wiring DAT supplies a high-level potential or a low-level potential to the holding circuit LTC2.

[0165] When each of the plurality of first latch circuits LA stores information of an image signal, the wiring DAT supplies a low-level potential to the enable input terminals E of the second latch circuits. In addition, when each of the plurality of first latch circuits LA stores information of an image signal, the input terminals of the second latch circuits LB are input with the image signal output from the output terminals of the first latch circuits LA on their columns. At this time, the second latch circuits LB store the information of the image signal. That is to say, when the storage of the information of the image signal by each of the plurality of first latch circuits LA is completed, the storage of the information of the image signal by the plurality of second latch circuits LB is also completed.

[0166] Then, by supplying a high-level potential from the wiring DAT to the enable input terminals E of the plurality of second latch circuits LB, the stored image signals are output all at once from the output terminals of the plurality of second latch circuits LB.

[0167] As an example, an amplifier circuit SF includes a plurality of source follower circuits SAM. Each of the input terminals of the plurality of source follower circuits SAM is electrically connected to each of the output terminals of the plurality of second latch circuits LB in a one-to-one manner. Note that in Figure 3 Source follower circuits SAM[1] to SAM[5] are schematically shown as the source follower circuit SAM.

[0168] As an example, the conversion circuit CVT includes a plurality of digital-to-analog conversion circuits DAC. Each of the input terminals of the plurality of digital-to-analog conversion circuits DAC is electrically connected one-to-one to each of the output terminals of the plurality of source follower circuits SAM. In addition, each of the output terminals of the plurality of digital-to-analog conversion circuits DAC is electrically connected one-to-one to each of the plurality of wirings SL. Note that in Figure 3 as the digital-to-analog conversion circuit DAC, the abstract shows the digital-to-analog conversion circuit DAC[1] to the digital-to-analog conversion circuit DAC[5]. In addition, in Figure 3 as the wiring SL, the abstract shows the wiring SL[1] to the wiring SL[5].

[0169] As an example, the digital-to-analog conversion circuit DAC has a function of converting an image signal as digital data input to the input terminal of the digital-to-analog conversion circuit DAC into analog data and outputting it to the output terminal of the digital-to-analog conversion circuit DAC.

[0170] As an example, the wiring SL can be a wiring equivalent to Figure 1 the wiring SLS shown. Therefore, the wiring SL can be used as a wiring for sending an image signal as analog data to the pixel circuit.

[0171] Since the shift register SR is preferably driven at high speed, the storage circuit RES included in the shift register SR preferably uses the transistor MTHN. In addition, since the amplifier circuit SF is driven using a high voltage, the source follower circuit SAM included in the amplifier circuit SF preferably uses the transistor MTCK.

[0172] In addition, the first latch circuit LA included in the holding circuit LTC1 and the second latch circuit LB included in the holding circuit LTC2 can use the transistor MTCK or the transistor MTHN. In addition, either the first latch circuit LA or the second latch circuit LB can also use both the transistor MTCK and the transistor MTHN.

[0173] In addition, by reducing the high-level potential of the start pulse signal and the clock signal input to the shift register SR, the power consumption of the shift register SR can be reduced. However, in this case, the high-level potential output from the second output terminals of the plurality of storage circuits RES also becomes low, so sometimes in the plurality of first latch circuits LA included in the holding circuit LTC1, it is not possible to smoothly receive the image signal sent to one or more of the plurality of first latch circuits LA from the wiring VIS.

[0174] In this case, it is only necessary to change the drive circuit SD1 to Figure 4 the drive circuit SD2 shown. The drive circuit SD2 is different from the drive circuit SD1 in that it includes an amplifier circuit LVS.

[0175] In the driving circuit SD2, the amplifier circuit LVS includes a plurality of level shift circuits LS. In addition, the input terminals of the plurality of level conversion circuits LS are respectively electrically connected one-to-one to the second output terminals of the plurality of storage circuits RES. Further, the output terminals of the plurality of level conversion circuits LS are respectively electrically connected one-to-one to the input terminals of the plurality of first latch circuits LA. Note that, in Figure 3 the level shift circuits LS[1] to LS[5] are schematically shown as the level conversion circuit LS.

[0176] As an example, the level converter circuit LS has a function of amplifying the high-level potential output from the second output terminal of the storage circuit RES, converting its level to a higher potential, and outputting it to the output terminal of the level conversion circuit LS.

[0177] As described above, by using the driving circuit SD2, a higher potential obtained by level-converting the high-level potential output from the second output terminal of the storage circuit RES can be input to the enable input terminal E of the plurality of first latch circuits LA, whereby an image signal transmitted to each of the plurality of first latch circuits LA can be easily received from the wiring VIS.

[0178] <<Driving Circuit GD>> As an example, the driving circuit GD includes a shift register. In this case, the shift register included in the driving circuit GD may have the same structure as the shift register SR included in the above-described driving circuit SD.

[0179] Figure 5A An example of the structure of the driving circuit GD according to one aspect of the present invention applicable to Figure 1 the display device DSP is shown. As an example, Figure 5A the driving circuit GD shown includes storage circuits RES[1] to RES[m] serving as shift registers. Note that, regarding the storage circuits RES[1] to RES[m], reference can be made to Figure 3 the description of the plurality of storage circuits RES included in the shift register SR shown.

[0180] The storage circuits RES[1] to RES[m] include, for example, a first input terminal, a second input terminal, a first output terminal, and a second output terminal in the same manner as the plurality of storage circuits RES included in Figure 3 and Figure 4 the shift register SR.

[0181] In addition, in each of the storage circuits RES[1] to RES[m], for example, in adjacent storage circuits RES, the first output terminal of the preceding-stage storage circuit RES is electrically connected to the first input terminal of the succeeding-stage storage circuit RES. In addition, the first input terminal of the foremost storage circuit RES[1] is electrically connected to the wiring SS. Further, each of the second input terminals of the plurality of storage circuits RES is electrically connected to the wiring CLS2.

[0182] The wiring CLS2 can refer to, for example, Figure 3 the description of the wiring CLS shown.

[0183] The second output terminal of the storage circuit RES[i] is electrically connected to the wiring GL[i], for example.

[0184] As an example, each of the storage circuits RES[1] to RES[m] has the following functions: a function of holding the information input to the first input terminal; and a function of outputting the held information to one or both of the first output terminal and the second output terminal. In addition, for the specific operation, reference can be made to Figure 3 the description of the shift register SR shown.

[0185] In addition, the above information can be, for example, a selection signal for selecting the pixel circuit PX to which image data is to be written in the pixel array PXA. Further, in Figure 5A the driving circuit GD, this selection signal is sent by the wiring SS, held in sequence in the storage circuits RES[1] to RES[m], and this selection signal is sent to the wirings GL[1] to GL[m] in sequence.

[0186] In addition, in Figure 5A the driving circuit GD shown, the storage circuit RES[m] has a first output terminal, but since the storage circuits RES[1] to RES[m] have the structure of a shift register, the storage circuit RES[m] may not have a first output terminal either.

[0187] In addition, the structure of the driving circuit GD applicable to Figure 1 the display device DSP is not limited to Figure 5A . For example, as the structure of the driving circuit GD applicable to Figure 1 the display device DSP, the driving circuit GD shown in Figure 5B can also be adopted. Figure 5B The driving circuit GD of Figure 5A differs from the driving circuit GD of Figure 5B in that the driving circuit GD of

[0188] includes the circuits BF[1] to BF[m].Figure 5B In the driving circuit GD, the input terminal of each of the circuits BF[1] to BF[m] is electrically connected one-to-one to the second output terminal of each of the storage circuits RES[1] to RES[m], and the output terminal of each of the circuits BF[1] to BF[m] is electrically connected one-to-one to each of the wirings GL[1] to GL[m].

[0189] Each of BF[1] to BF[m] can adopt a structure including an amplification circuit such as a buffer circuit, an inverter circuit, or a latch circuit, for example. Specifically, each of the circuits BF[1] to BF[m] can have a function of outputting a potential obtained by amplifying the potential of the second output terminal with reference to the potential of the wiring GL. In particular, since high voltage is sometimes processed in this amplification circuit, transistor MTCK is preferably used as a transistor having high voltage tolerance in this amplification circuit. In addition, when it is desired to increase the driving speed of the amplification circuit, transistor MTHN is preferably used as the transistor included in this amplification circuit.

[0190] In addition, in Figure 5A and Figure 5B In the driving circuit GD shown, wirings other than the wiring CLS and the wiring SS can also be extended. For example, a wiring for supplying a fixed potential for driving each of the storage circuits RES[1] to RES[m] can also be extended.

[0191] In addition, as an example, the driving circuit GD can also include a demultiplexer. In addition, when the potential corresponding to the signal sent from the demultiplexer is a high potential, the demultiplexer preferably includes transistor MTCK as a transistor having high voltage tolerance. In addition, when it is desired to increase the operating speed of the demultiplexer, the demultiplexer preferably includes transistor MTHN as a transistor having a high driving frequency.

[0192] <<Driving Circuit TSD>> As an example, the driving circuit TSD can also include a shift register. Therefore, the shift register included in the driving circuit TSD can have the same structure as the shift register SR included in the above driving circuit SD.

[0193] In addition, as an example, the driving circuit TSD can also include an amplification circuit for amplifying the weak signal generated by the touch sensor. The amplification circuit is sometimes supplied with a high power supply potential for amplifying the signal. At this time, the amplification circuit preferably includes transistor MTCK as a transistor having high voltage tolerance.

[0194] <<Protection Circuit PRT>> As an example, the protection circuit PRT has a function of releasing the charge of the wiring GLS[i] or the wiring SLS[j] to other wirings in order to reduce the potential outside the specified range supplied to the wiring GLS[i] or the wiring SLS[j]. That is, the protection circuit PRT processes the potential outside the specified range in the wiring GLS[i] or the wiring SLS[j]. Therefore, the protection circuit PRT preferably includes the transistor MTCK as a transistor having high tolerance to voltage.

[0195] Note that, in the case where it is desired to increase the operating speed of the protection circuit PRT, the protection circuit PRT preferably includes the transistor MTHN of a transistor having a high driving frequency.

[0196] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in this embodiment. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in other embodiments.

[0197] (Embodiment 2) In this embodiment, the structures of the respective circuits included in the driving circuit SD described in the above Embodiment 1 are described.

[0198] <Shift register SR> First, an example of the structure of the storage circuit RES included in the shift register SR of the driving circuit SD is described.

[0199] <<Example 1 of the structure of the storage circuit RES>> Figure 6A Shows a circuit structure example of the storage circuit RESA that can be used for Figure 3 or Figure 4 the storage circuits RES[1] to RES[5] shown.

[0200] As an example, the storage circuit RESA includes transistors MN1 to MN10, and capacitors C3 to C5. In addition, as Figure 6A shown, the storage circuit RESA is a unipolar circuit that does not include p-channel transistors and includes n-channel transistors. Therefore, the transistors MN1 to MN10 are n-channel transistors.

[0201] In addition, the storage circuit RESA includes terminals IT, CLK1, CLK2, PWC, GT, and OT that are used as input terminals or output terminals.

[0202] In addition, the storage circuit RESA can be functionally divided into a circuit LGC and a circuit OPC. As an example, the circuit LGC has the function of a logic circuit that processes signals input to the terminal IT, and as an example, the circuit OPC has the function of a logic circuit that generates signals output to the terminal OT and the terminal GT. In addition, one or both of the circuit LGC and the circuit OPC can also be an analog circuit instead of a logic circuit.

[0203] As Figure 6A shown, as an example, the circuit LGC includes transistors MN1 to MN4 and a capacitor C5, and as an example, the circuit OPC includes transistors MN5 to MN10, a capacitor C3, and a capacitor C4. In addition, Figure 6A the difference between the circuit LGC and the circuit OPC of the transistors MN1 to MN10 and the capacitors C3 to C5 shown is just an example, and there is no particular limitation on the respective structures of the circuit LGC and the circuit OPC. For example, in Figure 6A it, the capacitor C5 included in the circuit LGC can also be included in the circuit OPC.

[0204] In the present embodiment, for convenience, the circuit LGC includes a terminal LI, a terminal LO1, and a terminal LO2. The terminal LI is used as an input terminal in the circuit LGC, the terminal LO1 is used as a first output terminal in the circuit LGC, and the terminal LO2 is used as a second output terminal in the circuit LGC.

[0205] In addition, Figure 6A the circuit OPC included in the storage circuit RESA of Figure 6A has the function of holding the potential corresponding to the signal input to the terminal IT by the capacitors C3 and C4. That is, the circuit OPC has the function of holding the potential output from the terminal LO1 of the circuit LGC. In addition,

[0206] When making the pixel array PXA of the display device DSP smoothly display a moving image, it is preferable to increase the frame frequency of the display device DSP. Therefore, in order to increase this frame frequency, the shift register SR included in the driving circuit SD preferably uses a transistor with a high driving frequency. That is, the transistors MN1 to MN10 preferably use the transistor MTHN described in the above Embodiment 1.

[0207] The gate of transistor MN1 is electrically connected to terminal IT through terminal LI, and the first terminal of transistor MN1 is electrically connected to wiring VDE1. In addition, the gate of transistor MN3 is connected to terminal CLK2, and the first terminal of transistor MN3 is connected to wiring VDE2. Further, the gate of transistor MN2 is connected to the second terminal of transistor MN3, the first terminal of transistor MN4, and the first terminal of capacitor C5. The first terminal of transistor MN2 is connected to the second terminal of transistor MN1, and the second terminal of transistor MN2 is connected to wiring VSE1. Additionally, the first terminal of transistor MN2 is connected to the first terminal of transistor MN5 and the first terminal of transistor MN8 through terminal LO1. The gate of transistor MN2 is connected to the gate of transistor MN7 and the gate of transistor MN10 through terminal LO2. Moreover, the gate of transistor MN4 is electrically connected to terminal IT through terminal LI, and the second terminal of transistor MN4 is connected to wiring VSE3.

[0208] The gate of transistor MN5 is connected to wiring VDE3, and the second terminal of transistor MN5 is connected to the gate of transistor MN6 and the first terminal of capacitor C3. The first terminal of transistor MN6 is connected to terminal CLK1, and the second terminal of transistor MN6 is connected to the first terminal of transistor MN7, the second terminal of capacitor C3, and terminal OT. The second terminal of transistor MN7 is connected to wiring VSE4.

[0209] The gate of transistor MN8 is connected to wiring VDE4, and the second terminal of transistor MN8 is connected to the gate of transistor MN9 and the first terminal of capacitor C4. The first terminal of transistor MN9 is connected to terminal PWC, and the second terminal of transistor MN9 is connected to the first terminal of transistor MN10, the second terminal of capacitor C4, and terminal GT. The second terminal of transistor MN10 is connected to wiring VSE5.

[0210] Terminal IT is a terminal corresponding to Figure 3 or Figure 4 the first input terminal of the memory circuit RES.

[0211] Moreover, terminal CLK1, terminal CLK2, and terminal PWC are terminals corresponding to Figure 3 or Figure 4 the second input terminals of the memory circuit RES. Therefore, Figure 3 or Figure 4 the wiring CLS shown in

[0212] In particular, two of the wirings CLS electrically connected to the terminals CLK1 and CLK2 and one of the wirings CLS electrically connected to the terminal PWC are used as the wirings for supplying the pulse potential. In addition, the pulse widths of the pulse potential supplied by one of the wirings CLS electrically connected to the terminal CLK1 or the terminal CLK2 and one of the wirings CLS electrically connected to the terminal PWC may also be different from each other.

[0213] In particular, it is preferable to send clock signals with a constant pulse width to two of the wirings CLS electrically connected to the terminals CLK1 and CLK2. In addition, it is preferable to send a clock signal including a pulse width that can be changed during the operation of the drive circuit SD to one of the wirings CLS electrically connected to the terminal PWC. In this case, during the operation of the drive circuit SD, the pulse width of the clock signal input to the storage circuit RES through the terminal PWC can be arbitrarily set.

[0214] The terminal OT corresponds to Figure 3 or Figure 4 the first output terminal of the storage circuit RES.

[0215] The terminal GT corresponds to Figure 3 or Figure 4 the second output terminal of the storage circuit RES.

[0216] As an example, the wirings VDE1 to VDE4 are all used as the wirings for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. The wirings VDE1 to VDE4 can supply equal fixed potentials to each other, or can supply unequal fixed potentials to each other. In addition, among the wirings VDE1 to VDE4, two or more wirings can also supply equal fixed potentials to each other, and the remaining wirings can also supply a potential different from this fixed potential. In addition, two or more of the wirings VDE1 to VDE4 that supply equal fixed potentials to each other can also be the same wiring. For example, when the wirings VDE1 and VDE2 supply equal fixed potentials to each other, the wirings VDE1 and VDE2 can also be the same wiring.

[0217] One or more of the wirings VDE1 to VDE4 can also be a wiring that supplies a variable potential instead of a fixed potential.

[0218] As an example, wirings VSE1 to VSE5 are all used as wirings for supplying a fixed potential. The fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. Wirings VSE1 to VSE5 can supply the same fixed potential to each other, or can supply different fixed potentials to each other. Additionally, among wirings VSE1 to VSE5, two or more wirings can also supply the same fixed potential to each other, and the remaining wirings can also supply a potential different from this fixed potential. Further, two or more wirings among wirings VSE1 to VSE5 that supply the same fixed potential to each other can also be the same wiring. For example, when wirings VSE1 and VSE2 supply the same fixed potential to each other, wirings VSE1 and VSE2 can also be the same wiring.

[0219] One or more of wirings VSE1 to VSE4 can also be a wiring that supplies a variable potential instead of a fixed potential.

[0220] Here, assuming that wiring VDE1 and wiring VDE2 are input with a high-level potential and wirings VSE1 to VSE3 are input with a low-level potential, the Figure 6A operation of the shown circuit LGC will be described.

[0221] Figure 6A For the circuit LGC, for example, when a low-level potential is supplied to terminal IT and a high-level potential is supplied to terminal CLK2, a low-level potential supplied by wiring VSE1 is output from terminal LO1, and a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential supplied by wiring VDE2 is output from terminal LO2. In addition, the gate of transistor MN2 is input with a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential supplied by wiring VDE2, so the potential output from terminal LO1 is sometimes slightly higher than the low-level potential supplied by wiring VSE1 exactly.

[0222] Next, for example, when a low-level potential is supplied to terminal IT and a low-level potential is supplied to terminal CLK2, circuit LGC outputs from terminal LO1 the low-level potential (or a potential slightly higher than this low-level potential) of wiring VSE1 that is the potential of node N1, and outputs from terminal LO2 a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential supplied by wiring VDE2 that is the potential of node N2.

[0223] When a high-level potential is supplied to terminal IT and a low-level potential is supplied to terminal CLK2, circuit LGC outputs from terminal LO1 a potential obtained by subtracting the threshold voltage of transistor MN1 from the high-level potential supplied by wiring VDE1, and outputs from terminal LO2 the low-level potential supplied by wiring VSE3.

[0224] Next, for example, when a low-level potential is supplied to terminal IT and a low-level potential is supplied to terminal CLK2, circuit LGC outputs from terminal LO1 a potential obtained by subtracting the threshold voltage of transistor MN1 from the high-level potential supplied by wiring VDE1 of the potential of node N1, and outputs from terminal LO2 a potential obtained by subtracting the low-level potential supplied by wiring VSE3 of the potential of node N2.

[0225] In short, when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT, circuit LGC ideally outputs a high-level potential from terminal LO1 and a low-level potential from terminal LO2. Further, when a high-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, circuit LGC ideally outputs a low-level potential from terminal LO1 and a high-level potential from terminal LO2. Additionally, when a low-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, circuit LGC outputs from terminal LO1 the potential of node N1 (sometimes alternatively referred to as maintaining the potential output from terminal LO1), and outputs from terminal LO2 the potential of node N2 (sometimes alternatively referred to as maintaining the potential output from terminal LO2).

[0226] In addition, in Figure 6A the storage circuit RESA, by using the transistor MTCK described in Embodiment 1 for each of transistors MN1 to MN10, a storage circuit RESA having high tolerance to high voltages can be formed. In addition, in Figure 6A the storage circuit RESA, by using the transistor MTHN described in Embodiment 1 for transistors MN1 to MN10, the operating speed of the storage circuit RESA can be increased, and as a result, the frame frequency of the display device DSP can be increased.

[0227] Figure 7 is Figure 6A a layout diagram (plan view) of the storage circuit RESA. In Figure 7 it, transistors MTCK or transistors MTHN described in Embodiment 1 are illustrated as transistors MN1 to MN10. Further, in Figure 7 it, the storage circuit RESA includes conductor GEM, conductor SDD, conductor SDU, semiconductor SMC, and conductor PLG. Additionally, Figure 7 the insulators included in the storage circuit RESA are not illustrated.

[0228] As an example, conductor SDD is located below conductor SDU. Additionally, as an example, conductor SDU includes an opening KK in the region overlapping conductor SDD. In addition, in Figure 7In it, the opening KK is indicated by a dashed line. Additionally, as an example, the semiconductor SMC is located on the conductor SDU outside the area of the opening KK and on the conductor SDD in the area of the opening KK. Furthermore, the conductor GEM is located above the semiconductor SMC in a manner that fills the opening KK.

[0229] The conductor SDD corresponds to Figures 2A to 2D the conductor ME1 in Figures 2A to 2D and the conductor SDU corresponds to Figures 2A to 2D the conductor ME2 in Figures 2A to 2D and the semiconductor SMC corresponds to Figures 2A to 2D the semiconductor SC1 in

[0230] The semiconductor SMC, the conductor GEM, the conductor SDD, and the conductor SDU can all be formed, for example, by photolithography. Specifically, for example, in the case of forming the conductor GEM, a conductive material that will become the conductor GEM is formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition) methods, and then the desired pattern can be formed using photolithography. In addition, the semiconductor SMC, the conductor SDD, and the conductor SDU can also be formed using the same method as above.

[0231] In addition, insulators can be provided between the semiconductor SMC and the conductor GEM, between the conductor SDU and the conductor GEM, and between the conductor SDU and the conductor SDD, respectively. In particular, the insulator provided between the semiconductor SMC and the conductor GEM is sometimes used as a gate insulating film.

[0232] In addition, conductors PLG used as wirings or plugs are provided between the conductor SDD and the conductor SDU and between the conductor SDU and the conductor GEM, respectively. For example, an opening is formed in the above insulator, and a conductive material that will become the conductor PLG is filled in the opening to form the conductor PLG. Additionally, after forming the conductor PLG, planarization can be performed by a planarization process such as chemical mechanical polishing to make the heights of the film surfaces of the conductor PLG and the insulators in its vicinity uniform.

[0233] In addition, instead of providing the conductor PLG between the conductor SDU and the conductor GEM, an opening can be provided in the insulator between the conductor SDU and the conductor GEM to directly contact the conductor SDU and the conductor GEM, thereby electrically connecting the conductor SDU and the conductor GEM.

[0234] In addition, in Figure 7 capacitor C4, a part of the conductor GEM serves as the first terminal of capacitor C4, and a part of the conductor SDD serves as the second terminal of capacitor C4. In addition, in order to increase the capacitance of capacitor C4, in the region of capacitor C4 in Figure 7 , the insulator between the conductor GEM and the conductor SDD can also be thinned. In addition, an insulator with a high relative permittivity can also be provided between the conductor GEM and the conductor SDD. In addition, capacitor C5 can also refer to the description of capacitor C4.

[0235] In Figure 7 capacitor C3, a part of the conductor SDU serves as the first terminal of capacitor C3, and a part of the conductor SDD serves as the second terminal of capacitor C3. Therefore, in the region of capacitor C3 in Figure 7 , the conductor GEM is electrically connected to the conductor SDU, but the conductor SDU is not electrically connected to the conductor SDD. In addition, in order to increase the capacitance of capacitor C3, the insulator between the conductor SDD and the conductor SDU can also be thinned in the region of capacitor C3 in Figure 7 . In addition, an insulator with a high relative permittivity can also be provided between the conductor SDD and the conductor SDU.

[0236] In addition, in Figure 6A the storage circuit RESA, the transistor MTCK or transistor MTHN described in Embodiment 1 can also be used for a part of transistors MN1 to MN10, and transistors with other structures can be used for the remaining transistors. For example, a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor) can be used as the transistor included in the circuit LGC, and the transistor MTCK or transistor MTHN described in Embodiment 1 can be used as the transistor included in the circuit OPC.

[0237] As such silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (for example, low-temperature polycrystalline silicon (LTPS), etc.) or single-crystalline silicon can be cited.

[0238] In addition, as transistors with other structures, for example, transistors containing germanium (Ge), etc. in the channel formation region, transistors containing compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or silicon germanium (SiGe) in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region can be cited.

[0239] Figure 8AIt is a cross-sectional view of transistors that are part of the memory circuit RESA. As an example, Figure 8A it shows a structure in which the anti-interleaved transistor MA1 is provided below and the transistor MTCK is provided above it. In addition, in Figure 8A , the conductor MT1 that serves as the source or drain of the transistor MA1 is electrically connected to the conductor ME1 of the transistor MTCK through the conductors PG1 and PG2 that serve as wiring or plugs.

[0240] For example, Figure 8A in, the transistor MTCK and the transistor MA1 can each be Figure 6A the transistors MN1 and MN2 of the memory circuit RESA of Figure 8A . In addition, for example, Figure 6A in, the transistor MTCK and the transistor MA1 can each be Figure 8A the transistors MN5 and MN2 of the memory circuit RESA of Figure 6A . In addition, for example, Figure 8A in, the transistor MTCK and the transistor MA1 can each be the transistors MN8 and MN2. For example, Figure 6A in the memory circuit RESA of Figure 8A , the transistor MN5 can be

[0241] the transistor MTCK in Figure 8B , and Figure 8A in the memory circuit RESA of Figure 8B it shows a structure in which the TGTC (Top Gate Top Contact) type transistor MA2 is provided below and the transistor MTCK is provided above it. In Figure 8B , the conductor MT2 that serves as the source or drain of the transistor MA2 is electrically connected to the conductor ME1 of the transistor MTCK through the conductors PG1 and PG2 that serve as wiring or plugs.

[0242] Figure 8A and Figure 8B the transistors MA1 and MA2 shown in

[0243] Figure 8A and Figure 8B can both be Si transistors. The transistor MTCK shown in

[0244] can also be the transistor MTHN described in Embodiment 1.

[0245] <<Example 2 of the structure of the storage circuit RES>> The structure of the storage circuit RES that the shift register SR can include is not limited to Figure 6A the storage circuit RESA shown. For example, as the structure of the storage circuit RES that the shift register SR can include, the Figure 6B storage circuit RESB shown can also be used.

[0246] Figure 6B The storage circuit RESB of Figure 6A is a modified example of the storage circuit RESA of

[0247] and is different from the storage circuit RESA in that each transistor included in the storage circuit RESB is provided with a back gate.

[0247] As an example, Figure 6A the transistors MN1 to MN10 shown are n-channel transistors having a multi-gate structure including gates above and below the channel, and the transistors MN1 to MN10 include back gates in addition to the gates. Note that in this specification and the like, for the sake of convenience, the gate is referred to as the first gate (sometimes denoted as the front gate) and the back gate is denoted as the second gate for distinction. In addition, in this specification and the like, the first gate and the second gate can be interchanged with each other, so the "gate" can be denoted as the "back gate". Similarly, the "back gate" can be denoted as the "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be changed to the connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0248] Note that in Figure 6B , the electrical connection object of each back gate of the transistors MN1 to MN10 can be determined at the time of design. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, the gate and the back gate can also be electrically connected (corresponding to the transistors MN1, MN3, MN5, MN6, MN8, and MN9 in Figure 6B ). In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit can also be provided and a potential can be supplied to the back gate of the transistor through the external circuit (corresponding to the transistors MN2, MN4, MN7, and MN10 in Figure 6B ).

[0249] In addition, in Figure 6A and Figure 6BAmong them, transistors MN1 to MN10 are n-channel transistors, but transistors MN1 to MN10 can also be p-channel transistors depending on the situation.

[0250] Regarding the description of the above transistors, except for Figure 6A and Figure 6B In addition, it can sometimes be used in the same way for the transistors described in other parts of the specification or the transistors shown in other figures.

[0251] In each of transistors MN1, MN3, MN5, MN6, MN8, and MN9, the gate is electrically connected to the back gate. In addition, the second gate of transistor MN2 is electrically connected to wiring BG1. Further, the second gate of transistor MN4 is electrically connected to wiring BG2. In addition, the gate of each of transistors MN7 and MN10 is electrically connected to wiring BG3.

[0252] As an example, wirings BG1 to BG3 are all used as wirings for supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. In addition, each of wirings BG1 to BG3 can supply the same fixed potential to each other, or can supply different fixed potentials to each other. Further, when two or more selected from wirings BG1 to BG3 are wirings for supplying the same fixed potential to each other, the two or more selected wirings can also be the same wiring. In addition, one or more selected from wirings BG1 to BG3 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0253] When wirings BG1 to BG3 are different wirings from each other, different fixed potentials can be supplied to the back gates of each of transistors MN2, MN4, MN7, and MN10. That is, the threshold voltage of transistor MN2, the threshold voltage of transistor MN4, and the threshold voltage of each of transistors MN7 and MN10 can be independently controlled.

[0254] Thus, for example, by supplying a negative potential to the back gate of transistor MN4 and supplying a ground potential or a low-level potential (a potential higher than the negative potential) to the back gates of each of transistors MN7 and MN10, the off-state current amount of transistors MN7 and MN10 can be made larger than the off-state current amount of transistor MN4. Therefore, by using the Figure 6B storage circuit RESB of Figure 3 or Figure 4 for each of the multiple storage circuits RES of the

[0255] <<Example 3 of the structure of the storage circuit RES>> In addition, for example, as the structure of the storage circuit RES that can be included in the shift register SR, the Figure 9A shown storage circuit RESPMS can also be used.

[0256] The storage circuit RESPMS has a circuit structure that rewrites the Figure 6A storage circuit RESA, which is a unipolar circuit including n-channel transistors, into a unipolar circuit including p-channel transistors.

[0257] The storage circuit RESPMS includes the circuit LGC and the circuit OPC in the same way as the Figure 6A storage circuit RESA. As an example, the circuit LGC includes transistors MP1 to MP4 and capacitor C5. As an example, the circuit OPC includes transistors MP5 to MP10, capacitor C3, and capacitor C4. In addition, as described above, transistors MP1 to MP10 are all p-channel transistors.

[0258] The gate of transistor MP1 is electrically connected to terminal IT through terminal LI, and the first terminal of transistor MP1 is electrically connected to wiring VSE16. In addition, the gate of transistor MP3 is electrically connected to terminal CLK2, and the first terminal of transistor MP3 is electrically connected to wiring VSE17. In addition, the gate of transistor MP2 is electrically connected to the second terminal of transistor MP3, the first terminal of transistor MP4, and the first terminal of capacitor C5. The first terminal of transistor MP2 is electrically connected to the second terminal of transistor MP1, and the second terminal of transistor MP2 is electrically connected to wiring VDE16. In addition, the first terminal of transistor MP2 is electrically connected to the first terminals of transistor MP5 and transistor MP8 through terminal LO1. The gate of transistor MP2 is electrically connected to the gates of transistor MP7 and transistor MP10 through terminal LO2. In addition, the gate of transistor MP4 is electrically connected to terminal IT through terminal LI, and the second terminal of transistor MP4 is electrically connected to wiring VDE18.

[0259] The gate of transistor MP5 is electrically connected to wiring VSE5, and the second terminal of transistor MP5 is electrically connected to the gate of transistor MP6 and the first terminal of capacitor C3. The first terminal of transistor MP6 is electrically connected to terminal CLK1, and the second terminal of transistor MP6 is electrically connected to the first terminal of transistor MP7, the second terminal of capacitor C3, and terminal OT. The second terminal of transistor MP7 is electrically connected to wiring VDE19.

[0260] The gate of transistor MP8 is electrically connected to wiring VSE19, and the second terminal of transistor MP8 is electrically connected to the gate of transistor MP9 and the first terminal of capacitor C4. The first terminal of transistor MP9 is electrically connected to terminal PWC, and the second terminal of transistor MP9 is electrically connected to the first terminal of transistor MP10, the second terminal of capacitor C4, and terminal GT. The second terminal of transistor MP10 is electrically connected to wiring VDE20.

[0261] As an example, wirings VDE16 to VDE20 are all used as wirings for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. Wirings VDE16 to VDE20 can supply the same fixed potential to each other, or can supply different fixed potentials. Among wirings VDE16 to VDE20, two or more wirings can also supply the same fixed potential to each other, and the remaining wirings can also supply a potential different from this constant potential. In addition, two or more wirings among wirings VDE16 to VDE20 that supply the same fixed potential to each other can also be the same wiring. For example, when wirings VDE16 and VDE17 supply the same fixed potential to each other, wirings VDE16 and VDE17 can also be the same wiring.

[0262] One or more of wirings VDE16 to VDE20 can also be a wiring that supplies a variable potential instead of a fixed potential.

[0263] As an example, wirings VSE16 to VSE19 are all used as wirings for supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. In addition, each of wirings VSE16 to VSE19 can supply the same fixed potential to each other, or can supply different fixed potentials. In addition, among wirings VSE16 to VSE19, two or more wirings can also supply the same fixed potential to each other, and the remaining wirings can also supply a potential different from this fixed potential. In addition, two or more wirings among wirings VSE16 to VSE19 that supply the same fixed potential to each other can also be the same wiring. For example, when wirings VSE16 and VSE17 supply the same fixed potential to each other, wirings VSE1 and VSE17 can also be the same wiring.

[0264] One or more of wirings VSE16 to VSE19 can also be a wiring that supplies a variable potential instead of a fixed potential.

[0265] The operation of the storage circuit RESPMS can be referred to Figure 6ADescription of the operation example of the storage circuit RESA. Note that since the circuit LGC in the storage circuit RESPMS is a unipolar circuit including p-channel transistors, the logic of signals, potentials, etc. processed in the storage circuit RESPMS is reversed compared to that of a unipolar circuit including n-channel transistors Figure 6A in the storage circuit RESA.

[0266] In addition, in Figure 9A the storage circuit RESPMS, by using the transistor MTCK described in Embodiment 1 for each of the transistors MP1 to MP10, a storage circuit RESPMS with high tolerance to high voltages can be formed. In addition, in Figure 9A the storage circuit RESPMS, by using the transistor MTHN described in Embodiment 1 for the transistors MP1 to MP10, the operating speed of the storage circuit RESPMS can be increased, and as a result, the frame frequency of the display device DSP can be increased.

[0267] <<Structural Example 4 of the Storage Circuit RES>> In addition, for example, as the structure of the storage circuit RES that the shift register SR can include, the storage circuit RESCMS shown in Figure 9B can also be used.

[0268] The storage circuit RESCMS has a circuit structure that rewrites the storage circuit RESA, which is a unipolar circuit including n-channel transistors, into a CMOS (Complementary MOS) circuit including n-channel transistors and p-channel transistors. Figure 6A

[0269] Similar to Figure 6A the storage circuit RESA, the storage circuit RESCMS includes the circuit LGC and the circuit OPC. As an example, the circuit LGC includes the transistors MP1, MN2, MP3, MN4, the capacitor C5, and the inverter INV10. As an example, the circuit OPC includes the transistors MP6, MN7, MP9, and MP10. In addition, the transistors MP1, MP3, MP6, and MP9 are p-channel transistors, and the transistors MN2, MN4, MN7, and MN10 are n-channel transistors.

[0270] In addition, the inverter INV10 can be either a unipolar circuit including one of n-channel transistors and p-channel transistors or a CMOS circuit including both n-channel transistors and p-channel transistors.

[0271] ​The gate of transistor MP1 is electrically connected to the output terminal of inverter INV10. In addition, the input terminal of inverter INV10 is electrically connected to terminal IT through terminal LI. Further, the first terminal of transistor MP1 is electrically connected to wiring VDE1. In addition, the gate of transistor MP3 is electrically connected to terminal CLK2, and the first terminal of transistor MP3 is electrically connected to wiring VDE2. In addition, the gate of transistor MN2 is electrically connected to the second terminal of transistor MP3, the first terminal of transistor MN4, and the first terminal of capacitor C5. The first terminal of transistor MN2 is electrically connected to the second terminal of transistor MN1. The second terminal of transistor MN2 is electrically connected to wiring VSE1. In addition, the first terminal of transistor MN2 is electrically connected to the gates of transistor MP6 and transistor MP9 through terminal LO1. The gate of transistor MN2 is electrically connected to the gates of transistor MN7 and transistor MN10 through terminal LO2. In addition, the gate of transistor MN4 is electrically connected to terminal IT through terminal LI, and the second terminal of transistor MN4 is electrically connected to wiring VSE3.

[0272] The first terminal of transistor MP6 is electrically connected to terminal CLK1, and the second terminal of transistor MP6 is electrically connected to the first terminal of transistor MN7 and terminal OT. The second terminal of transistor MN7 is electrically connected to wiring VSE4.

[0273] The first terminal of transistor MP9 is electrically connected to terminal PWC, and the second terminal of transistor MP9 is electrically connected to the first terminal of transistor MN10 and terminal GT. The second terminal of transistor MN10 is electrically connected to wiring VSE5.

[0274] Regarding wiring VDE1, wiring VDE2, and wiring VSE1 to wiring VSE5, reference can be made to Figure 6A the descriptions of wiring VDE1, wiring VDE2, and wiring VSE1 to wiring VSE5 shown.

[0275] The operation of memory circuit RESCMS can be referred to Figure 6A the description of the operation example of memory circuit RESA. It should be noted that in memory circuit RESPMS, terminal CLK2 is electrically connected to the gate of transistor MP3 which is a p-channel transistor. Therefore, in memory circuit RESCMS, the logic of the signal input to the gate of transistor MP3 is the logic in which the logic of the signal input to the gate of transistor MN3 which is an n-channel transistor in Figure 6A memory circuit RESA is inverted.

[0276] In addition, in Figure 9BIn the storage circuit RESCMS, by using the transistor MTCK described in Embodiment 1 for each of the transistors included in the transistors MP1, MN2, MP3, MN4, MP6, MN7, MP9, MP10, and the inverter INV10, a storage circuit RESCMS with high tolerance to high voltages can be formed. In addition, in Figure 9B the storage circuit RESCMS, by using the transistor MTHN described in Embodiment 1 for each of the above-listed transistors, the operating speed of the storage circuit RESCMS can be increased, and as a result, the frame frequency of the display device DSP can be increased.

[0277] <<Structural Example 5 of the Storage Circuit RES>> In addition, for example, as the structure of the storage circuit RES that the shift register SR can include, the Figure 10 shown storage circuit RESC can also be adopted.

[0278] The storage circuit RESC includes a terminal ITA and a terminal ITB that serve as the first input terminals of the storage circuit RES for Figure 3 or Figure 4 and a terminal OTA and a terminal OTB that serve as the first output terminals of the storage circuit RES for Figure 3 or Figure 4 That is, the difference between the storage circuit RESC and the storage circuit RESA is that the storage circuit RESC includes two first input terminals and two first output terminals.

[0279] In addition, the terminal OTA of the previous-stage storage circuit RESC is electrically connected to the terminal ITA of the subsequent-stage storage circuit RESC, and the terminal OTB of the previous-stage storage circuit RESC is electrically connected to the terminal ITB of the subsequent-stage storage circuit RESC.

[0280] In addition, the storage circuit RESC includes a terminal CLK3 and a terminal CLK4. The terminal CLK3 and the terminal CLK4 are terminals corresponding to the second input terminals of the storage circuit RES for Figure 3 or Figure 4 Therefore, Figure 3 or Figure 4 the shown wiring CLS can be two or more.

[0281] In particular, one of the wirings CLS electrically connected to the terminal CLK3 or the terminal CLK4 and one of the wirings CLS electrically connected to the terminal PWC are used as the wirings for supplying the pulse potential. In addition, the pulse widths of the pulse potential supplied to the terminal CLK3 and the terminal CLK4 can also be different from each other.

[0282] In addition, the storage circuit RESC includes a terminal GT in the same manner as the storage circuit RESA. The terminal GT is a terminal corresponding to Figure 3 or Figure 4 the second output terminal of the storage circuit RES.

[0283] As an example, the storage circuit RESC includes transistors MN51 to MN59 and capacitors C6 to C8. In addition, as Figure 10 shown, the storage circuit RESC is a unipolar circuit that does not include p-channel transistors but includes n-channel transistors.

[0284] In addition, in Figure 10 the storage circuit RESC, the transistors MN51 to MN59 have a single-gate structure, but transistors with a multi-gate structure including gates above and below the channel can also be used.

[0285] When smoothly displaying a moving image on the pixel array PXA of the display device DSP, it is preferable to increase the frame frequency of the display device DSP. Therefore, in order to increase this frame frequency, the shift register SR included in the drive circuit SD preferably uses transistors with a high drive frequency. That is, it is preferable that the transistors MN51 to MN59 use the transistor MTHN described in the above Embodiment 1.

[0286] The first terminal of the capacitor C6 is electrically connected to the first terminal of the transistor MN52 and the terminal CLK4, and the second terminal of the capacitor C6 is electrically connected to the first terminal of the transistor MN51, the gate of the transistor MN52, and the first terminal of the transistor MN53. The second terminal of the transistor MN51 is electrically connected to the wiring VSE6, and the gate of the transistor MN51 is electrically connected to the terminal ITB. The second terminal of the transistor MN53 is electrically connected to the wiring VSE7, and the gate of the transistor MN53 is electrically connected to the terminal CLK3. The second terminal of the transistor MN52 is electrically connected to the gate of the transistor MN56, the first terminal of the transistor MN57, the gate of the transistor MN59, and the first terminal of the capacitor C8. The second terminal of the transistor MN57 is electrically connected to the wiring VSE9. The second terminal of the capacitor C8 is electrically connected to the wiring VSE10.

[0287] The first terminal of transistor MN54 is electrically connected to wiring VDE6, and the second terminal of transistor MN54 is electrically connected to the first terminal of transistor MN55, the gate of transistor MN57, the first terminal of transistor MN56, and terminal OTB. The second terminal of transistor MN56 is electrically connected to wiring VSE8. The second terminal of transistor MN55 is electrically connected to the gate of transistor MN58 and the first terminal of capacitor C7, and the gate of transistor MN55 is electrically connected to wiring VDE7. The first terminal of transistor MN58 is electrically connected to terminal CLK4, and the second terminal of transistor MN58 is electrically connected to the second terminal of capacitor C7, the first terminal of transistor MN59, terminal OTA, and terminal GT. The second terminal of transistor MN59 is electrically connected to wiring VSE11.

[0288] As an example, both wiring VDE6 and wiring VDE7 are used as wirings for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. Wiring VDE6 and wiring VDE7 can supply the same fixed potential to each other, or can supply different fixed potentials to each other. In addition, when wiring VDE6 and wiring VDE7 supply the same fixed potential to each other, wiring VDE6 and wiring VDE7 can also be the same wiring.

[0289] One or both of wiring VDE6 and wiring VDE7 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0290] As an example, all of wiring VSE6 to wiring VSE11 are used as wirings for supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. In addition, each of wiring VSE6 to wiring VSE11 can supply the same fixed potential to each other, or can supply different fixed potentials to each other. Also, among wiring VSE6 to wiring VSE11, two or more wirings can supply the same fixed potential to each other, and the remaining wirings can supply a potential different from this fixed potential. In addition, two or more wirings among wiring VSE6 to wiring VSE11 that supply the same fixed potential to each other can also be the same wiring. For example, when wiring VSE6 and wiring VSE7 supply the same fixed potential to each other, wiring VSE6 and wiring VSE7 can also be the same wiring.

[0291] One or more of wiring VSE6 to wiring VSE11 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0292] When smoothly displaying a moving image on the pixel array PXA of the display device DSP, in order to increase the frame frequency of the display device DSP, as the shift register SR included in the drive circuit SD, a transistor with a high drive frequency is preferably used. Therefore, transistors MN51 to MN59 preferably use the transistor MTHN described in the above Embodiment 1.

[0293] <<Example Structure 6 of the Storage Circuit RES>> A semiconductor device according to one aspect of the present invention may adopt a structure in which a part of the storage circuit RES is driven with a low power supply voltage and another part of the storage circuit RES is driven with a high power supply voltage. Specifically, for example, consider the case where the power supply voltage supplied to the shift register SR is reduced in the Figure 3 drive circuit SD1 to drive the shift register SR. Note that the power supply voltage may be, for example, Figure 6A the potential difference between the high-level potential supplied by the wirings VDE1 to VDE4 and the low-level potential supplied by the wirings VSE1 to VSE5 in Figure 6A . In addition, the power supply voltage may be, for example,

[0294] the voltage amplitude of the clock signal supplied to the terminals CLK1, CLK2, and PWC in

[0295] . In addition, the power supply voltage may be, for example, the potential difference between the high potential and the low potential of the start pulse signal input to the shift register SR.

[0296] Specifically, for example, in the case of adopting the Figure 6A storage circuit RESA, the potential (high-level potential or low-level potential) of the clock signal corresponding to the terminal CLK1 or the low-level potential supplied by the wiring VSE4 is output from the terminal OT (corresponding to the Figure 3 or Figure 4 first output terminal of the storage circuit RES), and the potential (high-level potential or low-level potential) of the clock signal corresponding to the terminal PWC or the low-level potential supplied by the wiring VSE5 is output from the terminal GT (corresponding to the Figure 3 or Figure 4 second output terminal of the storage circuit RES).

[0297] The voltage (the potential difference between the high potential and the low potential of the signal) of the signal output from the second output terminal of the storage circuit RES included in the shift register SR becomes low, Figure 3 and the low voltage is input to the enable input terminals of the plurality of first latch circuits LA included in the holding circuit LTC1. In the first latch circuit LA, when the voltage of the signal input to the enable input terminal becomes low, it may not be possible to smoothly receive the image signal transmitted to one or more of the plurality of first latch circuits LA from the wiring VIS.

[0298] A semiconductor device according to one aspect of the present invention is a storage circuit RES or a shift register SR including the storage circuit RES, wherein by driving a part of the storage circuit RES with a low power supply voltage and driving another part of the storage circuit RES with a high power supply voltage, the voltage output from the first output terminal of the storage circuit RES can be reduced and the voltage output from the second output terminal of the storage circuit RES can be increased. Specifically, in Figure 3 or Figure 4 A semiconductor device according to one aspect of the present invention is a storage circuit RES or a shift register SR including the storage circuit RES, wherein the signal transmitted from the previous-stage storage circuit RES to the subsequent-stage storage circuit RES is set to a low voltage (for example, the potential difference between the high-level potential and the low-level potential), and the signal transmitted from the storage circuit RES to the enable input terminal of the first latch circuit LA is set to a high voltage (for example, the potential difference between a potential higher than the high-level potential and the low-level potential). Hereinafter, a structural example of the semiconductor device will be described.

[0299] Figure 11A The storage circuit RESD1 shown in Figure 3 or Figure 4 shows an example of the circuit structure of the storage circuit included in the plurality of storage circuits RES included in the shift register SR that can be used for

[0300] Figure 11A The storage circuit RESD1 shown in includes a circuit LGC and a circuit OPC. The structure of the circuit OPC included in the storage circuit RESD1 is different from the circuit OPC shown in Figure 6A and Figure 6B shown.

[0301] In Figure 11A the storage circuit RESD1, the circuit OPC includes a transistor MNC1, a transistor MNC2, a transistor MNH1, and a transistor MNH2.

[0302] In addition, the circuit LGC includes a terminal LI and terminals LO1 to LO4.

[0303] The first terminal of transistor MNC1 is electrically connected to terminal PWC, the second terminal of transistor MNC1 is electrically connected to the first terminal of transistor MNC2 and terminal GT, and the gate of transistor MNC1 is electrically connected to terminal LO1. In addition, the second terminal of transistor MNC2 is electrically connected to wiring VSE22, and the gate of transistor MNC2 is electrically connected to terminal LO2. The first terminal of transistor MNH1 is electrically connected to terminal CLK5, the second terminal of transistor MNH1 is electrically connected to the first terminal of transistor MNH2 and terminal OT, and the gate of transistor MNH1 is electrically connected to terminal LO3. In addition, the second terminal of transistor MNH2 is electrically connected to wiring VSE21, and the gate of transistor MNH2 is electrically connected to terminal LO4.

[0304] and Figure 6A similar to the circuit LGC of the storage circuit RESA of Figure 11A the circuit LGC of the storage circuit RESD1 of Figure 11A has the function that when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT, desirably, a high-level potential is output from terminal LO1 and a low-level potential is output from terminal LO2. In addition, when a high-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, Figure 11A the circuit LGC has the function that desirably, a low-level potential is output from terminal LO1 and a high-level potential is output from terminal LO2. In addition, when a low-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT,

[0305] In addition, Figure 11A in the circuit LGC of Figure 11A when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT, the circuit LGC desirably can also have the function that a high-level potential is output from terminal LO3 and a low-level potential is output from terminal LO4. In addition, when a high-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, Figure 11A the circuit LGC desirably can also have the function that a low-level potential is output from terminal LO3 and a high-level potential is output from terminal LO4. In addition, when a low-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT,

[0306] In addition, Figure 11A the circuit LGC of the storage circuit RESD1 of Figure 6AThe circuit LGC of the storage circuit RESA has the same structure. For example, in Figure 6A the circuit LGC of the storage circuit RESA, a terminal LO3 is provided so as to be electrically connected to the second terminal of the transistor MN1 and the first terminal of the transistor MN2, and a terminal LO4 is provided so as to be electrically connected to the gate of the transistor MN2, the second terminal of the transistor MN3, the first terminal of the transistor MN4, and the first terminal of the capacitor C5.

[0307] As an example, similar to Figure 6A the terminals CLK2 and PWC of the storage circuit RESA, both the terminal CLK2 and the terminal PWC are terminals corresponding to Figure 3 the second input terminal of the storage circuit RES. In addition, the terminal CLK5 is also a terminal corresponding to Figure 3 the second input terminal of the storage circuit RES. Therefore, Figure 3 the wiring CLS shown in

[0308] As an example, similar to Figure 6A the terminal OT of the storage circuit RESA, the terminal OT corresponds to Figure 3 the first output terminal of the storage circuit RES. As an example, similar to Figure 6A the terminal GT of the storage circuit RESA, the terminal GT is a terminal corresponding to Figure 3 the second output terminal of the storage circuit RES.

[0309] As an example, both the wiring VSE21 and the wiring VSE22 are used as wirings for supplying a fixed potential. This fixed potential can be, for example, a low-level potential. The wiring VSE21 and the wiring VSE22 can be supplied with equal fixed potentials or unequal fixed potentials. In addition, when the wiring VSE21 and the wiring VSE22 are supplied with equal fixed potentials, the wiring VSE1 and the wiring VSE2 can also be the same wiring.

[0310] Here, consider Figure 11A the operation method of the storage circuit RESD1 shown in

[0311] A start pulse signal from the wiring SP or a signal from the terminal OT of the previous-stage storage circuit RESD1 is input to the terminal IT of the storage circuit RESD1. In addition, the high-potential side of these signals is the high-level potential V H , and the low-potential side is the low-level potential V L . In addition, the voltage amplitude of these signals at this time is V H - V L .

[0312] The clock signals are respectively input to the terminals CLK2 and CLK5 of the storage circuit RESD1. In addition, the high-potential side and the low-potential side of each clock signal are respectively set to the high-level potential V H and the low-level potential V L . In other words, the potential difference between the high-potential side and the low-potential side of this clock signal becomes V H -V L .

[0313] In addition, the wirings VSE21 and VSE22 are used as the wirings for supplying the low-level potential V L to the storage circuit RESD1.

[0314] The clock signal is supplied to the terminal PWC of the storage circuit RESD1. In addition, the potential difference between the high-potential side and the low-potential side of the clock signal supplied to the terminal PWC is higher than the potential difference V H -V L between the high-potential side and the low-potential side of the clock signal supplied to the terminals CLK2 and CLK5.

[0315] For example, the high-potential side of the clock signal supplied to the terminal PWC can also be set to be higher than V H by V EXH , the low-potential side is set to V L , and the potential difference between the high-potential side and the low-potential side of this clock signal is set to V EXH -V L . In addition, hereinafter, the high-potential side of the clock signal supplied to the terminal PWC is set to V EXH and the low-potential side is set to V L for description.

[0316] As described above, in the circuit LGC, during the period when the high-level potential V H is output from the terminal LO1 and the low-level potential V L is output from the terminal LO2, when the high-potential side V EXH of the clock signal is input to the terminal PWC, the potential output from the terminal GT of the storage circuit RESD1 is the potential obtained by subtracting the threshold voltage of the transistor MNC1 from V EXH . In addition, then when the terminal PWC changes from the high-potential side V EXH of the clock signal to the low-potential side V L , V L is output from the terminal GT of the storage circuit RESD1.

[0317] In addition, in the circuit LGC, during the period when the low-level potential V L is output from the terminal LO1 and the high-level potential VH During this period, the transistor MNC1 becomes in the off state, and the transistor MNC2 becomes in the on state. Therefore, V is output from the terminal GT of the storage circuit RESD1. L .

[0318] As described above, sometimes V higher than V is output from the terminal GT of the storage circuit RESD1. H of V EXH , so it is preferable that the transistors MNC1 and MNC2 use transistors with high voltage tolerance. That is, it is preferable that the transistors MNC1 and MNC2 use the transistor MTCK with a relatively thick gate insulating film described in Embodiment 1.

[0319] In addition, in the circuit LGC, during the period when a high-level potential V is output from the terminal LO3 H and a low-level potential V is output from the terminal LO4 L , when a high-potential side V of the clock signal is input to the terminal CLK5 H , a potential obtained by subtracting the threshold voltage of the transistor MNH1 from V is output from the terminal OT of the storage circuit RESD1. Further, then, when the terminal CLK5 changes from the high-potential side V of the clock signal H to the low-potential side V H , V is output from the terminal OT of the storage circuit RESD1. L L .

[0320] In addition, in the circuit LGC, during the period when a low-level potential V is output from the terminal LO3 L and a high-level potential V is output from the terminal LO4 H , the transistor MNH1 becomes in the off state, and the transistor MNH2 becomes in the on state. Therefore, V is output from the terminal OT of the storage circuit RESD1. L .

[0321] As described above, sometimes V is output as a high-level potential from the terminal OT of the storage circuit RESD1. H . Since V H is a potential lower than V EXH , transistors with lower voltage tolerance than the transistor MTCK can be used as the transistors MNH1 and MNH2. In addition, since the shift register SR including the storage circuit RESD1 preferably has a high driving speed, it is preferable that the transistors MNH1 and MNH2 use transistors with a high driving frequency. That is, it is preferable that the transistors MNH1 and MNH2 use the transistor MTHN with a relatively thin gate insulating film described in Embodiment 1.

[0322] In addition, the transistors included in the circuit LGC of the storage circuit RESD1 may also use the transistor MTHN with a thinner gate insulating film described in Embodiment 1. Thereby, the operating speed of the circuit LGC can be increased.

[0323] By adopting Figure 11A the circuit structure of the storage circuit RESD1, and using the transistor MTCK described in Embodiment 1 for the transistor MNC1 and the transistor MNC2, a potential higher than the high-level potential V H can be output from the terminal GT of the storage circuit RESD1. EXH In addition, by using the transistor MTHN described in Embodiment 1 for the transistors included in the circuit LGC, the transistor MNH1, and the transistor MNH2, the operating speed of the circuit LGC and the driving frequency of the transistor MNH1 and the transistor MNH2 can be increased.

[0324] By using Figure 11A the storage circuit RESD1 for Figure 3 the storage circuit RES included in the shift register SR, the high-potential side of the signal output from the second output terminal of the storage circuit RES can be set to be higher than V H by EXH . Thereby, for Figure 3 the enable input terminals of the multiple first latch circuits LA included in the holding circuit LTC1, V EXH is input. That is, a voltage (the potential difference between the high potential and the low potential of the signal) of a signal higher than V H - V L is input to the enable input terminals, whereby the first latch circuits can easily receive the image signal transmitted from the wiring VIS. EXH - V L

[0325] In addition, the structure of the storage circuit RES of the semiconductor device according to one aspect of the present invention is not limited to Figure 11A the storage circuit RESD1. The structure of the storage circuit RES of the semiconductor device according to one aspect of the present invention may also be a structure obtained by changing Figure 11A the storage circuit RESD1 according to circumstances.

[0326] <<Example 7 of the Structure of the Storage Circuit RES>> Figure 11B The storage circuit RESD2 shown in Figure 11A is a modified example of the storage circuit RESD1, and is different from the storage circuit RESD1 in that the transistors MNH1 and MNH2 are not provided; and the terminal OT is electrically connected to the terminal GT.

[0327] InFigure 11B In the storage circuit RESD2, the circuit OPC includes the transistor MNC1 and the transistor MNC2.

[0328] The circuit LGC includes the terminal LI, the terminal LO1, and the terminal LO2.

[0329] The first terminal of the transistor MNC1 is electrically connected to the terminal PWC, the second terminal of the transistor MNC1 is electrically connected to the first terminal of the transistor MNC2, the terminal GT, and the terminal OT, and the gate of the transistor MNC1 is electrically connected to the terminal LO1. In addition, the second terminal of the transistor MNC2 is electrically connected to the wiring VSE22, and the gate of the transistor MNC2 is electrically connected to the terminal LO2.

[0330] And Figure 6A Similar to the circuit LGC of the storage circuit RESA, Figure 11B The circuit LGC of the storage circuit RESD2 has the following function: when the low-level potential is input to the terminal CLK2 and the high-level potential is input to the terminal IT, it is desirable that the high-level potential is output from the terminal LO1 and the low-level potential is output from the terminal LO2. In addition, when the high-level potential is input to the terminal CLK2 and the low-level potential is input to the terminal IT, Figure 11A The circuit LGC has the function of preferably outputting the low-level potential from the terminal LO1 and the high-level potential from the terminal LO2. In addition, when the low-level potential is input to the terminal CLK2 and the low-level potential is input to the terminal IT, Figure 11A The circuit LGC has the function of maintaining the potential of the terminal LO1 and maintaining the potential of the terminal LO2.

[0331] In Figure 11B the storage circuit RESD2, similar to Figure 11A the storage circuit RESD1, the potential difference between the high-potential side and the low-potential side supplied to the terminal PWC becomes V EXH -V L of the clock signal. In addition, the wiring VSE22 is used as the wiring for supplying the low-level potential V L to the storage circuit RESD2.

[0332] As described above, similar to Figure 11A the storage circuit RESD1, in Figure 11B the storage circuit RESD2, the high-potential side of the signal output from the terminal GT is V EXH , and the low-potential side is V L . Furthermore, the high-potential side of the signal output from the terminal OT also becomes V EXH , and the low-potential side becomes V L .

[0333] By Figure 11BThe storage circuit RESD2 is used for Figure 3 For the storage circuit RES, except for the signal output from the second output terminal of the storage circuit RES, the high potential side of the signal output from the first output terminal can also be set to be higher than V H of V EXH . That is, it is also possible to send a signal with the high potential side being V EXH and the low potential side being V L to the first input terminal of the subsequent storage circuit electrically connected to the first output terminal of the storage circuit RES.

[0334] <<Example 8 of the structure of the storage circuit RES>> Figure 12A The storage circuit RESD3 shown is Figure 11A a modified example of the storage circuit RESD1. The difference from the storage circuit RESD1 is that: a transistor MNC3, a transistor MNH3, a capacitor CPW, and a capacitor CCL are also provided; and terminals LO3 and LO4 are not provided in the circuit LGC.

[0335] In Figure 12A the storage circuit RESD3, the circuit OPC includes a transistor MNC1, a transistor MNC2, a transistor MNC3, a transistor MNH1, a transistor MNH2, a transistor MNH3, a capacitor CPW, and a capacitor CCL.

[0336] The first terminal of the transistor MNC3 is electrically connected to the first terminal of the transistor MNH3 and the terminal LO1. The gate of the transistor MNC2 is electrically connected to the gate of the transistor MNH2 and the terminal LO2. The second terminal of the transistor MNC3 is electrically connected to the gate of the transistor MNC1 and the first terminal of the capacitor CPW, and the gate of the transistor MNC3 is electrically connected to the wiring VDE12. The first terminal of the transistor MNC1 is electrically connected to the terminal PWC, and the second terminal of the transistor MNC1 is electrically connected to the first terminal of the transistor MNC2, the second terminal of the capacitor CPW, and the terminal GT. The second terminal of the transistor MNC2 is electrically connected to the wiring VSE22. The second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1 and the first terminal of the capacitor CCL, and the gate of the transistor MNH3 is electrically connected to the wiring VDE11. The first terminal of the transistor MNH1 is electrically connected to the terminal CLK5, and the second terminal of the transistor MNH1 is electrically connected to the first terminal of the transistor MNH2, the second terminal of the capacitor CCL, and the terminal OT. The second terminal of the transistor MNH2 is electrically connected to the wiring VSE21.

[0337] Regarding Figure 12A the circuit LGC, reference can be made to Figure 11B the description of the circuit LGC.

[0338] Regarding Figure 12A For the terminal CLK5 and the terminal PWC shown, reference can be made to Figure 11B the description of the terminal CLK5 and the terminal PWC of the storage circuit RESD2 in

[0339] As an example, both the wiring VDE11 and the wiring VDE12 are used as wirings for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. The wiring VDE11 and the wiring VDE12 can be supplied with equal fixed potentials to each other, or can be supplied with unequal fixed potentials to each other. In addition, when the wiring VDE11 and the wiring VDE12 are supplied with equal fixed potentials to each other, the wiring VDE11 and the wiring VDE12 can also be the same wiring. Further, here, both the wiring VDE11 and the wiring VDE12 are wirings for supplying a high-level potential V H as

[0340] Next, an example of the operation of the connection structure of the transistors MNC1 to MNC3 and the capacitor CPW will be described.

[0341] First, consider the case where a low-level potential V L is input from the terminal LO1 to the first terminal of the transistor MNC3 H and a high-level potential V H is input from the terminal LO2 to the gate of the transistor MNC2. At this time, the gate of the transistor MNC3 is input with the high-level potential V L , so the transistor MNC3 becomes an on state, and the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW become V H . On the other hand, the second terminal of the transistor MNC2 is input with the high-level potential V L , so the transistor MNC2 becomes an on state, and V

[0342] is output from the terminal GT. When the potential input from the terminal LO1 to the first terminal of the transistor MNC3 changes from V L to V H , the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW rise from V L to V H -V th_MNC3 , and the transistor MNC3 becomes an off state. In addition, V th_MNC3 is the threshold voltage of the transistor MNC3. When the potential input from the terminal LO2 to the gate of the transistor MNC2 changes from V

[0343] to V H to V LWhen the transistor MNC2 is turned off, the potential of the terminal GT remains at V L .

[0344] Here, consider the case where the low-level potential V L is input from the terminal PWC to the first terminal of the transistor MNC1. At this time, the potential of the gate of the transistor MNC1 is V H -V th_MNC3 , and the potential of the second terminal of the transistor MNC1 is V L , so the potential of the terminal GT remains at V L .

[0345] When the potential input from the terminal PWC to the first terminal of the transistor MNC1 changes from V L to V EXH , the potential of the second terminal (terminal GT) of the transistor MNC1 rises from V L . At this time, the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW are in a floating state. Therefore, when the potential of the second terminal (terminal GT) of the capacitor CPW rises, due to the capacitive coupling of the capacitor CPW, the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW also rise. Thus, even when the potential of the terminal GT rises, the gate-source voltage of the transistor MNC1 does not change. Therefore, current continues to flow between the first terminal and the second terminal of the transistor MNC1 until the potential of the terminal GT reaches V EXH .

[0346] In this way, by using the capacitive coupling of the capacitor CPW, the potential of the gate of the transistor MNC3 can be raised. In this specification and the like, the following situation is called bootstrapping: using capacitive coupling to raise the gate potential as the potential of the first terminal or the second terminal of the transistor rises.

[0347] In addition, when the gate capacitance between the gate of the transistor MNC1 and the channel formation region (which may include one or both of the first terminal and the second terminal depending on the situation) is large, a structure in which the capacitor CPW is not provided in the circuit OPC can be adopted. At this time, the circuit area of the circuit OPC can be reduced.

[0348] Similar to the connection structure of the transistors MNC1 to MNC3 and the capacitor CPW, regarding the connection structure of the transistors MNH1 to MNH3 and the capacitor CCL, by using the bootstrapping of the capacitor CCL, the high-level potential V H on the high-potential side of the signal flowing through the terminal CLK5 can be output to the terminal OT.

[0349] As described above, the potential V of the second terminal of the transistor MNC3H -V th_MNC3 Sometimes, due to the bootstrap using the capacitor CPW, a voltage higher than V H is applied to V EXH . Therefore, the transistor MNC3 preferably uses a transistor with high voltage tolerance. That is, the transistor MNC3 preferably uses the transistor MTCK with a thicker gate insulating film described in Embodiment 1.

[0350] The driving speed of the shift register SR including the storage circuit RESD3 is preferably fast. Therefore, as the transistor MNH3, a transistor with a high driving frequency is preferably used. That is, the transistor MNH3 preferably uses the transistor MTHN with a thinner gate insulating film described in Embodiment 1.

[0351] The second terminal of the transistor MNH3 is sometimes applied with a voltage higher than V H due to the bootstrap using the capacitor CCL. Therefore, the transistor MNH3 can also use a transistor with high voltage tolerance. That is, the transistor MNH3 can also use the transistor MTCK with a thicker gate insulating film described in Embodiment 1.

[0352] Regarding the transistors MNH1, MNH2, MNC1, and MNC2, reference can be made to the description of each of the transistors MNH1, MNH2, MNC1, and MNC2 included in the storage circuit RESD1 of FIG. 11.

[0353] Figure 12A The storage circuit RESD3 of Figure 12B can also be changed to the structure of the storage circuit RESD4 shown in Figure 12B The storage circuit RESD4 of Figure 12A has a structure in which the transistors MNH3 and MNC3 in the circuit OPC of the storage circuit RESD3 of

[0354] Specifically, in the circuit OPC of the storage circuit RESD4 of Figure 12B , the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitor CCL, the gate of the transistor MNC1, and the first terminal of the capacitor CPW.

[0355] Similar to the storage circuit RESD3 of Figure 12A , the storage circuit RESD4 of Figure 12B can increase the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW and can increase the potential of the gate of the transistor MNH1 by using the bootstrap of the capacitor CCL.

[0356] Figure 12A The storage circuit RESD3 can also be changed to Figure 13 the structure of the storage circuit RESD5 shown. Figure 13 The storage circuit RESD5 shown has a combination Figure 12A of the terminals OT and GT of the storage circuit RESD3.

[0357] Specifically, compared with Figure 12A the storage circuit RESD3, in Figure 13 the storage circuit RESD5, the transistors MNH1 to MNH3 and the capacitor CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitor CPW, and the first terminal of the transistor MNC2.

[0358] Similar to Figure 12A the storage circuit RESD3, Figure 13 the storage circuit RESD5 can boost the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW. In addition, similar to Figure 11B the storage circuit RESD2, Figure 13 the storage circuit RESD5 can set the high-potential side of the signal output from the terminal OT to be higher than the high-level potential V H of V EXH and set the low-potential side to V L .

[0359] <<Example 9 of the structure of the storage circuit RES>> Figure 14A The storage circuit RESD6 shown is Figure 12A a modified example of the storage circuit RESD3, and is different from the storage circuit RESD3 in that: the gate of the transistor MNC3 is not electrically connected to the wiring VDE12 but is electrically connected to the first terminal of the transistor MNC3; and the gate of the transistor MNH3 is not electrically connected to the wiring VDE11 but is electrically connected to the first terminal of the transistor MNH3.

[0360] In Figure 14A , since the first terminal of the transistor MNC3 is electrically connected to the gate of the transistor MNC3, it can be said that the transistor MNC3 is diode-connected. Therefore, for example, when the high-level potential V H is input from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3, the potential of each of the first terminal and the gate of the transistor MNC3 becomes the high-level potential V H , so that the potential of the second terminal of the transistor MNC3, the gate of the transistor MNC3, and the first terminal of the capacitor CPW becomes V H - V th_MNC3 .

[0361] When the potential at the second terminal of transistor MNC3 reaches V H -V th_MNC3 , transistor MNC3 turns off. Thus, the electrical connection point of the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitor CPW becomes floating. Therefore, by using the bootstrap of capacitor CPW, the potential V H -V th_MNC3 of the gate of transistor MNC1 can be further increased. In addition, even if the potential of the gate of transistor MNC1 (the potential of the second terminal of transistor MNC3) becomes high, transistor MNC3 does not turn on.

[0362] In addition, when it is desired to lower the potential (the potential of the gate of transistor MNC1) V High -V th_MNC3 at the first terminal of capacitor CPW, in other words, when it is desired to discharge the charge stored in the first terminal of capacitor CPW (or the gate of transistor MNC1), the circuit OPC of Figure 14A needs to be further modified.

[0363] Similarly, in Figure 14A , the first terminal of transistor MNH3 is electrically connected to the gate of transistor MNH3. Thus, it can be said that transistor MNH3 is diode-connected. Therefore, for example, when a high-level potential V H is input from the terminal LO1 of circuit LGC to the first terminal of transistor MNH3, the potential of each of the first terminal and the gate of transistor MNH3 becomes the high-level potential V H , and thus the potential of the second terminal of transistor MNH3, the gate of transistor MNH3, and the first terminal of capacitor CCL becomes V H -V th_MNH3 .

[0364] When the potential at the second terminal of transistor MNH3 reaches V H -V th_MNH3 , transistor MNH3 turns off. Thus, the electrical connection point of the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitor CCL becomes floating. Therefore, by using the bootstrap of capacitor CCL, the potential V H -V th_MNC3 of the gate of transistor MNH1 can be further increased. In addition, even if the potential of the gate of transistor MNH1 (the potential of the second terminal of transistor MNH3) becomes high, transistor MNH3 does not turn on.

[0365] In addition, when it is desired to lower the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) V High -V th_MNH3 in other words, when it is desired to discharge the charge stored in the first terminal of the capacitor CCL (or the gate of the transistor MNH1), it is necessary to further modify the Figure 14A circuit OPC.

[0366] Figure 14B The circuit OPC of the storage circuit RESD6A shown in Figure 14A is a modified example of the circuit OPC of the storage circuit RESD6 of Figure 14A and is different from the circuit OPC of the storage circuit RESD6 of Figure 14A in that it has a structure capable of discharging the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1) and the first terminal of the capacitor CCL (or the gate of the transistor MNH1). Specifically, Figure 14B the circuit OPC of the storage circuit RESD6A shown in Figure 14A is different from the circuit OPC of the storage circuit RESD6 of Figure 14B in that the circuit OPC of the storage circuit RESD6A shown in Figure 14B includes the transistors MNC4 and MNH4.

[0367] The first terminal of the transistor MNC4 is electrically connected to the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW. The second terminal of the transistor MNC4 is electrically connected to the wiring VSE23. The gate of the transistor MNC4 is electrically connected to the wiring RS1. In addition, the first terminal of the transistor MNC4 is electrically connected to the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL. The second terminal of the transistor MNH4 is electrically connected to the wiring VSE24. The gate of the transistor MNH4 is electrically connected to the wiring RS2.

[0368] The wiring VSE23 and the wiring VSE24 are used as wirings for supplying a fixed potential, for example, in the same manner as the wiring VSE21 or the wiring VSE22. In addition, as the fixed potential, for example, a low-level potential can be cited. As other fixed potentials, a ground potential or a negative potential can be cited. In addition, depending on the situation, the wiring VSE23 and the wiring VSE24 can also be used as wirings for supplying a variable potential.

[0369] Note that here, the wiring VSE23 and the wiring VSE24 are used as wirings for supplying the low-level potential V L .

[0370] The wiring RS1 is used, for example, as a wiring for transmitting a signal for selecting whether to release the charge stored in the first terminal of the capacitor CCL (or the gate of the transistor MNH1). Specifically, for example, when the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) is not released, a low-level potential V is supplied to the wiring RS1 as a signal L to turn off the transistor MNH4. In addition, for example, when the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) is released, a high-level potential V is supplied to the wiring RS1 as a signal H to turn on the transistor MNH4

[0371] For example, when it is desired to increase the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) (when it is desired to make this potential V H -V th_MNH3 In addition, V th_MNH3 is the threshold voltage of the transistor MNH3), a low-level potential V is supplied to the wiring RS1 L to turn off the transistor MNH3, and then a high-level potential V is supplied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3 H In addition, when it is desired to decrease the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) (when it is desired to make this potential V L In this case), after the low-level potential V L is supplied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3 to turn off the transistor MNH3, a high-level potential V is supplied to the wiring RS1 H to turn on the transistor MNH4. Here, when the potential supplied to the wiring VSE23 is the low-level potential V L the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) flows through the wiring VSE23, and as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes V L .

[0372] Similarly, the wiring RS2 is used, for example, as a wiring for transmitting a signal for selecting whether to release the charge stored in the first terminal of the capacitor CPW (the gate of the transistor MNC1). Specifically, for example, when the charge of the first terminal of the capacitor CPW (or the gate of the transistor MNC1) is not released, a low-level potential V is supplied to the wiring RS2 as a signal LTurn off the transistor MNC4. Additionally, for example, in the case of discharging the charge of the first terminal of the capacitor CPW (or the gate of the transistor MNC1), supply a high-level potential V to the wiring RS2 as a signal. H Just turn on the transistor MNC4.

[0373] For example, when it is desired to increase the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) (when it is desired to make this potential V H -V th_MNC3 ), supply a low-level potential V to the wiring RS2. L After turning off the transistor MNC3, supply the high-level potential V H from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3. Additionally, when it is desired to decrease the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) (when it is desired to make this potential V L ), supply the low-level potential V L from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 to turn off the transistor MNC3, and then supply a high-level potential V to the wiring RS2. H Just turn on the transistor MNC4. Here, when the potential supplied by the wiring VSE24 is the low-level potential V L , the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNC1) flows through the wiring VSE24. As a result, the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) becomes V L .

[0374] The transistor MNC4 can use, for example, the transistor MTCK described in the above Embodiment 1. Additionally, the transistor MNH4 can use, for example, the transistor MTHN described in the above Embodiment 1. Additionally, depending on the situation, the transistor MNC4 can also use, for example, the transistor MTHN described in the above Embodiment 1, and the transistor MNH4 can also use, for example, the transistor MTCK described in the above Embodiment 1.

[0375] Figure 14A The storage circuit RESD6 of Figure 15A can also be changed to the structure of the storage circuit RESD7 shown in Figure 12B . Similar to the storage circuit RESD4 of Figure 15A , the storage circuit RESD7 of Figure 14A has a structure in which the transistors MNH3 and MNC3 in the circuit OPC of the storage circuit RESD6 of

[0376] Specifically, in Figure 15A the circuit OPC of the storage circuit RESD7, the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitor CCL, the gate of the transistor MNC1, and the first terminal of the capacitor CPW.

[0377] Similar to Figure 14A the storage circuit RESD6, in Figure 15A the storage circuit RESD7, the transistor MNH3 has a diode-connected structure, and can supply a potential V obtained by subtracting the threshold voltage of the transistor MNC1 from the high-level potential output from the terminal LO1 of the slave circuit LGC to the gates of the transistor MNH1 and the transistor MNC1. H -V th_MNH3 In addition, Figure 15A the storage circuit RESD7 can increase the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW and can increase the potential of the gate of the transistor MNH1 by using the bootstrap of the capacitor CCL.

[0378] Figure 15A When the storage circuit RESD7 wants to reduce the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) and the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1), in other words, when it wants to release the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1) and the first terminal of the capacitor CCL (or the gate of the transistor MNH1), similar to Figure 14A the storage circuit RESD6, it is necessary to further change Figure 15A the circuit OPC.

[0379] Figure 15B The circuit OPC of the storage circuit RESD7A shown is Figure 15A a modified example of the circuit OPC of the storage circuit RESD7, and is different from Figure 15A the circuit OPC of the storage circuit RESD7 in that: it has a structure capable of releasing the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1) and the first terminal of the capacitor CCL (or the gate of the transistor MNH1). Specifically, Figure 15B the circuit OPC of the storage circuit RESD7A shown is different from Figure 15A the circuit OPC of the storage circuit RESD7 in that Figure 15B the circuit OPC of the storage circuit RESD7A shown includes the transistor MNH4.

[0380] The first terminal of transistor MNH4 is electrically connected to the gate of transistor MNC1, the first terminal of capacitor CPW, the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitor CCL. The second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1.

[0381] Regarding wiring RS1 and wiring VSE23, reference can be made to Figure 14B the descriptions of wiring RS1 and wiring VSE23 shown.

[0382] Regarding Figure 15B the operation example of storage circuit RESD7A, reference can be made to Figure 14B the description of the operation example of storage circuit RESD6A.

[0383] Figure 14A The storage circuit RESD6 of Figure 16 can also be changed to the structure of storage circuit RESD8A shown. Figure 16 The storage circuit RESD8A shown has a structure that combines Figure 14B the terminals OT and GT of storage circuit RESD6A.

[0384] Specifically, compared with Figure 14B the storage circuit RESD6A of Figure 16 in the storage circuit RESD8A of

[0385] Transistors MNH1 to MNH4 and capacitor CCL are not provided, and terminal OT is electrically connected to terminal GT, the second terminal of transistor MNC1, the second terminal of capacitor CPW, and the first terminal of transistor MNC2.

[0385] Similar to Figure 13 the storage circuit RESD5 of Figure 16 the storage circuit RESD8A of Figure 13 can increase the potential of the gate of transistor MNC1 by using the bootstrap of capacitor CPW. In addition, similar to Figure 13 the storage circuit RESD5 of Figure 16 the storage circuit RESD8A of H can set the high potential side of the signal output from terminal OT to be higher than the high level potential V EXH and set the low potential side to V L .

[0386] <<Structural Example 10 of Storage Circuit RES>> Figure 17A The storage circuit RESD9 shown is Figure 12AA modified example of the storage circuit RESD3, which is different from the storage circuit RESD3 in that: the gate of the transistor MNC3 is not electrically connected to the wiring VDE12 but to the terminal LO1 of the circuit LGC; the first terminal of the transistor MNC3 is electrically connected to the wiring VDE14; the gate of the transistor MNH3 is not electrically connected to the wiring VDE11 but to the terminal LO1 of the circuit LGC; and the first terminal of the transistor MNH3 is electrically connected to the wiring VDE13.

[0387] As an example, both the wiring VDE13 and the wiring VDE14 are used as wirings for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. The wiring VDE13 and the wiring VDE14 can be supplied with equal fixed potentials to each other, or can be supplied with unequal fixed potentials to each other. In addition, when the wiring VDE13 and the wiring VDE14 are supplied with equal fixed potentials to each other, the wiring VDE13 and the wiring VDE14 can also be the same wiring. Also, here, both the wiring VDE13 and the wiring VDE14 are wirings for supplying a high-level potential V H of.

[0388] For Figure 17A a working example of the storage circuit RESD9 is described. For example, a high-level potential V H is input from the terminal LO1 of the circuit LGC to the gate of the transistor MNH3 and the gate of the transistor MNC3. In addition, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) and the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) are low-level potential V L .

[0389] The gate-source voltage of the transistor MNH3 (the voltage between the gate and the second terminal at this timing) becomes V H -V L , so the transistor MNH3 becomes in an on state. Therefore, current flows from the wiring VDE13 through the transistor MNH3 to the first terminal of the capacitor CCL (or the gate of the transistor MNH1), and charges are stored in the first terminal of the capacitor CCL until the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) rises until the transistor MNH3 becomes in an off state. Specifically, the transistor MNH3 becomes in an off state when the gate-source voltage of the transistor MNH3 drops to V th_MNH3 , so the potential of the first terminal of the capacitor CCL1 (the potential of the second terminal of the transistor MNH3) becomes V H -V th_MNH3 .

[0390] Similarly, the voltage between the gate and source of transistor MNC3 (the voltage between the gate and the second terminal at this timing) becomes V H -V L , so transistor MNC3 turns on. Therefore, current flows from wiring VDE14 through transistor MNC3 to the first terminal of capacitor CPW (or the gate of transistor MNC1), and charges are stored in the first terminal of capacitor CPW until the potential of the first terminal of capacitor CPW (the potential of the gate of transistor MNC1) rises until transistor MNC3 turns off. Specifically, transistor MNC3 turns off when the voltage between the gate and source of transistor MNC3 drops to V th_MNC3 . At this time, the potential of the first terminal of capacitor CPW1 (the potential of the second terminal of transistor MNC3) becomes V H -V th_MNC3 .

[0391] When the potential of the second terminal of transistor MNH3 reaches V H -V th_MNH3 , transistor MNH3 turns off. Therefore, the electrical connection point of the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitor CCL becomes floating. Then, the low-level potential V L is supplied from terminal LO1 of circuit LGC to each of the gates of transistor MNH3. Then, by supplying V H from terminal CLK5 to the first terminal of transistor MNH1, and by using the bootstrap of capacitor CCL, the potential V H -V th_MNH3 of the gate of transistor MNH1 can be further increased. In addition, even if the potential of the gate of transistor MNH1 (the potential of the second terminal of transistor MNH3) becomes high, transistor MNH3 does not turn on.

[0392] Similarly, when the potential of the second terminal of transistor MNC3 reaches V H -V th_MNC3 , transistor MNC3 turns off. Therefore, the electrical connection point of the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitor CPW becomes floating. Then, the low-level potential V L is supplied from terminal LO1 of circuit LGC to each of the gates of transistor MNC3. Then, by supplying V EXH from terminal PWC to the first terminal of transistor MNC1, and by using the bootstrap of capacitor CPW, the potential V H -V th_MNC3In addition, even if the potential of the gate of transistor MNC1 (the potential of the second terminal of transistor MNC3) becomes high, transistor MNC3 does not turn on.

[0393] In addition, when it is desired to lower the potential V of the first terminal of capacitor CCL (the gate of transistor MNH1) H -V th_MNH3 that is, when it is desired to discharge the charge stored in the first terminal of capacitor CCL (or the gate of transistor MNH1), it is necessary to further modify the circuit OPC of the storage circuit RESD9 of Figure 17A Similarly, when it is desired to lower the potential V of the first terminal of capacitor CPW (the potential of the gate of transistor MNC1) H -V th_MNH3 that is, when it is desired to discharge the charge stored in the first terminal of capacitor CPW (or the gate of transistor MNC1), it is necessary to further modify the circuit OPC of the storage circuit RESD9 of Figure 17A The circuit OPC of the storage circuit RESD9A shown in

[0394] Figure 17B is a modified example of the circuit OPC of the storage circuit RESD9 of Figure 17A and is different from the circuit OPC of the storage circuit RESD9 of Figure 17A in that it has a structure capable of discharging the charge stored in the first terminal of capacitor CPW (or the gate of transistor MNC1); a structure capable of discharging the charge stored in the first terminal of capacitor CCL (or the gate of transistor MNH1). Specifically, Figure 17B the circuit OPC of the storage circuit RESD9A shown in Figure 17A is different from the circuit OPC of the storage circuit RESD9 of Figure 17B in that the circuit OPC of the storage circuit RESD9A shown in

[0395] includes transistor MNC4 and transistor MNH4. The first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitor CPW. The second terminal of transistor MNC4 is electrically connected to wiring VSE23, and the gate of transistor MNC4 is electrically connected to wiring RS1. In addition, the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitor CCL. The second terminal of transistor MNH4 is electrically connected to wiring VSE24, and the gate of transistor MNH4 is electrically connected to wiring RS2.

[0396] Regarding wiring VSE23 and wiring VSE24, reference can be made toFigure 14B Description of wirings VSE23 and VSE24 of storage circuit RESD6A. Similarly, regarding wirings RS1 and RS2, reference can be made to Figure 14B Description of wirings RS1 and RS2 of storage circuit RESD6A. In addition, regarding transistors MNH4 and MNC4, reference can also be made to Figure 14B Description of transistors MNH4 and MNC4 of storage circuit RESD6A.

[0397] When it is desired to lower the potential of the first terminal of capacitor CCL (the potential of the gate of transistor MNH1) (when it is desired to make this potential V L ), for example, a low-level potential V is supplied from terminal LO1 of circuit LGC to the first terminal of transistor MNH3 L After turning off transistor MNH3, a high-level potential V is supplied to wiring RS1 H It is only necessary to turn on transistor MNH4. Here, when the potential supplied to wiring VSE23 is the low-level potential V L , the charge at the first terminal of capacitor CCL (the charge at the gate of transistor MNH1) flows through wiring VSE23. As a result, the potential at the first terminal of capacitor CCL (the potential at the gate of transistor MNH1) becomes V L .

[0398] When it is desired to lower the potential of the first terminal of capacitor CPW (the potential of the gate of transistor MNC1) (when it is desired to make this potential V L ), for example, a low-level potential V is supplied from terminal LO1 of circuit LGC to the first terminal of transistor MNC3 L After turning off transistor MNC3, a high-level potential V is supplied to wiring RS2 H It is only necessary to turn on transistor MNC4. Here, when the potential supplied to wiring VSE24 is the low-level potential V L , the charge at the first terminal of capacitor CCL (the charge at the gate of transistor MNC1) flows through wiring VSE24. As a result, the potential at the first terminal of capacitor CPW (the potential at the gate of transistor MNC1) becomes V L .

[0399] Figure 16 The storage circuit RESD9 can also be changed to Figure 18A the structure of the storage circuit RESD10 shown. Similar to Figure 12B the storage circuit RESD4 and Figure 15A the storage circuit RESD7, Figure 18AThe storage circuit RESD10 has Figure 14A a structure in which the transistors MNH3 and MNC3 in the circuit OPC of the storage circuit RESD9 are combined into the transistor MNH3.

[0400] Specifically, in Figure 18A the circuit OPC of the storage circuit RESD10, the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitor CCL, the gate of the transistor MNC1, and the first terminal of the capacitor CPW.

[0401] Similar to Figure 17A the storage circuit RESD9, in Figure 18A the storage circuit RESD10, the gate of the transistor MNH3 is electrically connected to the terminal LO1 of the circuit LGC, and a potential V H -V th_MNH3 is supplied to the gates of the transistor MNH1 and the transistor MNC1 as a potential obtained by subtracting the threshold voltage of the transistor MNH3 from the wiring VDE13. In addition, Figure 18A the storage circuit RESD10 can increase the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW and can increase the potential of the gate of the transistor MNH1 by using the bootstrap of the capacitor CCL.

[0402] Figure 18A When the storage circuit RESD10 wants to reduce the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) and the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1), in other words, when it wants to release the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1) and the first terminal of the capacitor CCL (or the gate of the transistor MNH1), similar to Figure 17A the storage circuit RESD9, it is necessary to further change Figure 18A the circuit OPC.

[0403] Figure 18B The circuit OPC of the storage circuit RESD10A shown is Figure 18A a modified example of the circuit OPC of the storage circuit RESD10, and is different from Figure 18A the circuit OPC of the storage circuit RESD10 in that it has a structure capable of releasing the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1) and the first terminal of the capacitor CCL (or the gate of the transistor MNH1). Specifically, Figure 18B the circuit OPC of the storage circuit RESD10A shown is different from Figure 18A the circuit OPC of the storage circuit RESD10 in thatFigure 18B The circuit OPC of the storage circuit RESD10A shown includes a transistor MNH4.

[0404] The first terminal of the transistor MNH4 is electrically connected to the gate of the transistor MNC1, the first terminal of the capacitor CPW, the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL. The second terminal of the transistor MNH4 is electrically connected to the wiring VSE23, and the gate of the transistor MNH4 is electrically connected to the wiring RS1.

[0405] Regarding the wiring RS1 and the wiring VSE23, reference can be made to Figure 17B the description of the wiring RS1 and the wiring VSE23 shown.

[0406] Regarding Figure 18B the operation example of the storage circuit RESD10A, reference can be made to Figure 17B the description of the operation example of the storage circuit RESD9A.

[0407] Figure 17A The storage circuit RESD9 can also be changed to Figure 19 the structure of the storage circuit RESD11 shown. The storage circuit RESD11 shown in Fig. 19 has a structure that combines ​ the terminals OT and GT of the storage circuit RESD9.

[0408] Specifically, compared with ​ the storage circuit RESD9, in ​ the storage circuit RESD11, the transistors MNH1 to MNH4 and the capacitor CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitor CPW, and the first terminal of the transistor MNC2.

[0409] Similar to ​ the storage circuit RESD5 and ​ the storage circuit RESD8A, ​ the storage circuit RESD11 can raise the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW. In addition, similar to ​ the storage circuit RESD5 and ​ the storage circuit RESD8A, ​ the storage circuit RESD11 can set the high potential side of the signal output from the terminal OT to be higher than the high-level potential V H the V EXH and set the low potential side to V L .

[0410] Furthermore, ​The storage circuit RESD11 can also be changed to a structure capable of discharging the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1). Specifically, similar to ​ the storage circuit RESD9A, as in ​ the storage circuit RESD11A, a transistor MNC4 can also be provided in the circuit OPC. In addition, regarding ​ the operation example of the storage circuit RESD11A, reference can be made to ​ the description of the operation example of the storage circuit RESD9A.

[0411] <<Example Structure 11 of the Storage Circuit RES>> ​ The storage circuit RESD12 shown is ​ a modified example of the storage circuit RESD3, and is different from the storage circuit RESD3 in that a transistor MNF1 is provided. That is, in ​ the storage circuit RESD12, the circuit OPC includes the transistor MNF1 in addition to the transistors MNH1 to MNH3, the transistors MNC1 to MNC3, the capacitor CCL, and the capacitor CPW.

[0412] ​ The connection structure of the circuit OPC of the storage circuit RESD12, in addition to ​ the connection structure of the storage circuit RESD3, also has the following structure: the first terminal of the transistor MNF1 is electrically connected to the terminal LO1 of the circuit LGC, the first terminal of the transistor MNH3, and the first terminal of the transistor MNC3; the second terminal of the transistor MNF1 is electrically connected to the wiring VDE15; and the gate of the transistor MNF1 is electrically connected to the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW.

[0413] As an example, the wiring VDE15 is used as a wiring for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. The fixed potentials supplied by the wiring VDE15, the wiring VDE11, and the wiring VDE12 can be equal to each other or different from each other. In addition, the fixed potential of the wiring VDE15 can be equal to two of the fixed potentials supplied by each of the wiring VDE11 and the wiring VDE12. In particular, when the fixed potentials supplied by each of the wiring VDE11, the wiring VDE12, and the wiring VDE15 are equal, the wiring VDE11, the wiring VDE12, and the wiring VDE15 can also be the same wiring. Here, the wiring VDE11, the wiring VDE12, and the wiring VDE15 are all wirings for supplying a high-level potential V H of.

[0414] The circuit LGC can refer to ​ the description of the circuit LGC in the storage circuit RESD3.

[0415] The terminal PWC, the wiring VSE21, and the wiring VSE22 can respectively refer to ​ the description of the terminal PWC, the wiring VSE21, and the wiring VSE22 in the storage circuit RESD3.

[0416] Next, an example of the operation of the circuit OPC of ​ the storage circuit RESD12 will be described.

[0417] First, consider supplying a low-level potential V to the first terminals of the transistor MNH3 and the transistor MNC3 from the terminal LO1 L and inputting a high-level potential V to the gates of the transistor MNH2 and the transistor MNC2 from the terminal LO2. H in this case.

[0418] At this time, the gate of the transistor MNH3 is input with the high-level potential V H , so the transistor MNH3 becomes in an on state, and the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL become V L . In addition, the gate of the transistor MNC3 is input with the high-level potential V H , so the transistor MNC3 becomes in an on state, and the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, the gate of the transistor MNF1, and the first terminal of the capacitor CPW also become V L . Therefore, the transistors MNH1, MNC1, and MNF1 are all in an off state.

[0419] On the other hand, the second terminal of the transistor MNH2 is input with the high-level potential V H , so the transistor MNH2 becomes in an on state, and V is output from the terminal OT L . In addition, the second terminal of the transistor MNC2 is input with the high-level potential V H , so the transistor MNC2 becomes in an on state, and V is output from the terminal GT L .

[0420] Next, when the potential input from the terminal LO1 to the first terminals of the transistor MNH3 and the transistor MNC3 changes from V L to V H , the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL rise from V L to V H - Vth_MNH3 , the transistor MNH3 becomes in an off state, and the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW rise from V L to V H -V th_MNC3 , and the transistor MNC3 becomes in an off state. Further, V th_MNH3 is the threshold voltage of the transistor MNH3, and V th_MNC3 is the threshold voltage of the transistor MNC3.

[0421] When the potential input from the terminal LO2 to the gates of the transistor MNH2 and the transistor MNC2 changes from V H to V L , both the transistor MNH2 and the transistor MNC2 become in off states, and the potentials of the terminal OT and the terminal GT both remain at V L .

[0422] At this time, the gate potential of the transistor MNF1 is V H -V th_MNC3 . Further, the potential of the first terminal of the transistor MNF1 is V supplied from the terminal LO1 H , and the potential of the second terminal of the transistor MNF1 is V supplied from the wiring VDE15 H , so that when the threshold voltage of the transistor MNF1 is an appropriate value, the transistor MNF1 becomes in an off state.

[0423] For example, when the high-level potential V input from the terminal LO1 of the circuit LGC to the first terminals of the transistor MNH3 and the transistor MNC3 is stopped, and the potential of the first terminal of the transistor MNF1 drops due to a leakage current (for example, the leakage current to the terminal LO1 of the circuit LGC) or the like, the transistor MNF1 becomes in an on state, charges are supplied from the wiring VDE15 to the first terminals of the transistor MNH3 and the transistor MNC3, and the potential of the first terminal of the transistor MNF1 rises to the potential corresponding to the gate of the transistor MNF1, V H -V H -V th_MNC3 and the threshold voltage of the transistor MNF1 (here it is V MNF1 ). Further, V MNF1 is preferably a potential lower than V H and infinitely close to V H .

[0424] That is to say, ​ even if the circuit LGC stops, the circuit OPC of the storage circuit RESD12 of Land becomes V MNF1 . Therefore, the circuit LGC can sometimes be a circuit that can be temporarily stopped.

[0425] In addition, consider the case where the potential at the gate of the transistor MNH1 and the first terminal of the capacitor CCL is V H -V th_MNH3 and a low-level potential V L is input from the terminal CLK5 to the first terminal of the transistor MNH1. At this time, the potential at the gate of the transistor MNH1 is V H -V th_MNH3 , and the potential at the second terminal of the transistor MNH1 is V L . Therefore, the potential at the terminal OT remains V L .

[0426] Next, when the potential input from the terminal CLK5 to the first terminal of the transistor MNH1 changes from V L to V H , the potential at the second terminal of the transistor MNH1 (the potential at the terminal OT) rises from V L . At this time, the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL are in a floating state. Therefore, by using the bootstrap of the capacitor CCL, the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL rise. As a result, even if the potential at the terminal OT rises, the gate-source voltage of the transistor MNH1 does not change. So, current continues to flow between the first terminal and the second terminal of the transistor MNH1 until the potential at the terminal OT reaches V H .

[0427] As described above, Figure 20A the circuit OPC of the storage circuit RESD12 can output a signal with a high-potential side of V H and a low-potential side of V L to the terminal OT.

[0428] Similarly, consider the case where a low-level potential V H -V th_MNC3 is input from the terminal PWC to the first terminal of the transistor MNC1 when the potential at the gate of the transistor MNC1 and the first terminal of the capacitor CPW is V L . At this time, the potential at the gate of the transistor MNC1 is V H -V th_MNC3 and the potential at the second terminal of the transistor MNC1 is V L . Therefore, the potential at the terminal GT remains V L .

[0429] Next, when the potential input from the terminal PWC to the first terminal of the transistor MNC1 changes from V L to V EXH , the potential of the second terminal of the transistor MNC1 (the potential of the terminal GT) rises from V L . At this time, the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW are in a floating state. Therefore, by using the bootstrap of the capacitor CPW, the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW rise. As a result, even if the potential of the terminal GT rises, the gate-source voltage of the transistor MNC1 does not change. So, until the potential of the terminal GT reaches V EXH , a current continues to flow between the first terminal and the second terminal of the transistor MNC1.

[0430] When the potential of the terminal GT reaches V EXH , the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW become V H -V th_MNC3 +(V EXH -V L ). In addition, the potential of the first terminal of the transistor MNF1 is V H (or V MNF1 ), and the potential of the second terminal of the transistor MNF1 is V H . Therefore, when the threshold voltage of the transistor MNF1 is an appropriate value, the transistor MNF1 can be in an on state.

[0431] As a result, a conduction state is established between the wiring VDE15 and the first terminals of the transistor MNH3 and the transistor MNC3, and the first terminals of the transistor MNH3 and the transistor MNC3 are supplied with V H from the wiring VDE15.

[0432] At this time, for example, even if the circuit LGC stops, the conduction state is maintained between the first terminals of the transistor MNH3 and the transistor MNC3 and the wiring VDE15. Therefore, the first terminals of the transistor MNH3 and the transistor MNC3 do not become floating states. Thus, even if noise is input to the first terminals of the transistor MNH3 and the transistor MNC3, the potentials of the first terminals of the transistor MNH3 and the transistor MNC3 are not easily changed. As a result, the fluctuations in the potentials output from the terminals OT and GT are not easily generated, so the signals output from the terminals OT and GT of the storage circuit RESD12 can be stabilized.

[0433] As described above, Figure 20AThe circuit OPC of the storage circuit RESD12 can output a signal with a high potential side of V and a low potential side of V to the terminal GT. Moreover, even when noise is input to the circuit OPC of the storage circuit RESD12, the signals output from the terminal OT and the terminal GT can be stabilized. EXH And the low potential side is V. L of the signal. Furthermore, Figure 20A the circuit OPC of the storage circuit RESD12 can stabilize each signal output from the terminal OT and the terminal GT even when noise is input.

[0434] In addition, since the gate of the bootstrap transistor MNF1 using the capacitor CPW is input with a potential higher than V - V, a transistor with high voltage tolerance is preferably used as the transistor MNF1. That is, as the transistor MNF1, a transistor MTCK with a relatively thick gate insulating film described in Embodiment 1 is preferably used. H -V th_MNC3 Moreover, since the driving speed of the shift register SR including the storage circuit RESD12 is preferably fast, a transistor with a high driving frequency can also be used as the transistor MNF1. That is, as the transistor MNF1, a transistor MTHN with a relatively thin gate insulating film described in Embodiment 1 can also be used.

[0435] In addition, regarding the transistors MNH1 to MNH3 and the transistors MNC1 to MNC3, the description of each of the transistors MNH1 to MNH3 and the transistors MNC1 to MNC3 included in the storage circuit RESD3 in FIG. 12 can be referred to. Figure 20A Moreover, the structure of the storage circuit RESD12 can also be changed to the structure of the storage circuit RESD12A shown in.

[0436] The storage circuit RESD12A shown in has a structure that combines the terminal OT and the terminal GT of the storage circuit RESD12.

[0437] Figure 20A Specifically, compared with the storage circuit RESD12A of, in the storage circuit RESD12A of, the transistors MNH1 to MNH3 and the capacitor CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitor CPW, and the first terminal of the transistor MNC2. Figure 20B shown. Figure 20B shown has a structure that combines Figure 20A the terminal OT and the terminal GT of the storage circuit RESD12.

[0438] Specifically, compared with the Figure 20A storage circuit RESD12A of, in the Figure 20B storage circuit RESD12A of, the transistors MNH1 to MNH3 and the capacitor CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitor CPW, and the first terminal of the transistor MNC2.

[0439] Compared with the Figure 13 storage circuit RESD5 of, Figure 16 the storage circuit RESD8A of, Figure 19A the storage circuit RESD11 of, and Figure 19BThe storage circuit RESD11A is the same. Figure 20B The storage circuit RESD12A can increase the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW. In addition, compared with Figure 13 the storage circuit RESD5, Figure 16 the storage circuit RESD8A, Figure 19A the storage circuit RESD11, and Figure 19B the storage circuit RESD11A is the same. Figure 20B The storage circuit RESD12A can set the high-potential side of the signal output from the terminal OT to be higher than the high-level potential V H of V EXH and set the low-potential side to V L .

[0440] Figure 20A The storage circuit RESD12 can also be changed to Figure 21A the structure of the storage circuit RESD12B shown. Figure 21A The storage circuit RESD12B shown is different from Figure 20A the storage circuit RESD12 in that: in Figure 21A the storage circuit RESD12B shown, the gate of the transistor MNF1 is not electrically connected to the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitor CPW, but is electrically connected to the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL.

[0441] Figure 21A The storage circuit RESD12B shown has a structure that increases the potential of the gate of the transistor MNF1 by using the bootstrap of the capacitor CCL to turn on the transistor MNF1. The potential of the gate of the transistor MNF1 increased by using the bootstrap of the capacitor CCL is lower than Figure 21A the potential of the gate of the transistor MNF1 increased by using the bootstrap of the capacitor CPW in the storage circuit RESD12. However, in Figure 21A the structure of the storage circuit RESD12B, by increasing the potential of the gate of the transistor MNF1 by using the bootstrap of the capacitor CCL, the transistor MNF1 can sometimes be fully turned on. That is to say, similar to Figure 20A the storage circuit RESD12, the signals output from the terminals OT and GT can be stabilized.

[0442] Figure 20A The storage circuit RESD12 can also be changed to Figure 21B the structure of the storage circuit RESD13 shown. Figure 21B The storage circuit RESD13 has Figure 20AIn the circuit OPC of the storage circuit RESD12, the combination of the transistor MNH3 and the transistor MNC3 forms the structure of the transistor MNH3.

[0443] Specifically, in Figure 21B the circuit OPC of the storage circuit RESD13, the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitor CCL, the gate of the transistor MNC1, the first terminal of the capacitor CPW, and the gate of the transistor MNF1.

[0444] Similar to Figure 20A the storage circuit RESD12, Figure 21B the storage circuit RESD13 can boost the potential of the gate of the transistor MNC1 by using the bootstrap of the capacitor CPW and can boost the potential of the gate of the transistor MNH1 by using the bootstrap of the capacitor CCL.

[0445] Figure 20A The storage circuit RESD12 can also be changed to Figure 22A the structure of the storage circuit RESD14 shown in Figure 14A Similar to Figure 22A the storage circuit RESD6, Figure 22A the difference between the storage circuit RESD14 and the storage circuit RESD12 is that: in

[0446] that is to say, Figure 22A in the storage circuit RESD14 shown in Figure 14A since both the transistor MNH3 and the transistor MNC3 are diode-connected, similar to H the storage circuit RESD6, a high-level potential V H -V th_MNH3 is supplied from the terminal LO1 of the circuit LGC1 to the first terminals of the transistor MNH3 and the transistor MNC3, and the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL become V H -V th MNH3 . In addition, then, when a high-level potential V H is input from the terminal CLK5, due to the occurrence of the bootstrap using the capacitor CCL, the potential of the terminal OT rises to V H。Similarly, when a high-level potential V is input from the terminal PWC EXH , since bootstrapping using the capacitor CPW occurs, the potential of the terminal GT rises to V EXH . As a result, since the potential of the gate of the transistor MNF1 also rises, the transistor MNF1 can be turned on, and thereby a conduction state can be established between the wiring VDE15 and the first terminals of the transistor MNH3 and the transistor MNC3. Thus, similar to Figure 20A 's storage circuit RESD12, the respective signals output from the terminals OT and GT can be stabilized.

[0447] In addition, when it is desired to lower the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) V High -V th_MNH3 , in other words, when it is desired to release the charge stored in the first terminal of the capacitor CCL (or the gate of the transistor MNH1), it is necessary to further modify Figure 22A 's circuit OPC. Furthermore, similarly, when it is desired to lower the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) V High -V th_MNC3 , in other words, when it is desired to release the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1), similar to Figure 14A 's storage circuit RESD6 and Figure 15A 's storage circuit RESD7, it is necessary to further modify Figure 22A 's circuit OPC.

[0448] Figure 22B The circuit OPC of the storage circuit RESD14A shown is Figure 22A a modified example of the circuit OPC of the storage circuit RESD14, and is different from Figure 22A 's circuit OPC of the storage circuit RESD14 in that it has a structure capable of releasing the charge stored in the first terminal of the capacitor CCL (or the gate of the transistor MNH1) and the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1). Specifically, Figure 22B the circuit OPC of the storage circuit RESD14A shown is different from Figure 22A 's circuit OPC of the storage circuit RESD14 in that Figure 22B the circuit OPC of the storage circuit RESD14A shown includes the transistors MNC4 and MNH4.

[0449] The first terminal of transistor MNH4 is electrically connected to the gate of transistor MNH1, the first terminal of capacitor CCL, and the second terminal of transistor MNH3. The second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1. In addition, the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, the first terminal of capacitor CPW, and the gate of transistor MNF1. The second terminal of transistor MNC4 is electrically connected to wiring VSE24, and the gate of transistor MNC4 is electrically connected to wiring RS2.

[0450] Regarding wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24, reference can be made to Figure 14B the descriptions of wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24 of the memory circuit RESD6A shown. In addition, regarding transistors MNH4 and MNC4, reference can also be made to Figure 14B the descriptions of transistors MNH4 and MNC4 of the memory circuit RESD6A.

[0451] For example, when it is desired to increase the potential of the first terminal of capacitor CCL (the potential of the gate of transistor MNH1) (when it is desired to make this potential V H -V th_MNH3 ), after supplying a low-level potential V L to wiring RS1 to turn off transistor MNH4, a high-level potential V H is supplied from terminal LO1 of circuit LGC to the first terminal of transistor MNH3. In addition, when it is desired to decrease the potential of the first terminal of capacitor CCL (the potential of the gate of transistor MNH1) (when it is desired to make this potential V L ), after supplying the low-level potential V L from terminal LO1 of circuit LGC to the first terminal of transistor MNH3 to turn off transistor MNH3, a high-level potential V H is supplied to wiring RS1 to turn on transistor MNH4. Here, when the potential supplied to wiring VSE23 is the low-level potential V L L , the charge at the first terminal of capacitor CCL (the charge at the gate of transistor MNH1) flows through wiring VSE23, and as a result, the potential at the first terminal of capacitor CCL (the potential at the gate of transistor MNH1) becomes V

[0452] For example, when it is desired to increase the potential of the first terminal of capacitor CPW (the potential of the gate of transistor MNC1) (when it is desired to make this potential V H -Vth_MNC3 In the case of), when supplying a low-level potential V to the wiring RS2 L After turning off the transistor MNC4, supply a high-level potential V from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 H That's all. In addition, in the case of wanting to lower the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) (in the case of wanting to make this potential V L In the case of), the low-level potential V L After supplying from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 to turn off the transistor MNC3, supply a high-level potential V to the wiring RS2 H Turn on the transistor MNC4. Here, when the potential supplied by the wiring VSE24 is the low-level potential V L At this time, the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNC1) flows through the wiring VSE24, and as a result, the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) becomes V L .

[0453] Figure 20A The storage circuit RESD12 of can also be changed to Figure 23 The structure of the storage circuit RESD15 shown. Similar to Figure 17A The storage circuit RESD9 of Figure 23 The difference between the storage circuit RESD15 of and the storage circuit RESD12 is that: in Figure 23 In the storage circuit RESD15 of, the gate of the transistor MNH3 is not electrically connected to the wiring VDE11 but to the terminal LO1 of the circuit LGC; the first terminal of the transistor MNH3 is electrically connected to the wiring VDE13; the gate of the transistor MNC3 is not electrically connected to the wiring VDE12 but to the terminal LO1 of the circuit LGC; and the first terminal of the transistor MNC3 is electrically connected to the wiring VDE14.

[0454] Regarding the wiring VDE13 and the wiring VDE14, reference can be made to Figure 17A The description of the wiring VDE13 and the wiring VDE14 of the storage circuit RESD9 of

[0455] In Figure 23 In the storage circuit RESD15 of, supply a high-level potential V to each of the gate of the transistor MNH3 and the gate of the transistor MNC3 from the terminal LO1 of the circuit LGC1 H , and the potential of each of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL reaches V H -Vth_MNH3 When this occurs, transistor MNH3 turns off. In addition, the potential of each of the second terminal of transistor MNC3, the gate of transistor MNC1, the gate of transistor MNF1, and the first terminal of capacitor CPW reaches V H -V th_MNC3 when transistor MNC3 turns off.

[0456] In addition, then, when a high-level potential V is input from terminal CLK5, the potential of terminal OT rises to V due to the bootstrap effect using capacitor CCL H because of the bootstrap effect using capacitor CCL. Similarly, when a high-level potential V is input from terminal PWC H the potential of terminal GT rises to V EXH due to the bootstrap effect using capacitor CPW. As a result, since the potential of the gate of transistor MNF1 also rises, transistor MNF1 can be turned on, and thus conduction can be established between wiring VDE15 and the first terminals of transistor MNH3 and transistor MNC3. As a result, similar to EXH the storage circuit RESD12, the signals output from terminals OT and GT can be stabilized. Figure 20A In addition, when it is desired to lower the potential of the first terminal of capacitor CCL (the potential of the gate of transistor MNH1) V

[0457] -V High in other words, when it is desired to discharge the charge stored in the first terminal of capacitor CCL (or the gate of transistor MNH1), further modification to the circuit OPC of th_MNH3 is required. Similarly, when it is desired to lower the potential of the first terminal of capacitor CPW (the potential of the gate of transistor MNC1) V Figure 23 -V High in other words, when it is desired to discharge the charge stored in the first terminal of capacitor CPW (or the gate of transistor MNC1), similar to th_MNC3 the storage circuit RESD9, further modification to the circuit OPC of Figure 17A is required. Figure 23 The circuit OPC of the storage circuit RESD15A shown in

[0458] Figure 24 is a modified example of the circuit OPC of Figure 23 the storage circuit RESD15, and is similar to Figure 23 ​The circuit OPC of the storage circuit RESD15 is different in that it has a structure capable of discharging the charge stored in the first terminal of the capacitor CCL (or the gate of the transistor MNH1) and the charge stored in the first terminal of the capacitor CPW (or the gate of the transistor MNC1). Specifically, Figure 24 The circuit OPC of the storage circuit RESD15A shown in Figure 23 is different from the circuit OPC of the storage circuit RESD15 in that Figure 24 the circuit OPC of the storage circuit RESD15A shown in includes the transistor MNC4 and the transistor MNH4.

[0459] The first terminal of the transistor MNH4 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitor CCL, and the second terminal of the transistor MNH3. The second terminal of the transistor MNH4 is electrically connected to the wiring VSE23, and the gate of the transistor MNH4 is electrically connected to the wiring RS1. In addition, the first terminal of the transistor MNC4 is electrically connected to the second terminal of the transistor MNC3, the gate of the transistor MNC1, the first terminal of the capacitor CPW, and the gate of the transistor MNF1. The second terminal of the transistor MNC4 is electrically connected to the wiring VSE24, and the gate of the transistor MNC4 is electrically connected to the wiring RS2.

[0460] Regarding the wiring RS1, the wiring RS2, the wiring VSE23, and the wiring VSE24, reference can be made to the description of the wiring RS1, the wiring RS2, the wiring VSE23, and the wiring VSE24 of the storage circuit RESD9A shown in Figure 17B For example, when it is desired to increase the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) (when it is desired to make this potential V

[0461] -V H -V th_MNH3 ), after supplying a low-level potential V to the wiring RS1 to turn off the transistor MNH4, a high-level potential V is supplied from the terminal LO1 of the circuit LGC to the gate of the transistor MNH3 L That's it. In addition, when it is desired to decrease the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) (when it is desired to make this potential V H ), after supplying a low-level potential V from the terminal LO1 of the circuit LGC to the gate of the transistor MNH3 to turn off the transistor MNH3, the wiring RS1 is supplied with a high-level potential V L to turn on the transistor MNH4. Here, when the potential supplied to the wiring VSE23 is the low-level potential V L to turn on the transistor MNH4. Here, when the potential supplied to the wiring VSE23 is the low-level potential V H to turn on the transistor MNH4. Here, when the potential supplied to the wiring VSE23 is the low-level potential V LWhen the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) flows through the wiring VSE23, as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes V L .

[0462] For example, in the case where it is desired to increase the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) (in the case where it is desired to make this potential V H -V th_MNC3 ), after supplying the low-level potential V to the wiring RS2 L to turn off the transistor MNC4, a high-level potential V is supplied from the terminal LO1 of the circuit LGC to the gate of the transistor MNC3 H That's all. In addition, in the case where it is desired to decrease the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) (in the case where it is desired to make this potential V L ), a low-level potential V is supplied from the terminal LO1 of the circuit LGC to the gate of the transistor MNC3 L to turn off the transistor MNC3, and then a high-level potential V is supplied to the wiring RS2 H to turn on the transistor MNC4. Here, when the potential supplied to the wiring VSE24 is the low-level potential V L the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNC1) flows through the wiring VSE24, and as a result, the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) becomes V L .

[0463] <Level converter circuit LS> Next, the level converter circuit LS included in the amplifier circuit LVS of the drive circuit SD2 of Figure 4 will be described. Figure 25A Fig. shows an example of the circuit structure of the level converter circuits LS[1] to LS[5] of the level converter circuit that can be used for Figure 4 .

[0464] Figure 25A The level converter circuit LSa shown in Fig. is an example of the circuit structure of the level converter circuit LS that can be used for Figure 4 and includes transistors MN11 to MN13. In addition, as shown in Figure 25A the level converter circuit LSa is a unipolar circuit that does not include p-channel transistors and includes n-channel transistors.

[0465] The level converter circuit LSa includes a terminal IN1L, a terminal IN2L, and a terminal OUTL.

[0466] The gate of transistor MN11 is electrically connected to wiring VE1, the first terminal of transistor MN11 is electrically connected to terminal IN1L, and the second terminal of transistor MN11 is electrically connected to the gate of transistor MN12. In addition, the first terminal of transistor MN12 is electrically connected to wiring VE2. In addition, the gate of transistor MN13 is electrically connected to terminal IN2L, the first terminal of transistor MN13 is electrically connected to the second terminal of transistor MN12 and terminal OUTL, and the second terminal of transistor MN13 is electrically connected to wiring VE3.

[0467] As an example, terminal IN1L corresponds to Figure 4 the input terminal of level converter circuit LS.

[0468] As an example, terminal IN2L is input with a signal obtained by logically inverting the signal input to terminal IN1L. For example, when a low-level potential is input to terminal IN1L, a high-level potential is input to terminal IN2L. In addition, for example, when a high-level potential is input to terminal IN1L, a low-level potential is input to terminal IN2L. Therefore, terminal IN2L is preferably electrically connected to the output terminal of an inverter and the input terminal of the inverter is electrically connected to terminal IN1L.

[0469] As an example, terminal OUTL corresponds to Figure 4 the output terminal of level converter circuit LS.

[0470] As an example, wiring VE1 is used as a wiring for supplying a fixed potential. In addition, this fixed potential is preferably a potential of the same level as the high-level potential that can be output from the second output terminal of storage circuit RES. In addition, wiring VE1 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0471] As an example, wiring VE2 is used as a wiring for supplying a fixed potential. In addition, this fixed potential is preferably a potential higher than the high-level potential that can be output from the second output terminal of storage circuit RES. In addition, this fixed potential can also be a potential of the same level as the low-level potential that can be output from the second output terminal of storage circuit RES. In addition, wiring VE2 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0472] As an example, wiring VE3 is used as a wiring for supplying a fixed potential. In addition, this potential is preferably the low-level potential that can be output from the second output terminal of storage circuit RES or the ground potential. In addition, wiring VE3 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0473] In the level shifter circuit LSa, the transistor MN11 has the function of transmitting the signal from the terminal IN1L to the gate of the transistor MN12. Therefore, a transistor with a high driving frequency is preferably used as the transistor MN11. That is, the transistor MTHN described in the above-described Embodiment 1 is preferably used as the transistor MN11. Further, when it is desired to improve the voltage tolerance of the transistor MN11, the transistor MTHN may be used as the transistor MN11 instead of the transistor MTCK.

[0474] In the level shifter circuit LSa, as described above, a potential higher than the high-level potential that can be output from the second output terminal of the storage circuit RES is supplied to the first terminal and the second terminal of the transistor MN12 or the first terminal of the transistor MN13 from the wiring VE2. Therefore, transistors with high voltage tolerance are preferably used as the transistor MN12 and the transistor MN13. That is, the transistor MTCK described in the above-described Embodiment 1 is preferably used as the transistor MN12 and the transistor MN13. Further, when the driving frequencies of the transistor MN12 and the transistor MN13 are to be increased, the transistor MTHN may be used as the transistor MN12 and the transistor MN13 instead of the transistor MTCK.

[0475] Next, a modified example of the level shifter circuit LSa will be described.

[0476] Figure 25B The shown level shifter circuit LSb1 is Figure 25A a modified example of the level shifter circuit LSa, and is different from the level shifter circuit LSa in that: the transistor MN11 is not provided; and the gate of the transistor MN12 is electrically connected to the first terminal of the transistor MN12.

[0477] The inverted signal of the signal input to the terminal IN1L is input to the terminal IN2L of the level shifter circuit LSa. Similarly, in the level shifter circuit LSb1, the inverted signal of the signal output from the second output terminal of the storage circuit RES is input to the terminal IN2L of the level shifter LSB1.

[0478] In addition, the structure of the level shifter circuit LSb1 can be changed in the circuit design stage.

[0479] For example, as Figure 3 or Figure 4 the level shifter circuit LS included in the amplifier circuit LVS shown, the level shifter circuit LSb2 shown in Figure 25C may also be used. Figure 25C The shown level shifter circuit LSb2 is Figure 25BA modified example of the level shifter circuit LSb1, which is different from the level shifter circuit LSb1 in that the gate of the transistor MN12 is not electrically connected to the first terminal of the transistor MN12 but to the second terminal of the transistor MN12.

[0480] Figure 25C The transistor MN12 shown is a normally-on transistor.

[0481] In addition, in this specification, etc., the normally-off state of the OS transistor means the following state: when the gate-source voltage is 0V, the current flowing through each channel width of 1μm of the transistor is 1×10 -20 A or less, at 85°C it is 1×10 -18 A or less, or at 125°C it is 1×10 -16 A or less. On the other hand, normally-on means a state in which a channel exists and current flows through the transistor even when the gate-source voltage is 0V.

[0482] For example, as Figure 3 or Figure 4 the level shifter circuit LS included in the amplifier circuit LVS shown, the level shifter circuit LSb3 shown in Figure 25D can also be used. Figure 25D The level shifter circuit LSb3 shown in Figure 25B is a modified example of the level shifter circuit LSb1, which is different from the level shifter circuit LSb1 in that the resistor R is used instead of the transistor MN12.

[0483] The first terminal of the resistor R is electrically connected to the wiring VE2, and the second terminal of the resistor R is electrically connected to the first terminal of the transistor MN13 and the terminal OUTL.

[0484] For example, as Figure 3 or Figure 4 the level shifter circuit LS included in the amplifier circuit LVS shown, the level shifter circuit LSb4 shown in Figure 25E can also be used. Figure 25E The level shifter circuit LSb4 shown in Figure 25B is a modified example of the level shifter circuit LSb1, which is different from the level shifter circuit LSb1 in that the diode DI is used instead of the transistor MN12.

[0485] The input terminal of the diode is electrically connected to the wiring VE2, and the output terminal of the diode is electrically connected to the first terminal of the transistor MN13 and the terminal OUTL.

[0486] <The holding circuit LTC1 or the holding circuit LTC2> Next, explain Figure 3 orFigure 4 The first latch circuit LA included in the holding circuit LTC1 shown and the second latch circuit LB included in the holding circuit LTC2. Figure 26A Illustrated as being usable for Figure 3 or Figure 4 An example of the circuit configuration of a latch circuit for the first latch circuit LA or the second latch circuit LB shown.

[0487] Figure 26A The first latch circuit LA (the second latch circuit LB) shown includes inverters INV1 to INV5, switches SW1 and SW2. In addition, the first latch circuit LA (the second latch circuit LB) includes an input terminal D, an output terminal Q, and an enable input terminal E.

[0488] The switch SW1 or the switch SW2 can also be an electrical switch such as an analog switch or a mechanical switch, for example. In addition, as one of the electrical switches, an OS transistor can also be used.

[0489] In this specification and the like, Figure 26A The switches SW1 and SW2 shown are in an ON state when a high-level potential is supplied to the control terminal and in an OFF state when a low-level potential is supplied to the control terminal.

[0490] The input terminal of the inverter INV1 is electrically connected to the input terminal D, and the output terminal of the inverter INV1 is electrically connected to the first terminal of the switch SW1. The input terminals of the inverter INV2, the inverter INV3, the second terminal of the switch SW1, and the first terminal of the switch SW2 are electrically connected, and the output terminal of the inverter INV2 is electrically connected to the output terminal Q. The output terminal of the inverter INV3 is electrically connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 is electrically connected to the second terminal of the switch SW2. The input terminal of the inverter INV5 is electrically connected to the enable input terminal E and the control terminal of the switch SW1, and the output terminal of the inverter INV5 is electrically connected to the control terminal of the switch SW2.

[0491] In Figure 26A In the first latch circuit LA (the second latch circuit LB) shown, when a high-level potential is input to the enable input terminal E, the switch SW1 becomes conductive and the switch SW2 becomes non-conductive. Therefore, the signal input to the input terminal D is output to the output terminal Q through the inverters INV1 and INV2. In addition, the signal input to the input terminal D is input to the first terminal of the switch SW2 through the inverters INV1, INV3, and INV4.

[0492] Here, when the high-level potential input to the enable input terminal E becomes a low-level potential, the switch SW1 becomes non-conductive and the switch SW2 becomes conductive. At this time, the signal previously input to the input terminal D can be held by the inverter INV3 and the inverter INV4. In addition, this signal is output to the output terminal Q through the inverter INV2.

[0493] Figure 26B The circuit structures of the inverters that can be used for each of the inverters INV1 to INV5 are shown. Figure 26B The shown inverter INV includes transistors MN21 to MN24 and a capacitor C21. In addition, as Figure 26B shown, the inverter INV is a unipolar circuit that does not include p-channel transistors but includes n-channel transistors.

[0494] The input terminal of the inverter INV is electrically connected to the gates of the transistors MN21 and MN23. In addition, the gate of the transistor MN22 is electrically connected to the first terminal of the transistor MN22 and the wiring VE11. The second terminal of the transistor MN22 is electrically connected to the first terminal of the transistor MN21, the gate of the transistor MN24, and the first terminal of the capacitor C21. In addition, the second terminal of the transistor MN21 is electrically connected to the wiring VE13. The first terminal of the transistor MN24 is electrically connected to the wiring VE12. The second terminal of the transistor MN24 is electrically connected to the second terminal of the capacitor C21, the first terminal of the transistor MN23, and the output terminal of the inverter INV. In addition, the second terminal of the transistor MN23 is electrically connected to the wiring VE14.

[0495] As an example, the wirings VE11 and VE12 are used as wirings for supplying a fixed potential. This fixed potential is preferably a high-level potential. In addition, the fixed potentials supplied by each of the wirings VE11 and VE12 may be the same or different from each other. In addition, one or both of the wirings VE11 and VE12 may also be wirings that supply a variable potential instead of a fixed potential.

[0496] As an example, the wirings VE13 and VE14 are used as wirings for supplying a fixed potential. This fixed potential is preferably a low-level potential or a ground potential. The fixed potentials supplied by each of the wirings VE13 and VE14 may be the same or different from each other. In addition, one or both of the wirings VE11 and VE12 may also be wirings that supply a variable potential instead of a fixed potential.

[0497] In the inverter INV, transistors MN21 to MN24 are used as circuit elements that invert the logic of a signal from the input terminal of the inverter INV and output the logically inverted signal to the output terminal of the inverter INV. Therefore, the time required from when a signal is input to the input terminal of the inverter INV to when the signal is output from the output terminal of the inverter INV is preferably short. In other words, transistors with a high drive frequency are preferably used as transistors MN21 to MN24 included in the inverter INV. That is, transistors MN21 to MN24 are preferably the transistors MTHN described in the above-described Embodiment 1.

[0498] When it is desired to improve the voltage tolerance of transistors MN21 to MN24, transistors MTCK may be used instead of transistors MTHN for transistors MN21 to MN24.

[0499] Figure 26C Shows the circuit structure of a switch that can be used for each of switch SW1 and switch SW2. Figure 26C The shown switch SW includes transistor MN26, transistor MN27, and capacitor C22. In addition, as Figure 26C shown, the switch SW is a unipolar circuit that does not include a p-channel transistor and includes an n-channel transistor.

[0500] The first terminal of transistor MN26 is electrically connected to the enable input terminal E of switch SW, the second terminal of transistor MN26 is electrically connected to the gate of transistor MN27 and the first terminal of capacitor C22, and the gate of transistor MN26 is electrically connected to wiring VE15. Additionally, the first terminal of transistor MN27 is electrically connected to the first terminal of switch SW, and the second terminal of transistor MN27 is electrically connected to the second terminal of capacitor C22 and the second terminal of switch SW2.

[0501] As an example, wiring VE15 is used as wiring for supplying a fixed potential. This fixed potential is preferably a high-level potential. In addition, the fixed potentials supplied by each of the wirings VE15 may be the same or different from each other. Furthermore, one or both of the wirings VE15 may be wiring that supplies a variable potential instead of a fixed potential.

[0502] In the switch SW, the transistor MN27 is used as a circuit element that switches between the conductive state and the non-conductive state between the input terminal and the output terminal of the switch SW. Therefore, the switching speed of the transistor MN27 is preferably fast. Thus, as the transistor MN27 included in the switch SW, a transistor with a high drive frequency is preferably used. That is to say, as the transistor MN27, the transistor MTHN described in the above Embodiment 1 is preferably used. When it is desired to improve the voltage tolerance of the transistor MN27, the transistor MTCK may be used as the transistor MN27 instead of the transistor MTHN.

[0503] When it is desired to improve the voltage tolerance, the transistor MTCK may be used as the transistor MN26. In addition, when it is desired to increase the drive frequency, the transistor MTHN may be used.

[0504] <Amplifier circuit SF> Next, the Figure 3 or Figure 4 source follower circuits SAM[1] to SAM[5] included in the amplifier circuit SF shown are described. Figure 27A Shows an example of the circuit structure of a source follower circuit that can be used for Figure 3 or Figure 4 the source follower circuits SAM[1] to SAM[5] shown.

[0505] Figure 27A The source follower circuit SAM shown includes transistors MN31 to MN38, capacitors C1 and C2. In addition, the source follower circuit SAM includes a terminal IP and a terminal OP.

[0506] The first terminal of transistor MN31 is electrically connected to terminal IP. The second terminal of transistor MN31 is electrically connected to the first terminal of transistor MN32 and the first terminal of capacitor C1. The gate of transistor MN31 is electrically connected to wiring DR1. In addition, the second terminal of capacitor C1 is electrically connected to wiring VE23. Further, the first terminal of transistor MN35 is electrically connected to wiring SG. The second terminal of transistor MN35 is electrically connected to the gate of transistor MN36 and the first terminal of capacitor C2. The gate of transistor MN35 is electrically connected to wiring DR2. The second terminal of transistor MN32 is electrically connected to the first terminal of transistor MN33 and the second terminal of capacitor C2. The gate of transistor MN32 is electrically connected to wiring DR3. In addition, the first terminal of transistor MN36 is electrically connected to wiring VE22. The second terminal of transistor MN36 is electrically connected to the second terminal of transistor MN33, the first terminal of transistor MN37, and the first terminal of transistor MN34. Additionally, the gate of transistor MN33 is electrically connected to wiring DR4. Additionally, the second terminal of transistor MN37 is electrically connected to wiring VE24. The gate of transistor MN37 is electrically connected to wiring VBIS. Further, the second terminal of transistor MN34 is electrically connected to the first terminal of transistor MN38 and terminal OP. The gate of transistor MN34 is electrically connected to wiring DR5. Additionally, the second terminal of transistor MN38 is electrically connected to wiring VE25. The gate of transistor MN38 is electrically connected to wiring INIT.

[0507] Wirings DR1 to DR5 and wiring INIT are used as wirings for transmitting signals for controlling source follower circuit SAM. Therefore, the signals transmitted by wirings DR1 to DR5 and wiring INIT are preferably variable potentials.

[0508] As an example, wiring SG is used as a wiring for supplying a fixed potential. This fixed potential is preferably above the low-level potential supplied by wirings VE23 to VE25 or above the ground potential described later and below the high-level potential supplied by wiring VE22. Additionally, this fixed potential can also be a potential outside the above range. Further, wiring SG can also be a wiring for supplying a variable potential instead of a fixed potential.

[0509] As an example, wiring VE22 is used as a wiring for supplying a fixed potential. Additionally, this fixed potential is preferably a high-level potential. Further, wiring VE22 can also be a wiring for supplying a variable potential instead of a fixed potential.

[0510] As an example, wirings VE23 to VE25 are used as wirings for supplying a fixed potential. This fixed potential is preferably a low-level potential or a ground potential. In addition, the fixed potentials supplied to each of wirings VE23 to VE25 may be the same as or different from each other. Further, one or more of wirings VE23 to VE25 may be a wiring for supplying a variable potential instead of a fixed potential.

[0511] Wiring VBIS is used as a wiring for supplying a fixed potential to the gate of transistor MN37. Further, the second terminal of transistor MN37 is electrically connected to wiring VE24, and when wiring VE24 supplies a fixed potential to the second terminal of transistor MN37, transistor MN37 is used as a constant current source.

[0512] As an example, terminal IP corresponds to Figure 3 or Figure 4 the input terminal of source follower circuit SAM.

[0513] As an example, terminal OP corresponds to Figure 3 or Figure 4 the output terminal of source follower circuit SAM.

[0514] Figure 27B is a timing chart showing Figure 27A an operation example of source follower circuit SAM shown. Figure 27B The timing chart of Figure 27B shows changes in the potentials of wirings DR1 to DR5 and wiring INIT at and near times T1 to T4. Further, in the

[0515] wiring VE22 is a wiring for supplying a high-level potential V DH . In addition, wirings VE23 to VE25 are used as wirings for supplying a low-level potential V SS . Further, wiring SG is used as a wiring for supplying a reference potential V X .

[0516] During times T1 to T2, initialization is performed in source follower circuit SAM. Specifically, wirings DR1, DR3, and DR5 all become low-level potentials, and wirings DR2, DR4, and INIT all become high-level potentials.

[0517] Therefore, transistors MN31, MN32, and MN34 are all in the off state. In addition, transistors MN33, MN35, and MN38 are all in the on state. Since transistor MN35 is in the on state, a conductive state is established between the first terminal of capacitor C2 and wiring SG, and the potential of the first terminal of capacitor C2 becomes the potential V of supply wiring SG X .

[0518] Since transistor MN33 is in the on state, a conductive state is established between the second terminal of capacitor C2 and wiring VE22. At this time, the potential of the second terminal of capacitor C2 rises until the current flowing through the source-drain of transistor MN36 equals the current flowing through the source and drain of transistor MN37. This is because: as the potential of the second terminal of capacitor C2 rises, the gate-source voltage of transistor MN36 becomes smaller, and the current flowing through the source-drain of transistor MN36 decreases. In addition, the potential of the second terminal of capacitor C2 at this time is V Y .

[0519] That is to say, by performing the operation during the period from time T1 to time T2, the current flowing through the source-drain of transistor MN36 can be made equal to the current flowing through the source-drain of transistor MN37. At this time, by changing the potential of wiring DR2 from the high-level potential to the low-level potential to turn transistor MN35 off, the voltage between the first terminal and the second terminal of capacitor C2 corresponding to this current can be maintained.

[0520] In addition, since transistor MN38 is in the on state, a conductive state is established between terminal OP and wiring VE25. Therefore, the potential of terminal OP becomes V supplied by wiring VE25 SS .

[0521] During the period from time T2 to time T3, an input signal is input to terminal IP of source follower circuit SAM. At this time, both wiring DR1 and wiring DR3 are at the high-level potential, and wiring DR2, DR4, and DR5 are all at the low-level potential. In addition, during the period from time T2 to time T3 in the timing diagram of Figure 27B , wiring INIT is at the high-level potential, but it can also be at the low-level potential.

[0522] At this time, both transistors MN31 and MN32 become in the on state. In addition, transistors MN33, MN34, and MN35 all become in the off state. Since transistors MN31 and MN32 are in the on state, a conductive state is established between terminal IP and the second terminal of capacitor C2, and the potential V of the second terminal of capacitor C2 Yrises to the potential V corresponding to the input signal supplied to the terminal IP in . At this time, the first terminal of the capacitor C2 is in a floating state. Therefore, the potential of the second terminal of the capacitor C2 changes, and the potential of the first terminal of the capacitor C2 also changes. When the capacitance coupling coefficient of the parasitic capacitance related to the capacitor C2 and its periphery is K, the potential of the first terminal of the capacitor C2 changes from V X to V X +K(V in -V Y ). Here, assuming K = 1, the potential of the first terminal of the capacitor C2 is V X +V in -V Y . Thus, the gate-source voltage of the transistor MN36 becomes higher, and the amount of current flowing through the source-drain also becomes larger.

[0523] During the period from time T3 to time T4, an output signal is output from the terminal OP of the source follower circuit SAM. At this time, both the wiring DR3 and the wiring DR5 become high-level potentials, and the wirings DR1, DR2, DR4, and the wiring INIT all become low-level potentials.

[0524] At this time, both the transistor MN32 and the transistor MN34 become in the on state. In addition, the transistors MN31, MN33, MN35, and MN38 all become in the off state. Since the transistor MN34 is in the on state, a conduction state is formed between the terminal OP and the second terminal of the transistor MN36, and the potential of the terminal OP becomes the potential corresponding to the gate-source voltage V GS of the transistor MN36. In addition, when the potential output from the terminal OP is V OUT , it satisfies V OUT =V in -V Y +V X -V GS .

[0525] Since the transistors MN31 and MN33 are in the off state, the first terminal of the capacitor C1 and the second terminal of the capacitor C2 are in a floating state. In addition, the potentials of the first terminal of the capacitor C1 and the second terminal of the capacitor C2 are maintained by the capacitor C1. That is, Figure 27A the source follower circuit SAM shown is also used as a sample and hold circuit. Therefore, after holding the potential corresponding to the input signal input from the terminal IP in the capacitors C1 and C2, the hold circuit LTC2 for inputting the signal to the terminal IP can be stopped.

[0526] In the source follower circuit SAM, transistors MN31 to MN35, transistor MN37, and transistor MN38 have the function of transferring a signal from terminal IP to terminal OP. Therefore, it is preferable to use transistors with a high driving frequency for the above-mentioned respective transistors. That is to say, it is preferable to use transistor MTHN described in the above Embodiment 1 for transistors MN31 to MN35, transistor MN37, and transistor MN38. Note that when it is desired to improve the voltage tolerance of transistors MN31 to MN35, transistor MN37, and transistor MN38, transistor MTCK can also be used instead of transistor MTHN for the above-mentioned respective transistors.

[0527] In addition, in the level shifter circuit LS, the gate of transistor MN36 is supplied with a voltage that rises due to capacitive coupling. Therefore, it is preferable to use a transistor with high voltage tolerance for transistor MN36. That is to say, it is preferable to use transistor MTCK described in the above Embodiment 1 for transistor MN36. In addition, when it is desired to increase the driving frequency of transistor MN36, transistor MTHN can also be used as transistor MN36 instead of transistor MTCK.

[0528] For example, when it is desired to reduce the amount of current flowing between the source and drain of transistor MN37, transistor MTCK can also be used as transistor MN37. In addition, a transistor with a channel length (for example, the length from the source electrode to the drain electrode in the channel formation region) longer than that of transistor MTCK and transistor MTHN can also be used. Figures 60A to 60C The transistor MTCK1 shown, Figures 61A to 61C The transistor MTHN1 shown, Figures 62A to 62C The transistor MTCK2 shown, and Figures 63A to 63C The transistor MTHN2 shown. In addition, transistor MTCK1, transistor MTHN1, transistor MTCK2, and transistor MTHN2 will be described in Embodiment 4.

[0529] Can be used for Figure 3 Or Figure 4 The circuit of the source follower circuit SAM is not limited to the above Figure 27A The source follower circuit SAM. As the circuit of the source follower circuit SAM that can be used for Figure 3 Or Figure 4 The source follower circuit SAM, a circuit that changes the Figure 27A The source follower circuit SAM can be used.

[0530] For example, it is also possible to Figure 27A Change the source follower circuit SAM to Figure 28 The source follower circuit SAM shown. Figure 28 The source follower circuit shown is the same as Figure 27AThe source follower circuit SAM is different in that Figure 28 In the source follower circuit shown, a switch SWP is provided between the first terminal of the transistor MN36 and the wiring VE22.

[0531] In Figure 28 In the source follower circuit SAM, the first terminal of the switch SWP is electrically connected to the wiring VE22, the second terminal of the switch SWP is electrically connected to the first terminal of the transistor MN36, and the control terminal of the switch SWP is electrically connected to the wiring SWPL.

[0532] As an example, the wiring SWPL is used as a wiring for transmitting a signal for switching the on state or off state of the switch SWP.

[0533] In Figure 28 In the source follower circuit SAM, the switch SWP has a function of making the connection between the wiring VE22 and the first terminal of the transistor MN36 conductive or non-conductive. Therefore, for example, by turning the switch SWP off, the power supply from the wiring VE22 to the first terminal of the transistor MN36 can be stopped, and as a result, Figure 28 the source follower circuit SAM can be temporarily stopped. Therefore, when the operation of Figure 28 the source follower circuit SAM stops, no power is supplied, so the power consumption of the source follower circuit SAM can be reduced.

[0534] <Modified Example> In Figure 3 the drive circuit SD1 shown or Figure 4 the drive circuit SD2 shown, the holding circuit LTC1 and the holding circuit LTC2 are continuously electrically connected. In other words, the first latch circuit LA and the second latch circuit LB are continuously electrically connected. That is, when an image signal is input to the drive circuit SD1 or the drive circuit SD2, the image signal is sent to the amplifier circuit SF side through the first latch circuit LA and the second latch circuit LB, so sometimes the image signal output from the second latch circuit LB is attenuated compared to the image signal input to the drive circuit SD1 or the drive circuit SD2.

[0535] Figure 29A The circuit LTCSF shown has a structure in view of the above problems and has the function of a latch circuit for temporarily holding an image signal and the function of a source follower circuit for amplifying the image signal. In Figure 29A , in order to show the electrical connection structure of the circuit LTCSF, a shift register SR and a conversion circuit CVT are also shown.

[0536] The circuit LTCSF includes a switch SW0, switches SW3a and SW3b, switches SW4a and SW4b, a source follower circuit SAMa, and a source follower circuit SAMb.

[0537] For example, the switches SW0, SW3a, SW3b, and SW4a can all use the switches that can be used for the above-mentioned switch SW1 or switch SW2.

[0538] In this specification and the like, Figure 29A the shown switches SW0, SW3a, SW3b, and SW4a are all in the on state when a high-level potential is supplied to their control terminals and in the off state when a low-level potential is supplied to their control terminals.

[0539] Each of the source follower circuit SAMa and the source follower circuit SAMb can use, for example, Figure 27A the shown source follower circuit SAM.

[0540] The first terminal of the switch SW0 is electrically connected to the wiring VDL, the second terminal of the switch SW0 is electrically connected to the first terminals of the switches SW3a and SW3b, and the control terminal of the switch SW0 is electrically connected to the shift register SR. In particular, the control terminal of the switch SW0 is preferably electrically connected to the second output terminal of the storage circuit RES included in the shift register SR (not shown in Figure 29A ). Here, for convenience, the wiring connecting the switch SW0 and the shift register SR is referred to as the wiring SWL0.

[0541] The second terminal of the switch SW3a is electrically connected to the input terminal of the source follower circuit SAMa, and the control terminal of the switch SW3a is electrically connected to the wiring SWL3a. In addition, the second terminal of the switch SW3b is electrically connected to the input terminal of the source follower circuit SAMb, and the control terminal of the switch SW3b is electrically connected to the wiring SWL3b.

[0542] The first terminal of the switch SW4a is electrically connected to the output terminal of the source follower circuit SAMa, the second terminal of the switch SW4a is electrically connected to the input terminal of the conversion circuit CVT, and the control terminal of the switch SW4a is electrically connected to the wiring SWL4a. In addition, the first terminal of the switch SW4b is electrically connected to the output terminal of the source follower circuit SAMb, the second terminal of the switch SW4b is electrically connected to the input terminal of the conversion circuit CVT, and the control terminal of the switch SW4b is electrically connected to the wiring SWL4b. In particular, the second terminals of the switch SW4a and the switch SW4b are preferably electrically connected to the input terminal of the digital-to-analog conversion circuit DAC included in the conversion circuit CVT (not shown in Fig. 27).

[0543] Next, the operation method of the circuit LTCSF will be described.

[0544] Figure 29B is a timing chart showing Figure 29A an operation example of the circuit LTCSF shown. Figure 29B The timing chart of shows the change in the image signal input to the wiring VDL from time T11 to time T14 and its vicinity, and the potential changes in the wirings SW0, SWL3a, SWL3b, SWL4a, and SWL4b. At Figure 29B In the timing chart of, the high-level potential is denoted as "High" and the low-level potential is denoted as "Low".

[0545] During the period from time T11 to time T12, a high-level potential is input to the control terminal of the switch SW0 from the shift register SR through the wiring SWL0. In addition, the wirings SWL3a and SWL4b are supplied with a high-level potential, and the control terminals of the switch SW3a and the switch SW4b are supplied with a high-level potential. Further, the wirings SWL3b and SWL4a are supplied with a low-level potential, and the control terminals of the switch SW3b and the switch SW4a are supplied with a low-level potential.

[0546] Therefore, the switches SW0, SW3a, and SW4b become in the on state, and the switches SW3b and SW4a become in the off state.

[0547] During the period from time T11 to time T12, the image signal SIG[1] is input from the wiring VDL to the first terminal of the switch SW0. Thereby, the image signal SIG[1] is input to the source follower circuit SAMa through the switch SW0 and the switch SW3a. Thereby, for example, the potential corresponding to the image signal SIG[1] is held at Figure 27A the first terminal of the capacitor C1 and the second terminal of the capacitor C2 shown, and the amplified image signal SIG[1] is output from the output terminal (terminal OP) of the source follower circuit SAMa. Since the switch SW4a is in the off state, the image signal SIG[1] output from the output terminal (terminal OP) of the source follower circuit SAMa does not reach the conversion circuit CVT.

[0548] On the other hand, the image signal held in the source follower circuit SAMb before time T11 is input to the conversion circuit CVT from the output terminal of the source follower circuit SAMb through the switch SW4b, for example. Therefore, during the period from time T11 to time T12, this image signal is converted from digital data to analog data and input to the pixel circuit PX of the pixel array PXA.

[0549] During the period from time T13 to time T14, a high-level potential is input to the control terminal of switch SW0 from the shift register SR through the wiring SWL0. In addition, the wiring SWL3b and the wiring SWL4a are supplied with a high-level potential, and a high-level potential is input to both the control terminal of switch SW3b and the control terminal of switch SW4a. In addition, the wiring SWL3a and the wiring SWL4b are supplied with a low-level potential, and a low-level potential is input to both the control terminal of switch SW3a and the control terminal of switch SW4b.

[0550] Therefore, switch SW0, switch SW3b, and switch SW4a are in an open state, and switch SW3a and switch SW4b are in a closed state.

[0551] During the period from time T13 to time T14, the image signal SIG[2] is input from the wiring VDL to the first terminal of switch SW0. Thus, the image signal SIG[2] is input to the source follower circuit SAMb through switch SW0 and switch SW3b. Thus, for example, the potential corresponding to the image signal SIG[2] is held at Figure 27A the first terminal of the capacitor C1 and the second terminal of the capacitor C2 shown, and the amplified image signal SIG[2] is output from the output terminal (terminal OP) of the source follower circuit SAMb. Since switch SW4b is in a closed state, the image signal SIG[2] output from the output terminal (terminal OP) of the source follower circuit SAMb does not reach the conversion circuit CVT.

[0552] On the other hand, the image signal SIG[1] held in the source follower circuit SAMa is input to the conversion circuit CVT through switch SW4a from the output terminal of the source follower circuit SAMa, for example, during the period from time T11 to time T12. Therefore, during the period from time T13 to time T14, the image signal SIG[1] is converted from digital data to analog data and input to the pixel circuit PX of the pixel array PXA.

[0553] As described above, by electrically connecting the source follower circuit SAMa having the function of holding the potential corresponding to the signal input thereto in parallel with the source follower circuit SAMb, the signal input can be held by one source follower circuit and the signal held in advance can be output by the other source follower circuit. As Figure 3 or Figure 4 shown, in a structure in which the first latch circuit LA and the second latch circuit LB are electrically connected in series, attenuation of the image signal sometimes occurs, but by using the above circuit LTCSF, the image signal can be temporarily held and attenuation of the image signal can be prevented.

[0554] The semiconductor device according to one embodiment of the present invention is not limited to the above circuit structures. The semiconductor device according to one embodiment of the present invention may also adopt a structure in which the above circuits are appropriately changed.

[0555] Note that this embodiment can be appropriately combined wit...

Claims

1. A semiconductor device, comprising: A shift register; And A source follower circuit, Wherein, the shift register includes a first transistor, The source follower circuit includes a second transistor, The first transistor and the second transistor include a first insulator, The first transistor includes a first gate insulating film, The second transistor includes a second gate insulating film, The first transistor has a first channel formation region along a side surface of a first opening formed in the first insulator, The second transistor has a second channel formation region along a side surface of a second opening formed in the first insulator, The first gate insulating film is located above the first channel formation region when viewed in plan, The second gate insulating film is located above the second channel formation region when viewed in plan, And, the thickness of the second gate insulating film is thicker than the thickness of the first gate insulating film.

2. The semiconductor device according to claim 1, Wherein the first gate insulating film includes a second insulator, The second gate insulating film includes the second insulator and a third insulator, And the third insulator is located on the second insulator.

3. The semiconductor device according to claim 2, further comprising a latch circuit, Wherein the latch circuit includes a third transistor, The third transistor includes a third gate insulating film, The third transistor has a third channel formation region along a side surface of a third opening formed in the first insulator, The third gate insulating film is located above the third channel formation region when viewed in plan, And the third gate insulating film includes the second insulator.

4. The semiconductor device according to claim 3, further comprising a level converter circuit, Wherein the level converter circuit includes a fourth transistor, The fourth transistor includes a fourth gate insulating film, The fourth transistor has a fourth channel formation region along a side surface of a fourth opening formed in the first insulator, The fourth gate insulating film is located above the fourth channel formation region when viewed in plan, And the fourth gate insulating film includes the second insulator and the third insulator.

5. The semiconductor device according to claim 4, Wherein the first channel formation region to the fourth channel formation region all contain one or more selected from indium, zinc, and element M, And the element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

6. The semiconductor device according to claim 5, Wherein the taper angle of each side surface of the first opening to the fourth opening is 70° or more and 110° or less.

7. A display device, comprising: The semiconductor device according to claim 6; And A pixel circuit, Wherein, the pixel circuit includes a driving transistor, The driving transistor includes a fifth gate insulating film, The driving transistor has a fifth channel formation region above the first insulator, The fifth gate insulating film is located above the fifth channel formation region when viewed in plan, And, the fifth gate insulating film includes the second insulator and the third insulator.

8. The display device according to claim 7, wherein the fifth channel formation region contains one or more selected from indium, zinc, and the element M.

9. The display device according to claim 8, wherein the pixel circuit includes a light-emitting device, and the light-emitting device contains an organic EL material.

10. An electronic device including the display device according to claim 9 and a housing.

11. A semiconductor device, comprising: a first transistor; a second transistor; a third transistor; and a fourth transistor, wherein each of the first transistor to the fourth transistor includes a first conductor located below a first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film, the gate insulating films of the first transistor and the second transistor are thicker than the gate insulating films of the third transistor and the fourth transistor, one of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor, and, one of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor.

12. The semiconductor device according to claim 11, wherein the gate insulating films of the first transistor and the second transistor both include a second insulator, the gate insulating films of the third transistor and the fourth transistor both include the second insulator and a third insulator, and the third insulator is located on the second insulator.

13. The semiconductor device according to claim 12, further including a first circuit, wherein the first circuit includes a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal is electrically connected to the gate electrode of the first transistor, the second terminal is electrically connected to the gate electrode of the second transistor, the third terminal is electrically connected to the gate electrode of the third transistor, the fourth terminal is electrically connected to the gate electrode of the fourth transistor, and the first circuit has a function of outputting one of a high-level potential and a low-level potential to each of the first terminal and the third terminal and a function of outputting the other of the high-level potential and the low-level potential to each of the second terminal and the fourth terminal.

14. A semiconductor device, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first capacitor; and a second capacitor, Among them, each of the first transistor to the sixth transistor includes a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first transistor, the second transistor, and the fifth transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, and the sixth transistor. One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor. The gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor and the other of a pair of terminals of the first capacitor. One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor. The gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor and the other of a pair of terminals of the second capacitor. The other of the first conductor and the second conductor of the fifth transistor is electrically connected to the other of the first conductor and the second conductor of the sixth transistor. Moreover, the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.

15. The semiconductor device according to claim 14, wherein the gate insulating films of the first transistor, the second transistor, and the fifth transistor each include a second insulator. The gate insulating films of the third transistor, the fourth transistor, and the sixth transistor each include the second insulator and a third insulator. And the third insulator is located on the second insulator.

16. The semiconductor device according to claim 15, further comprising a first circuit. Wherein the first circuit includes a first terminal and a second terminal. The first terminal is electrically connected to the other of the first conductor and the second conductor of the fifth transistor and the other of the first conductor and the second conductor of the sixth transistor. The second terminal is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the first circuit has a function of outputting one of a high-level potential and a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal.

17. A semiconductor device, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; The seventh transistor; The eighth transistor; The first capacitor; And The second capacitor, wherein, the first transistor to the eighth transistor each include a first conductor located below a first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film; the gate insulating films of the first transistor, the second transistor, the fifth transistor, and the seventh transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor; one of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor; the gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitor, and one of the first conductor and the second conductor of the seventh transistor; one of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor; the gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor, the other of the pair of terminals of the second capacitor, and one of the first conductor and the second conductor of the eighth transistor; the other of the first conductor and the second conductor of the fifth transistor is electrically connected to the gate electrode of the fifth transistor, the other of the first conductor and the second conductor of the sixth transistor, and the gate electrode of the sixth transistor; and, the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.

18. The semiconductor device according to claim 17, wherein the gate insulating films of the first transistor, the second transistor, the fifth transistor, and the seventh transistor each include a second insulator; the gate insulating films of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor each include the second insulator and a third insulator; and the third insulator is located on the second insulator.

19. The semiconductor device according to claim 15, further comprising a first circuit, wherein the first circuit includes a first terminal and a second terminal; the first terminal is electrically connected to the other of the first conductor and the second conductor of the fifth transistor and the other of the first conductor and the second conductor of the sixth transistor; The second terminal is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. Moreover, the first circuit has a function of outputting either a high-level potential or a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal.

20. A semiconductor device, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a ninth transistor; a first capacitor; and a second capacitor, wherein each of the first transistor to the sixth transistor and the ninth transistor includes a first conductor located below a first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with side surfaces of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film. The gate insulating films of the first transistor, the second transistor, the fifth transistor, and the ninth transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, and the sixth transistor. One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor. The gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitor, and the gate electrode of the ninth transistor. One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor. The gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor and the other of the pair of terminals of the second capacitor. The other of the first conductor and the second conductor of the fifth transistor is electrically connected to the other of the first conductor and the second conductor of the sixth transistor and one of the first conductor and the second conductor of the ninth transistor. Moreover, the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.

21. The semiconductor device according to claim 20, wherein the gate insulating films of the first transistor, the second transistor, the fifth transistor, and the ninth transistor each include a second insulator. The gate insulating films of the third transistor, the fourth transistor, and the sixth transistor each include the second insulator and a third insulator. Moreover, the third insulator is located on the second insulator.

22. The semiconductor device according to claim 21, further comprising a first circuit. Wherein the first circuit includes a first terminal and a second terminal, The first terminal is electrically connected to the other of the first conductor and the second conductor of the fifth transistor and the other of the first conductor and the second conductor of the sixth transistor, The second terminal is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, And the first circuit has a function of outputting one of a high-level potential and a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal.

23. A semiconductor device, comprising: A first transistor; A second transistor; A third transistor; A fourth transistor; A fifth transistor; A sixth transistor; A seventh transistor; An eighth transistor; A first capacitor; And A second capacitor, Wherein, the first transistor to the eighth transistor each include a first conductor located below the first insulator and serving as one of a source and a drain, a second conductor located above the first insulator and serving as the other of the source and the drain, a semiconductor in contact with a side surface of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film, The gate insulating films of the first transistor, the second transistor, the fifth transistor and the seventh transistor are thicker than the gate insulating films of the third transistor, the fourth transistor, the sixth transistor and the eighth transistor, One of the first conductor and the second conductor of the first transistor is electrically connected to one of the first conductor and the second conductor of the second transistor and one of a pair of terminals of the first capacitor, The gate electrode of the first transistor is electrically connected to one of the first conductor and the second conductor of the fifth transistor, the other of a pair of terminals of the first capacitor, and one of the first conductor and the second conductor of the seventh transistor, One of the first conductor and the second conductor of the third transistor is electrically connected to one of the first conductor and the second conductor of the fourth transistor and one of a pair of terminals of the second capacitor, The gate electrode of the third transistor is electrically connected to one of the first conductor and the second conductor of the sixth transistor, the other of a pair of terminals of the second capacitor, and one of the first conductor and the second conductor of the eighth transistor, The gate electrode of the fifth transistor is electrically connected to the gate electrode of the sixth transistor, And the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.

24. The semiconductor device according to claim 23, Wherein the gate insulating films of the first transistor, the second transistor, the fifth transistor and the seventh transistor each include a second insulator, The gate insulating films of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor each include the second insulator and the third insulator, and the third insulator is located on the second insulator.

25. The semiconductor device according to claim 24, further comprising a first circuit, wherein the first circuit includes a first terminal and a second terminal, the first terminal is electrically connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor, the second terminal is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the first circuit has a function of outputting either a high-level potential or a low-level potential to the first terminal and a function of outputting the other of the high-level potential and the low-level potential to the second terminal.

26. The semiconductor device according to any one of claims 11 to 25, wherein the taper angle of each side of each of the openings is 70° or more and 110° or less.

27. The semiconductor device according to claim 26, wherein the channel formation region of each of the semiconductors contains one or more selected from indium, zinc, and element M, and element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

28. A display device including a driving circuit having the semiconductor device according to claim 27 and a display unit.

29. The display device according to claim 28, wherein the display unit includes a pixel circuit having any one of a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode.

30. An electronic device including the display device according to claim 29 and a housing.

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