Semiconductor device and semiconductor device manufacturing method

Abstract

The present technology relates to a semiconductor device and a semiconductor device manufacturing method capable of preventing a reduction in bonding strength between semiconductor devices stacked on each other when the semiconductor devices are stacked on each other. Each of the semiconductor devices is provided with: a first electrode covered with a first insulating film; and a second electrode covered by the first insulating film and a second insulating film made of a material different from that of the first insulating film. At least one of the side surfaces of the second electrode is covered by the second insulating film, and the remaining side surfaces of the side surfaces of the second electrode are covered by the first insulating film. For example, the present technology can be applied to a semiconductor device in which, when a plurality of semiconductor devices are stacked on each other, each of the semiconductor devices is to be subjected to an inspection for determining whether or not the semiconductor devices are qualified products before stacking.

Description

Technical Field

[0001] The present technology relates to a semiconductor device and a method for manufacturing a semiconductor device. For example, it relates to a semiconductor device and a method for manufacturing a semiconductor device suitable for chips to be stacked. Background Art

[0002] For example, in an imaging device including imaging elements such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a CCD (Charge Coupled Device) image sensor, a technique using a stacked structure has been proposed, in which a chip on which an imaging element is formed and a logic circuit for processing signals transmitted from the imaging element are stacked on each other (for example, see Patent Document 1). [Citation List] [Patent Document]

[0003] [Patent Document 1] PCT Patent Application Publication No. WO2015 / 159766 Summary of the Invention [Technical Problem to be Solved]

[0004] In the case of adopting a stacked structure in which a plurality of chips are stacked, the following technical solution has been proposed: at a stage before stacking each chip, a determination is made as to whether each chip is a qualified product or a defective product, and the chips determined to be qualified products are used for stacking. When determining whether a chip is a qualified product, it is necessary to bring a test probe into contact with a test pad, but the probe in contact may cause irregularities on the electrode of the pad.

[0005] When processing a chip having irregularities and stacking it on another chip, the connection strength between the chips may be reduced.

[0006] The present technology has been made in view of the above circumstances, and the present technology can prevent a reduction in connection strength. [Technical Solution for Solving the Problem]

[0007] A semiconductor device according to one aspect of the present technology includes: a first electrode covered with a first insulating film; and a second electrode covered with the first insulating film and a second insulating film made of a material different from the first insulating film.

[0008] A method of manufacturing a semiconductor device according to another aspect of the present technology includes: removing the conductive material of the spacer located in the opening, and before the removal, when performing an inspection for determining whether the semiconductor device is a qualified product, the inspection needle will abut against the conductive material of the spacer located in the opening; forming a second insulating film on the region including the region where the conductive material has been removed, the second insulating film being made of a material different from the first insulating film formed on the conductive material of the spacer; and planarizing the thus formed second insulating film.

[0009] In a semiconductor device according to one aspect of the present technology, a first electrode and a second electrode are provided, the first electrode is covered with a first insulating film, and the second electrode is covered with the first insulating film and a second insulating film made of a material different from the first insulating film.

[0010] In a method of manufacturing a semiconductor device according to another aspect of the present technology, the conductive material of the spacer located in the opening is removed, and before the removal, when performing an inspection for determining whether the semiconductor device is a qualified product, the inspection needle will abut against the conductive material of the spacer located in the opening; a second insulating film is formed on the region including the region where the conductive material has been removed, the second insulating film being made of a material different from the first insulating film formed on the conductive material of the spacer; and the thus formed second insulating film is planarized.

[0011] Note that the semiconductor device can be a separate device or can also be an internal module for constituting a device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing the structure of an embodiment of a semiconductor device to which the present technology is applied. Figure 2 is a diagram showing the semiconductor device during inspection. Figure 3 Diagrams are shown for respectively explaining the convex portions generated after the inspection. Figure 4 Diagrams are shown for explaining the manufacturing process of the semiconductor device according to the first embodiment. Figure 5 is a diagram showing a structural example of the semiconductor device according to the first embodiment. Figure 6 is a diagram showing a structural example of the semiconductor device according to the second embodiment. Figure 7 Diagrams are shown for explaining the manufacturing process of the semiconductor device according to the second embodiment. Figure 8This is a diagram showing a structural example of a semiconductor device according to the third embodiment. Figure 9 This is a diagram for explaining the manufacturing process of a semiconductor device according to the third embodiment. Figure 10 This is a diagram showing a structural example of a semiconductor device according to the fourth embodiment. Figure 11 This is a diagram showing the manufacturing process of a semiconductor device according to the fourth embodiment. Figure 12 This is a diagram showing a structural example of a semiconductor device according to the fifth embodiment. Figure 13 This is a diagram showing a structural example of a semiconductor device according to the sixth embodiment. Figure 14 This is a diagram showing a structural example of a semiconductor device according to the seventh embodiment. Figure 15 This is a diagram showing a structural example of an electronic device. Detailed Description

[0013] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described.

[0014] <Structure of the Semiconductor Device According to the First Embodiment> Figure 1 This is a diagram showing the structure of an embodiment of a semiconductor device to which the present technology is applied. Figure 1 The illustrated semiconductor device 10a can be applied to: imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Device) image sensors; memories for storing signals from the imaging elements; processing circuits for processing signals from the imaging elements; and AI circuits for performing artificial intelligence (AI) processing, etc.

[0015] Figure 1 This shows a part related to the electrodes and wirings of the semiconductor device 10a and will be described here. The semiconductor device 10a has an electrode 12 formed in a semiconductor substrate 11. On Figure 1 the upper surface of the semiconductor substrate 11 in, a pad electrode and a wiring electrode 18 are provided.

[0016] Except for the parts to be described later, the spacer electrode 17 and the wiring electrode 18 basically have the same structure. Each of the spacer electrode 17 and the wiring electrode 18 has a stacked barrier metal 13, an aluminum (Al) film 14, and a titanium film 15.

[0017] As the barrier metal 13, for example, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), nitride films of these elements, or carbide films of these elements can be used. Instead of the aluminum film 14, metal (conductor) films such as cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), or gold (Au) can be used.

[0018] Figure 1 The upper surface of the spacer electrode 17 and one of the left and right side surfaces in the spacer electrode 17 are covered by the first insulating film 19, and the other of the left and right side surfaces of the spacer electrode 17 is covered by the second insulating film 20. The wiring electrode 18 is covered by the first insulating film 19, and the first insulating film 19 is covered by the second insulating film 20.

[0019] Here, it is assumed that the first insulating film 19 is an insulating film with high embeddability. As the first insulating film 19, for example, inorganic or organic oxide films such as high density plasma (HDP) or spin on glass (SOG) can be used. As the second insulating film 20, for example, plasma tetraethyl orthosilicate (pTEOS) can be used.

[0020] <Steps generated during manufacturing in the spacer portion> Figure 2 An enlarged view of the spacer electrode 17 during manufacturing is shown. As Figure 2 shown, the spacer electrode 17 is connected to the electrode 12 provided in the semiconductor substrate 11, and the electrode 12 is connected to the wiring 31 provided in the semiconductor substrate 11. The spacer electrode 17 forms a pad portion 51: during the manufacturing process, the inspection needle 61 abuts against this pad portion.

[0021] The pad portion 51 serves as a pad for inspection. The opening of the pad portion 51 is in a state where the aluminum film 14 is exposed, that is, in a state where the first insulating film 19 on the aluminum film 14 has been removed. Note that the second insulating film 20 has not been deposited during inspection.

[0022] The spacer portion 51 includes: an opening portion that exposes the aluminum film 14; and a spacer electrode 17. The first insulating film 19 is laminated on the spacer electrode 17, and the spacer electrode 17 is connected to the aluminum film 14 in the opening portion. In the following description, when describing the spacer portion 51, there are cases where the spacer portion 51 includes the spacer electrode 17 and cases where the spacer portion 51 includes only the opening portion.

[0023] When the inspection needle 61 is brought into contact with the exposed aluminum film 14 for inspection, it can be determined whether the semiconductor device 10a is a qualified product, and only the semiconductor device 10a determined to be a qualified product can be laminated with another semiconductor device. When the second insulating film 20 is deposited on the spacer portion 51 after inspection, film formation of the spacer portion 51 with the second insulating film 20 is achieved.

[0024] Refer to Figure 3 , and now the unevenness generated in the spacer portion 51 during inspection will be described. When the inspection needle 61 is brought into contact with the aluminum film 14 during inspection, as shown in A of Figure 3 , it is possible that a trace 71 of the needle 61 remains on the aluminum film 14' (here, the aluminum film 14' is described by adding a superscript symbol to the aluminum film 14 in order to distinguish the aluminum film 14' from the aluminum film 14 of the semiconductor device 10a to which this technology is applied). Since the trace 71 remains, for example, as shown in A of Figure 3 , a convex portion 72 may be formed, where the aluminum film 14' has a convex shape at the convex portion 72.

[0025] Although Figure 3 A of shows the case where the convex portion 72 is formed on the right side in this figure, there are also various other cases, such as the case where the convex portion 72 is formed on the left side and the case where the convex portion 72 is formed on both the left and right sides, etc. As described above, when the second insulating film 20 is formed in the case where the convex portion 72 is formed, the state shown in B of Figure 3 is obtained. In the spacer portion 51, the second insulating film 20 is formed on the aluminum film 14'. Since the aluminum film 14' has the trace 71 of the needle 61 and the convex portion 72, the second insulating film 20 cannot be formed uniformly.

[0026] For example, in the case where the convex portion 72 has a shape protruding from the second insulating film 20, when the semiconductor device 10a' and another semiconductor device are laminated with each other, connection failure may occur. Due to the unevenness generated in the spacer portion 51, when the second insulating film 20 is formed on the spacer portion 51, a space is generated in the second insulating film 20 formed on the spacer portion 51, resulting in a reduction in the bonding strength and possibly causing peeling.

[0027] <Manufacturing Process According to the First Embodiment> Now refer to Figure 4, a manufacturing process will be described to prevent a decrease in bonding strength due to unevenness generated on the aluminum film 14 during manufacturing as described with reference to Figure 3 .

[0028] Figure 4 FIG. shows a manufacturing process of a semiconductor device 10a according to a first embodiment. Step S11 shows the pad portion 51 of the semiconductor device 10a obtained after the inspection needle 61 for inspection is brought into contact and the inspection is performed, and this step corresponds to Figure 3 the semiconductor device 10a in the state shown in A. The first insulating film 19 is in a state where portions other than the necessary portions have been removed after the formation of the first insulating film.

[0029] As the first insulating film 19, as described above, an HDP (High Density Plasma) film having high burying property deposited by HDP CVD (High Density Plasma Chemical Vapor Deposition) method can be used. The HDP film is formed by a chemical vapor deposition process using a high density plasma or by a device for implementing a chemical vapor deposition process. Since a high density plasma is used, the decomposition efficiency of the source gas is high, and a high film formation rate is obtained. At the same time, since the ion density in the plasma is also high, the process further proceeds to apply a bias voltage to the substrate wafer, and these ions are actively incorporated into the substrate wafer, thereby allowing sputtering of the protrusions or corners of the deposited film, and also providing a self-planarization function. Therefore, when forming an interlayer insulating film for fine multilayer wirings, the burying property and flatness between wirings can be improved.

[0030] In step S12, the aluminum film 14 and the barrier metal 13 in the region of the pad portion 51 are removed by etching. By etching with the opening pattern of the pad portion 51, the aperture ratio can be increased, and the difference between the sparse pattern and the dense pattern can be reduced compared with the conventional technology.

[0031] In step S13, a second insulating film 20 is formed. For example, p TEOS can be used for deposition as the second insulating film 20. In step S14, for example, the second insulating film 20 is planarized by chemical mechanical polishing (CMP: Chemical Mechanical Polishing). CMP is performed on the global steps, so that planarization with a small deviation in film thickness within the wafer surface can be achieved.

[0032] As described above, unevenness such as traces 71 of pins 61 and protrusions 72 caused by contacting the pins 61 on the aluminum film 14 are removed by etching, thereby flattening it, and then the second insulating film 20 is formed, so that the generation of voids in the second insulating film 20 can be prevented, and peeling can be prevented when another semiconductor device is stacked on the second insulating film 20.

[0033] Through the above manufacturing process, the Figure 1 shown semiconductor device 10a is manufactured. Hereinafter, with reference to Figure 5 , the pad electrode 17 and the wiring electrode 18 will be described again.

[0034] Figure 5 is Figure 1 an enlarged view of a portion corresponding to the pad portion 51 and a portion where the wiring electrode 18 is disposed in the shown semiconductor device 10a. Since the aluminum film 14 and the barrier metal 13 have been removed by etching in step S12 (see Figure 4 ), the opening of the pad portion 51 is in a state where only the second insulating film 20 is formed.

[0035] Before performing the etching, the aluminum film 14 in the pad portion 51 is in the form of a single continuous film. However, after the etching, the aluminum film 14 is in a state of being divided into a part formed in the pad electrode 17-1 and another part formed in the pad electrode 17-2. Figure 5 The upper surface and the left side surface of the pad electrode 17-1 in Figure 5 are covered with the first insulating film 19, but Figure 5 the right side surface of the pad electrode 17-1 in Figure 5 is not covered with the first insulating film 19, but is covered with the second insulating film 20. Similarly,

[0036] On the other hand, Figure 5 the upper surface, the left side surface, and the right side surface of the wiring electrode 18 in

[0037] are all covered with the first insulating film 19.

[0038] The surfaces of the spacer electrode 17 and the wiring electrode 18 that come into contact with the semiconductor substrate 11 are referred to as the lower surfaces, and the upper surface, left side surface, and right side surface other than the lower surface are focused on. One of the upper surface, left side surface, and right side surface of the spacer electrode 17 is covered with an insulating film made of a material different from the insulating films on the other two surfaces. The upper surface, left side surface, and right side surface of the wiring electrode 18 are all covered with an insulating film of the same material. In this way, the spacer electrode 17 is covered with insulating films of different materials, while the wiring electrode 18 is covered with an insulating film of the same material.

[0039] Although the side surfaces of the spacer electrode 17 are covered with different insulating films, the side surfaces of the wiring electrode 18 are covered with the same insulating film.

[0040] At least one of the electrodes formed in the semiconductor device 10a is configured to be covered with two or more different insulating films.

[0041] Note that, as an example, here it has been described that when the substantially central portion of the spacer portion 51 is used as the opening portion, by removing the material for forming the electrode such as the aluminum film 14 in the opening portion, the spacer electrodes 17-1 and 17-2 are left. However, the following configuration may also be adopted: where the opening portion is provided on the left side or the right side of the spacer portion 51, and by removing the material for forming the electrode such as the aluminum film 14 in the opening portion, the spacer electrode 17-1 or the spacer electrode 17-2 is left.

[0042] <Configuration of the semiconductor device according to the second embodiment> Figure 6 is a diagram showing a structural example of the semiconductor device 10b according to the second embodiment. Although Figure 6 only the region where the spacer electrode 17b and the wiring electrode 18 are located in the semiconductor device 10b is shown, the basic structure of the semiconductor device 10b is the same as Figure 1 and Figure 6 the basic structure of the semiconductor device 10a shown. In the following description, components that are the same as those of the semiconductor device 10a according to the first embodiment are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0043] According to Figure 6 the semiconductor device 10b according to the second embodiment shown is different from the semiconductor device 10a according to Figure 6 the first embodiment shown in that a barrier metal 13b is formed in the opening portion of the spacer portion 51b, but the semiconductor device 10b is the same as the semiconductor device 10a in other respects.

[0044] The barrier metal 13b in the gasket portion 51b of the semiconductor device 10b is formed in a continuous state over the region from the gasket electrode 17b-1 to the gasket electrode 17b-2. In this way, the barrier metal 13b can be left in the opening portion of the gasket portion 51b.

[0045] <Manufacturing process according to the second embodiment> Figure 7 The figure shows the manufacturing process of the semiconductor device 10b according to the second embodiment. Step S21 shows the gasket portion 51b of the semiconductor device 10b obtained after the inspection needle 61 is brought into contact and the inspection is performed, and this step corresponds to Figure 3 the semiconductor device 10b in the state shown in B of. The first insulating film 19 is in a state where portions other than the necessary portions have been removed after the formation of the first insulating film.

[0046] In step S22, the aluminum film 14 in the region of the gasket portion 51b is removed by etching. In step S22, the aluminum film 14 is etched in such a way as to leave the barrier metal 13b, thereby leaving the barrier metal 13b.

[0047] In step S23, the second insulating film 20 is formed. In step S24, the second insulating film 20 is planarized, for example, by CMP. Since steps S21, S23, and S24 are substantially the same as Figure 4 the steps S11, S13, and S14 shown, their detailed description is omitted.

[0048] As described above, irregularities such as the trace 71 of the needle 61 and the convex portion 72 generated due to the contact of the needle 61 on the aluminum film 14 are removed by etching, thereby making it flat, and then the second insulating film 20 is formed, so that the generation of spaces in the second insulating film 20 can be prevented, and peeling can be prevented when another semiconductor device is laminated on the second insulating film 20.

[0049] Through the above manufacturing process, the Figure 6 shown semiconductor device 10b is manufactured. Hereinafter, it will be described again with reference to Figure 6 Before the etching is performed, the aluminum film 14 in the gasket portion 51 is in the form of a single continuous film. However, after the etching, the aluminum film 14 is in a state of being divided into a part formed in the gasket electrode 17b-1 and another part formed in the gasket middle electrode 17b-2. Figure 6 The upper surface and the left side surface of the gasket electrode 17b-1 in are covered with the first insulating film 19, but Figure 6 the right side surface of the gasket electrode 17b-1 in is not covered with the first insulating film 19 but is covered with the second insulating film 20. Similarly, Figure 6The upper surface and the right side surface of the spacer electrode 17b-2 in Figure 6 are covered by the first insulating film 19, but

[0050] the left side surface of the spacer electrode 17b-2 in

[0051] is not covered by the first insulating film 19, but is covered by the second insulating film 20.

[0052] <Configuration of the semiconductor device according to the third embodiment> Figure 8 is a diagram showing a structural example of the semiconductor device 10c according to the third embodiment. Although Figure 8 only the region where the spacer electrode 17c and the wiring electrode 18 are located in the semiconductor device 10c is shown, the basic configuration of the semiconductor device 10c is the same as Figure 1 and Figure 5 the basic configuration of the semiconductor device 10a shown.

[0053] According to Figure 8 the semiconductor device 10c according to the third embodiment shown in Figure 5 differs from the semiconductor device 10a according to the first embodiment shown in

[0054] that an aluminum film 14c is retained in the opening of the spacer portion 51c, but the semiconductor device 10c is otherwise the same as the semiconductor device 10a.

[0055] The convex portion 72 can be removed by etching so that the vertex of the convex portion 72 of the aluminum film 14c is located at a position lower than the interface between the first insulating film 19 and the second insulating film 20. The film thickness of the first insulating film 19 can be made thicker so that the interface between the first insulating film 19 and the second insulating film 20 is located at a higher position and the vertex of the convex portion 72 is located at a position lower than the interface between the first insulating film 19 and the second insulating film 20.

[0056] <Manufacturing process according to the third embodiment> Figure 9 The figure shows the manufacturing process of the semiconductor device 10c according to the third embodiment. Step S31 shows the semiconductor device 10c obtained after the inspection needle 61 is brought into contact and the inspection is performed, and this step corresponds to the state where the convex portion 72 exists in the gasket portion 51c.

[0057] In step S32, a part of the aluminum film 14c in the area of the gasket portion 51c is removed by etching. In step S32, the convex portion 72 of the aluminum film 14c is etched until the vertex of the convex portion 72 of the aluminum film 14c is located at a position lower than the interface between the first insulating film 19 and the second insulating film 20.

[0058] In step S33, the second insulating film 20 is formed. In step S34, the second insulating film 20 is planarized by CMP, for example. Since steps S31, S33, and S34 are substantially the same as Figure 4 the steps S11, S13, and S14 shown, their detailed description is omitted.

[0059] As described above, by removing a part of the convex portion 72 generated by bringing the needle into contact and then forming the second insulating film 20, it is possible to prevent the generation of a space in the second insulating film 20 and prevent peeling when another semiconductor device is laminated on the second insulating film 20.

[0060] Through the above manufacturing process, the Figure 8 shown semiconductor device 10c is manufactured. Referring to Figure 8 again for description. Even before the etching is performed, the vertex of the convex portion 72 of the aluminum film 14c in the gasket portion 51 is located at a position higher than the interface between the first insulating film 19 and the second insulating film 20, but after the etching is performed, the vertex of the convex portion 72 is also in a state of being located at a position lower than the interface between the first insulating film 19 and the second insulating film 20.

[0061] Figure 8 The upper surface and the left side surface of the gasket electrode 17c-1 in are covered by the first insulating film 19, but Figure 8The right surface of the spacer electrode 17c-1 in [the figure] is not covered by the first insulating film 19, but is covered by the second insulating film 20. Similarly, Figure 8 the upper surface and the right surface of the spacer electrode 17c-2 in [the figure] are covered by the first insulating film 19, but Figure 8 the left surface of the spacer electrode 17c-2 in [the figure] is not covered by the first insulating film 19, but is covered by the second insulating film 20.

[0062] The upper surface and one of the side surfaces of the spacer electrode 17c are covered by an insulating film made of a material different from that of the insulating film on the other side surface. In addition, the upper surface and each side surface of the wiring electrode 18 are covered by an insulating film of the same material. In this way, the spacer electrode 17c is covered by insulating films of different materials, but the wiring electrode 18 is covered by an insulating film of the same material. Although each side surface of the spacer electrode 17c is covered by a different insulating film, each side surface of the wiring electrode 18 is covered by the same insulating film.

[0063] At least one of the electrodes formed in the semiconductor device 10c is configured to be covered by two or more different insulating films.

[0064] <Configuration of the semiconductor device according to the fourth embodiment> Figure 10 is a diagram showing a structural example of the semiconductor device 10d according to the fourth embodiment. Although Figure 10 only the region where the spacer electrode 17d and the wiring electrode 18 are located in the semiconductor device 10d is shown in [the figure], the basic configuration of the semiconductor device 10d is the same as Figure 1 and Figure 5 the basic configuration of the semiconductor device 10a shown.

[0065] According to Figure 10 the semiconductor device 10d according to the fourth embodiment shown in [the figure] is different from the conductor device 10a according to the first embodiment shown in Figure 5 that the first insulating film 19 and the second insulating film 20 are made of the same material, and a liner film 101 is formed between the first insulating film 19 and the second insulating film 20, but the semiconductor device 10d is the same as the semiconductor device 10a in other aspects.

[0066] In the opening of the spacer portion 51d of the semiconductor device 10d, a liner film 101 is formed on the semiconductor substrate 11, and a second insulating film 20d made of the same material as the first insulating film 19 is formed on the liner film 101.

[0067] Note that, similar to the second embodiment, a structure in which the barrier metal 13 is retained, a lining film 101 is formed on the barrier metal 13, and a second insulating film 20d is formed on the lining film 101 can also be adopted. In addition, similar to the third embodiment, a structure in which the barrier metal 13 and the aluminum film 14 are retained, a lining film 101 is formed on the aluminum film 14, and a second insulating film 20d is formed on the lining film 101 can also be adopted.

[0068] <Manufacturing process according to the fourth embodiment> Figure 11 The figure shows the manufacturing process of the semiconductor device 10d according to the fourth embodiment. Step S41 shows the semiconductor device 10d obtained after the inspection needle 61 is brought into contact and the inspection is performed. At this time, the semiconductor device 10d is in a state where the aluminum film 14 contains the convex portion 72 as a part thereof.

[0069] In step S42, the aluminum film 14 and the barrier metal 13 in the region corresponding to the opening of the spacer portion 51 are removed by etching. In step S42, the second embodiment can also be applied to step S42. At this time, by using the same process as step S22, only the aluminum film 14 can be removed by etching. In step S42, the third embodiment can also be applied to step S42. At this time, by using the same process as step S32, only a part of the convex portion 72 of the aluminum film 14 can be removed by etching.

[0070] In step S43, a lining film 101 is formed on the first insulating film 19 and on the semiconductor substrate 11 exposed from the opening of the spacer portion 51d.

[0071] In step S44, a second insulating film 20d is formed. In step S45, the second insulating film 20d is planarized by CMP, for example. Since steps S41, S42, S44, and S45 are substantially the same as Figure 4 the steps S11, S12, S13, and S14 shown, their detailed description is omitted.

[0072] As described above, irregularities such as the trace 71 of the needle 61 and the convex portion 72 generated by bringing the needle 61 into contact on the aluminum film 14 are removed by etching, thereby making it flat, and then the lining film 101 and the second insulating film 20d are formed, so that it is possible to prevent the generation of a space in the second insulating film 20 and to prevent peeling when another semiconductor device is stacked on the second insulating film 20.

[0073] Through the above manufacturing process, the Figure 10 shown semiconductor device 10d is manufactured. Referring again to Figure 10This will be described below. Before performing etching, the aluminum film 14 in the spacer portion 51 is in the form of a single continuous film. However, after etching, the aluminum film 14 is in a state of being divided into a part formed in the spacer electrode 17d-1 and another part formed in the spacer electrode 17d-2. Figure 10 The upper surface and the left side surface of the spacer electrode 17d-1 in Figure 10 are covered by the first insulating film 19, but Figure 10 the right side surface of the spacer electrode 17d-1 in Figure 10 is not covered by the first insulating layer 19, but is covered by the lining film 101. Similarly, Figure 10 the upper surface and the right side surface of the spacer electrode 17d-2 in Figure 10 are covered by the first insulating film 19, but Figure 10 the left side surface of the spacer electrode 17d-2 in Figure 10 is not covered by the first insulating film 19, but is covered by the second insulating film 20.

[0074] The upper surface of the spacer electrode 17d and one side surface among the respective side surfaces are covered by an insulating film made of a material different from that of the insulating film on the other side surface. In addition, the upper surface and the respective side surfaces of the wiring electrode 18 are covered by insulating films of the same material. In this way, the spacer electrode 17d is covered by insulating films of different materials, but the wiring electrode 18 is covered by insulating films of the same material. Although the respective side surfaces of the spacer electrode 17d are covered by different insulating films, the respective side surfaces of the wiring electrode 18 are covered by the same insulating film.

[0075] At least one electrode among the respective electrodes formed in the semiconductor device 10d is configured to be covered by two or more different insulating films.

[0076] <Configuration of the semiconductor device according to the fifth embodiment> Figure 12 FIG. is a diagram showing a configuration example of a semiconductor device 10e according to the fifth embodiment. The fifth embodiment can be implemented in combination with any one of the first to fourth embodiments. Figure 12 FIG. is a diagram showing the configuration of the semiconductor device 10e obtained in the case where the fifth embodiment is combined with the first embodiment.

[0077] In the above first to fourth embodiments, the case where the electrode 12 is not formed in the region corresponding to the opening portion of the spacer portion 51 in the semiconductor substrate 11 is shown and described. However, as Figure 12 shown, the electrode 12 may be formed in the region corresponding to the opening portion of the spacer portion 51 in the semiconductor substrate 11. In Figure 12 the example shown, the electrodes 12-2 to 12-4 are formed in the region corresponding to the opening portion of the spacer portion 51 in the semiconductor substrate 11.

[0078] The electrode 12-1 is connected to the spacer electrode 17-1, and the electrode 12-5 is connected to the spacer electrode 17-2. Before performing etching, that is, when inspection is carried out, an aluminum film 14 also exists in the opening of the spacer portion 51 (the aluminum film 14 is not shown in Figure 12 ), and the aluminum film 14 is connected to the electrodes 12-2 to 12-4. As Figure 12 shown, after performing etching, since the aluminum film 14 in the opening of the spacer portion 51 has been removed, the electrodes 12-2 to 12-4 are left, and a second insulating film 20 is formed on the electrodes 12-2 to 12-4.

[0079] As described above, a structure in which the electrodes 12 are formed in a region of the semiconductor substrate 11 corresponding to the opening of the spacer portion 51 can also be adopted. When etching is performed, these electrodes 12 in the opening of the spacer portion 51 are exposed, but after etching, these electrodes 12 are covered with the second insulating film 20, thereby obtaining an insulating structure.

[0080] Regardless of the layout of the electrodes of the spacer portion 51, this technology can be applied, and the aluminum film 14 is removed, thereby enabling the above-described structure to be achieved.

[0081] <Structure of the semiconductor device according to the sixth embodiment> Figure 13 FIG. is a diagram showing a structural example of a semiconductor device 10f according to the sixth embodiment. The sixth embodiment can be implemented in combination with any one of the first to fifth embodiments. Figure 13 FIG. is a diagram showing the structure of a semiconductor device 10f obtained in the case where the sixth embodiment is combined with the first embodiment.

[0082] Figure 13 The semiconductor device 10f shown has the following structure: the spacer electrode 17 left after performing etching is connected to a wiring for establishing an electrical connection with another semiconductor device ( Figure 13 the semiconductor device 121 in) to be laminated. One end of the spacer electrode 17 is connected to an electrode 12 (referred to as a lower electrode 12) provided in the semiconductor substrate 11, and the other end of the spacer electrode 17 is connected to an electrode 81 (referred to as an upper electrode 81).

[0083] Since the spacer electrode 17 is configured to be connected to the upper electrode 81, the first insulating film 19 and the second insulating film 20 have been removed in the region where the upper electrode 81 is disposed. The upper electrode 81 is connected to the electrode 83 provided at the connection interface between the semiconductor device 10f and the semiconductor device 121. The electrode 83 is connected to the electrode 113 of the semiconductor device 121. Since the electrode 83 and the electrode 131 are connected to each other, the semiconductor device 10f and the semiconductor device 121 are electrically connected to each other and have the same potential.

[0084] In this way, the spacer electrode 17 can be configured to serve as a spacer for the inspection needle to drop onto during inspection in the manufacturing process and as an electrode for establishing electrical connection with another semiconductor device after the inspection and after performing etching.

[0085] In the semiconductor device 10f, the needle is dropped onto the aluminum film 14 in the spacer portion 51 to perform measurement, thereby allowing the screening out of qualified products. Then, the second insulating film 20 is planarized, and the upper electrode 81 is formed on the spacer electrode 17, so that the surface of the upper electrode 81 can be formed on a flat surface. The semiconductor device 121 stacked on the semiconductor device 10f also has a planarized electrode connected to the semiconductor device 10f, and thus a stacked structure in which the semiconductor device 121 and the semiconductor device 10f are electrically connected to each other can be formed.

[0086] <Configuration of the semiconductor device according to the seventh embodiment> Figure 14 is a diagram showing a structural example of the semiconductor device 10 according to the seventh embodiment. According to Figure 14 The semiconductor device 10 of the seventh embodiment shown shows the application of the first to sixth embodiments to a camera device.

[0087] In Figure 14 In the camera device 200 shown, the chips 202, 203, and 204 are stacked on the support substrate 201 in sequence. The chip 204 is a chip on which an imaging element is disposed. For example, the chip 203 can be a memory for storing signals from the imaging element, or a logic circuit for processing signals from the imaging element, etc. For example, the chip 204 can also be a memory for storing signals from the imaging element, or a logic circuit for processing signals from the imaging element, etc.

[0088] Since the chip 202 is smaller than the chip 203, therefore in Figure 14An embedded film 205 is formed on the right side of the chip 202 to absorb the dimensional difference between both the chip 202 and the chip 203. In the case where the chips 202 and 203 are formed with substantially the same dimensions, a configuration without the embedded film 205 may also be employed.

[0089] The chip 202 has the configuration of the semiconductor device 10 described above. The electrode 211 of the chip 202 corresponds to the pad electrode 17. The upper electrode 214 is connected to the electrode 211. The upper electrode 214 is connected to the connection electrode 216 provided on the interface between both the chip 202 and the chip 203.

[0090] The upper electrode 214 is provided in a region where the first insulating film 212 (corresponding to the first insulating film 19 in the above-described embodiment) and the second insulating film 213 (corresponding to the second insulating film 20 in the above-described embodiment) have been removed. In the chip 202, the Figure 13 configuration of the semiconductor device 10f shown is applied.

[0091] In the chip 203, a connection electrode 231 connected to the connection electrode 215 is formed on the interface between both the chip 202 and the chip 203. The electrode 232 is connected to the connection electrode 231. The electrode 233 is connected to the electrode 232. The electrode 233 is also connected to the electrode pad 251. The electrode pad 251 serves as an external connection terminal.

[0092] For example, in the case where a power source having a predetermined voltage is connected to the electrode pad 251 serving as an external connection terminal, the chips 202 and 203 may be configured to be powered from the externally connected power source.

[0093] The first insulating film 252 is laminated on both ends of the electrode pad 251, and the second insulating film 253 is laminated on the first insulating film 252. The electrode pad 251 for external connection may be formed at, but is not limited to, Figure 14 the position shown, and the electrode pad 251 may also be formed at a position deeper than Figure 14 the position shown inside the chip 203. The electrode pad 251 for external connection may be formed in the chip 204.

[0094] The chip 204 is a sensor chip, and in the chip 204, an imaging element layer 272 of a photodiode is formed on a wiring layer 271. A planarization film 273 is formed on the imaging element layer 272, and a light-shielding film 224 is formed in the planarization film 273. A color filter layer 275 is provided on the planarization film 273. An on-chip lens 276 is formed on the color filter layer 275 for each pixel.

[0095] Any one or some of the chips 202 to 204 included in the above-described imaging device 200 may be a chip having the configuration of the semiconductor device 10 according to the above-described embodiments. The number of chips to be stacked is not limited to three, and the chips may be stacked in any number according to the scope of application of the present technology. As described above, according to the present technology, when a plurality of chips (semiconductor devices) are stacked on each other, it is possible to prevent a decrease in the connection strength between the stacked chips.

[0096] Although the application of the present technology to the imaging device 200 has been described here as an example, the present technology can also be applied to other devices including semiconductor devices.

[0097] <Application Examples of Electronic Devices> The present technology is applicable to all electronic devices that use an imaging element in an image capturing unit (photoelectric conversion unit), such as: imaging devices such as digital cameras or video cameras; portable terminal devices having an imaging function; and copies that use an imaging element in an image reading unit. The imaging element may have a single-chip form, or may be in the form of an imaging function module that encapsulates an imaging unit and a signal processing unit or an optical system together.

[0098] Figure 15 It is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applicable.

[0099] Figure 15 The illustrated imaging device 1000 includes: an optical unit 1001 having a lens group or the like; an imaging element (imaging component) 1002; and a DSP (Digital Signal Processor) circuit 1003 as a camera signal processing circuit. In addition, the imaging device 1000 further includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.

[0100] The optical unit 1001 receives incident light (image light) from a subject and forms the incident light on the imaging surface of the imaging element 1002. After the incident light is formed on the imaging surface by the optical unit 1001, the imaging element 1002 converts the amount of incident light into an electrical signal for each pixel and outputs the electrical signal as a pixel signal.

[0101] For example, the display unit 1005 includes a thin display such as a liquid crystal display (LCD) or an organic electro - luminescence (EL) display, and displays a moving image or a still image captured by the imaging element 1002. The recording unit 1006 records the moving image or the still image captured by the imaging element 1002 on a recording medium such as a hard disk or a semiconductor memory.

[0102] The operation unit 1007 issues operation commands related to various functions of the imaging device 1000 under the operations performed by the user. The power supply unit 1008 appropriately supplies various power supplies corresponding to the operation power supplies of the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 to these power - supply targets.

[0103] Figure 14 The imaging device 200 shown can be applied to Figure 15 the imaging element 1002 shown.

[0104] In this specification, a system represents the entire device including a plurality of devices.

[0105] Note that the effects described in this specification are merely examples and are not restrictive, and other effects may also be produced.

[0106] Note that the embodiments of this technology are not limited to the above - described embodiments, and can be modified in various ways without departing from the gist of this technology.

[0107] Note that this technology may also include the following technical solutions. (1) A semiconductor device, comprising: a first electrode covered with a first insulating film; and a second electrode covered with the first insulating film and a second insulating film made of a material different from the first insulating film. (2) The semiconductor device according to (1) above, wherein at least one side of each side of the second electrode is covered with the second insulating film, and the remaining sides of each side of the second electrode are covered with the first insulating film. (3) The semiconductor device according to (1) or (2) above, wherein the second insulating film is formed on the first insulating film. (4) The semiconductor device according to any one of (1) to (3) above, wherein the second electrode includes a third electrode and a fourth electrode, and The second insulating film is formed between the third electrode and the fourth electrode. (5)The semiconductor device according to (4) above, wherein, The barrier metal included in the third electrode and the barrier metal included in the fourth electrode are connected to each other, and The second insulating film is formed on the barrier metal located between the third electrode and the fourth electrode. (6)The semiconductor device according to (4) above, wherein, The conductor included in the third electrode and the conductor included in the fourth electrode are connected to each other, and The second insulating film is formed on the conductor located between the third electrode and the fourth electrode. (7)The semiconductor device according to any one of (1) to (3) above, wherein, The first insulating film and the second insulating film are formed of the same material, and A lining film is formed between the first insulating film and the second insulating film. (8)The semiconductor device according to (7) above, wherein, At least one side surface of each side surface of the second electrode is covered by the lining film. (9)The semiconductor device according to any one of (1) to (8) above, wherein, The second electrode forms a part of a gasket, and when determining whether the semiconductor device is a qualified product, the inspection needle abuts against the gasket. (10)The semiconductor device according to any one of (1) to (9) above, wherein, The second electrode is electrically connected to another semiconductor device stacked with the semiconductor device. (11)The semiconductor device according to any one of (1) to (10) above, wherein, The second electrode is connected to an external connection terminal. (12)The semiconductor device according to any one of (1) to (11) above, wherein, The semiconductor device is stacked on a semiconductor device including an imaging element. (13)A method for manufacturing a semiconductor device, the manufacturing method including: Removing the conductive material of the gasket located in the opening, and before the removing, when performing an inspection for determining whether the semiconductor device is a qualified product, the inspection needle abuts against the conductive material of the gasket located in the opening; Form a second insulating film on a region including a region where the conductive material has been removed, the second insulating film being made of a material different from that of the first insulating film formed on the conductive material of the spacer; and Planarize the second insulating film thus formed. [List of Reference Numerals]

[0108] 10: Semiconductor device 11: Semiconductor substrate 12: Electrode 13: Barrier metal 14: Aluminum film 15: Titanium film 17: Spacer electrode 18: Wiring electrode 19: First insulating film 20: Second insulating film 31: Wiring 51: Spacer portion 61: Needle 71: Trace 72: Protrusion 81: Electrode 83: Electrode 101: Liner film 113: Electrode 121: Semiconductor device 131: Electrode 200: Imaging device 201: Support substrate 202: Chip 203: Chip 204: Chip 205: Embedded film 211: Electrode 212: First insulating film 213: Second insulating film 214: Upper electrode 215: Connection electrode 216: Connection electrode 224: Light-shielding film 231: Connection electrode 232: Electrode 233: Electrode 251: Electrode spacer 252: First insulating film 253: Second insulating film 271: Wiring layer 272: Imaging element layer 273: Planarization film 275: Color filter layer 276: On-chip lens

Claims

1. A semiconductor device, comprising: a first electrode covered with a first insulating film; and a second electrode covered with the first insulating film and a second insulating film made of a material different from that of the first insulating film.

2. The semiconductor device according to claim 1, wherein at least one side surface of each side surface of the second electrode is covered with the second insulating film, and the remaining side surfaces of each side surface of the second electrode are covered with the first insulating film.

3. The semiconductor device according to claim 1, wherein the second insulating film is formed on the first insulating film.

4. The semiconductor device according to claim 1, wherein the second electrode includes a third electrode and a fourth electrode, and the second insulating film is formed between the third electrode and the fourth electrode.

5. The semiconductor device according to claim 4, wherein the barrier metal contained in the third electrode and the barrier metal contained in the fourth electrode are connected to each other, and the second insulating film is formed on the barrier metal located between the third electrode and the fourth electrode.

6. The semiconductor device according to claim 4, wherein the conductor contained in the third electrode and the conductor contained in the fourth electrode are connected to each other, and the second insulating film is formed on the conductor located between the third electrode and the fourth electrode.

7. The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are formed of the same material, and a lining film is formed between the first insulating film and the second insulating film.

8. The semiconductor device according to claim 7, wherein at least one side surface of each side surface of the second electrode is covered with the lining film.

9. The semiconductor device according to claim 1, wherein the second electrode forms a part of a gasket, and when determining whether the semiconductor device is a qualified product, the inspection needle abuts against the gasket.

10. The semiconductor device according to claim 1, wherein the second electrode is electrically connected to another semiconductor device stacked with the semiconductor device.

11. The semiconductor device according to claim 1, wherein the second electrode is connected to an external connection terminal.

12. The semiconductor device according to claim 1, wherein the semiconductor device is stacked on a semiconductor device including an imaging element.

13. A method for manufacturing a semiconductor device, the manufacturing method comprising: removing the conductive material in the opening of the gasket, and before the removal, when performing an inspection for determining whether the semiconductor device is a qualified product, the inspection needle abuts against the conductive material in the opening of the gasket; forming a second insulating film on the region including the region where the conductive material has been removed, the second insulating film being made of a material different from that of the first insulating film formed on the conductive material of the gasket; and planarizing the thus formed second insulating film.

Images