Semiconductor device

Abstract

The invention provides a semiconductor device capable of suppressing the occurrence of damage. According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, a second electrode, a first insulating portion, and a second insulating portion. The semiconductor layer is disposed on the first electrode. The second electrode is disposed over the semiconductor layer and includes aluminum. The first insulating part comprises a first part and a second part. The first portion is provided between the semiconductor layer and an outer peripheral portion of the second electrode. The second portion is provided around the first portion along a first surface perpendicular to a first direction from the first electrode toward the semiconductor layer, and is provided with a protruding portion on an upper surface. The second insulating portion is provided on the outer peripheral portion and the second portion of the second electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] Semiconductor devices such as diodes, Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Insulated Gate Bipolar Transistors (IGBTs) are used for power conversion and other applications. It is desired that semiconductor devices are difficult to be damaged.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 2-30130 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the occurrence of damage.

[0008] Technical Solution for Solving the Technical Problem

[0009] The semiconductor device of the embodiment includes a first electrode, a semiconductor layer, a second electrode, a first insulating portion, and a second insulating portion. The semiconductor layer is provided above the first electrode. The second electrode is provided above the semiconductor layer and contains aluminum. The first insulating portion includes a first part and a second part. The first part is provided between the semiconductor layer and the outer peripheral portion of the second electrode. The second part is provided around the first part along a first plane perpendicular to a first direction from the first electrode toward the semiconductor layer, and has a convex portion on its upper surface. The second insulating portion is provided above the outer peripheral portion of the second electrode and the second part. Brief Description of the Drawings

[0010] Figure 1 is a plan view showing the semiconductor device of the first embodiment.

[0011] Figure 2 is Figure 1 a cross-sectional view taken along A1 - A2 of

[0012] Figure 3 is a cross-sectional view showing the semiconductor device of the reference example.

[0013] Figure 4 of (a) and Figure 4(b) is a schematic diagram for explaining the problems in the semiconductor device of the reference example.

[0014] Figure 5 (a) to Figure 5 (d) is a top view showing the layout of the convex portions provided in the first insulating portion.

[0015] Figure 6 is a cross-sectional view showing a part of the semiconductor device of the first modification of the first embodiment.

[0016] Figure 7 is a cross-sectional view showing a part of the semiconductor device of the second modification of the first embodiment.

[0017] Figure 8 is a cross-sectional view showing a part of the semiconductor device of the third modification of the first embodiment.

[0018] Figure 9 is a cross-sectional view showing a part of the semiconductor device of the fourth modification of the first embodiment.

[0019] Figure 10 is a cross-sectional view showing a part of the semiconductor device of the fifth modification of the first embodiment.

[0020] Figure 11 is a cross-sectional view showing a part of the semiconductor device of the second embodiment.

[0021] Figure 12 is a cross-sectional view showing a part of the semiconductor device of the third embodiment.

[0022] Figure 13 is a cross-sectional view showing a part of the semiconductor device of the fourth embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as in reality. In addition, even when showing the same part, there are cases where the mutual dimensions and ratios are shown differently depending on the drawings. In the present specification and each figure, the same reference numerals are assigned to the same elements as those already described, and detailed descriptions are appropriately omitted.

[0024] In the following description, n + , n, n - and p + , the expressions of p represent the relative levels of impurity concentrations in each conductivity type. That is, n + indicates that the impurity concentration of the n-type is relatively higher compared to n, and n -Indicates that the impurity concentration of the n-type is relatively low compared to n. Additionally, p + Indicates that the impurity concentration of the p-type is relatively high compared to p. For each of the embodiments described below, each embodiment can also be implemented by reversing the p-type and n-type of each semiconductor region.

[0025] (First Embodiment)

[0026] Figure 1 Is a top view showing a semiconductor device of the first embodiment. Figure 2 Is Figure 1 A sectional view taken along A1 - A2 of

[0027] The semiconductor device of the first embodiment is a diode. As Figure 1 And Figure 2 Shown, the semiconductor device 1 of the first embodiment includes a semiconductor layer 10, a lower electrode 21 (first electrode), an upper electrode 22 (second electrode), a first insulating portion 31, and a second insulating portion 32. Additionally, in Figure 1 The second insulating portion 32 is omitted.

[0028] Here, the direction from the lower electrode 21 toward the semiconductor layer 10 is defined as the Z direction (first direction). One direction perpendicular to the Z direction is defined as the X direction. The direction perpendicular to the X direction and the Z direction is defined as the Y direction. Additionally, for the sake of explanation, the direction from the lower electrode 21 toward the semiconductor layer 10 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the lower electrode 21 and the semiconductor layer 10 and are independent of the direction of gravity.

[0029] As Figure 1 Shown, an upper electrode 22 and a first insulating portion 31 are provided on the upper surface of the semiconductor device 1. The upper electrode 22 is provided at the central portion in the X - Y plane (first plane) of the semiconductor device 1, and the first insulating portion 31 is provided at the outer peripheral portion of the semiconductor device 1.

[0030] As Figure 2 Shown, a lower electrode 21 is provided on the lower surface of the semiconductor device 1. The semiconductor layer 10 is provided above the lower electrode 21. The upper electrode 22 is located above the semiconductor layer 10.

[0031] The first insulating portion 31 includes a first part 31a and a second part 31b. The first part 31a is located between the semiconductor layer 10 and the outer peripheral portion of the upper electrode 22 in the Z direction. The second part 31b is provided along the X - Y plane around the first part 31a. A convex portion P1 is provided on the upper surface of the second part 31b.

[0032] In Figure 1 And Figure 2In the example shown, a plurality of convex portions P1 are provided in the radial direction (second direction) from the first portion 31a toward the second portion 31b. The radial direction is perpendicular to the Z direction. Further, each convex portion P1 surrounds the upper electrode 22 along the X-Y plane.

[0033] As Figure 2 shown, at least a part of the convex portion P1 has the same position in the Z direction as at least a part of the upper electrode 22 in the Z direction. For example, the upper surface of the convex portion P1 is juxtaposed with a part of the upper electrode 22 in the radial direction.

[0034] The second insulating portion 32 is provided above the outer peripheral portion of the upper electrode 22 and the second portion 31b. The lower surface of the second insulating portion 32 is in contact with the convex portion P1. Accordingly, one or more concave portions are formed on the lower surface of the second insulating portion 32 corresponding to one or more convex portions P1.

[0035] The semiconductor layer 10 includes an n - -type (first conductivity type) semiconductor region 11 (first semiconductor region), an n + -type contact region 11a, a p-type (second conductivity type) semiconductor region 12 (second semiconductor region), a p + -type contact region 12a, and an n + -type semiconductor region 13 (third semiconductor region). In Figure 1 this, the p-type semiconductor region 12 and the n + -type semiconductor region 13 are indicated by dashed lines.

[0036] n + -type contact region 11a is provided above the lower electrode 21 and is electrically connected to the lower electrode 21. The n - -type semiconductor region 11 is provided above the n + -type contact region 11a. + The n-type impurity concentration of the n-type contact region 11a is higher than the n-type impurity concentration of the n - -type semiconductor region 11.

[0037] The p-type semiconductor region 12 is provided above the n - -type semiconductor region 11. The p-type semiconductor region 12 is located at the central portion in the X-Y plane of the semiconductor layer 10. The p + -type contact region 12a is selectively provided above the p-type semiconductor region 12. The p + -type impurity concentration of the p-type contact region 12a is higher than the p-type impurity concentration of the p-type semiconductor region 12.

[0038] The upper electrode 22 is located above the p-type semiconductor region 12 and the p + -type contact region 12a. The p-type semiconductor region 12 and the p +The type contact region 12a is electrically connected to the upper electrode 22.

[0039] n + The n-type semiconductor region 13 is disposed around the p-type semiconductor region 12 along the X-Y plane. n + The n-type semiconductor region 13 is separated from the p-type semiconductor region 12 and is located in the outer peripheral portion in the X-Y plane of the semiconductor layer 10. n + The n-type impurity concentration of the n-type semiconductor region 13 is higher than that of the - n-type semiconductor region 11.

[0040] An example of the material of each component will be described.

[0041] The semiconductor layer 10 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. For example, when silicon carbide is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0042] The lower electrode 21 and the upper electrode 22 contain aluminum. The lower electrode 21 and the upper electrode 22 may each have a stacked structure including a plurality of metal layers. For example, as Figure 2 shown, the upper electrode 22 includes a first metal layer 22a containing titanium, a second metal layer 22b containing titanium nitride, and a third metal layer 22c containing aluminum.

[0043] The first insulating portion 31 contains silicon oxide. The second insulating portion 32 contains an insulating resin such as polyimide. After the first insulating portion 31 is formed by chemical vapor deposition (CVD) or the like, a part of the first insulating portion 31 is removed by photolithography and anisotropic etching to form a convex portion P1.

[0044] The operation of the semiconductor device 1 will be described.

[0045] When a voltage larger than the forward voltage (V F ) is applied to the upper electrode 22 with respect to the lower electrode 21, current flows from the upper electrode 22 toward the lower electrode 21. Thus, the semiconductor device 1 becomes a conducting state. After that, when the voltage applied to the upper electrode 22 is lower than the forward voltage, the current decreases and the semiconductor device 1 becomes a cutoff state. When a positive voltage is applied to the lower electrode 21 with respect to the upper electrode 22, the depletion layer expands from the pn junction between the n - -type semiconductor region 11 and the p-type semiconductor region 12. At this time, the potential near the n + -type semiconductor region 13 is substantially the same as the potential of the lower electrode 21.

[0046] Figure 3 It is a cross-sectional view of a semiconductor device showing a reference example.

[0047] In Figure 3 the semiconductor device 1r shown, no convex portion P1 is provided on the upper surface of the first insulating portion 31. The upper surface of the first insulating portion 31 is flat. Other configurations of the semiconductor device 1r are the same as those of the semiconductor device 1.

[0048] Figure 4 (a) of Figure 4 and (b) of are schematic diagrams for explaining problems in the semiconductor device of the reference example.

[0049] Semiconductor devices are sometimes used in high-temperature and high-humidity environments. In this case, moisture easily enters the second insulating portion 32. When the entered moisture reaches the upper electrode 22, electrolysis of moisture occurs on the surface of the upper electrode 22 as described below.

[0050] 2H2O + 2e - → H2 + 2OH -

[0051] Due to the hydroxide ions, the polarity around the upper electrode 22 becomes alkaline. Moreover, as described below, aluminum complex ions are generated.

[0052] Al(OH)3 + OH - → [Al(OH)4] -

[0053] When the semiconductor device is in the off state, the potential near the n + -type semiconductor region 13 is substantially the same as the potential of the lower electrode 21. Therefore, an electric field is generated from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10. The interface between the first insulating portion 31 and the second insulating portion 32 is connected to the interface between the upper electrode 22 and the first insulating portion 31 and the interface between the upper electrode 22 and the second insulating portion 32. Therefore, as shown in (a) of Figure 4 , the aluminum complex ions C generated on the upper electrode 22 move along the electric field at the interface between the first insulating portion 31 and the second insulating portion 32.

[0054] Moreover, in the upper electrode 22, as the complex ions move, oxides are formed as follows.

[0055] 2[Al(OH)4] - → Al2O3 + 3H2O + 2OH -

[0056] In addition, when the moving complex ions reach the n + -type semiconductor region 13, between the upper electrode 22 and the n +Current begins to flow between the p-type semiconductor regions 13. According to the flow of this current, electrolysis in the upper electrode 22 and the formation of complex ions are promoted. The formation of aluminum oxide progresses, and the stress applied to the second insulating portion 32 increases. Eventually, as shown in (b) of Figure 4 , cracks are generated in the second insulating portion 32 due to the oxide 22ox. Through the cracks, discharge occurs between the upper electrode 22 and the outer peripheral portion of the semiconductor layer 10, and the semiconductor device 1r is damaged.

[0057] In the semiconductor device 1 of the first embodiment, a convex portion P1 is provided on the upper surface of the first insulating portion 31. When the convex portion P1 is provided, the movement of aluminum complex ions is obstructed by the convex portion P1. By obstructing the movement of complex ions, it is possible to suppress the flow of current between the upper electrode 22 and the n + -type semiconductor region 13. It is possible to suppress electrolysis in the upper electrode 22 and the formation of oxides, and reduce the possibility of cracks being generated in the second insulating portion 32 due to the oxides. As a result, it is less likely to cause damage to the semiconductor device 1 due to cracks in the second insulating portion 32.

[0058] According to the first embodiment, even when used in an environment of high temperature and high humidity, it is possible to suppress the occurrence of damage to the semiconductor device 1 and improve the breakdown tolerance of the semiconductor device 1.

[0059] The higher the voltage applied to the semiconductor device, the more likely the above problems are to occur. The higher the applied voltage, the more electrolysis of moisture occurs, and the easier it is to form oxides in the upper electrode 22. For example, when the semiconductor layer 10 contains silicon carbide, compared with the case where the semiconductor layer 10 contains single crystal silicon, the dielectric breakdown electric field strength of the semiconductor layer 10 can be further increased. Since a larger voltage can be applied to the semiconductor device, it is easier to generate electrolysis and oxide formation in the upper electrode 22.

[0060] According to the first embodiment, even when a high voltage is applied to the semiconductor device 1, it is possible to suppress the formation of oxides in the upper electrode 22. Therefore, the first embodiment of the present invention is more suitable for the semiconductor device 1 using silicon carbide.

[0061] As Figure 2 shown, the position p1 of the convex portion P1 in the radial direction is preferably located between the position p2 of the p-type semiconductor region 12 and the position p3 of the n + -type semiconductor region 13 in the radial direction. Since the position p1 of at least any one of the convex portions P1 is located between the position p2 and the position p3, it is possible to effectively suppress the movement of complex ions from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10.

[0062] Figure 5 of (a) to Figure 5Fig. (d) is a plan view showing the layout of the convex portions provided on the first insulating portion.

[0063] The annular convex portion P1 can be provided as shown in Figure 1 , or the linear convex portion P1 can be provided as shown in Figure 5 Fig. (a). In the example shown in Figure 5 Fig. (a), each convex portion P1 extends in the X direction or the Y direction along the side of the semiconductor device 1. The convex portions P1 intersect at the corners of the semiconductor device 1.

[0064] As shown in Figure 5 Fig. (b) and Figure 5 Fig. (c), more curved convex portions P1 or linear convex portions P1 can also be provided at the corners of the semiconductor device 1. Alternatively, as shown in Figure 5 Fig. (d), a plurality of convex portions P1 can also be arranged along the outer periphery of the semiconductor device 1.

[0065] As shown in Figure 1 and Figure 5 Figs. (a) to Figure 5 Fig. (d), the number and arrangement of the convex portions P1 are arbitrary. By providing at least one convex portion P1, the movement of the complex ions can be hindered. More preferably, as shown in Figure 2 and Figure 5 Figs. (a) to Figure 5 Fig. (c), the convex portions P1 surround the upper electrode 22 along the X - Y plane. Thus, in any direction from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10, the movement of the complex ions can be hindered by the convex portions P1.

[0066] (First Modified Example)

[0067] Figure 6 Fig. is a cross - sectional view showing a part of the semiconductor device according to the first modified example of the first embodiment.

[0068] In Figure 6 the semiconductor device 1a shown, the first insulating portion 31 and the convex portion P1 are composed of different components. For example, the first insulating portion 31 contains silicon oxide. The convex portion P1 contains silicon oxide or silicon nitride.

[0069] As in the semiconductor device 1a, the first insulating portion 31 and the convex portion P1 may not be integral components. In the semiconductor device 1a, both the first insulating portion 31 and the convex portion P1 are insulating materials containing silicon. At the interface between the convex portion P1 and the first insulating portion 31, complex ions are less likely to move compared to the interface between the second insulating portion 32 containing resin and the first insulating portion 31. Therefore, according to the first modified example, the breakdown tolerance of the semiconductor device 1a can be improved compared to the semiconductor device 1r of the reference example.

[0070] More preferably, the first insulating portion 31 and the convex portion P1 are integrally provided. For example, by processing one insulating layer, the first insulating portion 31 including the convex portion P1 is formed. In this case, there is no interface in the region between the first insulating portion 31 and the convex portion P1, and it is seamless. Therefore, it is possible to more reliably prevent the passage of complex ions between the first insulating portion 31 and the convex portion P1. By integrally providing the first insulating portion 31 and the convex portion P1, the breakdown tolerance of the semiconductor device 1 can be further improved compared to the semiconductor device 1a.

[0071] (Second modification example)

[0072] Figure 7 FIG. is a cross-sectional view showing a part of the semiconductor device according to the second modification example of the first embodiment.

[0073] In Figure 7 In the semiconductor device 1b shown, compared with the semiconductor device 1, the semiconductor layer 10 further includes a p-type surface field reduction region 14a (an example of a fourth semiconductor region). The p-type surface field reduction region 14a is provided along the X-Y plane around the p-type semiconductor region 12.

[0074] The p-type surface field reduction region 14a is in contact with the p-type semiconductor region 12. The lower surface of the p-type surface field reduction region 14a is located at a position above the lower surface of the p-type semiconductor region 12. The p-type impurity concentration of the p-type surface field reduction region 14a may be the same as the p-type impurity concentration of the p-type semiconductor region 12 or may be lower than the p-type impurity concentration of the p-type semiconductor region 12. The radial end E of the p-type surface field reduction region 14a is separated from the n + type semiconductor region 13.

[0075] By providing the p-type surface field reduction region 14a, the electric field intensity at the outer peripheral portion of the p-type semiconductor region 12 can be alleviated, and the breakdown voltage of the semiconductor device 1b can be improved.

[0076] In the semiconductor device 1b, the radial position p1 of the convex portion P1 is preferably between the radial position p2 of the p-type semiconductor region 12 and the radial position p4 of the end E of the p-type surface field reduction region 14a. Near the end E, the electric field intensity is higher than other portions. When complex ions move to the region directly above the end E, the complex ions are accelerated by the electric field. As a result, the complex ions are more likely to reach the n + type semiconductor region 13. By having the position p1 between the position p2 and the position p4, the movement of complex ions to the region directly above the end E can be suppressed. Thereby, the breakdown tolerance of the semiconductor device 1b can be further improved.

[0077] (Third modification example)

[0078] Figure 8 It is a cross-sectional view showing a part of a semiconductor device according to a third modification of the first embodiment.

[0079] In Figure 8 In the semiconductor device 1c shown, compared with the semiconductor device 1, the semiconductor layer 10 further includes a p-type guard ring region 14b (another example of the fourth semiconductor region). The p-type guard ring regions 14b are separated from the p-type semiconductor region 12 and the n + -type semiconductor region 13, and a plurality of them are provided in the radial direction. The p-type guard ring regions 14b are separated from each other and surround the p-type semiconductor region 12 in the X-Y plane.

[0080] The thickness of the p-type guard ring region 14b in the Z direction may be the same as the thickness of the p-type semiconductor region 12 in the Z direction, or may be smaller than the thickness of the p-type semiconductor region 12. The p-type impurity concentration of the p-type guard ring region 14b may be the same as the p-type impurity concentration of the p-type semiconductor region 12, or may be lower than the p-type impurity concentration of the p-type semiconductor region 12. The p-type impurity concentrations of the p-type guard ring regions 14b are the same as each other. It is also possible that the p-type impurity concentration of the p-type guard ring region 14b decreases as it is located more outside the semiconductor device 1c.

[0081] In the semiconductor device 1c, the position p1 of the convex portion P1 is preferably between the position p2 of the p-type semiconductor region 12 and the radial position p5 of the outermost p-type guard ring region 14b. Near the outermost p-type guard ring region 14b, the electric field intensity is higher than that in other parts. When the complex ions move to the region directly above the outermost p-type guard ring region 14b, the complex ions are accelerated by the electric field. As a result, the complex ions are more likely to reach the n + -type semiconductor region 13. By making the position p1 between the position p2 and the position p5, the movement of the complex ions to the region with high electric field intensity can be suppressed. Thereby, the breakdown tolerance of the semiconductor device 1c can be further improved.

[0082] (Fourth modification)

[0083] Figure 9 It is a cross-sectional view showing a part of a semiconductor device according to a fourth modification of the first embodiment.

[0084] Figure 9 The semiconductor device 1d shown is different from the semiconductor device 1 in that a convex portion P0 and a convex portion P2 are provided. The convex portion P0 is provided on the upper surface of the semiconductor layer 10. The convex portion P2 is provided on the upper surface of the second insulating portion 32. The positions of the convex portion P0, the convex portion P1, and the convex portion P2 in the X-Y plane are the same as each other.

[0085] After forming the semiconductor layer 10, other parts of the semiconductor layer 10 are removed in such a way that the parts corresponding to the convex portion P0 remain. Thus, the convex portion P0 is formed on the upper surface of the semiconductor layer 10. Then, by forming the first insulating portion 31 over the semiconductor layer 10, the convex portion P1 is formed according to the position and size of the convex portion P0. By forming the second insulating portion 32 over the first insulating portion 31, the convex portion P2 is formed according to the position and size of the convex portion P1.

[0086] In addition, the semiconductor device 1d is sometimes molded with resin. By providing the convex portion P2 on the upper surface of the second insulating portion 32, the contact area between the second insulating portion 32 and the molding resin can be increased, and the adhesion between the second insulating portion 32 and the molding resin can be improved.

[0087] (Fifth modification example)

[0088] Figure 10 It is a cross-sectional view showing a part of the semiconductor device according to the fifth modification example of the first embodiment.

[0089] Figure 10 The shown semiconductor device 1e is different from the semiconductor device 1 in that it further includes a third insulating portion 33. The third insulating portion 33 is provided over the second insulating portion 32. In the semiconductor device 1e, the second insulating portion 32 contains silicon oxide or silicon nitride. The third insulating portion 33 contains polyimide.

[0090] An insulating portion other than the first insulating portion 31 and the second insulating portion 32 may also be provided as in the semiconductor device 1e. In addition, in the semiconductor device 1e, the convex portion P2 may be provided on the second insulating portion 32 in the same manner as the semiconductor device 1d. In this case, the convex portion P3 is provided on the upper surface of the third insulating portion 33. By providing the convex portion P3, the adhesion between the third insulating portion 33 and the molding resin can be improved when the semiconductor device 1e is molded with resin.

[0091] (Second embodiment)

[0092] Figure 11 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0093] The semiconductor device according to the second embodiment is a MOSFET. Figure 11 The shown semiconductor device 2 further includes a gate electrode 25 as compared with the semiconductor device 1. In addition, the semiconductor layer 10 in the semiconductor device 2 further includes an n + -type semiconductor region 15 (fifth semiconductor region) as compared with the semiconductor layer 10 in the semiconductor device 1.

[0094] The gate electrode 25 faces the p-type semiconductor region 12 with a gate insulating layer 25a therebetween. p +p-type contact region 12a and n + An n-type semiconductor region 15 is provided over a p-type semiconductor region 12. The p-type semiconductor region 12, p + -type contact region 12a and n + -type semiconductor region 15 are electrically connected to an upper electrode 22.

[0095] For example, a plurality of p-type semiconductor regions 12, p + -type contact regions 12a, n + -type semiconductor regions 15, and gate electrodes 25 are provided in the X direction, respectively. Each p-type semiconductor region 12, each p + -type contact region 12a, each n + -type semiconductor region 15, and each gate electrode 25 extend in the Y direction.

[0096] The operation of the semiconductor device 2 will be described.

[0097] With a positive voltage applied to the lower electrode 21 with respect to the upper electrode 22, a voltage equal to or higher than a threshold value is applied to the gate electrode 25. As a result, a channel (inversion layer) is formed in the p-type semiconductor region 12, and the semiconductor device 2 becomes conductive. Electrons flow from the upper electrode 22 to the lower electrode 21 through the channel. If the voltage applied to the gate electrode 25 is lower than the threshold value, the channel in the p-type semiconductor region 12 disappears, and the semiconductor device 2 becomes non-conductive.

[0098] When the semiconductor device 2 is in the non-conductive state, an electric field is generated from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10, as in the case of the semiconductor device 1. By providing the convex portion P1 on the upper surface of the first insulating portion 31, the breakdown voltage of the semiconductor device 2 can be increased, as in the first embodiment.

[0099] Figure 11 The semiconductor device 2 shown is a trench gate type MOSFET, and the gate electrode 25 faces the p-type semiconductor region 12 in the X direction. The semiconductor device of the second embodiment may also be a planar gate type MOSFET. In this case, the gate electrode 25 faces the p-type semiconductor region 12 in the Z direction.

[0100] (Third Embodiment)

[0101] Figure 12 FIG. is a cross-sectional view showing a part of a semiconductor device of the third embodiment.

[0102] The semiconductor device of the third embodiment is an IGBT. In Figure 12 the semiconductor device 3 shown, as compared with the semiconductor device 2, the semiconductor layer 10 includes a p + -type semiconductor region 16 instead of n +Type contact region 11a. In addition, the semiconductor layer 10 further includes an n-type semiconductor region 11b.

[0103] p + The p-type semiconductor region 16 is disposed between the lower electrode 21 and the n- - type semiconductor region 11 and is electrically connected to the lower electrode 21. The n-type semiconductor region 11b is disposed between the p- + type semiconductor region 16 and the n- - type semiconductor region 11. The n-type impurity concentration of the n-type semiconductor region 11b is higher than that of the n- - type semiconductor region 11.

[0104] In a state where a positive voltage is applied to the lower electrode 21 with respect to the upper electrode 22, a voltage equal to or higher than the threshold value is applied to the gate electrode 25. As a result, a channel (inversion layer) is formed in the p-type semiconductor region 12. Electrons flow from the n- + type semiconductor region 15 to the n- - type semiconductor region 11 through the channel, and holes flow from the p- + type semiconductor region 16 to the n- - type semiconductor region 11. Conductance modulation occurs in the n- - type semiconductor region 11, and the resistance of the semiconductor device 3 is significantly reduced. A large current flows through the semiconductor device 3, and the semiconductor device 3 becomes in a conducting state. Thereafter, when the voltage applied to the gate electrode 25 becomes lower than the threshold value, the channel in the p-type semiconductor region 12 disappears, and the semiconductor device 3 becomes in a cutoff state.

[0105] When the semiconductor device 3 is in a cutoff state, similar to the semiconductor device 1, an electric field is generated from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10. By providing the convex portion P1 on the upper surface of the first insulating portion 31, similar to the first embodiment, the breakdown tolerance of the semiconductor device 3 can be improved.

[0106] The structures of the respective modified examples of the first embodiment can also be applied to the semiconductor devices of the second embodiment or the third embodiment. For example, a p-type surface field reducing region 14a or a p-type protection ring region 14b may be provided in the semiconductor device 2 or the semiconductor device 3. A convex portion P0 and a convex portion P2 may be provided in the semiconductor device 2 or the semiconductor device 3. A third insulating portion 33 may be provided in the semiconductor device 2 or the semiconductor device 3.

[0107] (Fourth Embodiment)

[0108] Figure 13 It is a cross-sectional view showing a part of the semiconductor device of the fourth embodiment.

[0109] In Figure 13In the semiconductor device 4 shown, instead of the convex portion P1, a concave portion R1 is provided on the upper surface of the first insulating portion 31. For example, a plurality of concave portions R1 are provided in the radial direction. Each concave portion R1 surrounds the upper electrode 22 along the X-Y plane. A part of the second insulating portion 32 is located inside the concave portion R1. Therefore, a convex portion is provided on the lower surface of the second insulating portion 32.

[0110] When the concave portion R1 is provided on the upper surface of the first insulating portion 31, similar to the case where the convex portion P1 is provided, it is possible to hinder the movement of the complex ions from the upper electrode 22 toward the outer peripheral portion of the semiconductor layer 10. Therefore, according to the fourth embodiment, similar to the first embodiment, the breakdown withstand of the semiconductor device 4 can be improved.

[0111] However, in the semiconductor device 4, the thickness of the first insulating portion 31 at the portion where the concave portion R1 is provided is smaller than the thickness of the other portions of the first insulating portion 31. Therefore, at the bottom of the concave portion R1, the electric field strength is higher than that of the other portions. If ions stay at the bottom of the concave portion R1 due to the strong electric field, the radial expansion of the depletion layer into the semiconductor layer 10 is affected. As a result, the breakdown voltage of the semiconductor device 4 may vary.

[0112] By providing the convex portion P1, at the interface between the first insulating portion 31 and the second insulating portion 32, an increase in the local electric field strength can be suppressed, and the breakdown voltage of the semiconductor device can be made more stable. Therefore, when comparing the concave portion R1 and the convex portion P1, it is more preferable to provide the convex portion P1.

[0113] Embodiments of the present invention include the following features.

[0114] (Configuration 1)

[0115] A semiconductor device, comprising:

[0116] A first electrode;

[0117] A semiconductor layer provided above the first electrode;

[0118] A second electrode provided above the semiconductor layer and containing aluminum;

[0119] A first insulating portion including a first part and a second part, the first part being provided between the semiconductor layer and the outer peripheral portion of the second electrode, the second part being provided around the first part along a first plane perpendicular to a first direction from the first electrode toward the semiconductor layer, and having a convex portion provided on the upper surface; and

[0120] A second insulating portion provided above the outer peripheral portion of the second electrode and the second part.

[0121] (Configuration 2)

[0122] The semiconductor device according to Configuration 1,

[0123] The convex portion surrounds the second electrode along the first surface.

[0124] (Configuration 3)

[0125] The semiconductor device according to Configuration 2,

[0126] A plurality of the convex portions are provided in a second direction from the first portion toward the second portion.

[0127] (Configuration 4)

[0128] The semiconductor device according to any one of Configurations 1 to 3,

[0129] The second portion is provided integrally with the convex portion.

[0130] (Configuration 5)

[0131] The semiconductor device according to any one of Configurations 1 to 4,

[0132] The semiconductor layer includes:

[0133] A first semiconductor region of a first conductivity type;

[0134] A second semiconductor region of a second conductivity type, provided above the first semiconductor region; and

[0135] A third semiconductor region of the first conductivity type, provided along the first surface around the second semiconductor region, separated from the second semiconductor region, and having a higher impurity concentration of the first conductivity type than the first semiconductor region,

[0136] The second electrode is provided above the second semiconductor region,

[0137] The position of the convex portion in the second direction from the first portion toward the second portion is between the position of the second semiconductor region in the second direction and the position of the third semiconductor region in the second direction.

[0138] (Configuration 6)

[0139] The semiconductor device according to Configuration 5,

[0140] The semiconductor layer further includes a fourth semiconductor region of the second conductivity type provided between the second semiconductor region and the third semiconductor region,

[0141] An end portion of the fourth semiconductor region in the second direction is separated from the third semiconductor region,

[0142] The position of the convex portion in the second direction is between the position of the second semiconductor region in the second direction and the position of the end portion in the second direction.

[0143] (Configuration 7)

[0144] The semiconductor device according to Configuration 5 or 6,

[0145] The semiconductor device further includes a gate electrode facing the second semiconductor region with a gate insulating layer therebetween.

[0146] The semiconductor layer further includes a fifth semiconductor region of a first conductivity type provided above the second semiconductor region.

[0147] (Configuration 8)

[0148] The semiconductor device according to any one of Configurations 1 to 7,

[0149] The semiconductor layer contains silicon carbide.

[0150] Regarding the relative magnitudes of the impurity concentrations between the respective semiconductor regions in the above-described embodiments, for example, a scanning capacitance microscope (SCM) can be used to confirm. In addition, the carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Therefore, regarding the relative magnitudes of the carrier concentrations between the respective semiconductor regions, SCM can also be used to confirm. Further, regarding the impurity concentration in each semiconductor region, for example, it can be measured by secondary ion mass spectrometry (SIMS).

[0151] As described above, although several embodiments of the present invention have been illustrated, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents. In addition, the above-described embodiments can be implemented in combination with each other.

[0152] Description of Reference Numerals

[0153] 1, 1a to 1e, 1r, 2 to 4: Semiconductor device, 10: Semiconductor layer, 11: n - -type semiconductor region, 11a: n + -type contact region, 11b: n-type semiconductor region, 12: p-type semiconductor region, 12a: p + -type contact region, 13: n +n-type semiconductor region, 14a: p-type reduced surface electric field region, 14b: p-type guard ring region, 15: n + -type semiconductor region, 16: p + -type semiconductor region, 21: lower electrode, 22: upper electrode, 22a: first metal layer, 22b: second metal layer, 22c: third metal layer, 22ox: oxide, 25: gate electrode, 25a: gate insulating layer, 31: first insulating portion, 31a: first part, 31b: second part, 32: second insulating portion, 33: third insulating portion, E1: end portion, P0 to P3: protrusions, R1: recess

Claims

1. A semiconductor device, characterized in that, Comprising: A first electrode; A semiconductor layer disposed above the first electrode; A second electrode disposed above the semiconductor layer and containing aluminum; A first insulating portion including a first part and a second part, the first part being disposed between the semiconductor layer and the outer peripheral portion of the second electrode, the second part being disposed around the first part along a first plane perpendicular to a first direction from the first electrode toward the semiconductor layer, and having a convex portion on an upper surface; And A second insulating portion disposed above the outer peripheral portion of the second electrode and the second part.

2. The semiconductor device according to claim 1, wherein: The convex portion surrounds the second electrode along the first plane.

3. The semiconductor device according to claim 2, wherein: A plurality of the convex portions are provided in a second direction from the first part toward the second part.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The second part is integrally provided with the convex portion.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor layer includes: A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type disposed above the first semiconductor region; and A third semiconductor region of the first conductivity type disposed around the second semiconductor region along the first plane, separated from the second semiconductor region, and having a higher impurity concentration of the first conductivity type than the first semiconductor region, The second electrode is disposed above the second semiconductor region, The position of the convex portion in the second direction from the first part toward the second part is between the position of the second semiconductor region in the second direction and the position of the third semiconductor region in the second direction.

6. The semiconductor device according to claim 5, wherein: The semiconductor layer further includes a fourth semiconductor region of the second conductivity type disposed between the second semiconductor region and the third semiconductor region, An end portion of the fourth semiconductor region in the second direction is separated from the third semiconductor region, The position of the convex portion in the second direction is between the position of the second semiconductor region in the second direction and the position of the end portion in the second direction.

7. The semiconductor device according to claim 5, wherein: The semiconductor device further includes a gate electrode facing the second semiconductor region with a gate insulating layer therebetween, The semiconductor layer further includes a fifth semiconductor region of the first conductivity type disposed above the second semiconductor region.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor layer contains silicon carbide.

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