Gate-all-around device with work function mismatch between inner and outer gates

Abstract

A gate-all-around (GAA) device is fabricated based on a gate (GAA) transistor structure that includes a stack of a plurality of semiconductor channel layers and one or more first gate layers alternately arranged in a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is sequentially arranged between two channel layers. The GAA transistor structure also includes two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure, and each second gate layer is made of a second work function metal structure different from the first work function metal structure. Each first gate layer has a first thickness, and each second gate layer has a second thickness greater than the first thickness.

Description

Technical Field

[0001] The present disclosure relates to a gate-all-around (GAA) device and a GAA transistor structure based on which the GAA device can be fabricated. The proposed GAA transistor structure provides a work function mismatch between an inner gate formed between channel layers and an outer gate formed around the channel layers and the inner gate for the GAA device. Background Art

[0002] The GAA device includes a plurality of semiconductor channel layers stacked on top of each other and a GAA metal structure that surrounds the stack of semiconductor channel layers and each individual channel layer. Each channel layer is surrounded by a gate dielectric layer to isolate it from the GAA metal structure. For example, the GAA nanosheet device includes a plurality of semiconductor nanosheets stacked on top of each other as channel layers. Another example is the GAA fork sheet device that integrates NMOS and PMOS nanosheet structures, with each nanosheet structure located on one side of a dielectric wall that separates the NMOS from the PMOS nanosheets. All these GAA devices are candidates for future CMOS logic and are particularly envisioned as replacements for FinFET devices.

[0003] For example, there is a need to vertically scale the GAA device by increasing the number of stacked channel layers to achieve a complementary field effect transistor (CFET) structure. Unfortunately, due to the increase in the effective capacitance of the GAA device, vertical scaling reduces device performance, particularly device speed. One way to facilitate vertical scaling is to reduce the pitch or distance between the stacked semiconductor channel layers, as this reduces the effective capacitance and thus improves the performance of the GAA device.

[0004] However, if the pitch is reduced, the space between the stacked channel layers will become more restricted. This is particularly true for input / output (I / O) devices that require a thicker gate oxide than logic devices.

[0005] A further result is that the design of the GAA metal structure of the GAA device becomes more difficult and may lead to performance losses. For example, the work function design of the GAA metal structure is both difficult and technically complex. In particular, if the design and manufacturing process should allow for the fabrication of different variants of GAA devices with different threshold voltages (multi-Vt options). These difficulties are exacerbated in the case of high aspect ratio GAA devices. Summary of the Invention

[0006] In view of the above, an object of the present disclosure is to provide a solution for reducing the pitch between stacked channel layers of a GAA device to improve device performance. Another object is to provide a solution for designing a GAA metal structure for such a reduced GAA device, where the GAA metal structure should be easy to fabricate, should provide good gate control over the channel layer, and should result in good device performance. Yet another objective is to provide a solution for multi-Vt options.

[0007] These and other objectives are achieved by the respective solutions of the present disclosure provided in the independent claims. Advantageous embodiments are described in the dependent claims.

[0008] The present disclosure and the solutions proposed therein are based on the recognition that for the device performance of a GAA device with a small channel layer pitch of less than 15 nm, it is not critical to have exactly the same threshold voltage (Vt) around and between channels (i.e., the threshold voltages of the outer gate and the inner gate are exactly the same). As further shown below, some mismatch in the threshold voltage between the outer gate and the inner gate has a negligible impact on the device performance of the GAA device.

[0009] A first aspect of the present disclosure provides a GAA transistor structure, comprising: a stack of two or more semiconductor channel layers and one or more first gate layers alternately arranged along a first direction; wherein each semiconductor channel layer is encapsulated by a gate dielectric layer, and wherein each first gate layer is sequentially arranged between two of the semiconductor channel layers in the first direction; and two second gate layers that sandwich the stack in a second direction perpendicular to the first direction and are connected to the one or more first gate layers; wherein each first gate layer is made of a first work function metal structure, and each second gate layer is made of a second work function metal structure having a work function different from that of the first work function metal structure; and wherein each first gate layer has a first thickness, and each second gate layer has a second thickness greater than the first thickness.

[0010] The GAA transistor structure of the first aspect can be used to construct a GAA device. The first gate layer can form the inner gate in the GAA device, while the second gate layer can form the outer gate (particularly the side gate) in the GAA device.

[0011] The first work function metal structure can be made of a single metal layer having a first work function, or can be made of multiple metal layers having a first work function (collectively as the structure). Each first work function metal structure is configured to act as a first gate. The second work function metal structure can be made of a single metal layer having a second work function, or can be made of multiple metal layers having a second work function (collectively as the structure). Each second work function metal structure is configured to act as a second gate.

[0012] Accordingly, the first work function is different from the second work function, that is, there is a work function mismatch between the first gate layer and the second gate layer in the GAA transistor structure, and thus there is also a work function mismatch between the inner gate and the outer gate in the GAA device made based on this GAA transistor structure. Therefore, in the GAA device, there may also be a mismatch between the threshold voltage of the transistor structure forming the inner gate and the threshold voltage of the transistor structure formed by the outer gate. However, this mismatch does not significantly affect the performance of the GAA device. For the GAA device made of the GAA transistor structure of the present disclosure, the reduction in the on-current is at most 10% or even lower. From a technical perspective, the work function mismatch makes the design and manufacture of the GAA metal structure of the GAA device including the first gate layer and the second gate layer easier and simpler.

[0013] In addition, the first gate layer is thinner than the second gate layer, where the first thickness is measured along a first direction and the second thickness is measured along a second direction. This enables the distance or pitch between the stacked semiconductor channel layers to be reduced. This reduction results in a decrease in the effective capacitance of the GAA device, which improves the device performance, especially the device speed. The improvement in performance easily offsets any performance loss caused by the reduction in the on-current due to the above-mentioned mismatch. The reduction in pitch allows for further vertical scaling of the GAA transistor structure, that is, increasing the number of channel layers in the stack. If the number of channel layers remains the same, this may also make the processing of the GAA transistor structure simpler due to the reduction in the stack height.

[0014] In the implementation of the GAA transistor structure, the ratio of the second thickness to the first thickness is equal to or greater than 4:1.

[0015] In the implementation of the GAA transistor structure, the first thickness is in the range of 1 - 2 nm, while the second thickness is in the range of 5 - 7 nm.

[0016] According to the above implementation, a very thin first gate layer (i.e., a very thin inner gate in the GAA device made of the GAA transistor structure) is possible and helps to reduce the channel layer pitch.

[0017] In the implementation of the GAA transistor structure, the difference between the first work function of the first work function metal structure and the second work function of the second work function metal structure is in the range of -250 meV to +250 meV.

[0018] Within the range of ±250 meV work function mismatch between at least the first gate layer and the second gate layer, the performance of the GAA transistor structure, and correspondingly the performance of an exemplary GAA device fabricated based on the GAA transistor structure (e.g., having four channel layers and a channel layer pitch of 11 nm), is not significantly affected. Other exemplary GAA devices may even allow for a greater work function mismatch. Specifically, the first work function of the first work function metal structure can be higher than the second work function of the second work function metal structure, but the first work function can also be lower than the second work function.

[0019] In one implementation of the GAA transistor structure, the GAA transistor structure is an NMOS transistor structure, the first work function is in the range of 4.4 - 4.6 eV, and the second work function is within ±250 meV of the first work function.

[0020] In one implementation of the GAA transistor structure, the GAA transistor structure is a PMOS transistor structure, the first work function is in the range of 4.6 - 4.8 eV, and the second work function is within ±250 meV of the first work function.

[0021] The GAA transistor structure can also be a CFET transistor structure that implements both NMOS and PMOS transistor structures.

[0022] In an implementation of the GAA transistor structure, the semiconductor channel layers are arranged at a certain pitch along a first direction, and the pitch is equal to or less than 13 nm.

[0023] The pitch is related to the case where the semiconductor channel layers are arranged at regular distances along the first direction, i.e., any two adjacent channel layers are arranged at the same distance from each other. This distance can be measured along the first direction from the center of one channel layer to the center of the adjacent channel layer. The pitch can be smaller, e.g., the pitch can be 11 nm or lower, or the pitch can be 10 nm or lower, or even the pitch can be 8 nm or lower.

[0024] It is worth noting that in the stack of the GAA transistor structure in the first aspect, the distance between adjacent channel layers does not have to be constant. For example, the first distance between the first pair of channel layers in the stack can be different from the second distance between the second pair of channel layers in the stack. Either the first distance or the second distance, or both the first distance and the second distance, can be equal to 13 nm or less. Thus, a GAA transistor structure with variable pitch between the channel layers in the stack is also possible.

[0025] In one implementation of the GAA transistor structure, the second work function metal structure includes a set of metal layers, and the first work function metal structure includes a subset of the metal layers included in the set of metal layers.

[0026] The set of metal layers of the second work function metal structure may include different types of metal layers. The set of metal layers of the second work function metal structure (collectively provided) may have a second work function. The subset of metal layers of the first work function metal structure may include one or more different types of metal layers. At least one of these metal layers may be included in the set of metal layers and the subset of metal layers. The set of metal layers of the first work function metal structure (collectively provided) may have a first work function. These two work function metal structures have a work function mismatch.

[0027] In the implementation of the GAA transistor structure, the second work function metal structure consists of three metal layers made of titanium nitride, tantalum nitride, and titanium aluminide, respectively.

[0028] These metal layers are examples that result in good device performance of GAA devices fabricated based on the GAA transistor structure. The titanium nitride layer, tantalum nitride layer, and titanium aluminide layer may form the above-mentioned set of metal layers. The tantalum nitride layer may be disposed on the titanium nitride layer, and the titanium aluminide layer may be disposed on the tantalum nitride layer. In this case, the titanium nitride layer and the titanium aluminide layer sandwich the tantalum nitride layer in the middle.

[0029] In the implementation of the GAA transistor structure, the first work function metal structure consists of a single metal layer made of titanium nitride, or two metal layers made of titanium nitride and tantalum nitride, respectively.

[0030] In other words, at least titanium nitride may be included in the second work function metal structure and the first work function metal structure. The titanium nitride layer, or the titanium nitride layer and the tantalum nitride layer, may form the above-mentioned subset of metal layers.

[0031] In one implementation, the GAA transistor structure further includes two additional second gate layers that sandwich the stack in a first direction and are connected to one or more first gate layers and two second gates that sandwich the stack in a second direction.

[0032] These additional second gate layers may also form outer gates (specifically, top and bottom gates compared to the side gates formed by the second metal layer) in GAA devices fabricated based on the GAA transistor structure. The additional second gate layers and the second gate layers may be the same. For example, the additional second gate layers are made of the same second work function metal structure as the second gate layers and have the same second thickness as the second gate layers (where for the additional second gate layers, the second thickness is measured along the first direction).

[0033] In one implementation, the GAA transistor structure further includes an encapsulation, such as made of tungsten, that surrounds the stack and the second gate layers.

[0034] Such an encapsulation can protect the GAA metal structure, which includes a second gate layer, a first gate layer, and optionally an additional second gate layer or consists of the same. The encapsulation can also protect the stack of channel layers. In addition, the encapsulation can be used to contact the GAA metal structure. It is noted that the encapsulation can be designed not to affect the work function, especially the work function mismatch between the second gate layer and the first gate layer.

[0035] In the implementation of the GAA transistor structure, each semiconductor channel layer is formed of nanosheets and / or made of one of silicon, silicon germanium, III-V semiconductor materials, and 2D materials.

[0036] For example, silicon nanosheets can be used as the channel layer. The two or more semiconductor channel layers can all be p-type, all be n-type, or can include n-type and p-type channel layers. The channel layers can each have a channel width (measured along the second direction) in the range of 10 - 60 nm. At least within this channel width range, the device performance of the GAA device made based on the GAA transistor structure is stable.

[0037] In one implementation of the GAA transistor structure, a first field-effect transistor (FET) structure is formed by a first gate layer, a gate dielectric layer encapsulating the semiconductor channel layer, and the semiconductor channel layer; a second FET structure is formed by a second gate layer, a gate dielectric layer encapsulating the semiconductor channel layer, and the semiconductor channel layer; wherein each first FET structure has a first threshold voltage, and each second FET structure has a second threshold voltage different from the first threshold voltage.

[0038] Such a threshold voltage mismatch caused by the work function mismatch described in the present disclosure does not significantly affect the device performance of the GAA device made based on the GAA transistor structure, and allows the scaling of the pitch between the channel layers without designing and manufacturing a complex GAA metal structure.

[0039] A second aspect of the present disclosure provides a GAA device, which includes the GAA transistor structure according to the first aspect or any implementation thereof, wherein the GAA device is a logic device or an input / output device.

[0040] Thus, the GAA device of the second aspect is made based on the GAA transistor structure of the first aspect. In addition to the GAA transistor structure, the GAA device may further include source contacts and drain contacts to contact the channel layers. For example, the source and drain contacts may be arranged on opposite sides of the stack along a third direction perpendicular to the first and second directions, and may contact the channel layers in the third direction. The GAA device may also include gate contacts to contact the first gate layer and the second gate layer, for example, commonly contacting a GAA metal structure that includes the first gate layer and the second gate layer. It should be noted that the GAA device may include a plurality of GAA transistor structures according to the first aspect, and in such a GAA device, different types of transistor structures (e.g., NMOS and PMOS) may be combined.

[0041] For a GAA device as a logic device, the reduction in the channel layer pitch achieved by the GAA transistor structure of the first aspect results in a net increase in speed, but with a very small possible loss in drive current (on-current). In addition, the GAA device being an I / O device means that the GAA transistor structure of the first aspect enables the I / O device to maintain process compatibility with its logic device counterpart, even if they may require a thicker gate dielectric layer.

[0042] The third aspect of the present disclosure provides a method for manufacturing a GAA transistor structure, the method including: forming a stack of two or more semiconductor channel layers and one or more first gate layers alternately arranged along a first direction; wherein each semiconductor channel layer is encapsulated by a gate dielectric layer, and wherein each first gate layer is sequentially arranged between two of the semiconductor channel layers in the first direction; and forming two second gate layers that sandwich the stack in a second direction perpendicular to the first direction and are connected to the one or more first gate layers; wherein each first gate layer is made of a first work function metal structure, and each second gate layer is made of a second work function metal structure having a work function different from that of the first work function metal structure; and wherein each first gate layer has a first thickness, and each second gate layer has a second thickness greater than the first thickness.

[0043] The method of the third aspect can be used to manufacture the GAA transistor structure of the first aspect and / or the GAA device of the second aspect. The method of the third aspect achieves the same advantages as the GAA transistor structure of the first aspect and can be extended by the corresponding implementations for the GAA transistor structure of the first aspect as described above. In other words, the method of the third aspect may include additional steps to manufacture various implementations of the GAA transistor structure of the first aspect.

[0044] According to the above aspects and implementations, the present disclosure respectively proposes a GAA transistor structure and a GAA device, taking into account the thin first gate layer for manufacturing the inner gate, and the work function mismatch between the second gate layer for manufacturing the outer gate and the first gate layer.

[0045] Simulations (TCAD) show that by changing the first work function of the first gate layer by ±250 meV compared to the second work function of the second gate layer, very good device performance (such as device speed) of logic devices and I / O devices can be achieved. Simulations were performed on GAA devices with a 11 nm channel layer pitch and four channel layers in the stack. The simulations specifically show that the on-current losses of the logic device and the I / O device do not exceed 9% and 3% respectively. The simulations show that the channel layer pitch can be reduced, for example, to 11 nm, which results in a significant reduction in the effective capacitance and a significant increase in the device speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above aspects and implementations are explained in the following detailed description with reference to the accompanying drawings:

[0047] Figure 1 A GAA transistor structure according to the present disclosure is shown.

[0048] Figure 2 An exemplary GAA transistor structure according to the present disclosure is shown.

[0049] Figure 3 Examples of the first work function metal structure of the first gate layer and examples of the second work function metal structure of the second gate layer in the GAA transistor structure according to the present disclosure are shown.

[0050] Figure 4 A flowchart of the method steps of a method for manufacturing a GAA transistor structure according to the present disclosure is shown.

[0051] Figure 5 Results of an exemplary GAA device according to the present disclosure, which is fabricated based on the GAA transistor structure according to the present disclosure, are shown. DETAILED DESCRIPTION

[0052] Figure 1 A GAA transistor structure 10 according to an embodiment of the present disclosure is shown. According to another embodiment of the present disclosure, the GAA transistor 10 may be included in a GAA device. The GAA device may be a nanosheet device or a fork-sheet device.

[0053] The GAA transistor structure 10 includes a stack 11 of two or more semiconductor channel layers 12 and one or more first gate layers 13, wherein the channel layers 12 and the first gate layers 13 are along a first direction 15 ( Figure 1in the vertical direction) are arranged alternately. Each first gate layer 13 is arranged between two semiconductor channel layers 12 and follows one another in the stack 11 along the first direction 15. In other words, the stack 11 starts with the first channel layer 12 and then alternately provides the first gate layer 11 and another channel layer 12 to form a stack on the first channel layer 12. Each channel layer 12 is encapsulated by a gate dielectric layer 14 to isolate and separate the channel layer 12 from the adjacent first gate layer 13. The gate dielectric layer 14 can be a single layer or a stack of dielectric layers. The first FET structure can be formed by each first gate layer 13, the semiconductor channel layer 12 adjacent to the first gate layer 13, and the gate dielectric layer 14 that separates the first gate layer 13 from the adjacent channel layer 12.

[0054] The GAA transistor structure 10 further includes two second gate layers 16, where the two second gate layers 16 sandwich the stack 11 in a second direction 17 ( Figure 1 in the horizontal direction) perpendicular to the first direction 15. In other words, one second layer 16 is arranged on either of the two opposite sides of the stack 11 along the second direction 17. It should be noted that if the GAA transistor structure 10 is used in a GAA cross-sheet device, the stack 11 can be divided by a dielectric wall into a first part and a second part of the stack 11, which are arranged side by side along the second direction 17. The first part of the stack 11 can include NMOS channel layers, while the second part of the stack 11 can include PMOS channel layers. In this case, one of the two second gate layers 16 and the dielectric wall sandwich the first part of the stack 11 in the second direction 17, while the other of the two second gate layers 16 and the dielectric wall sandwich the second part of the stack 11 in the second direction 17.

[0055] The second gate layer 16 is also connected to one or more first gate layers 13. Both the second gate layer 16 and the first gate layer 13 can be part of the GAA metal structure of the GAA transistor structure 10 or can be part of a GAA device made based on the GAA transistor 10, respectively. The second FET structure can be formed by each second gate layer 16, any semiconductor channel layer 12 (note that each channel layer is adjacent to the second gate layer 16), and the gate dielectric layer 14 that encapsulates the channel layer 12. Each gate dielectric layer 14 also isolates and separates the channel layer 12 it encapsulates from the second gate layer 16.

[0056] In addition, each first gate layer 13 of the GAA transistor structure 10 is made of a first work function metal structure, while each second gate layer 16 is made of a second work function metal structure. The work function metal structure may include one or more work function metals or metal layers. The first work function metal structure has a different work function from the second work function metal structure. Specifically, the first work function of the first work function metal structure is different from the second work function of the second work function metal structure. For example, the difference between the first work function of the first work function metal structure and the second work function of the second work function metal structure is in the range of -250 meV to +250 meV. In other words, the first work function is greater than the second work function, or the second work function is greater than the first work function.

[0057] In addition, each first gate layer 13 of the GAA transistor structure 10 has a first thickness 18 along a first direction 15, while each second gate layer 16 has a second thickness 19 along a second direction 17, where the second thickness 19 is greater than the first thickness 18. For example, the first thickness 18 can be 1 nm or 2 nm or any value between 1 nm and 2 nm, while the second thickness 19 can be 5 nm, 6 nm, or 7 nm or any value between 5 nm and 7 nm. Optionally, the ratio of the second thickness 19 to the first thickness 18 can be equal to or greater than 4:1, such as equal to or greater than 5:1, or even equal to or greater than 6:1.

[0058] Therefore, there is a work function mismatch and a thickness mismatch between the first gate layer 13 that forms the inner gate in the GAA device fabricated based on the GAA transistor structure 10 and the second gate layer 16 that forms the outer gate (specifically, the side gate) of the GAA device.

[0059] Figure 2 The GAA transistor structure 10 according to an exemplary embodiment of the present disclosure is shown. Compared with the Figure 1 GAA transistor structure 10, Figure 2 the GAA crystal structure 10 can have further optional features. Each of these optional features can be added to the Figure 1 GAA transistor structure 10 individually or in any combination with other optional features.

[0060] As Figure 2As shown, two or more semiconductor channel layers 12 of the GAA transistor structure 10 may be arranged along a first direction 15 with a pitch 22. The pitch 22 may be equal to or less than 13 nm, as described above. The pitch 22 may vary along the first direction 15, that is, it is not necessary that the same distance exists between every two adjacent semiconductor channel layers 12 along the first direction 15. However, in a possible embodiment, the pitch 22 is constant in the stack 11, that is, any two adjacent semiconductor channel layers 12 along the first direction 15 have the same distance from each other (corresponding to the pitch 22). This distance may be measured from the center to the center of two adjacent channel layers 12.

[0061] As Figure 2 As further shown, the GAA transistor structure 10 may further include two additional second gate layers 21 sandwiching the stack 11 in the first direction 15. That is, relative to the first direction 15, one of these additional second gate layers 21 may be arranged below the stack 11 and the other may be arranged above the stack 11. It is also possible to arrange only one additional second gate layer 21 above or below the stack 11. The second gate layer 12 and the additional second gate layers 21 may be designed similarly. In particular, they may have the same second thickness 19 and may be made of the same second work function metal structure. The additional second gate layers 21 are connected to one or more first gate layers 13 and two second gate layers 16 clamping the stack 11 in a second direction 17. The first gate layer 13, the second gate layers 16, and the additional second gate layers 21 may form the GAA metal structure of a GAA device made based on the GAA transistor structure 10. This GAA metal structure surrounds the channel layers 12 encapsulated by the gate dielectric layer 14 in the first direction 15 and the second direction 17. The channel layers 12 are surrounded individually and as the stack 11 in the first direction 15 and the second direction 17.

[0062] As Figure 2 As further shown, the GAA transistor structure 10 may further include an encapsulation 23, which may protect the stack 11 and the first and second gate layers 13, 16, 21, respectively. For example, the encapsulation 23 may be made of tungsten or another metal material. The encapsulation 23 may be arranged to at least partially surround the stack 11 and the (additional) second gate layers 16, 21. The encapsulation 23 may also be used to contact the gate layers 13, 16, 21. For example, one or more gate contacts may be used to contact the GAA metal structure formed by these gate layers 13, 16, 21. The stack 11 and optionally the two additional gate layers 21 may all be arranged on a substrate. In addition, the encapsulation 23 may be arranged on the substrate and may surround the stack 11 on the sides and the top, and optionally surround the two additional gate layers 21.

[0063] Figure 3Examples of the first gate layer 13 and the second gate layer 16 are shown respectively, as they can be implemented in the Figure 1 or Figure 2 GAA transistor structure 10. Specifically, Figure 3 An example of the first work function metal structure 34 is shown, from which each first gate layer 13 is made, and an example of the second work function metal structure 30, from which each second gate layer 16 is made.

[0064] Figure 3 The second work function metal structure 30 shown in the upper part of includes a plurality of metal layers, such as a set of metal layers. Here, it exemplarily includes three metal layers 31, 32, and 33. The second work function metal structure 30 can particularly consist of these metal layers 31, 32, 33. Figure 3 The first work function metal structure shown in the lower part of also includes a plurality of metal layers, such as a subset of metal layers. The subset of metal layers includes the metal layers included in the set of metal layers. Here, it exemplarily includes the metal layers 31 and 32 in the set of metal layers. The first work function metal structure 34 can consist of the subset of metal layers. For example, the first work function metal structure 34 can consist of only one layer 31, or can consist of two layers 31, 32 in the set of metal layers, where the second work function metal structure 30 consists of this set of metal layers (it is worth noting that this is exemplarily represented by the same shading in Figure 3 ).

[0065] In a first example, the second work function metal structure 30 can be composed of three metal layers, namely a titanium nitride layer 31, a tantalum nitride layer 32, and a titanium aluminide layer 33 (e.g., in this order). In a second example, the second work function metal structure 30 can be composed of three metal layers, namely a first titanium nitride layer 31, a titanium aluminide layer 33, and a second titanium nitride layer 31 (e.g., in this order). In a third example, the second work function metal structure 30 can be composed of five metal layers, namely a first titanium nitride layer 31, a tantalum nitride layer 32, a second titanium nitride layer 31, a titanium aluminide layer 33, and a third titanium nitride layer 31 (e.g., in this order). For example, the first or second example can be used for the NMOS stack 11, while the third example can be used for the PMOS stack 11. The titanium aluminide can also contain some carbon. According to the first, second, or third example, the first work function metal structure 34 can be composed of a subset of the metal layers of the second work function metal structure 30. In the example, the first work function metal structure 34 can be composed of a single metal layer that is the titanium nitride layer 31, or can be composed of two metal layers that are the titanium nitride layer 31 and the tantalum nitride layer 32 respectively. For a layer in the subset of metal layers (compared with the same layer in the set of metal layers), there may also be a partial layer. For example, the second work function metal structure 30 can be composed of a titanium nitride layer 31, a tantalum nitride layer 32, and a titanium aluminide layer 33, while the first work function metal structure 34 is composed of a titanium nitride layer 31 and a partial tantalum nitride layer 32, or is composed of a titanium nitride layer, a tantalum nitride layer 32, and a partial titanium aluminide layer 33. Partial means a reduction in layer thickness. Other metal layers that can be used for the set of metal layers and / or the subset of metal layers include a molybdenum nitride layer and a scandium oxide layer. The metal layers in the set of metal layers and / or the subset of metal layers can also be made of any one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, TiAl, Ru, Mo, Al, WN, Cu, W, Ir, Co, Ni or any combination of these metals, or made of any other suitable metal material.

[0066] The first metal layer metal structure 34 has a first work function, while the second metal layer metal structure 30 has a second work function, where the first work function can depend on the individual work functions and thicknesses of the metal layers 31, 32 in the subset of metal layers used for the first work function metal structure 34. The second work function can depend on the work functions and thicknesses of the individual work functions of the metal layers 31, 32, 33 in the set of metal layers used for the second work function metal structure 30. The same metal layers in the set of metal layers and the subset of metal layers can have the same corresponding thicknesses and work functions.

[0067] Figure 4 A flowchart showing the steps of a method 40 for manufacturing a GAA transistor structure 10 such as shown in Figure 1 and Figure 2 is shown.

[0068] Method 40 generally includes step 41 of forming a stack 11 of two or more semiconductor channel layers 12 and one or more first gate layers 13, which are alternately arranged along a first direction 15. Each semiconductor channel layer 12 is encapsulated by a gate dielectric layer 14, i.e., method 40 may include the step of encapsulating each channel layer 12 with a dielectric material. This may be a high-k material. The dielectric material of the gate dielectric layer 14 may also be silicon oxide and / or hafnium oxide. The material of the channel layer 12 may be silicon or a silicon-based material. Each first gate layer 13 is disposed between two semiconductor channel layers 12 that follow each other along the first direction 15 among two or more semiconductor channel layers 12.

[0069] Method 40 further includes step 42 of forming 42 two second gate layers 16 that sandwich the stack 11 in a second direction 17 perpendicular to the first direction 15, wherein the two second gate layers 16 are connected to one or more first gate layers 13.

[0070] Each first gate layer 13 is made of a first work function metal structure 34, and each second gate layer 16 is made of a second work function metal structure 30 different from the first work function metal structure 34. Each first gate layer 13 is made to have a first work function, while each second gate layer 16 is made to have a second work function. In addition, each first gate layer 13 is made to have a first thickness 18, and each second gate layer 16 is made to have a second thickness 19 greater than the first thickness 18. Method 40 may also include fabricating Figure 2 the additional second gate layers 21 shown, wherein these additional second gate layers 21 may be made to have the same second work function and second thickness 19 as the second layer 16.

[0071] In an example of implementing Figure 4 the method 40 shown, the channel layers 12 may first be fabricated and encapsulated separately with the gate dielectric layer 14. For example, the channel layers 12 may be fabricated in a dummy stack, where they are alternately arranged with dummy gate layers along the first direction 15. Then, these dummy gate layers may be selectively removed, leaving only the channel layers 12 and the gaps between the channel layers 12. Then, encapsulation may be performed with the gate dielectric layer 14. However, encapsulation with the gate dielectric layer 14 may also be performed before the dummy gate layers are removed. There may also be other ways to form the channel layers 12 with gaps therebetween.

[0072] Thereafter, a first metal material can be deposited, for example, titanium nitride can be deposited. The first metal material can be deposited into the gaps formed between the encapsulated channel layers 12. The first metal material can also be deposited simultaneously on the side surfaces of the channel layers 12 in a second direction 17 and optionally on top of the uppermost channel layer 12 and / or below the lowermost channel layer in a first direction 15. For example, by using bottom dielectric isolation, the deposition of the first metal material can be inhibited at least below the lowermost channel layer. The deposition of the first metal material can continue until the gaps between the channel layers 12 are completely filled. These gaps can each have a dimension in the first direction 15 that corresponds to Figure 1 the first thickness 18 shown. In this way, a first gate layer 13 can be formed by depositing the first metal material into the gaps, where the first metal material can include a single metal, such as titanium nitride, such that the titanium nitride layer 31 can form each first work function metal structure 34.

[0073] Meanwhile, during the deposition of the first metal material into the gaps, the first metal material is also deposited on the side surfaces of the channel layers 12 with the same first thickness 18 (but along the second direction 17). Now, a further deposition step can be carried out, where a second metal material can be deposited, for example, tantalum nitride can be deposited. Since the gaps have been completely filled with the first metal material, the second metal material will only be deposited on the first metal material disposed on the side surfaces of the channel layers 12 and on the side surfaces of the first metal material formed between the channel layers 12. The first metal material and the second metal material on the side surfaces of the channel layers 12 can form a second gate layer 16, so the second gate layers 16 can each include a bimetallic material. For example, the titanium nitride layer 31 and the tantalum nitride layer 32 can form each second work function metal structure 30.

[0074] It can be understood that after the deposition of the first metal material, the work function can be the same around the channel 12. However, with the further deposition of the second metal material, the work function may change on the side surfaces of the channel layers 12. In other words, the second metal material can be deposited in a work function tuning step. For example, the second work function metal structure 30 composed of the titanium nitride layer 31 and the tantalum nitride layer 32 ultimately has a second work function different from the first work function of the first work function metal structure 34, and the first work function structure 34 is composed of a single titanium nitride layer 31, for example.

[0075] Of course, the above examples for implementing method 40 can also separately produce different first work function metal structures 34 and different second work function metal structures 30. This may depend on when each metal material is deposited and for how long, as well as the frequency of changing the deposited metal material. For example, before the gaps between the channel layers 12 are completely filled, changes can also be made between the first metal material and the second metal material. In this case, each first work function metal structure 34 will consist of two metal layers, such as a titanium nitride layer 31 and a tantalum nitride layer 32. Once the gaps are completely filled by these two metal layers, a third metal material, such as titanium aluminide, can be deposited. In this case, the titanium aluminide layer 33 will only be formed on the two metal layers 31, 32 that have already been formed on the sides of the channel layer 12. Thus, each second work function metal structure 30 can ultimately consist of a titanium nitride layer 31, a tantalum nitride layer 32, and a titanium aluminide layer 33. In this way, many metal material combinations are possible, and the work function tuning can be adjusted depending on the type of the GAA transistor structure 10 and / or the type of the GAA device based on the GAA transistor structure.

[0076] As described above, the present disclosure provides a GAA device in which a metal gate has a work function mismatch between a side gate (formed by a second metal layer 16) and an inner gate (formed by a first metal layer 13), or generally between the inner gate and an outer gate (formed by the second metal layer 16 and an additional metal layer 21, respectively). The inner gate can be a very thin metal gate (e.g., the first metal layer 13 can be between 1 - 2 nm compared to the second metal layer 16 between 5 - 7 nm and an optional additional second metal layer 21).

[0077] Compared with a conventional GAA device having no work function mismatch between the inner gate and the outer gate, the GAA device of the present disclosure is easier to fabricate at the same channel layer pitch 22. The GAA device of the present disclosure also shows competitive device performance.

[0078] For example, the device performance can be evaluated by looking at the on - current I on and the off - current I off . At least for a mismatch within the range of ±250 meV between the first work function and the second work function, the decrease in I on of the GAA device according to the present disclosure is very small compared to a conventional GAA device. It is also found that even when the width of the channel layer 12 (along the second direction 17) is increased to a channel width within the range of, for example, 10 - 60 nm, the decrease in I on is limited to 4%. Thus, the GAA device according to the present disclosure having a thin inner metal gate and a work function mismatch is a viable option for a wide range of channel layer 12 widths and may even be superior to conventional FinFET devices.

[0079] Figure 5 shows simulation results of a GAA device (a device with a "tuned second WF (work function)") according to the present disclosure, the device including a GAA transistor structure 10 and two conventional GAA devices ("uniform WF"). The channel layer spacings of the two conventional GAA devices are 11 nm and 15 nm respectively, while the GAA device according to the present disclosure has a channel layer spacing of 11 nm 22 (see Figure 2 ).

[0080] Figure 5 The graph of off (A) analyzes the relationship with speed (%). Here, for the same I off , the conventional GAA device with a 11 nm channel layer spacing is expected to be faster than the conventional GAA device with a 15 nm channel layer spacing. The GAA device of the present disclosure is between these two conventional devices. That is, for the same I off as the conventional GAA device, the GAA device of the present disclosure is faster than the conventional GAA device with a 15 nm channel layer spacing. Although the GAA device of the present disclosure experiences a loss of I on relative to the conventional GAA device. In addition, the GAA device of the present disclosure is only slightly slower than the conventional GAA device with a 11 nm channel layer spacing. It is noted that the conventional GAA device with a 11 nm channel layer spacing is only a "hypothetical" device because it is almost impossible to fabricate in real life or can only be fabricated by a very technically complex process.

[0081] In addition, Figure 5 both graphs show that the GAA device of the present disclosure is very effective for different I off values. This means that the GAA device can be fabricated into different variants with different threshold voltages. Therefore, the process of fabricating the GAA transistor structure 10 and the GAA device of the present disclosure respectively realizes multiple Vt options.

Claims

1. A gate-all-around (GAA) transistor structure (10) comprising: A stack (11) of two or more semiconductor channel layers (12) and one or more first gate layers (13) alternately arranged along a first direction (15); Wherein each semiconductor channel layer (12) is encapsulated by a gate dielectric layer (14), and wherein each first gate layer (13) is sequentially arranged between two of the semiconductor channel layers (12) in the first direction (15); and Two second gate layers (16) that sandwich the stack (11) in a second direction (17) perpendicular to the first direction (15) and are connected to the one or more first gate layers (13); Wherein each first gate layer (13) is made of a first work function metal structure (34), and each second gate layer (16) is made of a second work function metal structure (30) having a work function different from that of the first work function metal structure (34); and Wherein each first gate layer (13) has a first thickness (18), and each second gate layer (16) has a second thickness (19) greater than the first thickness (18).

2. The GAA transistor structure (10) according to claim 1, wherein, The ratio of the second thickness (19) to the first thickness (18) is equal to or greater than 4:

1.

3. The GAA transistor structure (10) according to claim 1 or 2, wherein The first thickness (18) is in the range of 1 - 2 nm, and the second thickness (19) is in the range of 5 - 7 nm.

4. The GAA transistor structure (10) according to one of claims 1 to 3, characterized in that, The difference between the first work function of the first work function metal structure (34) and the second work function of the second work function metal structure (30) is in the range of -250 meV to +250 meV.

5. The GAA transistor structure (10) according to claim 4, wherein, The GAA transistor structure (10) is an NMOS transistor structure, the first work function is in the range of 4.4 - 4.6 eV, and the second work function is in the range of ±250 meV of the first work function.

6. The GAA transistor structure (10) according to claim 4, wherein The GAA transistor structure (10) is a PMOS transistor structure, the first work function is in the range of 4.6 - 4.8 eV, and the second work function is in the range of ±250 meV of the first work function.

7. The GAA transistor structure (10) according to any one of claims 1 to 6, characterized in that, The two or more semiconductor channel layers (12) are arranged with a pitch (22) along the first direction (15), and the pitch (22) is equal to or less than 13 nm.

8. The GAA transistor structure (10) according to any one of claims 1 to 7, characterized in that, The second work function metal structure (30) includes a set of metal layers (31, 32, 33), and the first work function metal structure (34) includes a subset of metal layers (31, 32) included in the set of metal layers (31, 32, 33).

9. The GAA transistor structure (10) according to one of claims 1 to 8, characterized in that, The second work function metal structure (30) consists of three metal layers (31, 32, 33) made of titanium nitride, tantalum nitride, and titanium aluminide, respectively.

10. The GAA transistor structure (10) according to one of claims 1 to 9, characterized in that, The first work function metal structure (34) consists of a single metal layer (31) made of titanium nitride, or consists of two metal layers (31, 32) made of titanium nitride and tantalum nitride, respectively.

11. The GAA transistor structure (10) according to any one of claims 1 to 10, characterized in that, It further includes two additional second gate layers (21), which sandwich the stack (11) in the first direction (15) and are connected to the one or more first gate layers (13) and the two second gate layers (16) that sandwich the stack in the second direction (17).

12. The GAA transistor structure (10) according to one of claims 1 to 11, characterized in that, Each semiconductor channel layer (12) is formed of nanosheets; and / or made of one of silicon, silicon germanium, III-V semiconductor materials, and 2D materials.

13. The GAA transistor structure (10) according to one of claims 1 to 12, characterized in that: The first field-effect transistor FET structure is formed by the first gate layer (13), the gate dielectric layer (14) encapsulating the semiconductor channel layer (12), and the semiconductor channel layer (12); And The second FET structure is formed by the second gate layers (16, 21), the gate dielectric layer (14) encapsulating the semiconductor channel layer (12), and the semiconductor channel layer (12); Each first FET structure has a first threshold voltage, and each second FET structure has a second threshold voltage different from the first threshold voltage.

14. A GAA device, comprising the GAA transistor structure (10) according to one of claims 1 to 13, wherein the GAA device is a logic device or an input / output device.

15. A method (40) for manufacturing a GAA transistor structure (10), the method (40) comprising: Forming (41) a stack (11) of two or more semiconductor channel layers (12) and one or more first gate layers (13) alternately arranged in a first direction (15); Wherein each semiconductor channel layer (12) is encapsulated by a gate dielectric layer (14), and wherein each first gate layer (13) is sequentially arranged between two of the semiconductor channel layers (12) in the first direction (15); And Forming (42) two second gate layers (16), which sandwich the stack (11) in a second direction (17) perpendicular to the first direction (15) and are connected to the one or more first gate layers (13); Wherein each first gate layer (13) is made of a first work function metal structure (34), and each second gate layer (16) is made of a second work function metal structure (30) having a work function different from that of the first work function metal structure (34); and Wherein each first gate layer (13) has a first thickness (18), and each second gate layer (16) has a second thickness (19) greater than the first thickness (18).

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