Fabrication of three-dimensional semiconductor structures

Abstract

In certain embodiments, a method includes forming a layer stack of alternating layers of first and second carbonaceous materials on a substrate by spin-on deposition. The layers of the first carbonaceous material include a reagent generating component for generating a solubility changing reagent in response to an activation trigger. The method includes performing an activation trigger, in response to the activation trigger, the solubility-changing reagent generating composition generation from the reagent in the layers of the first carbonaceous material, and modifying the layers of the first carbonaceous material to be soluble in a developer. The method includes etching a plurality of first openings through the layer stack, filling the first openings with a third material, etching a plurality of second openings through the layer stack, removing the layers of the first carbonaceous material from the layer stack by exposing them to the developer, and replacing the layers of the first carbonaceous material with a fourth material.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 17 / 978,674, filed on November 1, 2022, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This disclosure generally relates to the field of semiconductors and, in certain embodiments, to the fabrication of three - dimensional (3D) semiconductor structures. Background Art

[0004] Device formation within a microelectronic workpiece typically involves a series of fabrication techniques related to the formation, patterning, and removal of material layers on a substrate. To meet the physical and electrical specifications of current and next - generation semiconductor devices, the processing flow is required to reduce feature sizes while maintaining the structural integrity of various patterning processes.

[0005] 3D structures are becoming common structures on microelectronic workpieces to increase device density. Examples of such 3D structures for microelectronic workpieces include fin - field - effect transistors (FINFETs), 3D memory structures, and / or other 3D structures. However, with increasing density requirements, improvements are needed to reduce production costs and maintain device integrity and performance in 3D structures (e.g., 3D memory structures).

[0006] In the case of a typical two - dimensional (2D) or planar semiconductor device, the integration level can be judged by the area occupied by a unit memory cell, which can be related to the level of fine patterning technology used to form these cells. However, the cost associated with the processing equipment used for such fine patterning may limit the integration level of 2D or planar semiconductor devices. To overcome such limitations, 3D semiconductor devices, including three - dimensionally arranged memory cells (e.g., in a 3D vertical NAND (VNAND) memory structure) have been used. Summary of the Invention

[0007] In some embodiments, a method includes forming a layer stack of alternating layers of a first and a second carbonaceous material on a substrate by spin coating deposition. The layers of the first carbonaceous material include reagent generating components for generating solubility altering reagents in response to an activation trigger. The method includes performing the activation trigger, in response to which the solubility altering reagents are generated from the reagent generating components in the layers of the first carbonaceous material and the layers of the first carbonaceous material are modified to be soluble in a developer. The method includes etching a plurality of first openings through the layer stack, filling the first openings with a third material, etching a plurality of second openings through the layer stack, removing the layers of the first carbonaceous material from the layer stack by exposing the layers of the first carbonaceous material to the developer, and replacing the layers of the first carbonaceous material with a fourth material.

[0008] In some embodiments, a method includes forming a layer stack on a substrate composed of a plurality of first layers of a first carbonaceous material and a plurality of second layers of a second carbonaceous material. The first layers and the second layers are deposited by spin coating deposition. The first layers include a photoresist material or a developable anti-reflective coating and include a thermal acid generator (TAG). The method includes performing a first bake of the substrate. The first bake causes the TAG to generate an acid in the first layers, and the acid modifies the first layers to be soluble in a developer. The method includes etching a plurality of first openings through the layer stack; filling the first openings with a first fill material that includes a metal oxide material; etching a plurality of second openings through the layer stack; exposing the first layers to the developer to remove the first layers from the layer stack; replacing the first layers with a third material that is an oxide or a nitride; removing the second layers from the layer stack; replacing the second layers with a fourth material; removing the first fill material from the first openings; and replacing the first fill material in the first openings with a second fill material that includes one or more of silicon dioxide, silicon nitride, and polysilicon.

[0009] In some embodiments, a method for fabricating a 3D NAND device includes forming a layer stack on a substrate that consists of multiple first layers of a first carbon-containing material and multiple second layers of a second carbon-containing material that alternate. These first layers and these second layers are deposited by spin coating. These first layers include a photoresist material or a developable anti-reflective coating, and include a reagent generating component that generates a solubility-changing reagent in response to an activation trigger. The method includes performing the activation trigger, and the solubility-changing reagent is generated from the reagent generating component in these first layers in response to the activation trigger, and the solubility-changing reagent modifies these first layers to be soluble in a developer. The method includes etching a plurality of channel holes through the layer stack, filling these channel holes with a third material, and etching a plurality of slits through the layer stack, and these slits expose the alternating first layers and second layers of the layer stack. The method includes removing these first layers from the layer stack by exposing these first layers to the developer, and replacing these first layers with a fourth material, and the fourth material includes an oxide or a nitride. The method includes removing these second layers from the layer stack by exposing these second layers to an etching chemical, and replacing these second layers with a fifth material, and the fifth material is a metal-containing material.

[0010] Different or additional features, variations, and embodiments may also be implemented, and related systems and methods may also be used. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more fully understand the present disclosure and its advantages, reference is made to the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1A - 1M A cross-sectional view and a plan view of an exemplary semiconductor structure during an example process for forming a 3D semiconductor structure are illustrated in accordance with some embodiments;

[0013] Figure 2A - 2F A plan view of an exemplary semiconductor structure during an example process for forming a 3D semiconductor structure is illustrated in accordance with some embodiments;

[0014] Figure 3A - 3B A flowchart of an example method for forming a 3D semiconductor structure is illustrated in accordance with some embodiments;

[0015] Figure 4 A flowchart of an example method for forming a 3D semiconductor structure is illustrated in accordance with some embodiments;

[0016] Figure 5 A flowchart of an example method for forming a 3D semiconductor structure is illustrated in accordance with some embodiments;

[0017] Figure 6A block diagram of an exemplary coater - developer system in accordance with some embodiments is shown;

[0018] Figure 7 A block diagram of an exemplary coater - developer system in accordance with some embodiments is shown;

[0019] Figure 8 An exemplary liquid - based spin - coating deposition system in accordance with some embodiments is shown;

[0020] Figure 9 An example processing system for chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma - enhanced CVD (PECVD), plasma - enhanced ALD (PEALD), vapor etching, or plasma etching processes in accordance with some embodiments is shown; and

[0021] Figure 10A - 10B An example aspect of a 3D NAND memory array in accordance with some embodiments is shown.

[0022] Embodiments

[0023] To increase the density of memory devices and reduce the cost per bit, the processes of the present invention are used to form 3D memory structures. For example, 3D VNAND memory cells have been developed using 3D stacked structures. Fabricating such 3D semiconductor structures can include forming stacked films of alternating materials, such as oxide - nitride - oxide - nitride (ONON) alternating stacks or oxide - polysilicon - oxide - polysilicon (OPOP) stacks. These stacks can include up to 200 layers or more, and sometimes exceed 300 layers. Additionally, it is expected that the stack height will increase in the future.

[0024] However, unlike planar NAND (e.g., 2D NAND), 3D VNAND stacked thin films can stress the wafer, which can cause the wafer to bend and / or other defects. As the layer stack height of 3D VNAND devices (including additional layers in the layer stack) continues to increase, the corresponding manufacturing cost also increases. For example, to create the stacked films of these 3D semiconductor devices, the plasma processes for depositing each layer of the stacked film can be repeated, such as once for each layer of the stack. Repeating these processes is expensive in terms of manufacturing time and material / equipment cost. Additionally, repeating these plasma deposition processes stresses the wafer greatly, which can cause defects such as wafer bending. These stresses and bending can affect the ability to achieve precise lithography overlay during the fabrication of 3D semiconductor structures and may ultimately have an adverse effect on device performance.

[0025] According to some known techniques, multiple layers can be deposited in an alternating arrangement by using chemical vapor deposition (CVD) processing, plasma-enhanced PVD (PECVD) processing, physical vapor deposition (PVD) processing, or plasma-enhanced PVD (PEPVD) processing to form a layer stack. These deposition processes are expensive both in terms of time (e.g., low throughput) and money (e.g., materials, equipment (including wear) and other items). In addition, each instance of performing the deposition process imposes stress on the formed semiconductor structure, such as generating high internal stress, which may introduce defects over time, such as bending of the structure.

[0026] In addition, etching processes for forming various openings such as vias (e.g., channel vias) and slits (e.g., for lines) in the layer stack can be difficult, time-consuming, and have other problems.

[0027] Certain embodiments of the present disclosure include processes for reducing the manufacturing cost of 3D semiconductor structures (e.g., 3D memory devices) and for reducing overlay and internal stress issues. The techniques herein include the use of spin-on films and sacrificial coatings. Spin-on films can produce low-stress wafers and can facilitate high-throughput manufacturing of such 3D semiconductor structures, and can have a relatively low deposition cost. Certain embodiments may be particularly useful for 3D VNAND devices or other 3D semiconductor structures.

[0028] In certain embodiments, the spin-on materials used can include spin-on carbon (SOC), silicon oxycarbide (SiOC), organic dielectric layer (ODL), organic planarization layer (OPL), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), photoresist, bottom anti-reflective coating (BARC), developable BARC (DBARC), epoxy resin, etc. Some of these examples may overlap in type.

[0029] Generally, certain embodiments of the present disclosure include using spin-on deposition processing to form an initial layer stack of sacrificial materials, and then removing and replacing those sacrificial materials through various processes to obtain the desired layer stack of the 3D semiconductor structure. Different from the expensive and stress-inducing processes associated with directly constructing an initial layer stack with the desired layers, these sacrificial materials of the initial layer stack are deposited using spin-on techniques, which can be relatively fast and less stress-inducing. In addition, the desired layers deposited to replace these sacrificial layers can all be deposited in a single deposition step, such as using ALD or other CVD processing.

[0030] In addition to spin coating, in certain embodiments, carbon-based layers are used in a layer stack, and these carbon-based layers can be etched more effectively when openings (e.g., via holes for channels and / or slits for gates) are formed in the layer stack and when the layer is removed and replaced with another material. In certain embodiments, a layer is a carbon-based layer that includes a reagent generating component that can be activated in response to an activation trigger, thereby causing the generation of a solubility-changing reagent that causes a change in the solubility of the layer such that the layer is developable in a solvent. Other types of layers in the layer stack may be insoluble in the developer, and this can allow for selective removal and replacement of one type of layer in the layer stack each time. In certain embodiments, the reagent generating component is a thermal acid generator (TAG) or a photoacid generator (PAG), and the solubility-changing reagent is an acid.

[0031] Different or additional features, variations, and embodiments may also be implemented, and related systems and methods may also be used. Other advantages and implementations may also be achieved while still leveraging the advantages of the structures and processing techniques described herein.

[0032] Figure 1A - 1M Figures 2A - 2F illustrate cross-sectional views and, in some cases, plan views of an example process for forming a 3D semiconductor structure according to certain embodiments. For each of these figures, it should be understood that the example shown may depict a portion of the semiconductor structure being processed, and the structure shown may extend into and out of the page and / or to the left, right, top, and / or bottom of the portion shown. Throughout this disclosure, a semiconductor structure may also be referred to or indicated as a device, a semiconductor device, a wafer, a workpiece, etc. In certain embodiments, the process shown is for forming a 3D memory structure, such as a 3D VNAND structure, from a semiconductor structure.

[0033] Figure 1A - 1M Illustrates a cross-sectional view and a plan view of an example semiconductor structure 102 during an example process 100 for forming a 3D semiconductor structure according to certain embodiments.

[0034] Figure 1A Illustrates a cross-sectional view of an example process for forming a layer stack 106 on a substrate 104. The formed layer stack 106 may include alternating layers 108a and 108b, which may be collectively referred to as layer 108. The layer stack 106 may also be referred to as a wafer stack or a multi-layer stack.

[0035] In stage 1, particularly in the first pass of stage 1, layer 108a may be deposited over substrate 104. Substrate 104 may include any substrate material suitable for forming a 3D semiconductor structure (e.g., a 3D memory device). For example, substrate 104 may be silicon or include silicon.

[0036] Layer 108a can be a layer that undergoes a solubility change when exposed to a solubility-changing reagent (e.g., an acid), and is subsequently removed in a development step. Layer 108a can be a carbon-containing layer whose solubility can be altered to develop in a developer during a subsequent part of process 100. Layer 108a can be a multi-component material that includes two or more components upon deposition. Layer 108a can include a carbon-containing component and a reagent generating component 110 for generating a solubility-changing reagent in response to an activation trigger. In certain embodiments, layer 108a includes a solvent to facilitate deposition (e.g., using spin coating deposition techniques). For example, the solvent can allow the material of layer 108a to be spun, thereby forming a thin layer on the underlying layer.

[0037] The carbon-containing component of layer 108a can include a polymer or another suitable type of organic material whose solubility can be altered using a solubility-changing reagent (e.g., an acid) generated by the reagent generating component 110 of layer 108a. The carbon-containing component (e.g., the polymer) is designed to change its structure when exposed to a solubility-changing reagent (e.g., an acid).

[0038] The reagent generating component 110 can include any suitable material that generates a solubility-changing reagent (e.g., an acid) in response to a suitable reagent activation trigger (e.g., heat or radiation). Exemplary reagent generating component 110 can include a thermal acid generator (TAG) configured to generate an acid or otherwise release an acid in response to heat, or a photoacid generator (PAG) configured to generate an acid or otherwise release an acid in response to ultraviolet (UV) light exposure (e.g., actinic radiation). The generated solubility-changing reagent (e.g., an acid) can cause a further chemical reaction in layer 108a that modifies layer 108a to be soluble in the developer. For example, the generated reagent can be a substance configured to change the solubility of a material, where the reagent is set to respond to a suitable trigger signal (e.g., heat), and thus can be referred to as a solubility-changing reagent.

[0039] For Figure 1A - 1M the purposes of the exemplary process 100, the reagent generating component 110 will be described as a TAG. This disclosure describes another example Figure 2A - 2F where the reagent generating component 110 is a PAG.

[0040] In some embodiments, layer 108a includes a photoresist material having an embedded reagent generating component 110 (e.g., a TAG or a PAG). For example, the photoresist material can be a chemically amplified resist (CAR). The photoresist material of layer 108a can be suitable for the type of solubility changing reagent and developer to be used such that layer 108a can undergo a solubility change and be removed using a developer. The photoresist material of layer 108a can be a positive photoresist or a negative photoresist.

[0041] As another specific example, layer 108a can include a developable anti-reflective coating (ARC), such as a developable bottom ARC (DBARC) having a reagent generating component 110.

[0042] At stage 2, a first bake 112a of semiconductor structure 102 can be performed to initiate a crosslinking reaction (e.g., a polymer crosslinking reaction) in layer 108a. For example, the polymer chains of layer 108a can be crosslinked through thermally induced bond formation. In some embodiments, the crosslinking can include C-C bond formation or S-S bond formation, etc. As just one specific example, layer 108a can include hydroxystyrene, which can crosslink in response to sufficient heat.

[0043] This crosslinking reaction can cause layer 108a to harden or otherwise strengthen, which can enable layer 108a to better withstand the stress of additional layers 108 as the height of layer stack 106 increases.

[0044] In some embodiments, bake 112a can be performed by heating semiconductor structure 102 in a processing chamber, in a vacuum or under a gas flow, at a temperature between 50°C and 250°C (e.g., between 140°C and 150°C in some embodiments). In some embodiments, the temperature at which bake 112a is performed is lower than the temperature of a bake that can be performed in a subsequent processing step to cause the reagent generating component 110 of layer 108a to generate a solubility changing reagent and change the solubility of layer 108a (see, for example Figure 1C and 1D ) by about 20°C - 40°C. In a specific example, semiconductor structure 102 is baked for 1 to 3 minutes. The bake conditions for bake 112a can be selected to promote crosslinking of layer 108a. This disclosure contemplates performing bake 112a in any suitable manner.

[0045] In stage 3, layer 108b can be deposited over layer 108a. Layer 108b can be a carbon-containing layer. Layer 108b can be a multi-component material that includes two or more components upon deposition. For example, layer 108b can include a carbon-containing component. The carbon-containing component of layer 108b can include a polymer or another suitable type of carbon-containing material. As another example, layer 108b can include a solvent to facilitate deposition (e.g., using spin coating deposition techniques). For example, the solvent can allow the material of layer 108b to be spun, thereby forming a thin layer over the underlying layer.

[0046] In certain embodiments, the material for layer 108b can be an organic material that is not developable in the developer that will be used in a subsequent processing step to remove layer 108a. The material for layer 108b can lack a reagent generating component (e.g., such as reagent generating component 110) that is capable of generating a reagent that would render layer 108b soluble in the developer that will be used in a subsequent processing step to remove layer 108a. As a specific example, the material for layer 108b can include spin-on carbon (SOC), silicon oxycarbide (SiOC), organic dielectric layer (ODL), organic planarization layer (OPL), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), photoresist, ARC, BARC, epoxy resin, etc. Some of these examples can overlap in type.

[0047] In stage 4, a bake 112b of the semiconductor structure 102 can be performed to initiate a crosslinking reaction (e.g., a polymer crosslinking reaction) in layer 108b. For example, the polymer chains of layer 108b can be crosslinked through thermally induced bond formation. In certain embodiments, the crosslinking can include C-C bond formation or S-S bond formation, etc. As just one specific example, layer 108b can include hydroxystyrene, which can crosslink in response to sufficient heat.

[0048] This crosslinking reaction can cause layer 108b to harden or otherwise strengthen, which can enable layer 108b to better withstand the stress of additional layers 108 as the height of layer stack 106 increases. In certain embodiments, the crosslinking reaction can render layer 108b insoluble in the developer that will be used in a subsequent processing step to remove layer 108a; however, in certain embodiments, layer 108b may already be insoluble in such a developer.

[0049] In certain embodiments, similar to bake 112a, bake 112b can be performed by heating the semiconductor structure 102 in a processing chamber, either in a vacuum or under a gas flow, at a temperature between 50°C and 250°C (e.g., between 140°C and 150°C in certain embodiments). In certain embodiments, the temperature at which bake 112b is performed is lower than the temperature of the bake that can be performed in a subsequent processing step to cause a solubility-changing reagent of the reagent generating component 110 of layer 108a and change the solubility of layer 108a (see, for example Figure 1C and 1D ), e.g., about 20°C - 40°C lower. In a specific example, the semiconductor structure 102 is baked for 1 to 3 minutes. The bake conditions of bake 112b can be selected to promote crosslinking of layer 108b. The present disclosure contemplates performing bake 112b in any suitable manner.

[0050] Bakes 112a and 112b can be optimized to cause crosslinking of the respective materials of layers 108a and 108b. Bakes 112a and 112b can be performed according to the same or different conditions, depending on which is suitable for a given implementation. In the present disclosure, bakes 112a and 112b can be collectively referred to as bake 112.

[0051] Stages 1 - 4 can be performed to construct the layer stack 106 of alternating layers 108a and 108b. For example, stages 1 - 4 can be repeated an appropriate number of times, as indicated by the circular arrow 114, to construct the layer stack 106 having a target number of layers 108. An example layer stack 106 that can include multiple alternating layers 108a and 108b is depicted and described in conjunction with Figure 1B and

[0052] Although stages 1 - 4 are shown, additional stages can be performed, or stages 1 - 4 can be combined in any suitable manner. In certain embodiments, bake 112 can be performed after depositing each layer 108 or after depositing more than two layers 108. Further, in terms of performing multiple bakes 112, the temperatures of the multiple bakes 112 can be the same or different, which may be appropriate for a given implementation. Additionally, although the first instance of layer 108a is described as being deposited before the first instance of layer 108b, the first instance of layer 108b can be deposited before the first instance of layer 108a.

[0053] In certain embodiments, in Figure 1ADuring the formation process of the stack, layers 108a and 108b can be deposited on the semiconductor structure 102 in any suitable manner. For example, layer 108 can be deposited by spin coating, spraying, dip coating, or roll - coating. As a specific example, spin - coating deposition technology can be used to deposit layer 108 on the semiconductor structure 102, and this technology can also be referred to as spin - coating.

[0054] In certain embodiments, spin - coating deposition (which can also be referred to as spin - coating) includes depositing a specific material (e.g., the material of the deposited layer 108) on a underlying layer (e.g., for the first layer 108, the substrate 104, or for subsequent layers 108 of the layer stack 106, the underlying layer 108). Then, the structure 102 is rotated at a relatively high speed (if not already rotating, a relatively low speed can be used), such that the centrifugal force causes the deposited material to move towards the edge of the substrate, thereby coating the substrate. Excess material typically spins out of the substrate. In certain embodiments, this spin - coating deposition technology includes using a coating module with a liquid delivery system to dispense liquid chemicals onto the semiconductor structure 102 (e.g., on the top surface of the substrate 104 or on the layers of the layer stack 106), and the liquid delivery system can dispense one or more types of liquid chemicals. The dispensed volume can be between 0.2 ml and 10 ml, such as 0.5 ml to 2 ml. The substrate (e.g., structure 102) can be fixed to a chuck used to support the substrate. The rotation speed during liquid dispensing can be between 50 rpm and 3000 rpm, such as 1000 rpm to 2000 rpm. The system can also include an annealing module that can bake or apply light radiation to the substrate after the chemicals have been dispensed. It should be understood that this example of spin - coating deposition technology and related values are provided only as examples.

[0055] For example, a spin - coating deposition tool can be used to deposit the layers 108 of the layer stack 106, and a specific example of the spin - coating deposition tool is referred to Figure 8 and described below. In certain embodiments, the step of forming layer 108 using spin - coating deposition includes using spin - coating to deposit layer 108, and after deposition, the deposited layer 108 can be baked and / or cured. In certain embodiments, layer 108 can be deposited in a deposition module (e.g., a spin - coating module) of a larger - scale track system. An example of the track system is referred to Figure 6 - 7 and described in more detail below. In certain embodiments, the same tool can be used for deposition, baking, and curing; however, this disclosure contemplates the use of multiple tools. The baking can be a low - temperature baking step.

[0056] As Figure 1B shown, in Figure 1AAfter multiple iterations of the depicted stages, structure 102 includes a layer stack 106 formed on substrate 104, where layer stack 106 includes a plurality of alternating layers 108a and 108b. Figure 1B The cross-sectional view of structure 102 of Figure 1B is taken along section A-A' of the plan view of semiconductor structure 102. Figure 1C - 1M A similar section A-A' is used in Figure 1C - 1M .

[0057] Layer stack 106 may include alternating layers 108a and 108b, which may be collectively referred to as layer 108. Layer stack 106 may also be referred to as a wafer stack or a multi-layer stack. Layers 108 may be formed using spin-on deposition techniques. In certain embodiments, the spin-on materials used may include SOC, SiOC, ODL, OPL, SOH, SiOCN, SiC, photoresist, ARC, BARC, DBARC, epoxy resin, etc. In a specific example, layer 108a is a photoresist or DBARC and includes a reagent generating component for generating a solubility-altering reagent in response to an activation trigger, and layer 108b is SOC or epoxy resin. Thus, in a specific example, alternating layers 108 of photoresist or DBARC (e.g., as layer 108a) and SOC or epoxy resin (e.g., as layer 108b) are deposited by spin-on deposition to form layer stack 106.

[0058] Although layer stack 106 is shown as including a specific number of layers 108, layer stack 106 may include any suitable number of layers, including as few as two layers 108 and up to one hundred layers 108, two hundred layers 108, three hundred layers 108, four hundred layers 108, five hundred layers 108 or more (possibly exceeding hundreds). The number of layers 108 expected to be part of layer stack 106 will likely increase over time to increase deposition process instances. Just as an example, the thickness of layers 108 may be from about 5 nm to about 175 nm, and the thicknesses of these layers may be the same or may vary using any suitable combination.

[0059] At least in part because of the potentially higher speed of spin coating deposition relative to CVD, PECVD, PVD, or PEPVD deposition, relative to the process of directly depositing the layers of the desired layer stack using CVD, PECVD, PVD, or PEPVD deposition, forming layer stack 106 using spin coating deposition can allow layer stack 106 to be formed with a greater number of layers 108 with less impact on the total processing time. Additionally or alternatively, at least in part because of the lower cost of spin coating deposition relative to CVD, PECVD, PVD, or PEPVD deposition, relative to the process using CVD, PECVD, PVD, or PEPVD deposition, forming layer stack 106 using spin coating deposition can allow layer stack 106 to be formed at a lower cost. Additionally or alternatively, at least in part because of the potentially less stress-inducing characteristics of spin coating deposition relative to CVD, PECVD, PVD, or PEPVD deposition, relative to the process using CVD, PECVD, PVD, or PEPVD deposition, forming layer stack 106 using spin coating deposition can allow layer stack 106 to be formed with a greater number of layers 108 with less stress on structure 102, which can reduce defects in structure 102, including potential bending, and problems caused by the bending.

[0060] After a predetermined number of alternating layers 108a and 108b have been deposited as layer stack 106, mask layer 116a can be deposited on top of layer stack 106. Mask layer 116a can be used as an etch mask for subsequent etching steps. In certain embodiments, mask layer 116a is resistant to etching in a subsequent etching process for forming openings in layer stack 106. Considering the selectivity of the ongoing etching process, mask layer 116a can include materials suitable for use in the etching process to be performed. In certain embodiments, mask layer 116a is silicon, SiN (e.g., Si3N4), or a metal hard mask, but mask layer 116a can include any material suitable for use as an etch mask layer. In certain embodiments, mask layer 116a is deposited using ALD or other CVD deposition processes. In Figure 1B - 1M , the mask layer can generally be referred to as mask layer 116. Depending on the use of mask layer 116, this mask layer 116 can take any suitable form. Although shown in Figure 1B , in certain embodiments, one or more mask layers 116 can be deposited after the deprotection process described below with reference to Figure 1C and 1D .

[0061] As Figure 1C - 1D shown, an activation trigger can be performed so that the reagent generating component 110 of layer 108a generates a solubility-altering reagent. As described above, in order to Figure 1A - 1MFor the purpose of the example process 100, the reagent generating component 110 is described as a TAG. Thus, in Figure 1C - 1D the example of, the activation trigger for causing the reagent generating component 110 to generate a solubility-changing reagent is to perform a bake 124 of the semiconductor structure 102.

[0062] As Figure 1C illustrated, in response to the bake 124, the reagent generating component 110 can generate a solubility-changing reagent 126 in the layer 108a or otherwise release the solubility-changing reagent 126, which can be referred to as activating the solubility-changing reagent 126. The solubility-changing reagent 126 can cause a further chemical reaction in the layer 108a that modifies the layer 108a to be soluble in a developer. For example, the solubility-changing reagent 126 can be a substance that is configured to change the solubility of a material in which the solubility-changing reagent 126 is internally provided in response to a suitable trigger signal (e.g., heat). In certain embodiments, the solubility-changing reagent 126 is an acid.

[0063] As Figure 1D illustrated, the solubility-changing reagent 126 can modify the layer 108a (e.g., the carbon-containing material of the layer 108a) to be soluble for development (e.g., removal) in a developer. The bake 124 can cause the solubility-changing reagent 126 to react with other substances (e.g., polymers) in the layer 108a, thereby making the layer 108a soluble for development in a developer. For example, the bake 124 can cause the solubility-changing reagent to convert one or more side groups of another substance (e.g., a polymer) in the exposed area, resulting in the exposed area becoming soluble in a developer for development. This process can also be referred to as a deprotection reaction, which results in the exposed area being deprotected (e.g., soluble) in a given developer.

[0064] In certain embodiments, the bake 124 can be performed by heating the semiconductor structure 102 in a processing chamber, in a vacuum or under a gas flow, at a temperature between 50°C and 250°C (e.g., between 180°C and 200°C in certain embodiments). In certain embodiments, the temperature at which the bake 124 is performed is higher than the temperature of the bake 112, e.g., about 20°C - 40°C higher. In a specific example, the semiconductor structure 102 is baked for 1 to 3 minutes. The baking conditions for the bake 124 can be selected to promote the generation of the solubility-changing reagent 126 and the change in the solubility of the layer 108a. This disclosure contemplates performing the bake 124 in any suitable manner.

[0065] Although in separate figures ( Figure 1C - 1D) shows the generation of the solubility-altering reagent 126 and the modification to render layer 108a soluble for development, but in some embodiments, the generation of the solubility-altering reagent 126 in response to baking 124 and the modification to render layer 108a soluble for development can occur substantially simultaneously.

[0066] As Figure 1E shown, the opening 118 is formed through the layer 108 in the layer stack 106. In the illustrated example, the opening 118 is formed through the layer stack 106 until the surface of the substrate 104 is exposed. From Figure 1E the plan view, it can be understood that any suitable number of multiple openings 118 can be formed in the layer stack 106. Additionally, the openings 118 can be formed in any suitable arrangement. The openings 118 can be holes, trenches, vias, or any other suitable type of opening. In some embodiments, the openings 118 are channel vias used to form channels for a 3D semiconductor device being constructed (e.g., a 3D memory device, such as a 3D VNAND device). Although the openings 118 are shown as being generally cylindrical when extending through the layer stack 106, the openings 118 can have any suitable shape.

[0067] The opening 118 can be a channel via in which a channel for a semiconductor device (e.g., a 3D semiconductor device) can be formed. In some embodiments, the opening 118 can be used to form 3D memory cells, where the channels for these 3D memory cells are formed in the opening 118. For example, 3D VNAND memory cells can be fabricated by using the openings 118 formed in the layer stack 106. Additionally, these techniques can be used to form single-level cell (SLC) memories, multi-level cell (MLC) memories such as triple-level cell (TLC) memories and quad-level cell (QTC) memories, and / or other memory or device structures.

[0068] To form the opening 118, the mask layer 116a can be patterned (e.g., using one or more lithography processes) to form openings in the mask layer 116a that expose the surface of the layer stack 106 and are aligned with the desired positions of the openings 118; then, the patterned mask layer 116a can be used as an etch mask to etch out the opening 118 through the layer 108 of the layer stack 106. The lithography processes described herein can be implemented using optical lithography, dry lithography, immersion lithography, electron beam lithography, extreme ultraviolet (EUV) lithography, and / or other lithography processes. In embodiments where the opening 118 is ultimately used as a channel via for forming a channel for a device (e.g., a 3D NAND memory device), the pattern of the mask layer 116a can be a channel pattern or include a channel pattern.

[0069] According to specific requirements, any suitable type of etching process can be used to form the opening 118. The etching process for forming the opening 118 within the layer stack 106 can include one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, and / or other etching processes or combinations of multiple etching processes. In certain embodiments, the etching process for forming the opening 118 is an oxygen etching process, such as an oxygen RIE process. In certain embodiments, at least in part because both the layers 118a and 118b are formed of carbon-containing materials, the layers 118a and 118b can be easily etched relative to a layer stack including alternating oxide layers and nitride layers, or even relative to a layer stack including alternating organic layers and inorganic layers, which can reduce the processing time and improve the processing efficiency.

[0070] As Figure 1F shown, the opening 118 can be filled with the filling material 120. The filling material 120 can be a sacrificial material that is replaced at a subsequent stage of the process 100. Although the filling material 120 can include any material suitable for use as a sacrificial material (or dummy material), in certain embodiments, the filling material 120 is a metal oxide filling material. Any suitable type of deposition process or combination of multiple deposition processes can be used to deposit the filling material 120. For example, one or more of CVD processes (potentially including ALD processes), PECVD processes, PVD processes, and PEPVD processes can be used to deposit the filling material 120.

[0071] As Figure 1G shown, the opening 122 is formed through the layer 108 in the layer stack 106. In the illustrated example, the opening 122 is formed through the layer stack 106 until the surface of the substrate 104 is exposed. In the illustrated example, the opening 122 is formed on each side of a row of openings 118. Any suitable number of multiple openings 122 can be formed in the layer stack 106. Additionally, the openings 122 can be formed in any suitable arrangement. The openings 122 can be holes, trenches, vias, or any other suitable type of opening. In certain embodiments, the opening 122 refers to a slit that will ultimately be used to deposit conductive material for one or more gates in the construction of a 3D semiconductor device (e.g., a 3D memory device, such as a 3D VNAND device). Although the opening 122 is shown as being generally rectangular as it extends through the layer stack 106, the opening 122 can have any suitable shape.

[0072] The opening 122 can be formed in any suitable manner. In some embodiments, the mask layer 116b can be deposited on the top of the layer stack 106 (e.g., on the top of the mask layer 116a). The mask layer 116b can be used as an etching mask for subsequent etching steps. In some embodiments, the mask layer 116b is resistant to etching in the subsequent etching process for forming the opening 122 in the layer stack 106. Taking into account the selectivity of the ongoing etching process, the mask layer 116b may include a material suitable for use in the etching process to be performed. In some embodiments, the mask layer 116b is silicon, SiN (e.g., Si3N4) or a metal hard mask, but the mask layer 116b may include any material suitable for use as an etching mask layer. In some embodiments, the mask layer 116b is deposited using ALD or other CVD deposition processes.

[0073] To form the opening 122, the mask layer 116b may be patterned (e.g., using one or more photolithography processes) to form openings in the mask layer 116b that expose surfaces of the mask layer 116a and / or the layer stack 106 and that are aligned with the desired locations of the openings 122; the patterned mask layer 116b may then be used as an etch mask to etch the opening 122 through the mask layer 116a and the layer 108 of the layer stack 106. The mask layer 116b may protect the fill material 120 from being etched during the formation of the opening 122. In some embodiments, rather than depositing a new mask layer 116b on top of the mask layer 116a, the mask layer 116a may be removed and the mask layer 116b may replace the mask layer 116a. A different etch mask may be used to form the opening 122 than the etch mask used to form the opening 118. In other words, mask layer 116b and mask layer 116a may be different instances of mask layer 116, which are patterned in different ways according to the desired locations of openings 118 and 122, respectively. In embodiments where opening 122 is ultimately used as a gate line for forming a gate of a device (e.g., a 3D NAND memory device), the pattern of mask layer 116b may be or include a gate pattern.

[0074] According to specific requirements, any suitable type of etching process can be used to form the opening 122. The etching process for forming the opening 122 within the layer stack 106 can include one or more wet etching processes, plasma etching processes, RIE processes, and / or other etching processes or combinations of multiple etching processes. In certain embodiments, the etching process for forming the opening 122 is an oxygen etching process, such as an oxygen RIE process. In certain embodiments, at least in part because both layers 118a and 118b are formed of carbon-containing materials, layers 118a and 118b can be more easily etched relative to a layer stack including alternating oxide layers and nitride layers, or even relative to a layer stack including alternating organic layers and inorganic layers, which can reduce the processing time and improve the processing efficiency.

[0075] As Figure 1H shown, layers 108 of a particular type of material are selectively removed from the layer stack 106. In the illustrated example, layer 108a is selectively removed from the layer stack 106. As described above, in one example, layer 108a includes a first carbon-containing material (e.g., photoresist, DBARC, etc.), which has now been modified to be soluble for development due to the generation of the solubility-changing reagent 126, and layer 108b includes a second carbon-containing material (e.g., SOC, epoxy resin, etc.). In one example, layer 108a can be removed. In addition to the void created by the opening 122, removing layer 108a leaves a void 128 where layer 108a was previously located within the layer stack 106.

[0076] An appropriate developing process can be used to remove layer 108a to remove (e.g., develop) layer 108a that has been modified to be soluble in the developer. During the developing stage, an appropriate dry etching or wet etching process can be used to remove the soluble portion of the layer stack (e.g., layer 108a). This disclosure contemplates using any appropriate etching process to remove the set of layers 108 (e.g., layer 108a in this example). The appropriate etching process can include an etching process that is selective for etching the layer to be removed (e.g., layer 108a in this example) relative to the layer that is not removed (e.g., layer 108b in this example). In view of the fact that layer 108a has been modified to be soluble in a given developer for development, layer 108a can be removed from the layer stack 106 by exposing layer 108a to the developer.

[0077] For example, wet processing can be used to develop layer 108a by treating semiconductor structure 102 with developer solution 130 to dissolve layer 108a (e.g., to remove the soluble portion of layer 108a). The appropriate developer solution 130 can depend in part on the materials of layer 108a and layer 108b such that layer 108a is soluble in developer solution 130 while still maintaining selectivity relative to layer 108b. In some embodiments, developer solution 130 can include an aqueous alkaline solution containing a water-soluble organic base. As a specific example, developer solution 130 can include tetramethylammonium hydroxide (TMAH).

[0078] Alternatively, in other embodiments, dry processing can be used, which can introduce additional complexity and time. Dry processing can include, for example, selective plasma etching processing or heat treatment, which can eliminate the use of a developer solution. In some embodiments, reactive ion etching (RIE) processing or atomic layer etching (ALE) can be used for dry processing.

[0079] As Figure 1I shown, the removed layer 108a can be replaced with another material (shown as layer 108c). Layer 108c can be formed in any suitable manner. Layer 108c can include any suitable material, such as SiO2, SiN, SiON, SiC, SiOC, and / or metal oxides. As just one example, the material of layer 108c can be an oxide (e.g., SiO2) or a nitride (e.g., SiN). In some embodiments, the material of layer 108c is an insulating material.

[0080] In some embodiments, to utilize the material of layer 108c to replace the removed layer 108b, the open spaces in layer stack 106 can be partially or fully filled with the material that will become layer 108c. For example, the void 128 in layer stack 106 can be filled with the material of layer 108c, and the opening 122 in layer stack 106 can be partially or fully filled with the material of layer 108c. For example, the material of layer 108c can be deposited in void 128 and fill the void 128, and the material of layer 108c can extend into opening 122 and also partially or fully fill opening 122. In other words, an initial deposition of the material of layer 108c can be performed to fill void 128 and extend into opening 122. In the illustrated example, the excess material 132 (for forming the material of layer 108c) can be deposited as part of this initial deposition. Although excess material 132 is shown as only partially filling opening 122, this disclosure contemplates opening 122 being filled with less or more (and possibly all) of excess material 132. In some embodiments, the material of layer 108c (e.g., an oxide or a nitride), including excess material 132, can be deposited less than 20 nm. The material of layer 108c can be deposited using any suitable deposition technique or a combination of techniques, such as by ALD or other CVD processes.

[0081] As Figure 1J illustrated, the excess material 132 can be recessed to substantially reform the opening 122, thereby exposing the material of layer 108b within the opening 122 and forming layer 108c (by removing the excess material 132). An appropriate etch process can be used to remove the deposited material (excess material 132) of (layer 108c) within the region of opening 122, thereby exposing the materials of layers 108b and 108c within the opening 122. For example, the deposited material (excess material 132) of (layer 108c) within the region of opening 122 can be recessed using DHF acid, vapor, plasma etching, etc. The appropriate etch process will depend on the materials of layer stack 106. If appropriate, a suitable masking process (e.g., possibly using a new etch mask, such as a new mask layer 116) can be used to facilitate this etch process.

[0082] As Figure 1K illustrated, layer 108b is removed from layer stack 106. As described above, in one example, layer 108b is a SOC. Thus, in one example, the SOC (layer 108b) can be removed. In addition to the void created by opening 122, removing layer 108b leaves a void 134 within layer stack 106 where layer 108b was previously located.

[0083] This disclosure contemplates using any suitable etch process to remove the layer 108b. The etch process for removing the layer 108b can include one or more wet etch processes, plasma etch processes, RIE processes, and / or other etch processes or a combination of multiple etch processes. Suitable etch processes can include an etch process that is selective for etching the layer 108b relative to the layer 108c. Referring again to the example where the layer 108b is a SOC and the layer 108c is an oxide or nitride, and where the layer 108b (SOC) is removed, suitable etch processes can include DHF acid or vapor or plasma etching. In certain embodiments, the etch process for removing the layer 108b is an oxygen etch process, such as an oxygen RIE process. The etch process can remove all of the layer 108b from the layer stack 106.

[0084] As Figure 1L illustrated, the open spaces of the layer stack 106 can be filled with the material 136. For example, the void 134 (previously occupied by the layer 108b) can be filled with the material 136, and the opening 122 can also be filled with the material 136. The material 136 can be a metal-containing material suitable for the corresponding manufacturing process, such as for forming a 3D semiconductor structure (e.g., a 3D VNAND device). In certain embodiments, the material 136 can be a metal-containing material suitable for use as a gate in the 3D semiconductor structure being formed. Merely as one specific example, the fill material 120 can include a combination of AlO x , TiN, and W. Although primarily described as a metal-containing material, the material 136 can be any suitable conductive material, such as any material suitable for use as a gate in a transistor (e.g., a gate in a transistor of a 3D NAND memory device). Thus, in certain embodiments, in Figure 1L the illustrated state, the layer stack 106 includes alternating oxide layers and nitride layers such that the layer stack 106 is an ONON stack. Other stack types are also feasible, such as an OPOP stack.

[0085] As Figure 1M shown, the fill material 120 in the opening 118 can be removed and replaced with another material (e.g., the channel material 138). The fill material 120 can be removed from the region of the opening 118 to reform the opening 118 (which is subsequently refilled with the channel material 138). For example, any suitable etch process can be used to remove the fill material 120, such as one or more wet etch processes, plasma etch processes, RIE processes, or a combination of these or other etch processes. If appropriate, the mask layer 116a can be patterned (e.g., possibly using the same etch mask as used in the previous step for forming the opening 118) to facilitate the etch process.

[0086] In Figure 1MIn the illustrated example, the top portion of the material 136 in the mask layer 116b and the opening 122 can be removed to expose the fill material 120 at the top of the structure 102, and the channel material 138 can be used to replace the fill material 120. This disclosure contemplates other embodiments. For example, Figure 1L the mask layer 116b in Figure 1L can be patterned to expose the fill material 120 in the opening 118 such that the fill material 120 can be removed and replaced with the channel material 138.

[0087] In the case of a 3D memory device, the channel material 138 can include any material suitable for use as a channel (or a portion of a channel) of a 3D memory device. In certain embodiments, the channel material 138 can include multiple material layers, where the multiple material layers include silicon, oxide, SiN, oxide and silicon (e.g., SONOS structure). In certain embodiments, the channel material 138 can include an oxide-nitride-oxide (ONO) memory stack and a polysilicon material to form a polysilicon channel. In certain embodiments, the opening 118 can be filled with any one of SiO2, SiN, SiO2, and polysilicon. For example, the deposition of the channel material 138 can include depositing a layer of oxide (e.g., SiO2), a layer of nitride (e.g., SiN), and another layer of oxide (e.g., SiO2), while the remaining portion of the opening 118 is filled with polysilicon. The channel material 138 can be deposited using any suitable type of deposition process or a combination of multiple deposition processes. For example, one or more of CVD process (which may include ALD process), PECVD process, PVD process, PEPVD process can be used to deposit the channel material 138.

[0088] In certain embodiments, the channel material 138 is deposited (using an appropriate combination of etching and / or deposition processes) in such a way that a contact can be formed between the channel material layer 138 serving as a channel region and the conductive material at the bottom of the opening 118, and ultimately reach the source line or the drain line. In certain embodiments, at least a portion of the channel material 138 includes a material that serves as a gate dielectric.

[0089] Although in Figure 1A - 1M Figure 1A - 1M , the layer stack 106 is described as including specific alternating layers 108, the layer stack 106 can still include alternating layers of other suitable materials.

[0090] From Figure 1A - 1M and the related description of the process 100, it can be understood that at the stage illustrated in Figure 1B Figure 1B , the layer stack 106 initially includes alternating layers 108a and 108b, which are deposited using a spin coating deposition technique and serve as sacrificial layers, and these sacrificial layers are in Figure 1Mare removed during the illustrated stages and replaced by the layers of the cambium stack 106. In addition, the layers 108a can each be removed and replaced by the material that will ultimately constitute the stack 106 (during Figure 1M the illustrated stages), where the various replacement materials can be deposited in a single etch step (e.g., using ALD or other CVD processes). As opposed to repeatedly performing expensive and demanding deposition processes to obtain Figure 1M the desired stack 106 illustrated in, forming the layers 108a and 108b of the stack 106 using spin coating techniques, and then removing and replacing those sacrificial layers 108a and 108b can save time and money, and can also reduce stress in the semiconductor structure 102 and defects caused by that stress.

[0091] Although in the example of Figure 1A - 1M , the bake 124 used to change the solubility of the layer 108a (e.g., to protect the layer 108a) is described as occurring after the formation of the stack 106 and before the formation of the opening 118, the bake 124 can occur at any suitable time. By way of example only, the bake 124 can occur during the formation of the stack 106. In one example, the bake 112a and the bake 124 can be the same bake, where the bake 112 has a temperature sufficient to cause crosslinking in the layer 108a and cause the reagent generating component 110 in the layer 108a to generate the solubility changing reagent 126 in the layer 108a. In another example, the bakes 112a and 124 can occur during the formation of the stack 106, but remain separate bakes, where the bake 112a occurs after the deposition of the layer 108a and the bake 124 occurs after the bake 112a. In another example, the bake 124 can occur after the opening 122 is formed in the stack 106.

[0092] In certain embodiments, for using a nitride material (e.g., SiN) for the layer 108c (see, e.g., Figure 1I - 1J ) to replace an oxide layer, the order of the initially deposited layers 108a and 108b can be reversed, including which is removed and replaced first. Other differences in the deposition and etch processes performed can be adapted to accommodate the modified arrangement and materials.

[0093] Figure 2A - 2F A cross-sectional view of an example semiconductor structure 202 during an example process 200 for forming a 3D semiconductor structure according to certain embodiments is illustrated. In this example, the reagent generating component of certain layers of the stack is PAG.

[0094] In this example, certain aspects of the structure 202 and the process 200 can respectively correspond to those above referenced Figure 1A - 1MAspects of the structures 102 and processes 100 described above will not be elaborated further. For the sake of brevity and clarity, the following convention is adopted in this embodiment: In certain embodiments, elements attached to the pattern [x02] may be relevant embodiments of processes and / or semiconductor workpieces. For example, unless otherwise specified or obvious, the semiconductor structure 202 may be similar to the semiconductor structure 102, and the substrate 204 may be similar to the substrate 104, etc. Similar conventions are adopted for other elements, and it can be clearly seen by using similar terms in combination with the three-digit numbering system described. Through this convention, features that have been described are incorporated by reference where applicable, without further elaboration.

[0095] Figure 2A A cross-sectional view illustrating an example process for forming a layer stack 206 on a substrate 204 is shown. The formed layer stack 206 may include alternating layers 208a and 208b, which may be collectively referred to as layer 208. The layer stack 206 may also be referred to as a wafer stack or a multi-layer stack.

[0096] In stage 1, particularly in the first pass operation of stage 1, layer 208a may be deposited over the substrate 204. The substrate 204 may include any substrate material suitable for forming a 3D semiconductor structure (e.g., a 3D memory device). For example, the substrate 204 may be silicon or include silicon.

[0097] Layer 208a may be a layer that undergoes a solubility change when exposed to a solubility-changing reagent (e.g., an acid), and is thus subsequently removed in a development step. Layer 208a may be a carbon-containing layer, the solubility of which can be changed to develop in a developer during a subsequent part of process 200. Layer 208a may be a multi-component material that includes two or more components upon deposition. Layer 208a may include a carbon-containing component, as well as a reagent-generating component 210 for generating a solubility-changing reagent in response to an activation trigger. In certain embodiments, layer 208a includes a solvent to facilitate deposition (e.g., using spin coating deposition techniques). For example, the solvent may allow the material of layer 208a to be spun, thereby forming a thin layer on the underlying layer.

[0098] The carbon-containing component of layer 208a may include a polymer or another suitable type of carbon-containing material, the solubility of which can be changed using a solubility-changing reagent (e.g., an acid) generated by the reagent-generating component 210 of layer 208a. The carbon-containing component (e.g., the polymer) is designed to change its structure when exposed to a solubility-changing reagent (e.g., an acid).

[0099] In the example of process 200, the reagent generating component 210 can include any suitable material that generates a solubility-altering reagent (e.g., an acid) in response to radiation. In certain embodiments, the reagent generating component 210 is configured to generate an acid or otherwise release an acid-generating PAG in response to UV light exposure (e.g., actinic radiation). The generated solubility-altering reagent (e.g., an acid) can cause a further chemical reaction in layer 208a that modifies layer 208a to be soluble in a developer. For example, the generated reagent can be a substance configured to change the solubility of a material, where the reagent is set to respond to a suitable trigger signal (e.g., heat), and thus can be referred to as a solubility-altering reagent.

[0100] For Figure 2A - 2F the purposes of the example process 200, the reagent generating component 210 will be described as a PAG.

[0101] In certain embodiments, layer 208a includes a photoresist material having an embedded reagent generating component 210 (e.g., a PAG). For example, the photoresist material can be a CAR. The photoresist material of layer 208a can be suitable for the type of solubility-altering reagent and developer to be used, such that layer 208a can undergo a solubility change and be removed using the developer. The photoresist material of layer 208a can be a positive photoresist or a negative photoresist.

[0102] As another specific example, layer 208a can include a developable ARC, such as a DBARC having a reagent generating component 210.

[0103] In stage 2, an activation trigger can be performed to cause the reagent generating component 210 to generate a solubility-altering reagent. As described above, for the purposes of the example process 200, the reagent generating component 210 is described as a PAG. Thus, in Figure 2A - 2F the example, the activation trigger for causing the reagent generating component 210 to generate a solubility-altering reagent is to expose layer 208a to actinic radiation 211 (irradiate layer 208a), causing the reagent generating component 210 to generate a solubility-altering reagent 226 in layer 208a. For example, the actinic radiation 211 can be directed towards the semiconductor structure 202 and particularly to the surface of layer 208a, causing the reagent generating component 210 to generate a solubility-altering reagent 226 in layer 208a. As Figure 2A depicted in stage 2, in response to exposure to actinic radiation 211, the reagent generating component 210 can generate or otherwise release a solubility-altering reagent 226 in layer 208a, which can be referred to as an activated solubility-altering reagent 226.

[0104] The lithography technique for exposing layer 208a to actinic radiation 211 can include any suitable type of lithography technique. In certain embodiments, the exposure suitable for causing the PAG to generate the solubility-altering reagent 226 can be flood exposure. In the case of flood exposure, the exposure can be performed in the on-track module of an orbit-based lithography system without moving the semiconductor structure 202 to a stepper for a more complex exposure. In the case of a more complex exposure, the semiconductor structure 202 can be transferred from the track system to an exposure module (which can also be referred to as a stepper module or a scanner module) for exposing layer 208a to actinic radiation 211. An example lithography system including a projection scanner is described in more detail below with reference to Figure 6 - 7 and is described in more detail below. The present disclosure contemplates performing the exposure step in any suitable manner.

[0105] Of course, if appropriate, the present disclosure contemplates including other suitable types of reagent-generating components that generate the solubility-altering reagent 226 in response to a suitable activation trigger (e.g., heat, radiation, or other suitable trigger signal).

[0106] At stage 3, layer 208b can be deposited over layer 208a. Layer 208b can be a carbon-containing layer. Layer 208b can be a multi-component material that includes two or more components upon deposition. For example, layer 208b can include a carbon-containing component. The carbon-containing component of layer 208b can include a polymer or another suitable type of carbon-containing material. As another example, layer 208b can include a solvent to facilitate deposition (e.g., using spin-on deposition techniques). For example, the solvent can allow the material of layer 208b to be spun, thereby forming a thin layer over the underlying layer.

[0107] In certain embodiments, the material for layer 208b can include SOC, SiOC, ODL, OPL, SiOCN, SiC, photoresist, ARC, BARC, epoxy resin, etc. Some of these examples can overlap in type.

[0108] At stage 4, one or more bakes 212 / 224 of the semiconductor structure 202 can be performed. Heating the semiconductor structure 202 via the bake 212 / 224 can be used for one or more purposes.

[0109] For a first exemplary purpose, baking 212 of the semiconductor structure 202 can be performed to initiate a cross-linking reaction (e.g., a polymer cross-linking reaction) in layer 208a and / or 208b. For example, the polymer chains of layer 208a and / or 208b can be cross-linked by thermally induced bond formation. In certain embodiments, this cross-linking can include C-C bond formation or S-S bond formation, etc. Only as a specific example, layer 208a and / or 208b can include hydroxystyrene, which can cross-link in response to sufficient heat.

[0110] This cross-linking reaction can cause layer 208a and / or 208b to harden or otherwise strengthen, which can enable layer 208a and / or 208b to better cope with the stress of additional layer 208 as the height of layer stack 206 increases. In certain embodiments, this cross-linking reaction can render layer 208b insoluble in the developer that will be used to remove layer 208a in a subsequent processing step; however, in certain embodiments, layer 208b may already be insoluble in such a developer.

[0111] In certain embodiments, baking 212 can be performed by heating the semiconductor structure 202 in a processing chamber, in a vacuum or under an air flow, at a temperature between 50°C and 250°C (e.g., between 140°C and 150°C in certain embodiments). In certain embodiments, the temperature at which baking 212 is first performed is lower than the temperature of the baking (e.g., baking 224) that can be performed in a subsequent processing step to cause a solubility change reagent of component 210 of layer 208a to change the solubility of layer 208a, for example, the temperature is about 20°C - 40°C lower. In a specific example, the semiconductor structure 202 is baked for 1 to 3 minutes. The baking conditions of baking 212 can be selected to promote cross-linking of layer 208a and / or 208b. This disclosure contemplates performing baking 212 in any suitable manner.

[0112] For another exemplary purpose, baking 224 of the semiconductor structure 202 can be performed to modify layer 208a to become soluble in the developer. In response to baking 224, the solubility change reagent 226 can modify layer 208a (e.g., the carbon-containing material of layer 208a) to be soluble for development (e.g., removal) in the developer. The solubility change reagent 226 can cause a further chemical reaction in layer 208a that modifies layer 208a to be soluble in the developer. For example, the solubility change reagent 226 can be a substance that is configured to change the solubility of the material in which the solubility change reagent 226 is internally provided in response to a suitable trigger signal (e.g., heat). In certain embodiments, the solubility change reagent 226 is an acid.

[0113] For example, baking 224 can cause the solubility - altering reagent 226 to react with other substances (e.g., polymers) in layer 208a, rendering layer 208a soluble for development in a developer. For example, baking 224 can cause the solubility - altering reagent to transform one or more side - groups of another substance (e.g., polymer) in the exposed region, resulting in the exposed region becoming soluble in the developer for development. This process can also be referred to as a de - protection reaction, which causes the exposed region to be de - protected (e.g., soluble) in a given developer.

[0114] In some embodiments, baking 224 can be performed by heating the semiconductor structure 202 in a processing chamber, either in a vacuum or under an air flow, at a temperature between 50°C and 250°C (e.g., between 180°C and 200°C in some embodiments). In a specific example, the semiconductor structure 202 is baked for 1 to 3 minutes. The baking conditions of baking 224 can be selected to promote the change in solubility of layer 208a. This disclosure contemplates performing baking 224 in any suitable manner.

[0115] Baking 212 / 224 can be a single bake or multiple bakes performed at the same or different temperatures. For example, a first bake 212 can be performed at a first temperature to initiate a cross - linking reaction in layer 208a and / or 208b, and a second bake 224 can be performed at a second temperature to initiate a de - protection reaction in layer 208a. In some embodiments, the second temperature is higher than the first temperature. In some embodiments, the first bake 212 is performed before the second bake 224. For changing baking 212 / 224 to a single bake, baking 212 / 224 can be performed at a temperature at which the solubility - altering reagent 226 modifies layer 208a to be soluble for development, which can be a temperature higher than the temperature at which a cross - linking reaction is initiated in layer 208a and / or 208b, but still capable of initiating the cross - linking reaction in layer 208a and / or 208b.

[0116] In some embodiments, the first bake 212 (e.g., similar to bake 112a) for causing cross - linking in layer 208a can be performed between stage 1 and 2, and bake 224 can be performed between stage 2 and 3, causing the resulting solubility - altering reagent 226 to change the solubility of layer 208a in the developer, while the second bake 212 (e.g., similar to bake 112b) for causing cross - linking in layer 208b can be performed as bake 212 shown in stage 4.

[0117] Stages 1-4 can be performed to construct the layer stack 206 of alternating layers 208a and 208b. For example, stages 1-4 can be repeated an appropriate number of times, as indicated by the circular arrow 214, to construct the layer stack 206 having a target number of layers 208. An example layer stack 206 that can include multiple alternating layers 208a and 208 is illustrated and described in conjunction with Figure 2B and depicted.

[0118] Although stages 1-4 are illustrated, additional stages can be performed, or stages 1-4 can be combined in any suitable manner. In some embodiments, baking 212 can be performed after depositing each layer 208 or after depositing more than two layers 208. Additionally, in terms of performing multiple bakings 212, the temperatures of the multiple bakings 212 can be the same or different, which may be appropriate for a given implementation. Further, although the first instance of layer 208a is described as being deposited before the first instance of layer 208b, the first instance of layer 208b can be deposited before the first instance of layer 208a.

[0119] Although it is described that baking 212 is sufficient to cause the solubility-changing reagent 226 to change the solubility of layer 208a at stage 4, this disclosure contemplates that at another time point, such as after forming the opening 222, as described below with reference to Figure 2E (e.g., similar to the baking 124 described above with reference to Figure 1G ), a baking is performed to cause the solubility-changing reagent 226 to change the solubility of layer 208a.

[0120] In some embodiments, layer 208b can be deposited over layer 208a before exposing layer 208a to actinic radiation 211, or multiple layers 208a and 208b can be deposited before exposure to actinic radiation 211; however, doing so may present the following challenge: ensuring that layer 208a is exposed to sufficient actinic radiation 211 to ensure activation of a sufficient amount of the reagent generating component 210 in layer 208a, thereby modifying layer 208a during the deprotection step.

[0121] In some embodiments, during the Figure 2A stack formation process, layers 208a and 208b can be deposited on the semiconductor structure 202 in any suitable manner. For example, layer 208 can be deposited by spin coating, spraying, dip coating, or roll coating. As a specific example, spin coating deposition techniques can be used, such as the method described with respect to Figure 1A to deposit layer 208 on the semiconductor structure 202, which technique can also be referred to as spin coating.

[0122] For example, a spin coating system can be used to deposit the layers 208 of the layer stack 206, and a specific example of the spin coating system is referenced in Figure 8And is described below. In certain embodiments, the step of forming layer 208 using spin coating deposition processing includes depositing layer 208 using a spin coating process, and after deposition, the deposited layer 208 can be baked and / or cured. In certain embodiments, layer 208 can be deposited in a deposition module (e.g., a spin coating module) of a larger track system. Example track systems are referenced Figure 6 - 7 and described in more detail below.

[0123] In certain embodiments, the same tool can be used for deposition, baking, and curing; however, this disclosure contemplates the use of multiple tools. The baking can be a low-temperature baking step.

[0124] As Figure 2B shown, generally, structure 202 can correspond to Figure 1B structure 102 in the shown state, where structure 202 includes layer 208a, which is deposited with PAG as a reagent to produce component 210 instead of the TAG described above for structure 102, and the solubility of layer 208a has been pre-changed during the formation of layer stack 206. Thus, the layer stack 206 of layer 208a and layer 208b can be formed in a manner similar to Figure 1A layer stack 106, where layer 208a and layer 208b are deposited using spin coating techniques in a manner similar to that described for layers 108a and 108b of structure 102 above with reference to Figure 1A . Although this disclosure contemplates that layer 208a and layer 208b include any spin coating materials described herein, in one example, layer 208a includes a photoresist or a DBARC material and layer 208b includes an SOC. Additionally, structure 202 includes substrate 204 and mask layer 216a, which can be similar to Figure 1A - 1M substrate 104 and mask layer 116a of structure 102 in. In certain embodiments, mask layer 216a is a hard mask and can include silicon, nitride, metal oxide, or metal.

[0125] As Figure 2C shown, opening 218 is formed through layer 208 in layer stack 206. Opening 218 can be formed in a manner similar to that described for opening 118 above with reference to Figure 1C , and can be similar to opening 118, where appropriate mask and etch processes are used depending on the materials of layer 208a and 208b.

[0126] As Figure 2D shown, opening 218 can be filled with fill material 220. Fill material 220 can be similar to Figure 1D fill material 120 described above. Additionally, fill material 220 can be filled in a manner similar to that described above with reference to Figure 1DThe described fill material 120 is deposited in a similar manner. Fill material 220 can be a sacrificial material that is replaced at a later stage of process 200. Although fill material 220 can include any material suitable for use as a sacrificial material (or dummy material), in certain embodiments, fill material 220 is a metal oxide fill material.

[0127] As Figure 2E shown, opening 222 is formed through layer 208 in layer stack 206. Opening 222 can be formed in a manner similar to that described above with reference to Figure 1E opening 122 and can be similar to opening 122, where appropriate masking and etching processes are used depending on the materials of layers 208a and 208b and fill material 220. Opening 222 can be formed in any suitable manner. In certain embodiments, mask layer 216b can be deposited on top of layer stack 206 (e.g., on top of mask layer 216a). Mask layer 216b can be used as an etch mask for subsequent etching steps. In certain embodiments, mask layer 216b is resistant to etching in the subsequent etching process used to form opening 222 in layer stack 206. Considering the selectivity of the ongoing etching process, mask layer 216b can include a material suitable for use in the etching process to be performed. In certain embodiments, mask layer 216b is silicon, SiN (e.g., Si3N4), or a metal hard mask, but mask layer 216b can include any material suitable for use as an etch mask layer. In certain embodiments, mask layer 216b is deposited using an ALD or other CVD deposition process. Mask layer 216b can protect fill material 220 from being etched during the formation of opening 222. In certain embodiments, instead of depositing a new mask layer 216b on top of mask layer 216a, mask layer 216a can be removed and mask layer 216b can replace mask layer 216a.

[0128] As Figure 2F shown, a layer 208 of a particular type of material is selectively removed from layer stack 206. In the illustrated example, layer 208a is selectively removed from layer stack 206. As described above, in one example, layer 208a includes a first carbon-containing material (e.g., photoresist, DBARC, etc.) that has now been modified to be soluble for development due to the production of solubility-altering reagent 226, while layer 208b includes a second carbon-containing material (e.g., SOC). In one example, layer 208a can be removed. In addition to the void created by opening 222, removing layer 208a leaves a void 228 in the location within layer stack 206 where layer 208a was previously located.

[0129] An appropriate development process can be used to remove layer 208a to remove (e.g., develop) layer 208a that has been modified to be soluble in a developer. During the development stage, an appropriate dry etching or wet etching process can be used to remove the soluble portion of the layer stack (e.g., layer 208a). This disclosure contemplates using any appropriate etching process to remove the set of layers 208 (e.g., layer 208a in this example). An appropriate etching process can include an etching process that is selective for the etched layer (e.g., layer 208a in this example) relative to the layer that is not removed (e.g., layer 208b in this example). In view of layer 208a having been modified to be soluble in a given developer for development, layer 208a can be removed from the layer stack 206 by exposing layer 208a to the developer.

[0130] For example, the development of layer 208a (e.g., to remove the soluble portion of layer 208a) can be performed using an appropriate solvent rinse 230 (e.g., an organic solvent). Exemplary organic solvents that are available can include propylene glycol monomethyl ether acetate (PGMEA), 2-heptanone, isopropyl alcohol (IPA), 2-pentanone, or other suitable organic solvents. In one example, the solvent dispense volume can be between 5 ml and 500 ml, such as 10 ml to 100 ml. The substrate (e.g., structure 202) can be secured to a chuck used to support the substrate. The rotational speed during liquid dispense can be between 50 rpm and 3000 rpm, such as 1000 rpm to 2000 rpm. Although primarily described for organic solvents, this disclosure contemplates using any suitable solvent.

[0131] As another example, the development of layer 208a (e.g., to remove the soluble portion of layer 208a) can be performed in a gas phase with or without plasma. Exemplary gases for such a gas phase can include HBr, BCL3, or another appropriate gas / gas combination.

[0132] Subsequent processing of the semiconductor structure 202 using process 200 can be performed in a manner similar to that described above with reference to Figure 1I - 1M and details thereof are not repeated for the sake of brevity.

[0133] Figure 3A - 3BA flowchart illustrating an example method 300 for forming a 3D semiconductor structure in accordance with certain embodiments is shown. At step 302, a layer stack of alternating layers of a first carbon-containing material and a second carbon-containing material may be formed. The first carbon-containing material layer and the second carbon-containing material layer may be formed by spin coating deposition. For example, the layer stack may correspond to the initial state of layer stack 106 or 206 of structure 102 or 202, respectively. In certain embodiments, the first carbon-containing material includes a photoresist or a DBARC material, and the second carbon-containing material includes SOC, SiOC, ODL, OPL, SiOCN, SiC, BARC, or an epoxy resin. The first carbon-containing material and the second carbon-containing material may be different materials such that at least one of the first carbon-containing material or the second carbon-containing material may be selectively etched relative to the other of the first carbon-containing material or the second carbon-containing material or relative to another material of the structure being processed.

[0134] As described above, the first carbon-containing material layer (e.g., layer 108a or 208a) may be a layer that undergoes a solubility change when exposed to a solubility-changing reagent (e.g., an acid), and thus may be removed in a subsequent development step, and for this purpose the first carbon-containing material layer may include a reagent generating component 110 / 210 that produces a solubility-changing reagent 126 / 226 in response to an activation trigger (e.g., heat or radiation). The reagent generating component 110 / 210 may include any suitable material that produces a solubility-changing reagent (e.g., an acid) in response to a suitable reagent activation trigger (e.g., heat or radiation). For example, the reagent generating component 110 / 210 may be a TAG or a PAG, and the solubility-changing reagent 126 / 226 may be an acid.

[0135] At step 304, an activation trigger used to cause the reagent generating component 110 / 210 of the first layer 108 / 208a to generate a solubility-changing reagent 126 / 226 may be performed. As described above, in certain embodiments, the reagent generating component of the first layer of the layer stack is a TAG that is activated in response to sufficient heat. In such an example, the activation trigger for causing the reagent generating component 110 to generate a solubility-changing reagent is to perform a bake 124 of the semiconductor structure 102. In response to the bake 124, the reagent generating component 110 may produce a solubility-changing reagent 126 in layer 108a or otherwise release the solubility-changing reagent 126, which may be referred to as activating the solubility-changing reagent 126.

[0136] Using the TAG, in response to baking 124, the solubility-changing reagent 126 can cause a further chemical reaction in layer 108a that modifies layer 108a to be soluble in the developer. For example, the solubility-changing reagent 126 can be a substance configured to change the solubility of a material in which the solubility-changing reagent 126 is internally provided in response to a suitable trigger signal (e.g., heat). In some embodiments, the solubility-changing reagent 126 is an acid. In a specific example, the solubility-changing reagent 126 can modify layer 108a (e.g., the carbon-containing material of layer 108a) to be soluble for development (e.g., removal) in the developer.

[0137] Alternatively, as described above, in some embodiments, the reagent-generating component of the first layer of the layer stack activates a PAG in response to suitable actinic radiation. In such an example, the activation trigger for causing the reagent-generating component to generate the solubility-changing reagent 226 is to expose layer 208a to actinic radiation 211 (irradiating layer 208a), causing the reagent-generating component 210 to generate the solubility-changing reagent 226 in layer 208a. In some embodiments, the exposure suitable for causing the PAG to generate the solubility-changing reagent 226 can be flood exposure.

[0138] Using the PAG, post-exposure baking (e.g., baking 212) can be performed to modify layer 208a to become soluble in the developer. In response to baking 212, the solubility-changing reagent 226 can modify layer 208a (e.g., the carbon-containing material of layer 208a) to be soluble for development (e.g., removal) in the developer. In other words, the solubility-changing reagent 226 can cause a further chemical reaction in layer 208a that modifies layer 208a to be soluble in the developer.

[0139] Of course, if appropriate, the present disclosure contemplates including other suitable types of reagent-generating components 110 / 210 that generate the solubility-changing reagents 126 / 226 in response to suitable activation triggers (e.g., heat, radiation, or other suitable trigger signals).

[0140] At step 306, a first opening can be etched through the layer stack. For example, these first openings can respectively correspond to the openings 118 or 218 of the structures 102 or 202. These first openings can be channel openings.

[0141] At step 308, these first openings can be filled with a third material. In certain embodiments, the third material can be a fill material that will later be replaced by a channel material (e.g., at step 322). For example, the fill material can be fill material 120 or 220 of structure 102 or 202, respectively. Alternatively, the third material can be a material or combination of materials suitable for use in the channels of 3D memories or other 3D semiconductor devices. For example, the third material can be a channel material, such as channel material 138 of structure 102 (or, if additional steps of process 200 have been referenced Figure 2A - 2F and described, it would be channel material 238 of structure 202). As a specific example of a channel material, the channel material can include one or more of SiO2, SiN, and polysilicon.

[0142] At step 310, second openings can be etched through the layer stack. For example, these second openings can correspond to openings 122 or 222 of structure 102 or 202, respectively. The second openings can expose the alternating layers of the layer stack. For example, these second openings can be openings through which conductive gate material can be deposited in a subsequent step (e.g., step 318), and these second openings can also be used to remove selected sacrificial layers of the layer stack and / or deposit and remove additional fill material.

[0143] At step 312, multiple layers of a first carbon-containing material can be removed from the layer stack. For example, the layers of the first carbon-containing material can be removed from the layer stack by exposing the first carbon-containing material layer to a first etch chemical. The first spin-on material can correspond to layer 108a or 208a of structure 102 or 202, respectively. Any suitable etching process can be used to remove the layers of the first carbon-containing material, including, for example, exposing the layers of the first carbon-containing material to a suitable developer in which the first carbon-containing material is soluble. For example, a wet process can be used to develop layer 108a (e.g., to remove the soluble portion of layer 108a) by treating semiconductor structure 102 with developer solution 130 to dissolve layer 108a. As a specific example, developer solution 130 can include TMAH.

[0144] At step 314, the layers of the first carbon-containing material can be replaced with a fourth material. The fourth material can correspond to the material of layer 108c of structure 102 (or, if additional steps of process 200 have been referenced Figure 2A - 2F and described, it would be layer 208c of structure 202). In certain embodiments, the fourth material can be an insulating material, such as a nitride (e.g., SiN) or an oxide (e.g., SiO2). The fourth material can be deposited using any suitable deposition technique, such as including ALD or other CVD processes.

[0145] At step 316, these layers of the second carbonaceous material can be removed from the layer stack. For example, these layers of the second carbonaceous material can be removed from the layer stack by exposing these layers of the second carbonaceous material to a second etch chemical. The second carbonaceous material can correspond to layer 108b or 208b of structure 102 or 202, respectively. Any suitable etching process can be used, such as including a wet etching process or a plasma process to remove these layers of the second carbonaceous material.

[0146] At step 318, these layers of the second carbonaceous material can be replaced with a fifth material. In certain embodiments, the fifth material can include a conductive material, such as a metal-containing material or a combination of materials suitable for use as a conductive gate / word line (e.g., of a 3D memory device). The fifth material can be deposited using any suitable deposition technique, such as including ALD or other CVD processes.

[0147] In certain embodiments, replacing these layers of the second carbonaceous material with the fifth material includes replacing these layers of the second carbonaceous material (e.g., removed in step 316) with a fill material (e.g., an oxide material), removing the fill material (using a suitable etch chemical), and replacing the fill material with the fifth material. In certain embodiments, a portion of the fill material (e.g., in the second opening) can be removed (using a suitable etch chemical) and replaced with yet another fill material (e.g., a metal oxide), and both fill materials can be removed (using a suitable etch chemical) and replaced with the fifth material.

[0148] At step 320, the third material in these first openings can be removed from the layer stack. For example, the third material (which can be, for example, the fill material described above with reference to step 306) can be removed from the layer stack by exposing the third material to an etch chemical. The third material can correspond to fill material 120 or 220 of structure 102 or 202, respectively. Any suitable etching process can be used, such as including a wet etching process or a plasma process to remove the third material.

[0149] At step 322, the third material in these first openings can be replaced with a sixth material. The sixth material can be a material or a combination of materials suitable for use in the channels of a 3D memory or other 3D semiconductor device. For example, the sixth material can be a channel material, such as channel material 138 of structure 102 (or, if already referred to Figure 2A - 2FDescribing additional steps for processing 200, it would then be the channel material 238 of structure 202. As a specific example of the channel material, the channel material may include one or more of SiO2, SiN, and polysilicon. The sixth material can be deposited using any suitable deposition technique, such as including ALD or other CVD processes.

[0150] As described above with reference to step 308, in some embodiments, the third material may already be the sixth material, rather than a fill material to be subsequently replaced with the sixth material (e.g., channel material). In such an example, steps 320 and 322 can be omitted.

[0151] Figure 4 A flowchart illustrating an example method 400 for forming a layer stack according to some embodiments is shown. In some embodiments, method 400 can be used to form a layer stack of alternating layers, where some of the layers include TAG as a reagent generating component. For example, method 400 can be used to form layer stack 106. Method 400 can be combined with other techniques described throughout this disclosure, such as, by way of example only, in combination with method 300. In some embodiments, method 400 is an illustrative technique for performing Figure 3A - 3B step 302 of method 300.

[0152] At step 402, a layer of a first carbon-containing material can be deposited over a substrate. In some embodiments, the layer of the first carbon-containing material can be deposited over the substrate using a spin-on deposition technique. The layer of the first carbon-containing material can correspond to layer 108a deposited over substrate 104, as Figure 1A - 1M described above. As described above, the layer of the first carbon-containing material (e.g., layer 108a) can be a layer that undergoes a solubility change when exposed to a solubility-changing reagent (e.g., an acid), and can thus be removed in a subsequent development step, and for this purpose the first carbon-containing material layer can include a reagent generating component for generating a solubility-changing reagent in response to an activation trigger. For the purpose of exemplifying method 400, it will be assumed that the reagent generating component 110 is TAG, the solubility-changing reagent 126 is an acid, and the activation trigger is heat.

[0153] In some embodiments, layer 108a includes a photoresist material having an embedded reagent generating component 110 (e.g., TAG). For example, the photoresist material can be CAR. As another specific example, layer 108a can include a developable ARC, such as DBARC having reagent generating component 110.

[0154] At step 404, a bake can be performed on the semiconductor structure including the deposited layer of the first carbon-containing material (e.g., layer 108a). This bake can correspond to that referred to above Figure 1AThe described bake 112a. The bake 112a of the semiconductor structure 102 can cause a cross-linking reaction (e.g., a polymer cross-linking reaction) to occur in the layer 108a. For example, the polymer chains of the layer 108a can be cross-linked by thermally induced bond formation. This cross-linking reaction can cause the layer 108a to harden or otherwise strengthen, which can enable the layer 108a to better handle the stress of additional layers 108 as the height of the layer stack 106 increases.

[0155] At step 406, a layer of a second carbon-containing material can be deposited over the layer of the first carbon-containing material. In certain embodiments, the layer of the second carbon-containing material can be deposited over the layer of the first carbon-containing material using a spin-on deposition technique. The layer of the second carbon-containing material can correspond to the layer 108b deposited over the substrate 108a, as described above. Figure 1A - 1M In certain embodiments, the material for the layer 108b can include SOC, SiOC, ODL, OPL, SiOCN, SiC, photoresist, ARC, BARC, epoxy resin, etc. Some of these examples can overlap in type.

[0156] At step 408, the semiconductor structure including the deposited layer of the second carbon-containing material can be baked. This bake can correspond to the bake 112b described above with reference to Figure 1A The described bake 112b. The bake 112b of the semiconductor structure 102 can cause a cross-linking reaction (e.g., a polymer cross-linking reaction) to occur in the layer 108b. For example, the polymer chains of the layer 108b can be cross-linked by thermally induced bond formation. This cross-linking reaction can cause the layer 108b to harden or otherwise strengthen, which can enable the layer 108b to better handle the stress of additional layers 108 as the height of the layer stack 106 increases.

[0157] At step 410, it can be determined whether an additional layer of the first and / or second carbon-containing material is to be added to the layer stack being formed. If it is determined that an additional layer of the first and / or second carbon-containing material is to be added, the method 400 can return to step 402 to deposit the additional layer. If it is determined not to add an additional layer of the first and / or second carbon-containing material, the method 400 can proceed to step 410 for additional processing. In certain embodiments, the additional processing can include forming a hard mask layer (e.g., the mask layer 116a) over the layer stack 106. In certain embodiments, the additional processing can include proceeding to Figure 3A - 3B step 304 of the method 300. Although the first instance of the layer 108a is described as being deposited before the first instance of the layer 108b, the first instance of the layer 108b can be deposited before the first instance of the layer 108a.

[0158] Figure 5A flowchart illustrating an example method 500 for forming a layer stack in accordance with certain embodiments is shown. In certain embodiments, method 500 may be used to form a layer stack of alternating layers, where certain layers include a PAG as a reagent generating component. For example, method 500 may be used to form layer stack 206. Method 500 may be combined with other techniques described throughout this disclosure, such as in combination with method 300 by way of example only. In certain embodiments, method 500 is an illustrative technique for performing Figure 3A - 3B step 302 of method 300.

[0159] At step 502, a first layer of a carbon-containing material may be deposited over a substrate. In certain embodiments, the first layer of the carbon-containing material may be deposited over the substrate using a spin coating deposition technique. The first layer of the carbon-containing material may correspond to layer 208a deposited over substrate 204, as Figure 2A - 2F described above. As described above, the first layer of the carbon-containing material (e.g., layer 208a) may be a layer that undergoes a solubility change when exposed to a solubility-changing reagent (e.g., an acid), and thus is subsequently removed in a development step, and for this purpose the first layer of the carbon-containing material may include a reagent generating component for generating a solubility-changing reagent in response to an activation trigger. For the purpose of exemplifying method 500, it will be assumed that the reagent generating component 210 is a PAG, the solubility-changing reagent 226 is an acid, and the activation trigger is radiation.

[0160] In certain embodiments, layer 208a includes a photoresist material having an embedded reagent generating component 210 (e.g., a PAG). For example, the photoresist material may be a CAR. As another specific example, layer 208a may include a developable ARC, such as a DBARC having a reagent generating component 210.

[0161] In step 504, the first layer 208a of the carbon-containing material may be exposed to actinic radiation 211, causing the reagent generating component 210 (PAG) to generate a solubility-changing reagent 226 (e.g., an acid). For example, actinic radiation 211 may be directed towards semiconductor structure 202, and in particular to the surface of layer 208a, causing the reagent generating component 210 to generate a solubility-changing reagent 226 in layer 208a. The lithography technique for exposing layer 208a to actinic radiation 211 may include any suitable type of lithography technique. In certain embodiments, an exposure suitable for causing a PAG to generate a solubility-changing reagent 226 may be a flood exposure.

[0162] At step 506, a second layer of a second carbonaceous material can be deposited over the first layer of the first carbonaceous material. In some embodiments, the second layer of the second carbonaceous material can be deposited over the first layer of the first carbonaceous material using a spin coating deposition technique. The second layer of the second carbonaceous material can correspond to layer 208b deposited over substrate 208a, as described above. In some embodiments, the material for layer 208b can include SOC, SiOC, ODL, OPL, SiOCN, SiC, photoresist, ARC, BARC, epoxy resin, etc. Some of these examples can overlap in type. Figure 2A - 2F At step 508, the semiconductor structure including the deposited first and second layers can be baked. This baking can correspond to the baking 212 / 224 of semiconductor structure 202 described above. As described above, the baking 212 / 224 can be a single bake or multiple bakes performed at the same or different temperatures.

[0163] In some embodiments, the baking 212 / 224 can be performed to modify layer 208a to be soluble in a developer. In response to the baking 212 / 224, the solubility altering reagent 226 can modify layer 208a (e.g., the carbonaceous material of layer 208a) to be soluble for development (e.g., removal) in a developer. Additionally or alternatively, the baking 212 / 224 of semiconductor structure 202 can cause a crosslinking reaction (e.g., a polymer crosslinking reaction) to occur in layer 208a and / or 208b. For example, the polymer chains of layer 208a and / or 208b can be crosslinked by thermally induced bond formation. This crosslinking reaction can cause layer 208a and / or 208b to harden or otherwise strengthen, which can enable layer 208a and / or 208b to better withstand the stress of additional layers 208 as the height of layer stack 206 increases. Figure 2A

[0164]

[0165]

[0166] In some embodiments, step 508 can be performed after depositing each layer 208 or after depositing more than two layers 208. Additionally, in terms of performing multiple bakes 212 / 224, the temperatures of the multiple bakes 212 / 224 can be the same or different, which may be appropriate for a given implementation. Additionally, although the first instance of layer 208a is described as being deposited before the first instance of layer 208b, the first instance of layer 208b can be deposited before the first instance of layer 208a.

[0166] Although the baking 212 / 224 is described as being sufficient for the solubility altering reagent 226 to change the solubility of layer 208a at step 508, this disclosure contemplates that at another time point, such as as described above with reference to Figure 2EPerforming a bake to change the solubility of layer 208a with the solubility-changing reagent 226 after forming the opening 222.

[0167] At step 510, it can be determined whether an additional layer of the first and / or second carbon-containing material is to be added to the layer stack being formed. If it is determined that an additional layer of the first and / or second carbon-containing material is to be added, method 500 can return to step 502 to deposit the additional layer. If it is determined not to add an additional layer of the first and / or second carbon-containing material, method 500 can proceed to step 512 to perform additional processing. In certain embodiments, the additional processing can include forming a hard mask layer (e.g., mask layer 216a) over the layer stack 206. In certain embodiments, the additional processing can include proceeding to Figure 3A - 3B step 304 of method 300 of

[0168] Figure 6 - 9 Illustrating exemplary processing tools that can be used alone or in combination to implement certain embodiments of the present disclosure.

[0169] Figure 6 Illustrating a block diagram of an exemplary coater-developer system 600 according to certain embodiments. Coater-developer system 600 is merely an example of a coater-developer system that can be used with certain embodiments of the present disclosure. In the illustrated example, coater-developer system 600 includes a track system 602 and a projection scanner 604. In certain embodiments, coater-developer system 600 is generally configured to perform a portion of process 100, method 300, and / or method 400.

[0170] Track system 602 includes a series of processing modules that are assembled to allow for the execution of processing in a viable order for the processing being performed using coater-developer system 600. Track system 602 provides material processing, such as coating a wafer with a carbon-containing material (e.g., photoresist or SOC), baking the photoresist (possibly more than once), and developing the photoresist.

[0171] In the illustrated example, these processing modules of the track system 602 include a spin coating module 606 (e.g., for depositing a carbon-containing material of layer 108a, such as a photoresist or a DBARC, which has a reagent generating component 110, such as a TAG), a baking module 608 (e.g., for promoting crosslinking in layer 108a), a spin coating module 610 (e.g., for depositing a carbon-containing material of layer 108b, such as an SOC), a baking module 612 (e.g., for promoting crosslinking in layer 108b), a baking module 614 (e.g., for generating a solubility-changing reagent 126 from the reagent generating component 110 and / or for the solubility-changing reagent 126 to change the solubility of layer 108a), and a developing module 616 for developing the deprotected layer 108a.

[0172] Spin coating modules 606 and 610 include spin coaters, examples of which are referred to Figure 8 and described below. The carbon-containing materials, solvents, etc. of layers 108a and 108b are connected from a liquid supply system via pipelines, filters, valves, and pumps to appropriate processing modules (e.g., spin coating modules 606 and 610, developing module 616, etc.).

[0173] The coater-developer system 600 may include a transfer system for moving a wafer (e.g., semiconductor structure 102) between the modules of the track system 602, and from the track system 602 to a projection scanner 604 (which can be regarded as "off the track"), and back from the projection scanner 604 to the track system 602. As shown by the dashed line 618, in some embodiments, the wafer being processed can be cycled through modules 606, 608, 610, and 612 a sufficient number of times so that the layer stack reaches the target number of layers.

[0174] Within the range of use, the scanner 604 can be configured to perform an exposure phase. The scanner 604 can be a combination of an optical and a mechanical system for scanning an optical image of a pattern printed on a photomask onto the surface of a wafer coated with a resist. After scanning the pattern once, the scanner 604 can be operated to step to an adjacent position on the same wafer, where the scanning is repeated to form another copy of the pattern. In this way, the photoresist layer is exposed to multiple copies of the pattern configured in a rectangular matrix on the wafer surface. In some embodiments, at least for the purpose of depositing, deprotecting, and removing certain layers 108 of the layer stack 106 (e.g., in certain embodiments of the reagent generating component 110 as a TAG), a projection scanner is not used.

[0175] Figure 7A block diagram of an exemplary coater-developer system 700 in accordance with certain embodiments is shown. Coater-developer system 700 is merely an example of a coater-developer system that may be used with certain embodiments of the present disclosure. In the illustrated example, coater-developer system 700 includes a track system 702 and a projection scanner 704. In certain embodiments, coater-developer system 700 is generally configured to perform a portion of process 200, method 300, and / or method 500. Generally speaking, coater-developer system 600 is similar to coater-developer system 700 except that coater-developer system 700 is configured to perform patterning process 200. The description of coater-developer system 700 is incorporated by reference.

[0176] Track system 702 includes a series of processing modules that are assembled to allow for a viable sequence of process execution for the processes to be performed using coater-developer system 700. Track system 702 provides material processing, such as coating a wafer with a carbon-containing material (e.g., photoresist or SOC), exposing certain layers of the wafer to actinic radiation, baking the photoresist (possibly more than once), and developing the photoresist.

[0177] In the illustrated example, these processing modules of track system 702 include a spin coat module 706 (e.g., for depositing a carbon-containing material of layer 208a, such as photoresist or DBARC, which has a reagent generating component 210, such as PAG), a flood exposure module 708 (e.g., for exposing layer 208a to actinic radiation and thereby generating a solubility-altering reagent 226 in layer 208a from the reagent generating component 210), a spin coat module 710 (e.g., for depositing a carbon-containing material of layer 208b, such as SOC), a bake module 712 (e.g., for promoting crosslinking of one or more of layers 208a / 208b and for causing the solubility-altering reagent 226 to alter the solubility of layer 208a), and a develop module 714 for developing the deprotected layer 208a.

[0178] Spin coat modules 706 and 710 include spin coaters, examples of which are described below with reference to Figure 8 The carbon-containing materials, solvents, etc. of layers 208a and 208b are connected from a liquid supply system to the appropriate processing modules (e.g., spin coat modules 706 and 710, develop module 714, etc.) via tubing, filters, valves, and pumps.

[0179] The coater-developer system 700 may include a transfer system for moving a wafer (e.g., semiconductor structure 202) between modules of the track system 702, and from the track system 702 to the projection scanner 704 (which may be considered "off-track"), and back from the projection scanner 704 to the track system 702. As shown by the dashed line 716, in certain embodiments, the wafer being processed may be cycled through modules 706, 708, 710, and 712 a sufficient number of times such that the layer stack reaches a target number of layers.

[0180] Within the scope of use, the scanner 704 may be configured to perform the exposure phase in a manner similar to that described above for the scanner 704. In certain embodiments, for at least the purposes of depositing, deprotecting, and removing certain layers 208 of the layer stack 206, the projection scanner is not used. For example, the track system 702 may include a flood exposure module 708 configured to expose the layer 208a to actinic radiation, rather than transferring the wafer to the projection scanner 704 for exposure (related to the PAG of the activated layer 208a). Figure 7 Regarding the two exemplary coater-developer systems 600 and 700 respectively, each coater-developer system 600 and 700 may include additional modules, and / or during the entire process 100 / 200 and / or method 300 / 400 / 500, the wafer may be moved from the coater-developer system 600 / 700 to another tool for selected processing. For example, for forming the openings 118 / 218 and / or the openings 122 / 222, including the relevant patterning of the mask layer 116, the coater-developer system 600 / 700 may include additional modules for performing some or all of these steps, and / or may move the wafer to one or more other tools for some or all of these processes, and the wafer may potentially return to the coater-developer system 600 / 700 for one or more processing steps (e.g., development), and then may again be moved to one or more other tools for further processing.

[0181] Regarding Figure 6 and Figure 7 An exemplary liquid-based spin coating deposition system 800 is illustrated in accordance with certain embodiments. For example, the liquid-based spin coating deposition system 800 may be used to process any of the described semiconductor structures to deposit any one of the layers 108 / 208 or other suitable materials described in this disclosure. In certain embodiments, the spin coating deposition system 800 may be a semi-closed spin coating deposition system for coating a substrate (wafer) with a desired layer. This semi-closed configuration may allow for particulate contaminant control and minimize exhaust volume.

[0182] Figure 8

[0183] ​In the illustrated example, the spin coating deposition system 800 includes: a processing chamber 802 that includes a substrate holder 804 (which may include any semiconductor structure described in this disclosure during appropriate processing stages) for supporting, heating, and rotating (spinning) a substrate 806; a rotating device 808 (e.g., a motor); and a liquid delivery nozzle 810 that is configured to supply a processing liquid 812 to the upper surface of the substrate 806. Liquid supply systems 814, 816, and 818 supply different processing liquids to the liquid delivery nozzle 810. For the deposition of photoresist, the different processing liquids may include, for example, a first reactant in a first liquid, a second reactant in a second liquid, and a rinse liquid. In certain embodiments, the spin coating deposition system 800 includes additional liquid delivery nozzles for supplying different liquids to the substrate 806. During exposure of the upper surface of the substrate 806 to the processing liquid 812, an exemplary rotational speed may be between about 500 rpm and about 1500 rpm, such as 1000 rpm.

[0184] The spin coating deposition system 800 may include a controller 820 that may be coupled to and control the processing chamber 802; the liquid supply systems 814, 816, and 818; the liquid delivery nozzle 810; the rotating device 808, and a mechanism for heating the substrate holder 804. During film deposition, the substrate 806 may be under an inert atmosphere. The spin coating deposition system 800 may be configured to process substrates 806 of any suitable size.

[0185] Figure 9 An example processing system 900 for CVD, ALD, PECVD, plasma enhanced ALD (PEALD), gas phase etching, or plasma etching processes according to certain embodiments is illustrated. In the illustrated example, the processing system 900 includes a processing chamber 902 that has a substrate holder 904 configured to support a substrate 906 (similar to Figure 8 the substrate 806) (e.g., on which a layer stack 106 / 206 has been deposited).

[0186] The processing chamber 902 may include an upper assembly 908 (e.g., a showerhead) coupled to a first precursor supply system 910 that is configured to supply one or more first precursor gases. A second precursor supply system 912 is configured to supply a second precursor gas (e.g., enol, alcohol, diol, phenol, carboxylic acid, or a combination thereof). The processing system 900 may include a purge gas supply system 914 and auxiliary gas supply systems 916, 918, and 920 (e.g., for supplying additional precursor gases to the processing chamber 902).

[0187] The processing system 900 includes a substrate temperature control system 922 coupled to a substrate holder 904 and configured to control the temperature of a substrate 906. The substrate temperature control system 922 includes temperature control elements, such as a cooling system including a recirculating coolant flow that receives heat from the substrate holder 904 and transfers the heat to a heat exchanger system, or from the heat exchanger system when heating. Additionally, the temperature control elements may include heating / cooling elements, such as resistive heating elements or thermoelectric heaters / coolers, which may be included in the substrate holder 904, the chamber walls of the processing chamber 902, and any other components located within the processing system 900. The substrate temperature control system 922 may be configured to control the substrate temperature, for example, from room temperature to about 350 °C to about 550 °C. The temperature of the substrate 906 may be selected based on the desired temperature for depositing a particular layer on the surface of a given substrate 906.

[0188] The processing system 900 may include a controller 924 that may be coupled to the processing chamber 902; the substrate holder 904; an upper assembly 908 configured to introduce a processing gas into the processing chamber 902; precursor supply systems 910 and 912; a purge gas supply system 914; auxiliary gas supply systems 916, 918, and 920; and the substrate temperature control system 922. The controller 924 may be coupled to one or more additional controllers / computers, and the controller 924 may obtain setpoint and / or configuration information from the additional controllers / computers.

[0189] In the illustrated example, although specific processing elements (902, 904, 908, 910, 912, 914, 916, 918, 920, and 922) are shown, the processing system 900 may include any number of processing elements with any number of associated controllers. The controller 924 may be used to configure any number of processing elements and may collect, provide, process, store, and display data from the processing elements. The controller 924 may include multiple applications for controlling one or more processing elements. For example, the controller 924 may include a graphical user interface (GUI) component that may provide an easy-to-use interface that allows a user to monitor and / or control one or more processing elements.

[0190] The processing system 900 may be configured to process substrates 906 of any suitable size. Additionally, batch system implementations may be capable of processing multiple substrates 906 simultaneously.

[0191] In some embodiments, various techniques can be used to introduce precursor gases into the processing chamber 902. One technique includes vaporizing the precursor by using a separate bubbler or a direct liquid injection (DLI) system or a combination thereof, and then mixing it in the gas phase within the processing chamber 902 or before introducing it into the processing chamber 902. Another technique includes separately controlling two or more different liquid sources (pure precursors or precursor solutions), which are then mixed before entering a common vaporizer. This technique can be used when the precursors are compatible in solution or liquid form and have similar vaporization characteristics. Another technique includes controlling the flow of a liquid precursor mixture (pure precursor or precursor solution) to a common vaporizer. Other techniques include using compatible mixed solid or liquid precursors within a bubbler. The liquid source precursors can include pure liquid precursors, or solid or liquid precursors dissolved in a compatible solvent. Feasible compatible solvents include, but are not limited to, ionic liquids, hydrocarbons (aliphatic, olefinic, and aromatic), amines, esters, diglyme, crown ethers, ethers, and polyethers. In some embodiments, one or more compatible solid precursors can be dissolved in one or more compatible liquid precursors. By controlling the relative concentration levels of the first and second precursors within the gas pulse, a film with a desired stoichiometry can be deposited.

[0192] The purge gas supply system 914 can be configured to introduce a purge gas into the processing chamber 902. For example, a purge gas can be introduced between pulses of the first precursor gas and the second precursor gas into the processing chamber 902. The purge gas can include an inert gas, such as a noble gas (i.e., He, Ne, Ar, Kr, Xe), nitrogen gas (N2), or hydrogen gas (H2).

[0193] To improve the heat transfer between the substrate 906 and the substrate holder 904, the substrate holder 904 can include a mechanical clamping system or an electrical clamping system, such as an electrostatic clamping system, to fix the substrate 906 to the upper surface of the substrate holder 904. The substrate holder 904 can include a substrate backside gas delivery system for guiding gas to the backside of the substrate 906, thereby improving the gas-gap heat conduction between the substrate 906 and the substrate holder 904. Such a system can be used when it is necessary to control the temperature of the substrate 906 at elevated or reduced temperatures.

[0194] The processing chamber 902 can be coupled to a pressure control system 926 through a conduit 932, including a vacuum pump system 928 and a valve 930. The pressure control system 926 can be configured to controllably evacuate the processing chamber 902 to a pressure suitable for forming a desired film on the substrate 906 and a pressure suitable for using the precursor. The vacuum pump system 928 can include a turbomolecular pump (TMP) or a cryopump capable of achieving a pumping speed of about 5000 liters per second (or greater), while the valve 930 can include a gate valve for regulating the chamber pressure. In addition, a device for monitoring the chamber pressure can be coupled to the processing chamber 902. As an example, the pressure control system 926 can be configured to control the processing chamber pressure between about 0.1 torr and about 100 torr during the deposition of the film.

[0195] The precursor supply systems 910 and 912; the purge gas supply system 914; the auxiliary gas supply systems 916, 918, and 920 can include one or more pressure control devices, one or more flow control devices, one or more filters, one or more valves, and / or one or more flow sensors. The flow control devices can include pneumatically actuated valves, electromechanical (electromagnetic) valves, and / or high-speed pulsed gas injection valves. These gases can be pulsed into the processing chamber 902 sequentially and alternately, where the length of each gas pulse can be between, for example, about 0.1 second and about 100 seconds (e.g., between about 1 second and about 10 seconds). Exemplary gas pulse lengths for the precursor gas can be between 0.3 second and 3 seconds, such as 1 second. Exemplary purge gas pulses can be between 1 second and 20 seconds, such as 3 seconds.

[0196] The controller 924 can include a microprocessor, a memory, and digital I / O ports that are capable of generating control voltages sufficient to transmit and initiate inputs to the processing system 900 and monitor outputs from the processing system 900. In addition, the controller 924 can be coupled to and can exchange information with: the processing chamber 902; the substrate holder 904; the upper assembly 908; the precursor supply systems 910 and 912; the purge gas supply system 914; the auxiliary gas supply systems 916, 918, and 920; the substrate temperature control system 922; the substrate temperature control system 922; and the pressure control system 926. For example, a program stored in the memory can be used to initiate inputs to these components of the processing system 900 according to a recipe to perform a deposition process.

[0197] The plasma processing system 900 further includes a plasma generation system configured to generate plasma during at least a portion of the gas exposure in the processing chamber 902. The plasma generation system includes a first power source 934 coupled to the processing chamber 902 and configured to couple power to the gas introduced into the processing chamber 902. The first power source 934 may be a variable power source and may include a radio frequency (RF) generator and an impedance matching network, and may include an electrode through which RF power is coupled to the plasma in the processing chamber 902. The electrode may be formed in the upper assembly 936 and may be configured to face the substrate holder 904. The impedance matching network may be configured to optimize the RF power transfer from the RF generator to the plasma by matching the output impedance of the matching network with the input impedance of the processing chamber 902 (including the electrode and the plasma). For example, the impedance matching network is used to improve the RF power transfer to the plasma in the processing chamber 902 by reducing the reflected power.

[0198] Alternatively, the first power source 934 may include an RF generator and an impedance matching network, and may further include an antenna, such as an induction coil, through which RF power is coupled to the plasma in the processing chamber 902. The antenna may include, for example, a helical coil or a solenoid coil located in an inductively coupled plasma source or a helical source, or it may include, for example, a flat coil in a transformer coupled plasma source. Alternatively, the first power source 934 may include a microwave frequency generator, as well as a microwave antenna and a microwave window, through which microwave power is coupled to the plasma in the processing chamber 902. Electron cyclotron resonance (ECR) technology or surface wave plasma technology may be used to achieve the coupling of microwave power.

[0199] In some embodiments, plasma processing system 900 includes a substrate bias generation system configured to generate or assist in generating plasma (by biasing the substrate holder) during at least a portion of an alternating introduction of gas into processing chamber 902. The substrate bias system may include a substrate power source 938 coupled to processing chamber 902 and configured to couple power to substrate 906. Substrate power source 938 may include an RF generator and an impedance matching network, and may also include an electrode (e.g., formed in substrate holder 904), through which RF power is coupled to substrate 906. For example, the substrate holder 904 may be electrically biased at an RF voltage by transmitting RF power from the RF generator through the impedance matching network to the substrate holder 904. The typical frequency range of the RF bias may be from about 0.1 MHz to about 100 MHz, and may be 13.56 MHz. Alternatively, multiple frequencies may be utilized to apply RF power to the substrate holder electrode. Although the plasma generation system and the substrate bias system are shown as separate entities in Figure 9 they may include one or more power sources coupled to substrate holder 904.

[0200] In some embodiments, plasma processing system 900 includes a remote plasma system 940 for providing and remotely plasma exciting a gas before flowing the plasma-excited gas into processing chamber 902 where it is exposed to substrate 906. Remote plasma system 940 may include a microwave frequency generator. The processing chamber pressure may be between about 0.1 Torr and about 10 Torr, or between about 0.2 Torr and about 3 Torr.

[0201] Figure 10A - 10B Illustrates an example aspect of a 3D NAND memory array in accordance with some embodiments. Figure 10A Illustrates a projected view of a cross section of a 3D-NAND memory array formed in accordance with some embodiments. Figure 10B Illustrates a cross-sectional view through a stack of memory transistors in a 3D-NAND memory array formed in accordance with some embodiments (e.g., which may be layer stacks 106 or 206 after processing 100 or 200, respectively). Specifically, Figure 10B Illustrates a cross-sectional view of an exemplary 3D NAND word line stack of alternating gates (word lines) and insulating layers formed in accordance with some embodiments (e.g., which may be layer stacks 106 or 206 after processing 100 or 200, respectively).

[0202] Figure 10AA semiconductor substrate 1002 in which a common drain bit line 1004 is formed is shown. This cross-section shows alternating layers of a dielectric material 1008 that electrically isolate multiple layers of word lines 1006. The word lines 1006 are alternating metal gates of stacked memory transistors in a 3D NAND array. In some embodiments, the dielectric material 1008 is a remaining oxide or nitride material corresponding to a layer stack formed from the above-mentioned process 100 or 200. The word lines 1006 may correspond to at least a part of the material 136 in the layer stack formed by the above-mentioned process 100 (or 200) (or would be material 236 if the process 200 description extends beyond Figure 2F ).

[0203] A common source bit line 1014 (e.g., which may include polysilicon) is perpendicular to the word lines 1006 and spans the top surface of the 3D NAND memory array. The drain bit line 1004 and the source bit line 1014 are connected to a thin transistor channel 1016 (shown in Figure 10B ) made of, for example, silicon and located on the sidewalls of the channel 1018. The channel 1018 may correspond to at least a part of the channel material that fills the above-mentioned opening 118 or 218 (e.g., material 138 for process 100, or would be material 238 if the process 200 description extends beyond Figure 2F ). These memory transistors in the layers of the bit line 1006 share the common source bit line 1014 and the common drain bit line 1004.

[0204] Figure 10B The cross-sectional view through the non-volatile transistor stack in the 3D NAND memory array shown in Figure 10A is delineated by the dashed square 1000 in

[0205] Each transistor includes a gate (bit line 1006) that is isolated from the transistor channel 1016 by a gate dielectric 1020. The gate dielectric 1020 may correspond to a part of the above-mentioned channel material. During programming, electrons can be trapped in the gate dielectric 1020. The trapped electrons increase the turn-on voltage of the non-volatile transistor. A transistor with electrons trapped in the gate dielectric 1020 stores the logic state "1", while a transistor without trapped electrons stores the logic state "0". These logic states are retained for 10 years or more even when the 3D NAND memory is not connected to a power supply. In some embodiments, these transistors may be SONOS transistors. In other embodiments, these transistors may be TANOS transistors. Other types of transistors may also be considered.

[0206] Multiple transistors are stacked one above another in a word line stack. The metal gate (word line 1006) of one transistor is isolated from other non-volatile transistors stacked above and below by a layer of dielectric material 1008. These transistors in the stack share a common source terminal 1022 and also share a common drain terminal 1024. A thin layer of lightly doped silicon layer 1026 (e.g., doped between 10 14 cm -3 to 10 17 cm -3 is the channel 1016 used to form the stacked transistors in the 3D NAND memory array. The thin layer of the lightly doped silicon layer 1026 can be in-situ doped with an n-type dopant to form an n-channel transistor. One end of the thin layer of the lightly doped silicon layer 1026 is shorted to the common source bit line 1014, i.e., the opposite end of the thin layer of the lightly doped silicon layer 1026 is shorted to the common drain bit line 1004.

[0207] During operation, a voltage can be applied to the common drain bit line 1004 (drain terminal 1024), and the common source bit line 1014 (source terminal 1022) is kept grounded. By turning on one of the gate select transistors 1030, the voltage on the gate terminal 1028 can be connected to one of these gates (bit line 1006). If the transistor is programmed to zero (no trapped electrons), the channel 1016 will conduct and additional current will flow through the channel 1016 of the transistor. However, if the transistor is programmed to 1 (trapped electrons), the channel 1016 will remain closed and no additional current will flow.

[0208] Embodiments of the present disclosure may provide some, none, or all of the following technical advantages. Additionally, based on this implementation, these and other technical advantages will be apparent to those skilled in the art.

[0209] In certain embodiments, using a spin coating and a sacrificial layer to initially construct a layer stack of alternating layers of a 3D semiconductor structure reduces the stress on the semiconductor structure during layer stack formation. This stress reduction can reduce or eliminate defects in the semiconductor structure, such as warping (so-called wafer warping) or other defects. For example, a caliper or other tool for measuring wafer warping can be used to measure the stress on the semiconductor structure. In certain embodiments, compared to repeatedly performing CVD deposition processes to deposit each layer of the layer stack, using a spin coating process technology to deposit the layers of the layer stack as sacrificial layers and then replacing these sacrificial layers with the desired layers of the layer stack can reduce the stress in the resulting semiconductor structure by half, two-thirds, or more.

[0210] In some embodiments, as opposed to repetitively performing CVD deposition processes to deposit each layer of a layer stack, using a spin coating process technique to deposit the layers of the layer stack as sacrificial layers and then replacing these sacrificial layers with the desired layers of the layer stack can reduce costs in terms of processing time and expense. For example, repetitively performing CVD deposition processes to deposit each layer of a layer stack can be both time-consuming and expensive. In contrast, spin coating techniques are relatively fast and inexpensive. Additionally, it may be possible to use as few as one deposition step (per layer type of the layer stack), such as using ALD or other CVD processes to remove these sacrificial layers of the layer stack (layers deposited by spin coating) and replace these sacrificial layers with the desired layers of the layer stack.

[0211] In some embodiments, forming a layer stack of alternating carbon-containing material layers can reduce or eliminate the complexity of etching various openings in the layer stack to form elements of a semiconductor structure. That is, a layer stack in which both of the two layer types forming the alternating layers of the layer stack are carbon-containing layers can allow for the use of a relatively straightforward etching process to etch the openings, such as for forming channels and / or gates of a 3D semiconductor structure.

[0212] As just one specific example, a first set of layers of the layer stack can be formed of a photoresist or DBARC material that includes a reagent generating component (e.g., a TAG or PAG) for generating a solubility-altering reagent (e.g., an acid) in response to an activation trigger and can alter the solubility of the first set of layers for development in a developer. A second set of layers can be a carbon-containing material that is insoluble in the developer, such as SOC. Such an arrangement can allow for both layers to be carbon-containing layers, providing the ability to more easily form openings in these layers while still allowing for the selective removal of these layers for replacement with other layers. In some embodiments, the processing time for forming openings in the layer stack can be reduced by up to one-third or more as compared to a solution where a carbon-containing layer (or even a non-carbon-containing layer) can be used as one layer type in the layer stack and a non-carbon-containing layer (e.g., spin-on glass or SOG) can be used as the other layer type in the layer stack.

[0213] Additionally, the processing time for removing the first and second layers can be reduced as compared to a solution where a carbon-containing layer (or even a non-carbon-containing layer) can be used as one layer type in the layer stack and a non-carbon-containing layer (e.g., spin-on glass or SOG) can be used as the other layer type in the layer stack. For example, the step of removing a carbon-containing layer that has been modified to be soluble in a developer can be faster as compared to an etching process for removing a non-carbon-containing layer (e.g., SOG).

[0214] In some embodiments, since the ability to etch a layer stack in which both types of alternating layers are carbon-containing layers is relatively easy, the thickness of a mask layer (e.g., a hard mask) used to form an opening in the layer stack can be reduced, which can reduce the processing time for depositing the mask layer, the material usage / cost for depositing the mask layer, and the stress on the layer stack (e.g., due to the thinner mask layer). If the layer stack includes a layer (e.g., a SOG layer) in which an opening is formed in the layer stack using a more stringent and time-consuming etching process, the mask layer can be thicker to withstand those etching processes.

[0215] Embodiments of the present disclosure can be used to fabricate 3D semiconductor structures, such as 3D VNAND structures; however, 3D memory structures are just one example of 3D semiconductor structures that can utilize the techniques described herein. The techniques described herein can be used with other structures, including other 3D structures in addition to 3D memory cell structures that may include layer stacks.

[0216] Exemplary embodiments of the present disclosure are summarized herein. Other embodiments can also be understood from the entire specification and the claims presented herein.

[0217] Example 1. A method includes forming a layer stack of alternating layers of a first and a second carbon-containing material on a substrate by spin coating deposition. The layers of the first carbon-containing material include reagent generating components for generating a solubility-changing reagent in response to an activation trigger. The method includes performing the activation trigger, in response to which the solubility-changing reagent is generated from the reagent generating components in the layers of the first carbon-containing material, and modifying the layers of the first carbon-containing material to be soluble in a developer. The method includes etching a plurality of first openings through the layer stack, filling the first openings with a third material, etching a plurality of second openings through the layer stack, removing the layers of the first carbon-containing material from the layer stack by exposing the layers of the first carbon-containing material to the developer, and replacing the layers of the first carbon-containing material with a fourth material.

[0218] Example 2. The method of Example 1, wherein the reagent generating component includes a thermal acid generator, the solubility-changing reagent includes an acid, the activation trigger includes heat, and performing the activation trigger includes baking the substrate.

[0219] Example 3. The method of any one of Examples 1 to 2, wherein performing the activation trigger is performed after etching the second openings through the layer stack and before replacing the layers of the first carbon-containing material with the fourth material.

[0220] Example 4. A method according to any one of Examples 1, wherein the reagent generating component comprises a photoacid generator, the solubility altering reagent comprises an acid, the activation trigger comprises actinic radiation, and performing the activation trigger comprises exposing the layers of the first carbon-containing material containing the reagent generating component to actinic radiation.

[0221] Example 5. A method according to any one of Examples 1 and 4, wherein performing the activation trigger is carried out after forming each layer of the first carbon-containing material, such that each layer of the first carbon-containing material is exposed to actinic radiation as the formation of the layer stack progresses.

[0222] Example 6. A method according to any one of Examples 1 to 5, further comprising removing the layers of the second carbon-containing material from the layer stack and replacing the layers of the second carbon-containing material with a fifth material, wherein the fifth material is a metal-containing material.

[0223] Example 7. A method according to any one of Examples 1 to 6, further comprising removing the third material from the first openings and, after replacing the layers of the first carbon-containing material with the fourth material, replacing the third material with a sixth material.

[0224] Example 8. A method according to any one of Examples 1 to 7, wherein the third material comprises a metal oxide material and the sixth material comprises one or more of silicon dioxide, silicon nitride, and polysilicon.

[0225] Example 9. A method according to any one of Examples 1 to 8, wherein the fourth material comprises an oxide material or a nitride material.

[0226] Example 10. A method according to any one of Examples 1 to 9, wherein: the first carbon-containing material comprises SOC, SiOC, ODL, OPL, organic SOH, SiOCN, SiC, photoresist, BARC, or DBARC; and the second carbon-containing material comprises SOC, SiOC, ODL, OPL, organic SOH, SiOCN, SiC, photoresist, BARC, or epoxy resin.

[0227] Example 11. A method for manufacturing a 3D NAND device includes forming, on a substrate, a layer stack composed of a plurality of first layers of a first carbon-containing material and a plurality of second layers of a second carbon-containing material that alternate. These first layers and these second layers are deposited by spin coating. These first layers include a photoresist material or a developable anti-reflective coating, and include a reagent generating component for generating a solubility-changing reagent in response to an activation trigger. The method includes performing the activation trigger, the solubility-changing reagent being generated from the reagent generating component in these first layers in response to the activation trigger, the solubility-changing reagent modifying these first layers to be soluble in a developer. The method includes etching a plurality of channel vias through the layer stack, filling these channel vias with a third material, and etching a plurality of slits through the layer stack, the slits exposing the alternating first layers and second layers of the layer stack. The method includes removing these first layers from the layer stack by exposing these first layers to the developer, and replacing these first layers with a fourth material, the fourth material including an oxide or a nitride. The method includes removing these second layers from the layer stack by exposing these second layers to an etching chemical, and replacing these second layers with a fifth material, the fifth material being a metal-containing material.

[0228] Example 12. The method of Example 11 further includes, during the formation of the layer stack, performing one or more second bakes of the substrate to initiate a crosslinking reaction in the first carbon-containing material and the second carbon-containing material.

[0229] Example 13. The method of any one of Examples 11 to 12, wherein the first bake is performed at a temperature of 180°C to 200°C, and the one or more second bakes are performed at a temperature of 140°C to 150°C.

[0230] Example 14. The method of any one of Examples 11 to 13, wherein the step of etching these first openings through the layer stack includes etching out these first openings using an oxygen etching process, and the step of etching these second openings through the layer stack includes etching out these second openings using an oxygen etching process.

[0231] Example 15. The method of any one of Examples 11 to 14, wherein the fourth material includes a metal-containing material.

[0232] Example 16. A method for manufacturing a 3D NAND device includes forming a layer stack on a substrate, the layer stack consisting of multiple first layers of a first carbon-containing material and multiple second layers of a second carbon-containing material that alternate. These first layers and these second layers are deposited by spin coating. These first layers include a photoresist material or a developable anti-reflective coating, and include a reagent generating component for generating a solubility-changing reagent in response to an activation trigger. The method includes performing the activation trigger, the solubility-changing reagent being generated from the reagent generating component in these first layers in response to the activation trigger, the solubility-changing reagent modifying these first layers to be soluble in a developer. The method includes etching a plurality of channel vias through the layer stack, filling these channel vias with a third material, and etching a plurality of slits through the layer stack, the slits exposing the alternating first layers and second layers of the layer stack. The method includes removing these first layers from the layer stack by exposing these first layers to the developer, and replacing these first layers with a fourth material, the fourth material including an oxide or a nitride. The method includes removing these second layers from the layer stack by exposing these second layers to an etching chemical, and replacing these second layers with a fifth material, the fifth material being a metal-containing material.

[0233] Example 17. The method as in Example 16, wherein the reagent generating component includes a thermal acid generator, the solubility-changing reagent includes an acid, the activation trigger includes heat, performing the activation trigger is carried out before etching these first openings through the layer stack, and performing the activation trigger includes baking the substrate.

[0234] Example 18. The method as in Example 16, wherein the reagent generating component includes a photoacid generator, the solubility-changing reagent includes an acid, the activation trigger includes actinic radiation, performing the activation trigger is carried out after forming each first layer of the first carbon-containing material, such that each first layer of the first carbon-containing material is exposed to actinic radiation as the layer stack is formed, and performing the activation trigger includes exposing these first layers of the first carbon-containing material containing the reagent generating component to actinic radiation.

[0235] Example 19. The method as in Examples 16 to 18, wherein the step of removing these second layers from the layer stack by exposing these second layers to an etching chemical includes removing these second layers from the layer stack using a wet etching process.

[0236] Example 20. The method as in Examples 16 to 19, wherein the third material includes a metal oxide material, and the method includes, after replacing these second layers with the fifth material, removing the third material from these channel vias and replacing the third material with a sixth material, the sixth material including one or more of silicon dioxide, silicon nitride, and polysilicon.

[0237] It should be understood that the specific materials, etching processes, and deposition processes described herein are provided only as examples. The specific spin-on materials and combinations of multiple spin-on materials used for the layer stacks described herein are provided only as examples. Additionally, the specific content of the final layer stack described herein (where the sacrificial spin-on material is replaced by the target content of the layer stack) is provided only as examples. Additionally, the specific fill materials described herein used as intermediate sacrificial materials (e.g., as fill materials within the channel openings or open areas of the layer stack at an intermediate stage) are provided only as examples. The specific materials, deposition processes (and associated process conditions), and etching processes (and associated process conditions) can be determined based on the processing integration objectives in the semiconductor structure being formed, etching selectivity, the desired content of the layer stack (and possibly channel vias, where applicable), and other factors.

[0238] One or more deposition processes can be used to form the material layers described herein. For example, spin coating, CVD, PECVD, PVD, ALD, and / or other deposition processes can be used to implement one or more depositions. The type of deposition process used, the chemicals / gases selected for this deposition process, and the process conditions for this deposition process can be chosen to achieve the desired deposition material and the rate of the deposited material, or depending on other applicable factors.

[0239] Similarly, wet etching processes, plasma etching processes, discharge etching processes, and / or other desired etching processes can be used to implement the etching process. The type of etching process used, the chemicals / gases selected for this etching process, and the process conditions for this etching process can be chosen to achieve the desired etching rate, as well as the selectivity of the material being etched relative to the material not being etched, or according to other applicable factors.

[0240] References throughout the specification to "one embodiment", "an embodiment", "certain embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with that embodiment are included in at least one embodiment of the present disclosure, but do not mean that they are present in every embodiment. Thus, the phrases "in one embodiment", "in an embodiment", "in certain embodiments", etc. that appear throughout the specification do not necessarily refer to the same embodiment of the present disclosure. Additionally, the specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments. In other embodiments, various additional layers and / or structures can be included, and / or the features can be omitted. It should be understood that the references to "first", "second", "third", etc. in this specification do not necessarily correspond to the use of these terms in the claims, as the use in the claims may depend on the order of introduction.

[0241] As used herein, "substrate", "target substrate", "structure", or "device" generally refers to an object being processed in accordance with the present invention, and may include any material part or structure of the device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a mask, or a layer overlying or covering the base substrate structure, such as a thin film. Thus, the substrate, structure, or device is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is intended to include any such layer or base structure, as well as any combination of layers and / or base structures. This description may refer to a particular type of substrate, structure, or device, but this is for illustrative purposes only.

[0242] Systems and methods for fabricating semiconductor structures are described in various embodiments. Those skilled in the art will appreciate that the various embodiments may be implemented without one or more of the specific details, or using other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the various embodiments of the present disclosure. Similarly, specific numbers, materials, and configurations are set forth for purposes of explanation in order to provide a thorough understanding of the present disclosure. However, the present disclosure may be practiced without specific details. Additionally, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0243] Although the present disclosure describes specific processing / method steps as occurring in a particular order, the present disclosure contemplates these processing steps occurring in any suitable order. Given this specification, further modifications and alternative embodiments of the systems and methods described will be apparent to those skilled in the art. Accordingly, it will be appreciated that the systems and methods described are not limited to these illustrative arrangements. Thus, although aspects of the present disclosure are described with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive, and such modifications are intended to be included within the scope of the present disclosure. Additionally, any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not to be construed as critical, required, or essential features or elements of any or all claims.

Claims

1. A method, comprising: forming, by spin coating deposition, a layer stack on a substrate, the layer stack being composed of alternating layers of a first and a second carbon-containing material, the layers of the first carbon-containing material including reagent generating components for generating a solubility-changing reagent in response to an activation trigger; performing the activation trigger, the solubility-changing reagent being generated from the reagent generating components in the layers of the first carbon-containing material in response to the activation trigger, the solubility-changing reagent modifying the layers of the first carbon-containing material to be soluble in a developer; etching a plurality of first openings through the layer stack; filling the first openings with a third material; etching a plurality of second openings through the layer stack; removing the layers of the first carbon-containing material from the layer stack by exposing the layers of the first carbon-containing material to the developer; and replacing the layers of the first carbon-containing material with a fourth material.

2. The method according to claim 1, wherein: the reagent generating component includes a thermal acid generator; the solubility-changing reagent includes an acid; the activation trigger includes heat; and performing the activation trigger includes baking the substrate.

3. The method according to claim 2, wherein The activation trigger is performed after etching the second openings through the layer stack and before replacing the first carbon-containing material with the fourth material.

4. The method according to claim 1, wherein: the reagent generating component includes a photoacid generator; the solubility-changing reagent includes an acid; the activation trigger includes actinic radiation; and performing the activation trigger includes exposing the layers of the first carbon-containing material containing the reagent generating component to actinic radiation.

5. The method according to claim 4, wherein, The activation trigger is performed after forming each layer of the first carbon-containing material such that each layer of the first carbon-containing material is exposed to actinic radiation as the layer stack is formed.

6. The method according to claim 1, further comprising: removing the layers of the second carbon-containing material from the layer stack; and replacing the layers of the second carbon-containing material with a fifth material, wherein the fifth material is a metal-containing material.

7. The method according to claim 6, further comprising: removing the third material from the first openings; and after replacing the layers of the first carbon-containing material with the fourth material, replacing the third material with a sixth material.

8. The method according to claim 7, wherein: the third material includes a metal oxide material; and the sixth material includes one or more of silicon dioxide, silicon nitride, and polysilicon.

9. The method according to claim 1, wherein The fourth material includes: an oxide material; or a nitride material.

10. The method according to claim 1, wherein: the first carbon-containing material includes spin-on carbon (SOC), silicon oxycarbide (SiOC), organic dielectric layer (ODL), organic planarization layer (OPL), organic spin-on hard mask (SOH), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), photoresist, bottom anti-reflective coating (BARC), or developable BARC (DBARC); and the second carbon-containing material includes SOC, SiOC, ODL, OPL, organic SOH, SiOCN, SiC, photoresist, BARC, or epoxy resin.

11. A method, comprising: Form a layer stack on a substrate, which consists of multiple first layers of a first carbon-containing material and multiple second layers of a second carbon-containing material that are deposited by spin coating. These first layers contain: Photoresist material or developable antireflective coating; And A thermal acid generator (TAG); Perform a first bake on the substrate, which causes the TAG to generate acid in these first layers, and the acid modifies these first layers to be soluble in a developer; Etch multiple first openings through the layer stack; Fill these first openings with a first filling material that contains a metal oxide material; Etch multiple second openings through the layer stack; Expose these first layers to the developer to remove these first layers from the layer stack; Replace these first layers with a third material, which is an oxide or a nitride; Remove these second layers from the layer stack; Replace these second layers with a fourth material; Remove the first filling material from these first openings; And Replace the first filling material in these first openings with a second filling material that contains one or more of silicon dioxide, silicon nitride, and polysilicon.

12. The method according to claim 11, further comprising, during the formation of the layer stack, performing one or more second bakes on the substrate to initiate a crosslinking reaction in the first carbon-containing material and the second carbon-containing material.

13. The method according to claim 12, wherein: The first bake is performed at a temperature of 180°C to 200°C; and The one or more second bakes are performed at a temperature of 140°C to 150°C.

14. The method according to claim 11, wherein: Etching these first openings through the layer stack includes etching out these first openings using an oxygen etching process; And Etching these second openings through the layer stack includes etching out these second openings using an oxygen etching process.

15. The method according to claim 11, wherein, The fourth material includes a metal-containing material.

16. A method for manufacturing a three-dimensional (3D) NAND device, comprising: Form a layer stack on a substrate, which consists of multiple first layers of a first carbon-containing material and multiple second layers of a second carbon-containing material that are deposited by spin coating. These first layers contain: Photoresist material or developable antireflective coating; And A reagent generating component for generating a solubility-changing reagent in response to an activation trigger; perform the activation trigger, and the solubility-changing reagent is generated from the reagent generating component in these first layers in response to the activation trigger, and the solubility-changing reagent modifies these first layers to be soluble in a developer; Etch multiple channel vias through the layer stack; Fill these channel vias with a third material; Etch multiple slits through the layer stack, and these slits expose the alternating first and second layers of the layer stack; Remove these first layers from the layer stack by exposing these first layers to the developer; Replace these first layers with a fourth material, which is an insulating material and contains an oxide or a nitride; Remove these second layers from the layer stack by exposing these second layers to an etching chemical; And Replace these second layers with a fifth material, which is a metal-containing material.

17. The method according to claim 16, wherein: the reagent generating component comprises a thermal acid generator; the solubility changing reagent comprises an acid; the activation trigger comprises heat; the activation trigger is performed before the first openings etch through the layer stack; and performing the activation trigger comprises baking the substrate.

18. The method according to claim 16, wherein: the reagent generating component comprises a photoacid generator; the solubility changing reagent comprises an acid; the activation trigger comprises actinic radiation; the activation trigger is performed after each first layer of the first carbonaceous material is formed, such that each first layer of the first carbonaceous material is exposed to actinic radiation as the layer stack is formed; and performing the activation trigger comprises exposing the first layers containing the reagent generating component to actinic radiation.

19. The method according to claim 16, wherein, The step of removing the second layers from the layer stack by exposing the second layers to an etch chemical comprises removing the second layers from the layer stack using a wet etch process.

20. The method according to claim 16, wherein: the third material comprises a metal oxide material; and the method comprises removing the third material from the channel vias and replacing the third material with a sixth material after replacing the second layers with the fifth material, the sixth material comprising one or more of silicon dioxide, silicon nitride, and polysilicon.

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