Electrical property testing method for silicon-based product embedded with active chip / passive device

Abstract

The invention belongs to the technical field of electronics, and relates to an electrical property testing method for a silicon-based product embedded with an active chip / passive device. An adapter plate silicon through hole test, a double-sided connectivity test, an isolation characteristic test, a signal open / short circuit test and a passive device electrical parameter test are added in the production process of a silicon-based product. And the connectivity of the through silicon vias is judged through the through silicon via test of the adapter plate. The problems of bridging, breakage or poor contact of an RDL (redistribution layer) line are detected through a double-sided connectivity test. And identifying line adhesion or isolating layer defects caused by process deviation through an isolating characteristic test. Whether the signal pins are open-circuited or short-circuited is judged through a signal open-short circuit test. And screening out passive device performance degradation products caused by the embedding process through a passive device electrical parameter test. According to the invention, the whole-process test of the silicon-based product can be realized, the process problem can be found in time, the yield is obviously improved, the product reliability is ensured, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a method for testing the electrical characteristics of a silicon-based product with buried active chips / passive devices. Background Art

[0002] By burying active chips or passive components into an interposer, higher integration can be achieved to form a systematic functional product. However, the process of burying products has high process difficulty, low production efficiency, and low yield.

[0003] During the process of burying active chips / passive devices in a silicon-based interposer, short-circuit faults such as open connections, RDL line bridging, and isolation layer rupture often occur. Therefore, during the production process of buried products, electrical performance testing is one of the basic tests.

[0004] Currently, the testing of buried products is still one of the key problems in production. The industry generally chooses to design a dedicated probe card after the production of the product and use a fully automatic testing device to perform DC parameter and function testing, that is, ATE testing. Although ATE testing can complete the electrical testing of the product, the line coverage rate is incomplete and process monitoring cannot be carried out. For stacked buried products, a single-layer product usually contains passing power supplies and signals, and the double-sided connectivity of the wafer needs to be tested, while ATE testing cannot monitor it.

[0005] In summary, when using ATE testing to perform electrical testing on buried products, there are problems that process monitoring and double-sided connectivity monitoring of the wafer cannot be carried out. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for testing the electrical characteristics of a silicon-based product with buried active chips / passive devices to solve the technical problems that process monitoring and double-sided connectivity monitoring of the silicon-based product cannot be carried out.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a method for testing the electrical characteristics of a silicon-based product with buried active chips / passive devices, including the following steps: Through-silicon via (TSV) testing of the interposer: Apply a current at both ends of the TSV in the silicon interposer through a flying probe test system and monitor the voltage, calculate the resistance value according to the current and voltage, and judge the connectivity of the TSV according to the resistance value; Double-sided connectivity testing: After burying an active chip in the silicon interposer, apply a current between the measurement points on the front and back of the silicon interposer through a flying probe test system and monitor the voltage, calculate the resistance value according to the current and voltage, and judge the connectivity of the redistribution layer according to the resistance value; Isolation characteristic test: Apply a voltage drop between different circuits of the buried chip using a flying probe test system and monitor the leakage current. Calculate the resistance value based on the leakage current. When the resistance value is lower than the design threshold, it is determined as a short - circuit failure; Signal open - short test: Detect the diode voltage drop between the signal pin and the power supply, and between the signal pin and the ground through a flying probe test system. If the voltage drop is within the threshold range, it is determined as normal; if it is less than the threshold range, it is determined as a short - circuit; if it is greater than the threshold range, it is determined as an open - circuit; Electrical parameter test of passive devices: Test the resistance, capacitance, and inductance parameters of the buried integrated passive devices, and compare the test results with the design standard values. When the deviation exceeds the allowable range, it is determined as an open - / short - circuit failure.

[0008] Furthermore, judging the connectivity of the through - silicon via according to the resistance value is as follows: When the resistance value is less than or equal to the resistance threshold of the through - silicon via, the connectivity performance of the through - silicon via does not meet the requirements.

[0009] Furthermore, the resistance threshold of the through - silicon via is 3Ω.

[0010] Furthermore, judging the connectivity of the redistribution layer according to the resistance value is as follows: When the resistance value is less than or equal to 5Ω, the connectivity is determined to be good; when it is greater than 5Ω, it is determined as an open - circuit.

[0011] Furthermore, apply a current between the measurement points on the front and back of the silicon interposer and monitor the voltage. Set a clamping voltage during the test process, and the clamping voltage is the minimum voltage that the buried chip can withstand.

[0012] Furthermore, the isolation characteristic test further includes: Conduct isolation characteristic tests between power supply and ground, power supply and signal, and signal and signal respectively through a flying probe test system, and add isolation characteristic tests for bypass power supply and bypass signal for multi - layer stacked products.

[0013] Furthermore, the isolation characteristic test further includes: Set a differentiated design threshold according to the chip type.

[0014] Furthermore, the design threshold is greater than 10KΩ.

[0015] Furthermore, the threshold range is 0.1V - 0.9V. If the voltage drop is within 0.1V - 0.9V, it is determined as normal; if it is less than 0.1V, it is determined as a short - circuit; if it is greater than 0.9V, it is determined as an open - circuit.

[0016] Furthermore, the electrical characteristic test method further includes the following steps: After the through-silicon vias are fabricated and the front-side redistribution layer process is patterned, a measurement point path is generated by parsing with circuit layout software, and wafer-level open and short pre-screening is performed using a double-sided flying probe test system. After the active chips / passive devices are embedded, the measurement point attributes and test programs are defined in combination with layout software.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. During the production process of silicon-based products, the present invention adds through-silicon via testing, double-sided connectivity testing, isolation characteristic testing, signal open / short testing, and passive device electrical parameter testing for the interposer. The connectivity of the through-silicon vias is judged through the through-silicon via testing for the interposer. The bridging, breakage, or poor contact problems of the RDL (redistribution layer) lines are detected through the double-sided connectivity testing. The line adhesion or isolation layer defects caused by process deviations are identified through the isolation characteristic testing. Whether the signal pins are open or short is judged through the signal open / short testing. The products with deteriorated passive device performance caused by the embedding process are screened out through the passive device electrical parameter testing. The present invention can realize the full-process process monitoring of the electrical characteristics of silicon-based products, covering the full-process testing after TSV fabrication, RDL wiring, chip embedding, and packaging, realize real-time defect location during the manufacturing process, is beneficial to timely discovering process problems and improving process parameters, significantly improving the yield, ensuring product reliability, and improving production efficiency.

[0018] 2. By setting the resistance threshold of the through-silicon vias, the present invention standardizes the judgment criterion for the conduction performance of the through-silicon vias, which is beneficial to the accurate judgment of the conduction performance of the through-silicon vias.

[0019] 3. The present invention applies a current between the measurement points on the front and back sides of the silicon interposer and monitors the voltage. A clamping voltage is set during the test, and the clamping voltage is the minimum voltage that the embedded chip can withstand, preventing the test current / voltage from overloading and damaging the chip.

[0020] 4. By expanding the isolation test range to power-ground, power-signal, signal-signal, and the passing power / signals of stacked products, covering all potential short-circuit paths, the present invention is beneficial to ensuring product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flowchart of the method of the present invention; Figure 2 is a schematic diagram of the adhesion failure of the metal lines of the silicon interposer embedded product; Figure 3 is a process diagram of the silicon interposer embedded product; Figure 4 is a schematic diagram of the finished product module of the silicon interposer embedded product; Figure 5 is an example diagram of the circuit layout software for editing measurement points and resolution; Figure 6 Schematic diagram for testing the electrical impedance of the battery and the voltage drop of the diode by a typesetting software; Figure 7 Schematic diagram for editing the electrical characteristic test program of passive devices by a typesetting software; Figure 8 Schematic diagram for typesetting and marking alignment by a typesetting software; Figure 9 Schematic diagram of the electrical test results of an 8-inch wafer of a buried silicon interposer. Specific implementation manners

[0022] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings: Refer to Figure 1 , the present invention discloses a method for testing the electrical characteristics of a silicon-based product with buried active chips / passive devices, including the following steps: S1, Through-Silicon Via (TSV) test of the interposer: By using a flying probe test system, apply current at both ends of the TSV of the silicon interposer and monitor the voltage, calculate the resistance value according to the current and voltage, and judge the connectivity of the TSV according to the resistance value. The conduction state of the TSV can be accurately detected. The TSV test is a key link in 3D packaging, and its connectivity directly affects the signal transmission efficiency and power consumption of stacked chips; S2, Dual-sided Connectivity Test: After embedding active chips in the silicon interposer, an electric current is applied between the measurement points on the front and back sides of the silicon interposer through a flying probe test system, and the voltage is monitored. The resistance value is calculated based on the current and voltage, and the connectivity of the redistribution layer is judged according to the resistance value, which is used to detect problems such as bridging, breakage, or poor contact of the RDL (redistribution layer) lines; S3, Isolation Characteristic Test: A voltage drop is applied between different lines of the embedded chips by using a flying probe test system, and the leakage current is monitored. The resistance value is calculated based on the leakage current. When the resistance value is lower than the design threshold, it is determined as a short-circuit failure. This step can effectively identify line adhesion or isolation layer defects caused by process deviations. See Figure 2 for a schematic diagram of the line adhesion failure of the silicon interposer embedded product.

[0025] S4, Signal Open / Short Test: The diode voltage drop between the signal pin and the power supply and between the signal pin and the ground is detected through a flying probe test system. If the voltage drop is within the threshold range, it is judged as normal; if it is less than the threshold range, it is judged as a short circuit; if it is greater than the threshold range, it is judged as an open circuit; S5, Electrical Parameter Test of Passive Devices: The resistance, capacitance, and inductance parameters of the embedded integrated passive devices are tested, and the test results are compared with the design standard values. When the deviation exceeds the allowable range, it is judged as an open / short circuit failure. This step can screen out products with deteriorated performance of passive devices caused by the embedding process.

[0026] The present invention can realize the full-process process monitoring of the electrical characteristics of silicon-based products, covering the full-process tests after TSV preparation, RDL wiring, chip embedding, and packaging, realize real-time defect location in the manufacturing process, significantly improve the yield, and ensure product reliability. Through the flexible probe configuration of the flying probe system, it is compatible with different product designs, avoiding the high cost and long cycle of traditional ATE probe card customization.

[0027] Embodiment 1: See Figure 1 , this embodiment discloses a method for testing the electrical characteristics of a silicon-based product embedded with active chips / passive devices, including the following steps: S1, Through-Silicon Via Test of the Interposer: An electric current is applied between both ends of the through-silicon vias of the silicon interposer through a flying probe test system, and the voltage is monitored. The resistance value is calculated based on the current and voltage, and the connectivity of the through-silicon vias is judged according to the resistance value, which can accurately detect the conduction state of the TSV (through-silicon via). The TSV test is a key link in 3D packaging, and its connectivity directly affects the signal transmission efficiency and power consumption of stacked chips; Preferably, judging the connectivity of the through-silicon vias according to the resistance value is specifically as follows: When the resistance value is less than or equal to the resistance threshold of the through-silicon via, the connectivity performance of the through-silicon via does not meet the requirements.

[0028] Preferably, the resistance threshold of the through-silicon via is 3 Ω. Setting the TSV resistance threshold to 3 Ω standardizes the determination criterion for TSV conduction performance.

[0029] S2. Double-sided connectivity test: After embedding the active chip in the silicon interposer, apply current between the measurement points on the front and back of the silicon interposer through a flying probe test system and monitor the voltage. Calculate the resistance based on the current and voltage, and judge the connectivity of the redistribution layer according to the resistance to detect problems such as bridging, breakage, or poor contact of the RDL (redistribution layer) lines; Preferably, the judgment of the connectivity of the redistribution layer according to the resistance is as follows: When the resistance is less than or equal to 5 Ω, it is judged that the connectivity is good; when it is greater than 5 Ω, it is judged as an open circuit.

[0030] Preferably, when applying current between the measurement points on the front and back of the silicon interposer and monitoring the voltage, a clamping voltage is set during the test process. The clamping voltage is the minimum voltage that the embedded chip can withstand to prevent damage to the chip due to overloaded test current / voltage.

[0031] S3. Isolation characteristic test: Apply a voltage drop between different lines of the embedded chip using a flying probe test system and monitor the leakage current. Calculate the resistance based on the leakage current. When the resistance is lower than the design threshold, it is judged as a short-circuit failure. This step can effectively identify line adhesion or isolation layer defects caused by process deviations. See Figure 2 .

[0032] Preferably, the isolation characteristic test further includes: Perform isolation characteristic tests between power supply and ground, power supply and signal, and signal and signal respectively through a flying probe test system, and add isolation characteristic tests for passing power supply and passing signal for multi-layer stacked products. By expanding the isolation test range to power supply - ground, power supply - signal, signal - signal, and passing power supply / signal of stacked products to cover all potential short-circuit paths, it is beneficial to ensure product reliability.

[0033] Preferably, the isolation characteristic test further includes: Set a differentiated design threshold according to the chip type. The customized threshold can improve the test accuracy.

[0034] The design threshold is greater than 10 KΩ, that is, 10 KΩ is the minimum design threshold.

[0035] S4. Signal open / short test: Detect the diode voltage drop between the signal pin and the power supply and between the signal pin and the ground through a flying probe test system. If the voltage drop is within the threshold range, it is judged as normal; if it is less than the threshold range, it is judged as a short circuit; if it is greater than the threshold range, it is judged as an open circuit; Preferably, the threshold range is 0.1V to 0.9V. If the voltage drop is within 0.1V to 0.9V, it is determined to be normal; if it is less than 0.1V, it is determined to be short-circuited; if it is greater than 0.9V, it is determined to be open-circuited.

[0036] S5. Electrical parameter testing of passive devices: Test the resistance, capacitance, and inductance parameters of the buried integrated passive devices, compare the test results with the design standard values, and determine open / short-circuit failure when the deviation exceeds the allowable range. This step can screen out the performance degradation of passive devices caused by the embedding process.

[0037] Preferably, the electrical characteristic testing method further includes the following steps: After the through-silicon via preparation is completed and the front-side redistribution layer process is patterned, generate a measurement point path through circuit layout software parsing, and use a double-sided flying probe test system for wafer-level open-circuit and short-circuit pre-screening; After burying the active chip / passive device, define the measurement point attributes and test procedures in combination with layout software.

[0038] The present invention can realize the full-process process monitoring of the electrical characteristics of silicon-based products, covering the full-process testing after TSV preparation, RDL wiring, chip embedding, and packaging, realize real-time defect location in the manufacturing process, significantly improve the yield, and ensure product reliability.

[0039] Example 2: See Figure 1 This embodiment discloses a method for testing the electrical characteristics of a silicon-based product with buried active chips / passive devices. See Figure 3 for the preparation process diagram of the silicon interposer buried product, Figure 4 and for the schematic diagram of the finished product module of the silicon interposer buried product. The process of the silicon interposer buried product is: TSV preparation, front-side patterning (RDL1, RDL2), back-side bottom window opening, back-side burying of active chips / passive devices, back-side patterning (B-RDL1, B-RDL2, according to the design).

[0040] During the preparation process of the silicon interposer buried product, the electrical characteristics to be tested include: Double-sided Connectivity Test of Silicon Interposer Embedded Products: The front and back sides of the silicon interposer are mainly connected through TSV (Through-Silicon Via). The test structures are divided into a structure with direct up-and-down conduction through TSV and a structure with RDL lines connected on one side. The specific test method is based on a double-sided flying probe test system. The upper and lower flying probes simultaneously contact two measurement points on the front and back sides of the same line, apply current and measure voltage, display the resistance value, and judge the connectivity based on the resistance value. For example, in a typical structure, when testing the connectivity of the front and back sides of a certain line, a current with no fixed direction is applied between two measurement points of the line through two flying probes, and the voltage value between these two points is monitored simultaneously. According to Ohm's law, the resistance value between the two measurement points can be obtained. The smaller the resistance value, the better the connectivity is considered. The connectivity of the front and back sides of all lines of the silicon-based embedded product is tested in turn. For the open circuit test, a clamping voltage needs to be set. The clamping voltage is usually the minimum voltage acceptable to the embedded chip to protect the product. Generally, when there is no special design, if the resistance value is less than 5Ω, the double-sided interconnection performance of the interposer is considered good, and if it is greater than 5Ω, it is an open circuit. Isolation Characteristic Test between Different Lines of the Chip: When an active chip is embedded in the silicon interposer, it is necessary to judge whether there are abnormalities such as line adhesion in the chip pins after the embedding process. See Attachment Figure 2 , which may cause a short circuit between different lines. This is mainly carried out by the method of applying voltage and measuring current. Specifically, through the flying probe test system, two flying probes are controlled to simultaneously contact a measurement point of Line 1 and a measurement point of Line 2. A certain voltage drop is applied between the two measurement points, and the leakage current between the two flying probes is monitored. According to Ohm's law, the resistance value between the two measurement points can be obtained, which can be equivalent to the isolation resistance value between Line 1 and Line 2. Generally, the larger the resistance value, the better the isolation. If the resistance value is less than the designed value, abnormal failures such as line adhesion may have occurred. All the lines of the product are tested in turn, and flying probe tests are carried out pairwise to monitor the isolation characteristics. According to the type of the chip and the device manual, the judgment basis can be set. Different product types have different isolation test items. For example, when embedding a DDR3 chip memory chip, the isolation characteristic test between different lines can be detailedly divided into the isolation test between the power ground and the short circuit test between different power supplies and different signals. The difference in the resistance value judgment of different test items is also relatively large.

[0041] Open - short circuit test of signals: According to the characteristics that the signal pins of the chip have protection diodes for the power supply and reverse protection diodes for the ground, the open - short circuit test can be carried out by using the lead - out measurement points of the chip signal pins. The designed value of the diode voltage drop is generally between 0.1V and 0.9V. By testing the diode voltage drop, it can be judged whether there is an open circuit or a short circuit when the chip signal pins are led out to the front and back of the adapter board, so as to judge whether the I / O fan - out is intact. Specifically, when testing the diode voltage drop between the signal - power pins, use the flying - probe test system. Set a flying probe to contact the measurement point where the signal is led out (usually the position of the farthest lead - out end), and at the same time, another flying probe contacts the lead - out measurement point of the power supply, apply a current flowing from the signal to the power supply, and monitor the voltage drop between the two measurement points. If the voltage drop value is between 0.1V and 0.9V, the signal pins and power pins of the buried chip are normally led out; if it is less than 0.1V, it is considered that there is a short - circuit failure between the signal and power lines; if it is greater than 0.9V, it is considered that the connection line between the measurement point of the signal or power supply and the chip is open - circuited. Similarly, when testing the diode voltage drop between the signal - ground pins, through the flying - probe test system, set a flying probe to contact the measurement point where the signal is led out, and at the same time, another measurement point contacts the lead - out measurement point of the ground, apply a current flowing from the ground to the signal, and monitor the voltage drop between the two measurement points. If the voltage drop value is between 0.1V and 0.9V, the signal and ground pins of the buried chip are correctly led out; if it is less than 0.1V, it is considered that there is a short - circuit failure between the signal and ground lines; if it is greater than 0.9V, it is considered that there is no connection between the signal or ground line and the chip pin, and the connected line is open - circuited. According to this test method, sequentially test the diode voltage drops of all the signal pins of the chip with respect to the power supply and the ground to conduct the open - short circuit test of the signals; When burying passive devices in the silicon adapter board, such as IPD (Integrated Passive Devices), after burying, by testing the electrical parameters of the IPD itself, such as resistance, capacitance and other characteristic values, at the lead - out points of the adapter board, products with abnormal electrical characteristics can be screened out. For example, when testing the standard resistance of the buried IPD, use the flying probe to simultaneously contact the lead - out points at both ends of the standard resistance on the adapter board, apply a current between the two measurement points, measure the resistance value, and compare it with the designed standard value. If it is less than the standard value, it indicates a short circuit; if it is equal to the standard value, it is considered that the line connection is normal; if it is greater than the standard value, the line is open - circuited. Sequentially test all the resistors, capacitors or inductors and other passive devices of the chip to check whether there is an open - short circuit in the IPD chip network. In addition, similar to burying active chips, in addition to testing the electrical characteristics of the passive devices themselves, it is also necessary to test the isolation characteristics between all different lines to obtain a silicon - based buried product with good performance.

[0042] Example Three: In order to be able to test the electrical characteristics of the silicon interposer embedded products, so that the products embedded with active chips / passive devices can achieve the monitoring of the basic electrical performance during the production process, through flying probe contact testing, accurately and completely judge the electrical characteristics of the products, guide the process production, improve the production efficiency and reduce the production cost.

[0043] See Figure 1 , this embodiment provides a method for using a flying probe test system to test the electrical characteristics of products with active chips / passive devices embedded in a silicon interposer. The electrical characteristics include the interconnection characteristics of the silicon interposer itself and the electrical characteristics of the embedded chips and passive devices, including: Open / short circuit characteristics of the silicon interposer: The production process of the embedded products mainly includes the production of the RDL lines on the front side of the interposer, backside grooving, chip embedding, and the production of the RDL lines on the backside. First, it is necessary to monitor the production process on the front side of the interposer, that is, the open / short circuit test of the interposer lines. This testing technology at the wafer level is basically mature. Usually, the flying probe testing technology is used. In the circuit editing software, the layout file of the product is imported. According to the imported file, the line information such as the test surface and test points of the product is defined in the software. After adjusting the resolution for identifying different line definitions of the product and generating a layout path consistent with the actual product, the test file of a single product is exported. The generated test files are typeset to generate the test files of multiple products at the wafer level. Thus, a flying probe test system can be used to screen out the interposers with good performance for subsequent processes.

[0044] Double-sided connectivity and open / short circuit test of the wafer after chip embedding: After embedding the active chips and passive devices, first, the connectivity and open / short circuit test of the embedded interposer are carried out in the same way as the test method for the open / short circuit characteristics of the silicon interposer. When using the double-sided flying probe testing technology of the silicon interposer, it should be particularly noted that when setting the test points, the lead-out positions connected to the pins of the embedded chips must be screened out according to the test information of the product to prevent the embedded chips and devices from being damaged during the machine testing.

[0045] Electrical performance test of the chips: After the embedding process, it is necessary to test the electrical performance of the embedded products, which is an important part of the present invention. The lines of the chips are mainly divided into three categories, including signals, power supply, and ground. According to the electrical performance of the chips, the test is mainly divided into three parts: The first test part is the electrical ground short - circuit test of the buried chip and the reverse diode performance test of the signal pins: The essence of the first - part test is the short - circuit test between power supply and ground, and between signal and ground. Different from the test of the passive adapter board, when using circuit layout software to edit and add test points, according to the design information of the product, all the power supplies, signals and grounds of the chip need to be marked as test points. After setting the resolution, the test file is exported. Then, using typesetting software to further design the test file, defining the attributes of the marked test points, test items, excitation direction and judgment criteria, setting the excitation current and direction that the chip can accept for testing. Use the resistance range to conduct the electrical ground short - circuit test, measure the resistance value between the power supply and the ground, and compare it with the designed impedance. If it is less than the set value, it is judged that a short - circuit failure has occurred; use the voltage range to conduct the voltage drop test of the protection diode of the signal pin to judge the open - short of the chip signal pin (the specific test method was introduced earlier).

[0046] The second test part is the short - circuit test between different circuits of the buried chip, that is, the isolation characteristic test: The essence of the second - part test content is the short - circuit test between power supply and signal, between power supply and power supply, and between signal and signal. Because the test of the active chip must pay attention to the excitation direction and excitation magnitude, so when testing, the active chip needs to be fully protected. For a single - layer wafer, the short - circuit test of all the signal and power pins of the active chip itself needs to be carried out. During the test, all test points are added, and the flying probe is used to randomly contact two by two at the same time. A certain voltage drop is applied between the two test points, and the magnitude of the leakage current is measured and compared with the designed value to judge whether a short - circuit failure has occurred during the process of burying and leading out the chip.

[0047] It should be noted that for the buried adapter substrate used for subsequent multi - layer stacking, there will be passing signals and passing power supplies involved. For the wafer - level single - layer test of this type of buried adapter board, in addition to the short - circuit test of the signal and power pins of the active chip itself, the short - circuit test of the passing signals and passing power supplies also needs to be carried out. The specific test method is carried out according to the test method of the silicon adapter board, and all the leading - out test points need to be covered.

[0048] The third test part is the open - short test of the buried passive devices: According to the design of the product, after completing the double - sided connectivity test of the product and the short - circuit test between different circuits, the electrical characteristics of the buried components need to be tested. For example, for the resistance performance test, after editing the test point and circuit information, use the flying probe test resistance range to test the resistance characteristics. Similarly, the voltage and capacitance and other characteristics can be tested using the voltage range and capacitance range of the flying probe test system.

[0049] After the above tests are completed, all electrical tests of the embedded chip / passive device products in the adapter board have been fully covered, realizing the monitoring of abnormal problems such as open circuits and short circuits of the products. The test method of the present invention realizes the real-time monitoring of the process of the embedded chip / passive device products in the adapter board, which is beneficial to timely discovering process problems and improving process parameters. The products passing the tests can ensure good electrical performance. Then, the products with good electrical performance are further subjected to functional tests, avoiding a large number of functional tests and reducing the test cost of the products.

[0050] Embodiment 4: See Figure 1 is the method flow chart of the present invention.

[0051] As Figure 1 shown, after the TSV is fabricated, RDL (Redistribution Layer process) is performed on the front side of the silicon adapter board. Generally, multiple-layer front-side redistribution layer processes can be carried out according to the product design. After each redistribution layer, the open / short circuit test of the adapter board must be performed. As Figure 5 shown, according to the test file provided by the design, using circuit layout software, the lines and test points can be automatically identified. After all the settings are completed, it is converted into a test file in IPD format. As Figure 8 shown, after further editing and typesetting using typesetting software, an automatic test can be realized with a double-sided flying probe tester to monitor each redistribution layer process and timely discover process problems.

[0052] After the active chips are embedded in the silicon adapter board, 3 programs are set using circuit layout software according to the nature of different test points for testing. Figure 6 is a picture of different test files of the typesetting software. The first program can test the connectivity of both sides of the silicon adapter board, the electrical insulation between the test points led out by the active chips and the ground, and the reverse diode characteristics of the signal pins. Generally, it is considered that the silicon adapter board with a TSV test resistance below 3Ω meets the connectivity requirements; if there are no special requirements, the resistance between different lines should generally be higher than 10KΩ; the isolation characteristics between the power supply and the ground of the active chips have different resistances according to different product designs. The second program is responsible for performing the short circuit test between the power supply pins and the signal pins of the chips. Since the isolation resistances of different chips are different, the criteria need to be formulated according to the product design; the third program performs the isolation characteristic test between the passing power supply, signal and ground of the three types of lines to judge whether there are short circuit problems in the products for stacking. Through these 3 types of tests, the process monitoring of the products with active chips embedded in the silicon adapter board can be realized, facilitating the adjustment of process parameters and being able to completely test the electrical performance of the products to obtain products with good performance.

[0053] After the passive devices are embedded in the silicon adapter board, as Figure 7As shown, different test files are typeset, and the pads led out from the passive devices are used as the measurement points to test the electrical characteristics of the passive devices, so as to judge the open / short circuit information of the products after the passive devices are buried. Figure 7 This is a schematic diagram of the IPD test file edited by the typesetting software provided by the embodiment of the present invention, using resistance, voltage and capacitance to test the electrical characteristics of passive devices. After completing the test procedure for a single chip, further typesetting is carried out. Figure 8 This is a schematic diagram of the wafer typesetting edited. Thus, the electrical characteristics of all the chips on the whole wafer can be measured. Figure 9 This is the electrical test result of the embodiment of the present invention.

[0054] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A method for testing the electrical characteristics of a silicon-based product embedding an active chip / passive device, characterized in that, Including the following steps: Through-silicon via (TSV) test of the interposer: By using a flying probe test system, apply current at both ends of the TSV in the silicon interposer and monitor the voltage, calculate the resistance value based on the current and voltage, and judge the connectivity of the TSV according to the resistance value; Double-sided connectivity test: After burying active chips in the silicon interposer, by using a flying probe test system, apply current between the measurement points on the front and back of the silicon interposer and monitor the voltage, calculate the resistance value based on the current and voltage, and judge the connectivity of the redistribution layer according to the resistance value; Isolation characteristic test: Use a flying probe test system to apply a voltage drop between different circuits of the buried chips and monitor the leakage current, calculate the resistance value based on the leakage current, and determine it as a short-circuit failure when the resistance value is lower than the design threshold; Signal open / short test: Detect the diode voltage drop between the signal pin and the power supply and between the signal pin and the ground through a flying probe test system. If the voltage drop is within the threshold range, it is judged as normal; if it is less than the threshold range, it is judged as a short circuit; if it is greater than the threshold range, it is judged as an open circuit; Electrical parameter test of passive devices: Test the resistance, capacitance, and inductance parameters of the buried integrated passive devices, compare the test results with the design standard values, and determine it as an open / short circuit failure when the deviation exceeds the allowable range.

2. The electrical characteristic test method for the silicon-based product with buried active chips / passive devices according to claim 1, characterized in that The judgment of the connectivity of the TSV according to the resistance value is specifically as follows: When the resistance value is less than or equal to the resistance threshold of the TSV, the connectivity performance of the TSV does not meet the requirements.

3. The electrical property testing method for the silicon-based product embedding active chips / passive devices according to claim 2, characterized in that, The resistance threshold of the TSV is 3Ω.

4. The electrical property testing method for a silicon-based product embedding an active chip / passive device according to claim 1, characterized in that, The judgment of the connectivity of the redistribution layer according to the resistance value is specifically as follows: When the resistance value is less than or equal to 5Ω, it is judged that the connectivity is good; when it is greater than 5Ω, it is judged as an open circuit.

5. The electrical property testing method of the silicon-based product with buried active chips / passive devices according to claim 1, wherein Apply current between the measurement points on the front and back of the silicon interposer and monitor the voltage. Set the clamping voltage during the test process, and the clamping voltage is the minimum voltage that the buried chips can withstand.

6. The electrical property testing method for the silicon-based product with buried active chips / passive devices according to claim 1, wherein The isolation characteristic test further includes: Conduct isolation characteristic tests between power supply and ground, power supply and signal, and signal and signal respectively through a flying probe test system, and add isolation characteristic tests for bypass power supply and bypass signal for multi-layer stacked products.

7. The electrical property testing method of the silicon-based product with embedded active chips / passive devices according to claim 1, characterized in that, The isolation characteristic test further includes: Set different design thresholds according to the chip type.

8. The electrical property testing method of the silicon-based product with embedded active chips / passive devices according to claim 7, characterized in that, The design threshold is greater than 10KΩ.

9. The electrical property testing method of the silicon-based product with embedded active chips / passive devices according to claim 1, characterized in that The threshold range is 0.1V to 0.9V. If the voltage drop is within 0.1V to 0.9V, it is judged as normal; if it is less than 0.1V, it is judged as a short circuit; if it is greater than 0.9V, it is judged as an open circuit.

10. The electrical property testing method of the silicon-based product with embedded active chips / passive devices according to claim 1, characterized in that, The electrical characteristic test method further includes the following steps: After the TSV is fabricated and the front-side redistribution process is patterned, generate the measurement point path through circuit layout software analysis, and use a double-sided flying probe test system for wafer-level open and short pre-screening; After burying active chips / passive devices, define the measurement point attributes and test procedures in combination with layout software.

Images