Damage detection circuit, method and device for chip

Abstract

The invention discloses a damage detection circuit, method and device for a chip, which are used for realizing online real-time detection and judging a damage position. According to the circuit part, n equivalent detection resistors are arranged between a substrate of a chip damage detection area and a polycrystalline silicon layer, n is larger than or equal to 2, and the damage detection circuit comprises a power supply unit, a switch unit and a voltage detection unit; wherein one end of the first equivalent detection resistor is connected with the ground end, one end of the nth equivalent detection resistor is connected with one end of the switch unit, and the other end of the switch unit is connected with the power supply end of the power supply unit; the resistors between the first equivalent detection resistor and the nth equivalent detection resistor are sequentially connected in series, and the detection end of the voltage detection unit is connected between any two adjacent equivalent detection resistors in the n equivalent detection resistors.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and in particular, to a damage detection circuit, method, and device for a chip. Background Art

[0002] Semiconductor chips have application forms such as bare Dies and packaged chips. During the process of making a bare Die into a module or packaging, there are influences such as contact pressure in the process, which may cause damage to the chip, affect the chip performance or function, and even some minor damages may lead to the risk of early failure of the chip during subsequent use.

[0003] Currently, there is no relevant solution for directly online testing the damage of chips. General chip online testing can only indirectly test the electrical characteristics of chips, such as chip current leakage (leakage), while the offline testing method requires the use of external equipment to detect damage, such as scanning electron microscopes, atomic force microscopes, infrared thermal imaging, electron beam lithography (E-beam lithography), etc. The methods using equipment are all offline measurements and cannot provide real-time feedback on chip damage.

[0004] It can be seen that the existing solutions currently cannot achieve online real-time testing of chips, and there may be damaged products flowing out, with the risk of early failure later. Moreover, for damaged chips, the location of the damage cannot be determined. Summary of the Invention

[0005] The present invention provides a damage detection circuit, method, and device for a chip, which are used to achieve online real-time detection and determine the location of damage.

[0006] A damage detection circuit for a chip, where there are n equivalent detection resistors between the substrate and the polysilicon layer in the chip damage detection area, n≥2. The damage detection circuit includes a power supply unit, a switch unit, and a voltage detection unit; Wherein, one end of the first equivalent detection resistor is connected to the ground terminal, one end of the nth equivalent detection resistor is connected to one end of the switch unit, and the other end of the switch unit is connected to the power supply terminal of the power supply unit; the resistors between the first equivalent detection resistor and the nth equivalent detection resistor are connected in series in sequence, and the detection terminal of the voltage detection unit is connected between any two adjacent equivalent detection resistors among the n equivalent detection resistors.

[0007] In one implementation, the n equivalent detection resistors include n substrate resistors.

[0008] In one implementation, the n equivalent detection resistors include n polysilicon layer resistors.

[0009] In one implementation, the n equivalent detection resistors include j substrate resistors and j polysilicon layer resistors, where j≥1.

[0010] In one implementation, the chip damage detection regions are distributed around the periphery of the chip.

[0011] In one implementation, the chip damage detection regions include a plurality of segmented damage detection regions located around the periphery of the chip and separated from each other.

[0012] In one implementation, the chip damage detection regions are distributed on any one side of the chip, or the chip damage detection regions are distributed on all sides of the chip.

[0013] In one implementation, the power supply unit is the internal power supply unit of the chip, and the voltage detection unit is the internal analog-to-digital conversion unit of the chip.

[0014] A damage detection method based on the damage detection circuit according to any one of the foregoing items, the method comprising: When triggering the chip damage detection in the first test stage, closing the switch unit; Comparing the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection region.

[0015] In one implementation, the designed voltage value includes a minimum designed voltage value and a maximum designed voltage value. The comparing the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection region includes: Judging whether the first test voltage value detected by the voltage detection unit satisfies the condition that the minimum designed voltage value ≤ the first test voltage value ≤ the maximum designed voltage value; When not satisfied, it is judged that there is damage in the chip damage detection region.

[0016] In one implementation, after judging whether the first test voltage value detected by the voltage detection unit satisfies the condition that the minimum designed voltage value ≤ the first test voltage value ≤ the maximum designed voltage value, the method further includes: When satisfied, storing the first test voltage value as a test storage value in the electronic fuse Efuse or the one-time programmable memory OTP of the chip; When triggering the test in the second test stage, comparing the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether there is damage in the chip damage detection region.

[0017] In one implementation, comparing the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether there is damage in the chip damage detection area includes: Determining whether the second test voltage value detected by the voltage detection unit satisfies the minimum test storage value stored in the Efuse or OTP ≤ the second test voltage value ≤ the maximum test storage value stored in the Efuse or OTP; When not satisfied, it is determined that there is damage in the chip damage detection area; When satisfied, it is determined that there is no damage in the chip damage detection area.

[0018] In one implementation, the first test stage is the chip package CP test stage, and the second test stage is the back-end test stage of the CP test stage.

[0019] In one implementation, the method further includes: When chip damage detection is not triggered, turning off the switch unit.

[0020] A damage detection device based on the damage detection circuit described in any one of the foregoing, the device includes: A control module, configured to close the switch unit when chip damage detection is triggered; A determination module, configured to compare the first test voltage value detected by the voltage detection unit with a design voltage value to determine whether there is damage in the chip damage detection area.

[0021] It can be seen that the present application provides a damage detection solution for a chip, including providing a specific damage detection topology for the chip. The circuit implementation is very simple, and the resistance design of the substrate and polysilicon layer, as well as the power supply unit VDD, are ingeniously applied. The voltage detection unit ADC can realize chip damage detection without relying on additional external devices such as a scanning electron microscope, and basically does not increase additional costs; the power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss; it can realize on-line damage testing, timely detect damaged abnormal products, effectively intercept damaged chips, and prevent them from flowing out; at the same time, it can also locate the damaged area in real time on-line, reducing the workload of subsequent analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 It is a top - view structural schematic diagram of a chip in an embodiment of the present invention; Figure 2 It is a side - view structural schematic diagram of a chip in an embodiment of the present invention; Figure 3 It is a circuit - structure schematic diagram of a damage - detection circuit for a chip in an embodiment of the present invention; Figure 4 It is a schematic diagram of one of the corresponding relationships between a damage - detection circuit for a chip and a chip damage - detection area in an embodiment of the present invention; Figure 5 It is a first - example structural schematic diagram of a damage - detection circuit for a chip in an embodiment of the present invention; Figure 6 It is a second - example structural schematic diagram of a damage - detection circuit for a chip in an embodiment of the present invention; Figure 7 It is a third - example structural schematic diagram of a damage - detection circuit for a chip in an embodiment of the present invention; Figure 8 It is a second - distribution schematic diagram of a chip damage - detection area in an embodiment of the present invention; Figure 9 It is a third - distribution schematic diagram of a chip damage - detection area in an embodiment of the present invention; Figure 10 It is a fourth - distribution schematic diagram of a chip damage - detection area in an embodiment of the present invention; Figure 11 It is a fifth - distribution schematic diagram of a chip damage - detection area in an embodiment of the present invention; Figure 12 It is a sixth - distribution schematic diagram of a chip damage - detection area in an embodiment of the present invention; Figure 13 It is a flowchart schematic diagram of a damage - detection method in an embodiment of the present invention; Figure 14 It is another flowchart schematic diagram of a damage - detection method in an embodiment of the present invention. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be understood that the existing solutions cannot achieve on-line real-time testing of chips, which may result in defective products flowing out, and there is a risk of premature chip failure in the future. Moreover, for damaged chips, the location of the damage cannot be determined. The methods using equipment are all off-line measurements, which cannot provide real-time feedback on chip damage and require additional equipment such as scanning electron microscopes, atomic force microscopes, infrared thermal imagers, and electron beam exposure equipment. In response to this, the present application provides a chip-level self-diagnosis solution for damage, including circuit structures, methods, and devices for self-diagnosis topologies for damage, which can achieve on-line detection of chip damage, prevent abnormal products from flowing out, and can also detect the location of the damage, facilitating effective monitoring and positioning of problems during production and use. It is also not necessary to rely on external equipment such as additional scanning electron microscopes, reducing the equipment cost of detection. Descriptions will be given separately below.

[0026] In one embodiment, a damage detection circuit for a chip is provided. There are n equivalent detection resistors between the substrate and the polysilicon layer (Poly layer) in the chip damage detection area, where n≥2. The damage detection circuit includes a power supply unit VDD, a switch unit SW1, and a voltage detection unit ADC. One end of the first equivalent detection resistor is connected to the ground terminal, one end of the nth equivalent detection resistor is connected to one end of the switch unit, and the other end of the switch unit is connected to the power supply terminal of the power supply unit. The resistors between the first equivalent detection resistor and the nth equivalent detection resistor are connected in series in sequence, and the detection terminal of the voltage detection unit is connected between any two adjacent equivalent detection resistors among the n equivalent detection resistors.

[0027] It should be noted that the n equivalent detection resistors are resistors equivalent to the substrate and the polysilicon layer and are used to achieve the detection purpose of the present application. Therefore, they are denoted as equivalent detection resistors in the embodiments of the present application.

[0028] It should be understood that the specific types of chips in the embodiments of the present application may include, but are not limited to, semiconductor chips such as fingerprint detection and pressure detection chips, and may specifically include ultrasonic fingerprint detection chips, etc. The embodiments of the present application do not make limitations.

[0029] In this embodiment, according to the detection requirements, the layout of the chip damage detection area can be flexibly designed, and the length or area position of the damage detection area can also be flexibly designed according to the actual situation. The following embodiments will describe various layout methods of the damage detection area provided in the embodiments of the present application.

[0030] As an example, the structure of the chip can be as Figure 1 And Figure 2 Shown, Figure 1 Is a top view of the chip, Figure 2 Is a side view of the chip, Figure 1 And Figure 2Shows the basic structure of a conventional chip. It can be seen that the chip includes a silicon layer, a substrate layer, a polysilicon layer located above, and a Metal layer. The structure of the chip also includes structural designs such as vertical vias (VIA) and silicon dioxide (Sio2); there are generally Pad points for external connection at the four edges of the chip. Take Figure 1 as an example. In the embodiment of the present application, the damage detection regions can be distributed on the four side strips of the chip. The lengths of each damage detection region can be the same or different. It should be understood that the damage detection regions can also be other situations. See more descriptions in subsequent embodiments, and no specific limitations are made here.

[0031] In this embodiment, in terms of the physical layer design, there are n equivalent detection resistors equivalent between the substrate and the polysilicon layer of the chip. As Figure 3 shown, they are respectively defined as R_1, R_2, R_i - 1, R_i, R_n - 1, and R_n, a total of n equivalent detection resistors. Among them, the equivalent detection resistors between the equivalent detection resistor R_1 and the equivalent detection resistor R_n are connected in series in sequence. One end of the equivalent detection resistor R_1 is connected to the ground terminal GND, one end of the equivalent detection resistor R_n is connected to one end of the switch unit SW1, and the other end of the switch unit SW1 is connected to the power supply terminal of the power supply unit VDD; the detection terminal of the voltage detection unit ADC is connected between any two adjacent equivalent detection resistors among the n equivalent detection resistors. As Figure 3 in the example of, the detection terminal of the voltage detection unit ADC is connected between the equivalent detection resistor R_i - 1 and R_i. The voltage read by the voltage detection unit ADC is defined as V_Crack. R_L represents the equivalent resistance on the left side of the reading point of the voltage detection unit ADC, and R_R represents the equivalent resistance on the right side of the reading point of the voltage detection unit ADC. It should be understood that using a circuit for detection between the substrate and the polysilicon layer conforms to the chip damage law because silicon is brittle and chip damage usually starts from the silicon surface cracking.

[0032] Refer to Figure 3 the equivalent circuit. A current loop will be formed from the power supply unit VDD through the equivalent detection resistors of the substrate and the polysilicon layer to the ground terminal GND. During testing, the switch of the switch unit SW1 can be closed to add the power excitation of the power supply unit VDD to the damage detection circuit. When there is no damage detection, the switch unit SW1 can be disconnected to prevent increasing the static power consumption. It should be understood that when the switch unit SW1 is closed, the current path at this time is: VDD SW1 R_R R_L GND; then, according to the resistor voltage division, there is the following relationship: V_Crack = VDD * R_L / (R_L + R_R); Since R_L and R_R have theoretical design values, by comparing the measured test voltage value V_Crack with the V_Design calculated from the design values, it is possible to confirm whether there is damage.

[0033] As an example, as Figure 4 shown, the damage detection regions on the four sides of the chip each correspond to a damage detection circuit. For example, the damage detection region on the right side of the chip corresponds to a damage detection circuit. By using the above detection method, it is possible to know whether there is damage in the damage detection region on the right side.

[0034] It can be seen that in this embodiment, a damage detection circuit for a chip is provided, and a specific damage detection topology for the chip is provided. The circuit implementation is very simple. By cleverly applying the equivalent resistance design of the substrate and the polysilicon layer, and the power supply unit VDD, the voltage detection unit ADC can realize chip damage detection without the need to rely on external devices such as additional scanning electron microscopes, and basically does not increase additional costs; the power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss; it can realize on-line damage testing, timely detect damaged abnormal products, effectively intercept damaged chips and prevent them from flowing out; at the same time, it can also locate the damaged area in real time on-line, reducing the workload of subsequent analysis.

[0035] It should be noted that in this application, there are n equivalent detection resistors between the substrate and the polysilicon layer of the chip damage detection region. The physical layer implementation can be designed by using at least one of the substrate and the polysilicon layer (Poly layer) of the chip to realize the equivalent resistance. In this application, the substrate resistance is defined as R_Subi, and the Poly resistance is defined as R_Polyi. Based on this, there can be various different processing schemes in this application, so that each different scheme has its corresponding characteristics, which will be described separately below.

[0036] In one embodiment, as the first example, the n equivalent detection resistors include n substrate resistors. That is, in the physical layer design, the substrate of the chip is equivalent to n substrate resistors, which are respectively defined as R_Sub1, R_Sub2, R_Subi-1, R_Subi, R_Subn-1, and R_Subn. As Figure 5 shown, the substrate resistors between the substrate resistor R_Sub1 and the substrate resistor R_Subn are connected in series in sequence. One end of the substrate resistor R_Sub1 is connected to the ground terminal GND, and one end of the substrate resistor R_Subn is connected to one end of the switch unit SW1. The other end of the switch unit SW1 is connected to the power supply terminal of the power supply unit VDD; the detection terminal of the voltage detection unit ADC is connected between any two adjacent substrate resistors among the n substrate resistors. As Figure 5In the example, the detection terminal of the voltage detection unit ADC is connected between the substrate resistor R_Subi-1 and the substrate resistor R_Subi. The voltage read by the voltage detection unit ADC is defined as V_Crack. R_L represents the equivalent substrate resistor on the left side of the reading point of the voltage detection unit ADC, and R_R represents the equivalent substrate resistor on the right side of the reading point of the voltage detection unit ADC.

[0037] Similarly, based on Figure 5 the equivalent circuit, it is also possible to confirm whether there is damage by comparing the measured test voltage value V_Crack with the corresponding design value V_Design.

[0038] It can be seen that in this embodiment, a specific example of a damage detection circuit for a chip is provided. The circuit implementation is very simple. By cleverly applying the substrate resistor design and the power supply unit VDD, the voltage detection unit ADC can achieve chip damage detection without relying on external devices such as additional scanning electron microscopes, and basically does not increase additional costs. The power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss. It can realize on-line damage testing, timely detect damaged abnormal products, effectively intercept damaged chips to prevent them from flowing out. At the same time, it can also locate the damaged area in real time on-line, reducing the workload of subsequent analysis. In addition, this embodiment only uses substrate resistors, and the circuit is relatively simpler, and can detect the damage and location of the substrate layer.

[0039] In one embodiment, as a second example, the n equivalent detection resistors include n polysilicon layer resistors. That is, in the physical layer design, the polysilicon layer of the chip is equivalently designed with n polysilicon layers, which are respectively defined as R_Poly1, R_Poly2, R_Polyi-1, R_Polyi, R_Polyn-1, and R_Polyn. As Figure 6 shown, the polysilicon layer resistors between the polysilicon layer resistor R_Poly1 and the polysilicon layer resistor R_Polyn are connected in series in sequence. One end of the polysilicon layer resistor R_Poly1 is connected to the ground terminal GND, one end of the polysilicon layer resistor R_Polyn is connected to one end of the switch unit SW1, and the other end of the switch unit SW1 is connected to the power supply terminal of the power supply unit VDD. The detection terminal of the voltage detection unit ADC is connected between any two adjacent polysilicon layer resistors among the n polysilicon layer resistors, as Figure 6In the example, the detection end of the voltage detection unit ADC is connected between the polysilicon layer resistance R_Polyi-1 and the polysilicon layer resistance R_Polyi, the voltage read by the voltage detection unit ADC is defined as V_Crack, R_L represents the equivalent polysilicon layer resistance on the left side of the voltage detection unit ADC reading point, and R_R represents the equivalent polysilicon layer resistance on the right side of the voltage detection unit ADC reading point.

[0040] Similarly, based on Figure 6 The equivalent circuit can also be based on the comparison of the test voltage value V_Crack with the corresponding design value V_Design to confirm whether there is damage.

[0041] It can be seen that in this embodiment, another specific example of a damage detection circuit for a chip is provided. The circuit is very simple to implement. The polysilicon layer resistance design, power supply unit VDD, and voltage detection unit ADC are cleverly applied to realize chip damage detection. No external equipment such as an additional scanning electron microscope is required, and basically no additional cost is added. The power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss. Online damage testing can be realized to detect abnormal damaged products in time to effectively intercept damaged chips and prevent outflow. At the same time, the damaged area can also be located online in real time to reduce the workload of subsequent analysis. In addition, this embodiment only uses equivalent polysilicon layer resistance, and the equivalent circuit is relatively simpler, which can detect the damage and position of the polysilicon layer.

[0042] In one embodiment, as a third example, the n equivalent detection resistors include j substrate resistors and j polysilicon layer resistors, wherein j≥1. That is, in terms of physical layer design, the substrate and polysilicon layer of the chip are equivalently designed with j polysilicon layer resistors and j substrate resistors, and the j polysilicon layer resistors are respectively defined as R_Poly1, R_Poly2, R_Polyi-1, R_Polyi, R_Polyj-1, and R_Polyj; and the j substrate resistors are respectively defined as R_Sub1, R_Sub2, R_Subi-1, R_Subi, R_Subj-1, and R_Subj.

[0043] As an example, Figure 7As shown, one end of the substrate resistor R_Sub1 is connected to the ground terminal GND, the other end of the substrate resistor R_Sub1 is connected to one end of the polysilicon layer resistor R_Poly1, the other end of the polysilicon layer resistor R_Poly1 is connected to the next substrate resistor, and so on, the substrate resistor R_Sub and the polysilicon layer resistor R_Poly are connected in series in sequence, and one end of the last polysilicon layer resistor R_Polyj is connected to one end of the switch unit SW1, and the other end of the switch unit SW1 is connected to the power supply end of the power supply unit VDD; the detection end of the voltage detection unit ADC is connected between any two adjacent polysilicon layer resistors in the equivalent detection resistor, such as Figure 7 In the example, the detection end of the voltage detection unit ADC is connected between the polysilicon layer resistor R_Polyi and the multi-substrate resistor R_Subi, the voltage read by the voltage detection unit ADC is defined as V_Crack, R_L represents the left equivalent resistance of the voltage detection unit ADC reading point, and R_R represents the right equivalent resistance of the voltage detection unit ADC reading point.

[0044] Similarly, based on Figure 7 The equivalent circuit can also be based on the comparison of the test voltage value V_Crack with the corresponding design value V_Design to confirm whether there is damage.

[0045] It can be seen that in this embodiment, another specific example of a damage detection circuit for a chip is provided. The circuit is very simple to implement. The equivalent resistance design of the substrate and the polysilicon layer is cleverly applied, as well as the power supply unit VDD and the voltage detection unit ADC can realize chip damage detection without the need for additional external equipment such as an additional scanning electron microscope, and basically does not increase additional costs; the power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss; online damage testing can be realized, and abnormal damaged products can be discovered in time to effectively intercept damaged chips and prevent outflow; at the same time, the damaged area can also be located online in real time to reduce the workload of subsequent analysis. In addition, this embodiment utilizes the equivalent substrate resistance and polysilicon layer resistance, and can detect the damage and position of the polysilicon layer and the substrate layer. Compared with the previous two schemes, the detection is more comprehensive.

[0046] It should be noted here that in the above three solutions, during testing, the corresponding design value V_Design will vary depending on the resistor design, and is not specifically limited.

[0047] It should be understood that in one embodiment, according to the above circuit design, the chip damage detection area can be distributed around the chip to detect damage around the chip, so as to achieve more flexible detection. Specifically, there is no limitation. The chip damage detection area can be distributed on any side of the chip, or the chip damage detection area can be distributed on all sides.

[0048] In one embodiment, as a first example, as Figure 1 shown, the chip damage detection area can be distributed on the four sides around the chip. In this embodiment, comprehensive and full-domain detection can be achieved, and the detection is more comprehensive.

[0049] In one embodiment, as an example, as Figure 8 shown, the chip damage detection area includes a plurality of segmented damage detection areas located around the chip and separated from each other. Figure 8 In the example of, it is a segmented detection area distribution. Two segmented damage detection areas can be divided on the upper side of the chip, and two segmented damage detection areas are also distributed on the other three sides. The segmented distribution method can accurately locate the damage position. It can also be other segmented quantities, and specific limitations are not made.

[0050] In one embodiment, as an example, as Figure 9 shown, the damage detection area can be distributed on the left side of the chip.

[0051] In one embodiment, as an example, as Figure 10 shown, the damage detection area can be distributed on the upper side of the chip.

[0052] In one embodiment, as an example, as Figure 11 shown, the damage detection area can be distributed on the right side of the chip.

[0053] In one embodiment, as an example, as Figure 12 shown, the damage detection area can be distributed on the lower side of the chip.

[0054] In the above embodiments, any side can be selected for damage detection. When the damage position is not easy to locate, the corresponding damage detection area distribution method can also be selected according to the actual weak points of the chip, making the scheme more flexible and targeted, and the circuit implementation will also be simpler.

[0055] In one embodiment, the power supply unit is the internal power supply unit of the chip, and the voltage detection unit is the internal analog-to-digital conversion unit of the chip. In this way, the circuit implementation of the scheme is simpler, and self-checking can be achieved only by relying on the chip, which is convenient for real-time detection.

[0056] It should be understood that, regardless of which of the above layout methods is adopted, the damage detection area can be implemented by using various damage detection circuits mentioned in the foregoing embodiments. For details, reference can be made to the explanation of Figure 4 , which will not be repeated here.

[0057] Please refer to Figure 13 and Figure 14 As shown, based on the damage detection method of the damage detection circuit described in any one of the foregoing embodiments, the method includes the following steps: When triggering the chip damage detection in the first test stage, close the switch unit; Compare the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area.

[0058] It can be seen that in this embodiment, a damage detection method based on the above damage detection circuit is provided. The implementation is very simple. By ingeniously applying the equivalent resistance design of at least one of the substrate and the polysilicon layer, and the power supply unit VDD, the voltage detection unit ADC can realize chip damage detection without relying on additional external devices such as scanning electron microscopes, and basically does not increase additional costs; the power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss; it can realize on-line damage testing, timely detect damaged abnormal products, effectively intercept damaged chips and prevent them from flowing out; at the same time, it can also locate the damaged area in real time on-line, reducing the workload of subsequent analysis.

[0059] In this embodiment, the first test stage is the chip package CP test stage or other stages, which is not specifically limited.

[0060] When triggering the chip damage detection in the first test stage, close the switch unit in the circuit, compare the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area.

[0061] In one embodiment, the designed voltage value includes the minimum designed voltage value V_Design_Min and the maximum designed voltage value V_Design_Max. The comparing the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area includes: Judge whether the first test voltage value detected by the voltage detection unit satisfies the minimum designed voltage value ≤ the first test voltage value ≤ the maximum designed voltage value; if not, judge that there is damage (Fail) in the chip damage detection area; if satisfied, store the first test voltage value as a test storage value in the electronic fuse Efuse or the one-time programmable memory OTP of the chip; That is, when the minimum design voltage value V_Design_Min ≤ the first test voltage value V_Crack1 ≤ the maximum design voltage value V_Design_Max is not satisfied, it indicates that damage exists in the chip damage detection area. For example, if the detection is performed on the detection area shown in Figure 10 , it indicates that there is damage in the detection area shown in Figure 4 . When the minimum design voltage value V_Design_Min ≤ the first test voltage value V_Crack1 ≤ the maximum design voltage value V_Design_Max is satisfied, the first test voltage value V_Crack1 will be stored as the test storage value V_Crack_Cali in the electronic fuse Efuse or one-time programmable memory OTP of the chip ( Figure 13 taking the example of storing in OTP) for subsequent use. In other embodiments, it can also be judged by comparing only the maximum design voltage value or the minimum design voltage value, and the specific method is not limited.

[0062] When triggering the test in the second test stage, the second test voltage value V_Crack2 detected by the voltage detection unit is compared with the test storage value V_Crack_Cali stored in the Efuse or OTP to determine whether damage exists in the chip damage detection area.

[0063] Specifically, in one embodiment, as shown in Figure 14 , the comparison of the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether damage exists in the chip damage detection area includes: Judging whether the second test voltage value V_Crack2 detected by the voltage detection unit satisfies: the minimum test storage value V_Crack_Cali_Min stored in the Efuse or OTP ≤ the second test voltage value V_Crack2 ≤ the maximum test storage value V_Crack_Cali_Max stored in the Efuse or OTP; When the minimum test storage value V_Crack_Cali_Min ≤ the second test voltage value V_Crack2 ≤ the maximum test storage value V_Crack_Cali_Max stored in the Efuse or OTP is not satisfied, it is judged that damage exists in the chip damage detection area (Fail); When the minimum test storage value V_Crack_Cali_Min stored in the Efuse or OTP ≤ the second test voltage value V_Crack2 ≤ the maximum test storage value V_Crack_Cali_Max stored in the Efuse or OTP, it is determined that there is no damage in the chip damage detection area (Pass).

[0064] It should be noted that due to some influencing factors in the actual application form of the chip, R_L and R_R are equivalent resistances realized through the substrate and Poly, which may be affected by temperature, physical stress, etc. In the actual test process, the scheme will be optimized to be closer to the actual situation. That is, after testing in the first test stage (such as after the wafer state of the CP test) to determine that there is no damage to the chip, the voltage V_Crack_Cali read by the ADC in the CP test stage is stored in the Efuse. In the subsequent test stage, V_Crack is compared with V_Crack_Cali stored in the Efuse, and whether there is chip damage is judged through the voltage difference, so as to exclude the occurrence of damage caused by the above-mentioned influences and achieve more comprehensive and effective detection.

[0065] In other embodiments, it can also be judged only by comparing the minimum test storage value or the maximum test storage value, and no specific limitation is made.

[0066] In one embodiment, the first test stage is the chip packaging CP test stage, and the second test stage is the backend test stage of the CP test stage, and no specific limitation is made.

[0067] In one embodiment, the method further includes: when the chip damage detection is not triggered, turning off the switch unit, which can help prevent the increase of static power consumption.

[0068] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0069] In one embodiment, there is also provided a damage detection device based on the damage detection circuit described in any one of the foregoing embodiments. The damage detection device can be implemented by a module inside the chip, or integrated into the chip, or a processing module outside the chip, and no specific limitation is made. The device includes: A control module, configured to close the switch unit when the chip damage detection is triggered; A determination module, configured to compare the first test voltage value detected by the voltage detection unit with the design voltage value to determine whether there is damage in the chip damage detection area.

[0070] In one embodiment, the design voltage value includes a minimum design voltage value and a maximum design voltage value, and the determination module is configured to: Determine whether the first test voltage value detected by the voltage detection unit satisfies the condition: minimum design voltage value ≤ first test voltage value ≤ maximum design voltage value; If not satisfied, it is determined that there is damage in the chip damage detection area.

[0071] In one embodiment, the determination module is further configured to: If satisfied, store the first test voltage value as a test storage value in the electronic fuse Efuse or one-time programmable memory OTP of the chip; When triggering the test in the second test stage, compare the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether there is damage in the chip damage detection area.

[0072] In one embodiment, the processing module is configured to: Determine whether the second test voltage value detected by the voltage detection unit satisfies the condition: the minimum test storage value stored in the Efuse or OTP ≤ second test voltage value ≤ the maximum test storage value stored in the Efuse or OTP; If not satisfied, it is determined that there is damage in the chip damage detection area; If satisfied, it is determined that there is no damage in the chip damage detection area.

[0073] In one embodiment, the first test stage is the chip package CP test stage, and the second test stage is the back-end test stage of the CP test stage.

[0074] In one embodiment, the determination module is further configured to: When chip damage detection is not triggered, turn off the switch unit.

[0075] It can be seen that in this embodiment, a damage detection device based on the above damage detection circuit is provided. The implementation is very simple. By skillfully applying the resistance design of the substrate and polysilicon layer, and the power supply unit VDD and voltage detection unit ADC, chip damage detection can be achieved without relying on external devices such as additional scanning electron microscopes, and basically no additional cost is incurred; the power supply unit VDD can be disconnected by a switch, which does not affect the normal performance of the chip and does not increase additional current loss; online damage testing can be realized to timely detect damaged abnormal products, effectively intercept damaged chips and prevent them from flowing out; at the same time, the damaged area can also be located in real time online, reducing the workload of subsequent analysis.

[0076] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be assigned to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0077] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A damage detection circuit for a chip, characterized in that, There are n equivalent detection resistors between the substrate and the polysilicon layer in the chip damage detection area, where n≥2. The damage detection circuit includes a power supply unit, a switch unit, and a voltage detection unit; Among them, one end of the first equivalent detection resistor is connected to the ground terminal, one end of the nth equivalent detection resistor is connected to one end of the switch unit, and the other end of the switch unit is connected to the power supply terminal of the power supply unit; the resistors between the first equivalent detection resistor and the nth equivalent detection resistor are connected in series in sequence, and the detection terminal of the voltage detection unit is connected between any two adjacent equivalent detection resistors among the n equivalent detection resistors.

2. The damage detection circuit according to claim 1, wherein The n equivalent detection resistors include n substrate resistors.

3. The damage detection circuit according to claim 1, wherein The n equivalent detection resistors include n polysilicon layer resistors.

4. The damage detection circuit according to claim 1, wherein The n equivalent detection resistors include j substrate resistors and j polysilicon layer resistors, where j≥1.

5. The damage detection circuit according to claim 1, wherein The chip damage detection area is distributed around the chip.

6. The damage detection circuit according to claim 5, wherein The chip damage detection area includes a plurality of segmented damage detection areas located around the chip and separated from each other.

7. The damage detection circuit according to claim 5, wherein The chip damage detection area is distributed on any one side of the chip, or the chip damage detection area is distributed on all sides.

8. The damage detection circuit according to claim 1, wherein The power supply unit is the internal power supply unit of the chip, and the voltage detection unit is the internal analog-to-digital conversion unit of the chip.

9. A damage detection method based on the damage detection circuit according to any one of claims 1-8, characterized in that, The method includes: When triggering the chip damage detection in the first test stage, close the switch unit; Compare the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area.

10. The damage detection method according to claim 9, characterized in that, The designed voltage value includes the minimum designed voltage value and the maximum designed voltage value. The comparing the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area includes: Judge whether the first test voltage value detected by the voltage detection unit satisfies the condition: minimum designed voltage value ≤ first test voltage value ≤ maximum designed voltage value; If not satisfied, it is determined that there is damage in the chip damage detection area.

11. The damage detection method according to claim 10, wherein, After judging whether the first test voltage value detected by the voltage detection unit satisfies the condition: minimum designed voltage value ≤ first test voltage value ≤ maximum designed voltage value, the method further includes: If satisfied, store the first test voltage value as a test storage value in the electronic fuse Efuse or one-time programmable memory OTP of the chip; When triggering the test in the second test stage, compare the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether there is damage in the chip damage detection area.

12. The damage detection method according to claim 11, characterized in that, The comparing the second test voltage value detected by the voltage detection unit with the test storage value stored in the Efuse or OTP to determine whether there is damage in the chip damage detection area includes: Determine whether the second test voltage value detected by the voltage detection unit satisfies that the minimum test storage value stored in the Efuse or OTP ≤ the second test voltage value ≤ the maximum test storage value stored in the Efuse or OTP; If not satisfied, determine that there is damage in the chip damage detection area; If satisfied, determine that there is no damage in the chip damage detection area.

13. The damage detection method according to claim 11, wherein The first test stage is the chip package CP test stage, and the second test stage is the back-end test stage of the CP test stage.

14. The damage detection method according to any one of claims 9-13, characterized in that, The method further includes: When chip damage detection is not triggered, turn off the switch unit.

15. An injury detection device based on the injury detection circuit according to any one of claims 1-8, characterized in that, The device includes: A control module, configured to close the switch unit when chip damage detection is triggered; A determination module, configured to compare the first test voltage value detected by the voltage detection unit with the designed voltage value to determine whether there is damage in the chip damage detection area.

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