Low-pin-number chip test circuit, test method and equipment

Abstract

The invention relates to a low-pin-number chip test circuit, test method and equipment, the low-pin-number chip test circuit is characterized in that a control module is connected with a test module, input and output pins are connected with a function module and an enable module, and the enable module is connected with the control module and the test module; wherein when the enabling module gates the test mode, the control module generates a one-hot code according to a first test requirement so as to gate the test module based on the one-hot code; the input / output pin generates a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or, when the enabling module gates the function mode, the input and output pins generate a second test signal according to a second test requirement, the function module triggers the function test state in response to the second test signal and generates a test result, and the problem that the number of the input and output pins cannot meet the chip test requirement is solved.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and particularly to a low-pin-count chip testing circuit, a testing method, and a device. Background Art

[0002] In the field of chip testing, for some projects, there are strict restrictions on the number of gpio (General Purpose Input / Output) pins. Also, because these projects simultaneously need to implement functions such as dft (Design for Test) and SoC (System on Chip) self-testing, the number of gpio pins planned for chip testing projects cannot meet the dft design and testing requirements.

[0003] Regarding the problem that the number of gpio pins cannot meet the chip testing requirements in the related art, no effective solution has been proposed yet. Summary of the Invention

[0004] Based on this, it is necessary to provide a low-pin-count chip testing circuit, a testing method, and a device to solve the problem that the number of input / output pins cannot meet the chip testing requirements.

[0005] In a first aspect, in the present embodiment, a low-pin-count chip testing circuit is provided, including: input / output pins, a control module, at least two testing modules, an enabling module, and a function module; the control module is connected to the testing module, the input / output pins are connected to the function module and the enabling module, and the enabling module is respectively connected to the control module and the testing module for selecting a function mode and a testing mode; wherein,

[0006] When the enabling module selects the testing mode, the control module generates a one-hot code according to the first testing requirement to select the testing module based on the one-hot code; the input / output pins generate a first testing signal according to the first testing requirement, and the testing module generates a testing result in response to the first testing signal; or,

[0007] When the enabling module selects the function mode, the input / output pins generate a second testing signal according to the second testing requirement, and the function module triggers a function testing state and generates a testing result in response to the second testing signal.

[0008] In some of the embodiments, the control module includes a first pin, a second pin, and a third pin, the first pin is connected to the testing module, and the second pin is connected to the third pin; wherein,

[0009] The first pin is used to generate the one-hot code;

[0010] The second pin is used to generate a control signal for the control module according to the test requirements;

[0011] The third pin is used to control the control module to maintain its current state based on the control signal after the control signal is generated by the second pin.

[0012] In some embodiments, the circuit further includes a register module. The first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module; wherein,

[0013] The register module is used to control the gating of the test module according to the one-hot code and control the control module to maintain its current state according to the control signal.

[0014] In some embodiments, the register module includes a first shift register unit, a second shift register unit, and a first logic gate unit; wherein,

[0015] The first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit;

[0016] The second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit;

[0017] The first output end of the first logic gate unit is further connected to the third pin, and multiple second output ends of the first logic gate unit are connected to the test module.

[0018] In some embodiments, the register module includes multiple first shift register units respectively corresponding to multiple first pins, and the first logic gate unit includes an AND gate and a first OR gate; wherein,

[0019] The input ends of each first OR gate are respectively connected to the output ends of multiple first shift register units and the output end of the second shift register unit;

[0020] The output ends of each first OR gate are connected to the input end of the AND gate, and the output ends of the first OR gate are further connected to the corresponding test module;

[0021] The output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0022] In some of these embodiments, the register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate, where,

[0023] The first pin is connected to the input end of the third shift register unit;

[0024] The input ends of the second OR gate are connected to the output end of the third shift register unit and the output end of the second shift register unit;

[0025] The output end of the second OR gate is connected to the input end of the AND gate;

[0026] The control module generates a one-hot code according to a third test requirement to turn off the test module based on the one-hot code.

[0027] In some of these embodiments, the enabling module includes an enabling signal interface and a second logic gate unit. One end of the second logic gate unit is connected to the enabling signal interface and the input / output pin, and the other end of the second logic gate unit is connected to the test module. The enabling signal interface is also connected to the functional module; where,

[0028] When the enabling signal interface outputs a first level signal to the second logic gate unit, the functional mode is selected. The second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers a functional test state in response to the second test signal and generates a test result;

[0029] When the enabling signal interface outputs a second level signal to the second logic gate unit, the test mode is selected. The second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

[0030] In some of these embodiments, the second logic gate unit includes a plurality of third AND gates and a plurality of fourth AND gates. The input ends of the third AND gates are connected to the input / output pin and the enabling signal interface; the output ends of the third AND gates are connected to the input ends of the fourth AND gates. The register module is connected to the input ends of the fourth AND gates, and the fourth AND gates are connected to the test unit.

[0031] Second, in this embodiment, a test method for a low pin count chip test circuit is provided, which is applied to the low pin count chip test circuit described in the first aspect above. The method includes:

[0032] When the enabling module enables the test mode, configure the control module and input / output pins of the low-pin-count chip test circuit according to the first test requirement, so that the control module generates a one-hot code according to the first test requirement, and the input / output pins generate a first test signal according to the first test requirement; based on the one-hot code, select the test module, so that the test module generates a test result in response to the first test signal; or,

[0033] When the enabling module enables the functional mode, configure the input / output pins of the low-pin-count chip test circuit according to the second test requirement, so that the input / output pins generate a second test signal according to the second test requirement, and the functional module triggers the functional test state and generates a test result in response to the second test signal.

[0034] In a third aspect, in this embodiment, a chip test device is provided, including the low-pin-count chip test circuit described in the first aspect above.

[0035] The above-mentioned low-pin-count chip test circuit, test method and device enter the test mode or functional mode through the enabling module. In the test mode, the one-hot code generated by the control module is used to select the test module for testing, which meets the requirements of various chip tests without increasing the number of input / output pins, and solves the problem that the number of input / output pins cannot meet the chip test requirements. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a block diagram of the structure of the low-pin-count chip test circuit in an embodiment;

[0038] Figure 2 It is a schematic flow chart of the low-pin-count chip test circuit in an embodiment;

[0039] Figure 3 It is a block diagram of the structure of another low-pin-count chip test circuit in another embodiment;

[0040] Figure 4 It is a block diagram of the structure of the register module in an embodiment;

[0041] Figure 5 It is a schematic diagram of scan LPC based on self-locking design in an embodiment;

[0042] Figure 6 Schematic diagram of one-hot code judgment in an embodiment;

[0043] Figure 7 Schematic diagram of scan LPC in an embodiment. Detailed implementation manners

[0044] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It can be understood that the terms "first", "second", etc. used in this application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of this application, the first resistor can be called the second resistor, and similarly, the second resistor can be called the first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0047] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is electrical signal or data transmission between the connected circuits, modules, units, etc.

[0048] It can be understood that "at least one" means one or more, and "a plurality" means two or more. "At least part of an element" means part or all of the element.

[0049] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0050] LPC (Low Pin Count) is a system bus standard with low power consumption and high integration. It is mainly used to connect processors and peripheral devices, such as memory controllers, input / output pins, etc. It is particularly suitable for mobile devices and low-power applications to reduce the number of pins on the circuit board and improve the flexibility and efficiency of system design.

[0051] The number of GPIO (General Purpose Input / Output) pins refers to the number of general-purpose input / output pins available on an integrated circuit (such as a microcontroller or a system-on-chip). These pins can be configured as inputs or outputs for communication and control with other devices or circuits. For some projects, there are strict restrictions on the number of GPIO pins, but functions such as DFT and SoC self-test need to be implemented, and the number of GPIO pins cannot meet the chip test requirements.

[0052] In one embodiment, Figure 1 A structural block diagram of a low-pin-count chip test circuit is provided, as Figure 1 shown. The low-pin-count chip test circuit includes: input / output pins, a control module, at least two test modules, an enable module, and a function module; the control module is connected to the test modules, the input / output pins are connected to the function module and the enable module, and the enable module is respectively connected to the control module and the test modules for selecting the function mode and the test mode.

[0053] Among them, the low-pin-count chip test circuit may include multiple test modules. The test modules are used to implement chip testing to determine whether the chip can work properly after manufacturing. The function module, also called the function module, is the module on the chip responsible for executing actual application functions. By triggering the function test state, the function module can be verified and tested.

[0054] The input / output pins, also called I / O interfaces, are used to transmit the signals required for the test mode to the selected test module or transmit the signals required for the function mode to the function module, and to transmit the input signals of the test module or the function module. The low-pin-count chip test circuit may include one or more input / output pins. It can be understood that in the case of including multiple input / output pins, each input / output pin is respectively connected to the control module, the function module, and the test modules.

[0055] The control module is used to output one-hot codes. Among them, the one-hot code is a coding method in which each possible value is represented by only one code bit, and only one code bit is "hot" (i.e., 1), and the rest of the code bits are "cold" (i.e., 0). The control module can output multiple one-hot codes through multiple pins respectively, and each pin is correspondingly connected to a different test module, so as to respectively control the gating or shutdown of different test modules through different one-hot codes. By increasing the length of the code bits, multiple test modes can be correspondingly set. For example, a 5-bit one-hot code can support 5 independent test modes. Optionally, a binary code is output to the control module based on the first test requirement, and the control module converts and outputs a one-hot code according to the binary input in the first test requirement. The control module can use a decoder to convert the binary input into a one-hot code output, or implement the conversion of the one-hot code through a programmable array or a programmable logic device.

[0056] The enable module is used to receive an enable signal and, based on the enable signal, adjust the validity of the output signal of the input / output pins according to the test mode. Optionally, when the enable module selects the function mode, through the level signal output by the enable module, the signal output from the input / output pins to the test module is an invalid signal; when the enable module selects the test mode, the level signal output by the enable module is adjusted so that the signal output from the input / output pins to the test module is a valid signal. Further, according to actual requirements, the input / output pins can also be connected to the function module through the enable module, so that the enable module can be used to limit the signal output from the input / output pins to the function module. Among them, the enabling mechanism of the enable module can be implemented through basic logic gates. For example, logical calculation is performed on the signal output from the input / output pins and the signal output from the enable module using a logical gate such as an AND gate or an OR gate to achieve the effect of enabling or shielding the validity of the signal output from the input / output pins.

[0057] Figure 2 A schematic diagram of the process of a low-pin-count chip test circuit is provided, as Figure 2 shown. When the enable module selects the test mode, the control module generates a one-hot code according to the first test requirement to gate the test module based on the one-hot code; the input / output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal. Or, when the enable module selects the function mode, the input / output pins generate a second test signal according to the second test requirement, and the function module triggers the function test state and generates a test result in response to the second test signal.

[0058] Optionally, when the enable module enables the test mode, the enable module receives an enable signal and controls the first test signal output from the input / output pins to each test module to be a valid signal according to the enable signal. The control module converts the binary input in the first test requirement into a one-hot code for output. Each one-hot code is respectively used to control different test modules, and there is exactly one bit equal to 1 in the one-hot code, and different one-hot codes correspond to different test modules being selected. Taking a 3-bit one-hot code as an example, the one-hot code can control the selection of up to 3 different test modules.

[0059] Optionally, when the enable module enables the function mode, the enable signal received by the enable module controls the signal output from the input / output pins to each test module to be an invalid signal, that is, only the function module can receive the second test signal of the input / output pins and trigger the function test state based on the second test signal.

[0060] The first test requirement and the second test requirement can be modified according to the actual test requirements of the test module and the function module, and are not limited here.

[0061] In this embodiment, under the test module, the control module generates a one-hot code according to the first test requirement, and the one-hot code controls the selection and shutdown of the test module. Without increasing the number of input / output pins, different test modules can be selected and enter the test; in the function mode, the function test state of the function module can still be triggered based on the input / output pins; through the multiplexing of the input / output pins, various test requirements of the chip are met, and the problem that the number of input / output pins cannot meet the chip test requirements is solved.

[0062] In one embodiment, the control module includes a first pin, a second pin, and a third pin. The first pin is connected to the test module, and the second pin is connected to the third pin; wherein, the first pin is used to generate a one-hot code; the second pin is used to generate a control signal of the control module according to the test requirement; the third pin is used to keep the control module in the current state based on the control signal after the second pin generates the control signal.

[0063] Among them, the number of the first pins is greater than or equal to the number of one-hot codes, so that each one-hot code can be respectively connected to the corresponding test module through multiple first pins. The control signal is used to adjust the working state of the control module. Optionally, the first pin is connected to the third pin. After the second pin generates the control signal, the control signal is input to the third pin and makes the control module not perform data shift operations and does not update the register content, that is, makes the control module keep the current state.

[0064] Optionally, the control module can be made to maintain its current state through a state machine: A state machine is provided in the control module. When the first pin is used to generate a one-hot code, the state machine outputs a control signal through the second pin, causing the third pin to receive the control signal and enter a waiting state based on the control signal.

[0065] In this embodiment, the test module receives corresponding one-hot codes through the first pin, and through the second and third pins, the one-hot code output by the first pin can always be maintained at the expected value, avoiding chip test failures caused by changes in the one-hot code output by the first pin, and improving the anti-interference ability of the low-pin-count chip test circuit.

[0066] In one embodiment, the low-pin-count chip test circuit further includes a register module. The first and second pins are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module. Among them, the register module is used to control the gating of the test module according to the one-hot code and control the control module to maintain its current state according to the control signal.

[0067] Among them, the register module includes one or more registers. The clock signal generates pulses within a clock cycle, and each register performs operations such as signal writing and reading based on the pulse signal within a time period. Optionally, the register module includes multiple registers, and the first and second pins are respectively connected to the input ends of different registers, so as to control the output of the one-hot code and the control signal through multiple registers respectively.

[0068] Optionally, when the enable module gates the test mode, the one-hot code is transmitted to the register module through the clock signal, and the register connected to the first pin is opened, thereby gating the corresponding test module. While the control module outputs the one-hot code, a control signal is output to the third pin according to the register connected to the second pin, causing the control module to maintain its current state.

[0069] Furthermore, the output end of the register module is connected to the test module through an enable module. Figure 3 Another structural block diagram of the low-pin-count chip test circuit is provided, as Figure 3 shown. When the enable module gates the test mode, the register module outputs a signal to the test module through the enable module. When the enable module gates the function mode, the signal output by the register module is not transmitted to the test module.

[0070] In this embodiment, the gating of the test module and the output of the control signal can be controlled through the register, improving the stability and controllability of the low-pin-count chip test circuit.

[0071] Further, in one embodiment, the register module includes a first shift register unit, a second shift register unit, and a first logic gate unit; wherein, the first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit; the second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit; the first output end of the first logic gate unit is further connected to the third pin, and multiple second output ends of the first logic gate unit are connected to the test module.

[0072] Among them, the register module includes multiple first shift register units corresponding to multiple first pins, and the number of the first shift register units is the same as the number of the first pins. In the case where there are multiple first pins, the first pins can be correspondingly connected to the input ends of the respective first shift register units.

[0073] Optionally, the first shift register unit may further include a shift register and a NOT gate. The output end of the first pin is connected to the input end of the NOT gate, the output end of the NOT gate is correspondingly connected to the input end of the shift register, and the output end of the shift register is connected to the input end of the first logic gate unit. The signal input to the shift register is adjusted through the NOT gate.

[0074] Similarly, the second shift register unit may include a shift register, or may include an inverter, an AND gate, and a shift register connected in sequence. The structures in the first shift register unit and the second shift register unit can be adjusted according to the test requirements, which will not be elaborated here.

[0075] The output ends of the first shift register unit and the second shift register unit are connected to the input end of the first logic gate unit. Therefore, the first logic gate unit can perform a logic operation on the signal output after being processed by the first shift register unit and the control signal output after being processed by the second shift register unit, ensuring that when the control module outputs the one-hot code and the control signal simultaneously, the corresponding test module is selected through the output signal of the second output end of the first logic gate unit, and the control module is maintained in the current state through the output signal of the first output end of the first logic gate unit.

[0076] In this embodiment, by setting the first logic gate unit to simultaneously receive the signal output by the first shift register unit and the control signal output by the second shift register unit, chip testing is achieved when the control module synchronously outputs the one-hot code and the control signal, avoiding the situation where the chip testing is unstable due to the control module only outputting the one-hot code or only outputting the control signal.

[0077] According to the different internal structures of the first shift register unit and the second shift register unit, the first logic gate unit can be adaptively adjusted according to the high and low levels of the output signals of the first shift register unit and the second shift register unit. In one embodiment, Figure 4 A structural block diagram of a register module is provided, as Figure 4 shown. The register module includes a plurality of first shift register units corresponding to a plurality of first pins respectively. The first logic gate unit includes an AND gate and a first OR gate. Among them, the input ends of each first OR gate are respectively connected to the output ends of the plurality of first shift register units and the output end of the second shift register unit. The output ends of each first OR gate are connected to the input end of the AND gate, and the output end of the first OR gate is also connected to the corresponding test module. The output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0078] Among them, the first OR gate performs a logical "OR" operation on the signal output after being processed by the first shift register unit and the control signal output after being processed by the second shift register unit. In the case of including a plurality of first shift register units and one second shift register unit, the first input ends of different first OR gates are respectively connected to different first shift register units. At the same time, the first input end of each first OR gate is also connected to the second shift register unit.

[0079] In this embodiment, after the AND gate performs a logical "AND" calculation on the outputs of the plurality of first OR gates, by inputting the calculation result of the AND gate into the second shift register unit again, a feedback loop can be constructed to improve the stability of the control signal output.

[0080] In one embodiment, the register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate. Among them, the first pin is connected to the input end of the third shift register unit. The input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit. The output end of the second OR gate is connected to the input end of the AND gate. The control module generates a one-hot code according to the third test requirement to turn off the test module based on the one-hot code.

[0081] Among them, the one-hot code generated by the control module according to the third test requirement is different from the one-hot code generated by the second test requirement. The third shift register unit at least includes a shift register.

[0082] Optionally, the third shift register unit includes an inverter and a shift register connected in sequence. After the control module generates a one-hot code according to the third requirement, a first pin in the control module is connected to the inverter in the third shift register unit. The second OR gate performs a logical "OR" operation on the signal processed and output by the third shift register unit and the control signal output by the second shift register unit, ensuring that when the control unit outputs a one-hot code and a control signal simultaneously, since the output end of the second OR gate is not connected to any test module, none of the test modules are selected and enabled.

[0083] In this embodiment, when the enable module selects and enables the test mode, the one-hot code generated by the control module according to the third test requirement shuts down each test module, thereby obtaining a reserved self-test mode path, thus improving the expandability of the low-pin-count chip test circuit.

[0084] In one embodiment, the enable module includes an enable signal interface and a second logic gate unit. One end of the second logic gate unit is connected to the enable signal interface and the input / output pin, and the other end of the second logic gate unit is connected to the test module. The enable signal interface is also connected to the functional module; wherein, when the enable signal interface outputs a first-level signal to the second logic gate unit, the functional mode is selected and enabled. The second logic gate unit prohibits the second test signal from being input to the test module, and the functional module responds to the second test signal to trigger the functional test state and generate a test result; when the enable signal interface outputs a second-level signal to the second logic gate unit, the test mode is selected and enabled. The second logic gate unit allows the first test signal to be input to the test module, and the test module responds to the first test signal to generate a test result.

[0085] Wherein, the enable signal interface is used to receive the enable signal. Optionally, the second logic gate unit includes a plurality of third AND gates. The input ends of each third AND gate are respectively connected to the input / output pin, and the input ends of each third AND gate are also connected to the enable signal interface. The first-level signal is a low level, and the second-level signal is a high level. Depending on the second logic gate unit, the corresponding first-level signal and second-level signal can be different. For example, when the second logic gate unit includes a plurality of NAND gates, the first-level signal is a high level and the second-level signal is a low level. There is no limitation on the first-level signal and the second-level signal here. Optionally, the second logic gate unit includes a plurality of third AND gates and a plurality of fourth AND gates. The input ends of the third AND gates are connected to the input / output pin and the enable signal interface; the output end of the third AND gate is connected to the input end of the fourth AND gate. The first OR gate in the register module is connected to the input end of the fourth AND gate through an inverter, and the fourth AND gate is connected to the test unit. Thus, through the second logic gate unit, the signal output of the register module is restricted from being output to the test module.

[0086] Further, the control module can also be enabled through an enable signal: connect the enable signal interface to the enable pin of the control module. When the enable signal interface outputs a second-level signal, the control module can output a one-hot code; when the enable signal interface outputs a first-level signal, the control module does not output a one-hot code.

[0087] Further, the input of the control signal can also be restricted through an enable module. Among them, the register unit can also be provided with a first AND gate and a second AND gate. The first AND gate is the logic gate connected to the output end of the first OR gate in the above-mentioned embodiment. The input ends of the second AND gate are respectively connected to the first AND gate and the second logic unit, and the output end of the second AND gate is connected to the third pin of the control module. When the enable signal interface outputs a first-level signal, a logical "AND" calculation is performed through the second AND gate to prohibit the control signal processed by the register unit from being input to the third pin of the control module. Optionally, the other end of the second logic gate unit is connected to the test module and the clock pin of the control module, so that the clock signal input during the operation of the control module is synchronized with the test module.

[0088] In this embodiment, an enable module is formed by the enable signal interface and the second logic gate unit, and the switching between the test mode and the function mode can be realized based on a simple structure.

[0089] In one embodiment, the control module is a JTAG module.

[0090] Optionally, the JTAG (Joint Test Action Group) module includes multiple LOCK TDRs (Test Data Registers), and the number of LOCK TDRs is consistent with the number of bits of the generated one-hot code. Configure the LOCK TDR through ijtag (Internal JTAG) so that the LOCK TDR generates a corresponding one-hot code according to the first test requirement or the third test requirement. Among them, the TDR (Test Data Register) is used to store the configuration data in the test mode. By configuring the TDR with a one-hot code, different test modules can be selected to enter different test modes, such as boundary scan test, function test, etc., to meet the requirement of GPIO multiplexing.

[0091] Optionally, the JTAG module includes a TAP (Test Access Port) state machine. The second pin of the JTAG module is the idle pin, and the third pin is the tms pin. The operation process of the TAP state machine in the control module to control the JTAG interface is: after the JTAG module completes the JTAG operation to generate a one-hot code, a control signal is output from the second pin to the third pin through the TAP state machine, so that the control module is in the idle state.

[0092] In one embodiment, pins such as the pins of JTAG, scan_en (scan enable), tdi (test data input), tdo (test data output), and tck (test clock input) need to be multiplexed on a chip project. The number of gpios in a conventional project plan often cannot meet the DFT design and test requirements. Therefore, it is difficult to complete the DFT (Design for Testability) design under the limitation of the limited number of gpios, and to switch between the function mode and the DFT mode according to the test requirements or functional requirements to check the defects and faults generated during the chip manufacturing process. Based on this, Figure 5 A schematic diagram of a scan (scan chain) LPC based on a self-locking design is provided, as Figure 5 shown, where function is the functional module. CAT and flash are two different test modules. Gpio is the input / output pin. Among the input / output pins, gpio1 is multiplexed as the pin input of function, the test_clock of the CAT module, and the tck pin input of the jtag module; gpio0 is multiplexed as the pin input of function, the scan_in of the CAT module, and the tdi pin input of the jtag module; gpio 3 is multiplexed as the pin input of function, the scan_en of the CAT module, and the tms pin input of the jtag module; gpio 5 is multiplexed as the cat_update signal input; gpio 4 is multiplexed as the BIO signal input of flash; gpio2 is multiplexed as the output of the function module. JTAG is the control module, including the first pins: FLASHLOCK, SOCLOCK, SCANLOCK; the second pin idle; the third pin tms. The enable module includes an enable signal interface test_en, an AND gate, and an inverter.

[0093] The register module includes a first shift register unit, a second shift register unit, a third shift register unit, and a first logic gate unit. The first shift register unit includes a NOT gate and a shift register connected in sequence. The second shift register unit includes an inverter, an AND gate, and a shift register connected in sequence. The third shift register unit includes a NOT gate and a shift register connected in sequence. The first logic gate unit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate. The input terminal of the first OR gate is connected to the second shift register unit, another input terminal of the first OR gate is connected to the first shift register unit, the output terminal of the first OR gate is connected to the input terminal of the first AND gate and the test module, the input terminal of the second OR gate is connected to the output terminal of the third shift register unit and the output terminal of the second shift register unit, and the output terminal of the second OR gate is connected to the input terminal of the first AND gate. The output terminal of the first AND gate is connected to the input terminal of the second shift register unit and the input terminal of the second AND gate. The input terminal of the second AND gate is further connected to the input terminal of the enable module, and the output terminal of the second AND gate is connected to the third pin.

[0094] Among them, according to different functional modes in the chip test requirements for functional division and multiplexing, different test modes can be designed. Figure 5 As shown, 4 self-locking modes are designed: The SCAN LOCK mode is used to execute the dft scantest (scan test) in the design for testability; The SOCTEST LOCK mode is used to execute the debug test of the SoC; The FLASH LOCK mode is used to execute the flash test, connect the input and output pins to the flash, and control the flash test by the external signals output from the input and output pins; The TAP LOCK mode is used to configure the TAP state machine and ijtag in the JTAG, and make the TAP state machine in the idle state and the value of the TDR in the JTAG remain the expected value.

[0095] Optionally, Figure 5 There are 3 1-bit LOCK TDR registers in the Jtag network, namely register LOCK_tdr0, register LOCK_tdr1, and register LOCK_tdr2. These three registers are configured through ijtag to generate one-hot codes, and according to different one-hot codes, different lock states are entered to realize the function multiplexing of GPIO and meet the requirements of DFT and SoC self-testing.

[0096] Three 1-bit LOCK TDRs (LOCK_tdr0, LOCK_tdr1, LOCK_tdr2) are combined to form three possible one-hot codes: 100, 010, and 001. Among them, 100 represents FLASH LOCK. When the one-hot code 100 is output, the system enters the flash test mode correspondingly, and the lpc enters the FLASH LOCK state; 010 represents SCAN LOCK. When the one-hot code 010 is output, the system enters the dft scan test mode, and the lpc enters the SCAN LOCK state; 001 represents SOCTEST LOCK. When the one-hot code 001 is output, it enters the self-test mode of the function, and the lpc enters the SOCTEST LOCK state.

[0097] As Figure 5 shown, after the three 1-bit LOCK TDRs output one-hot codes, it can be judged whether to enter the SCAN LOCK state, FLASH LOCK state, or TAP LOCK state through Logic A, Logic B, and Logic C respectively. Taking entering the SCAN LOCK state through Logic A as an example, Figure 6 a schematic diagram for judging one-hot codes is provided. As Figure 6 shown, the JTAG module includes register 0 (tdr0), register 1 (tdr1), and register 2 (tdr2) respectively. The registers are used to output level signals "0" or "1". Among them, the level signal output by tdr0 and the constant level signal "0" are respectively input to the first exclusive-OR gate, the level signal output by tdr1 and the constant level signal "1" are respectively input to the second exclusive-OR gate, and the level signal output by tdr2 and the constant level signal "0" are respectively input to the third exclusive-OR gate. The output terminals of the three exclusive-OR gates are commonly connected to an OR gate. When the output one-hot code is 010, the lpc enters the SCAN LOCK state based on the output of the OR gate; when the output one-hot code is 100 or 001, the lpc does not enter the SCAN LOCK state. Similarly, according to the one-hot codes corresponding to the FLASH LOCK state or TAP LOCK state, by adjusting the constant level signals input to the exclusive-OR gates in Logic B and Logic C, the one-hot code judgment for the FLASH LOCK state or TAP LOCK state can be achieved, and Logic B and Logic C will not be elaborated here. It can be understood that in addition to implementing one-hot code judgment according to the Figure 5 method shown, one-hot code judgment can also be achieved through other methods such as software algorithms or FPGA (Field Programmable Gate Array).

[0098] Through the above 4 self-locking modes, while 5 GPIOs can perform normal functions, they can also complete scan tests, MBIST tests, flash tests, and SoC self-test modes required for DFT. The specific execution logic is as follows:

[0099] Step 301, define and determine the self-locking mode required for testing. The self-locking mode is one of FLASH LOCK, SCAN LOCK, SOCTEST LOCK, and TAP LOCK.

[0100] Step 302, configure the TDR (Test Data Register) in JTAG according to the required self-locking mode.

[0101] Step 303, with the configured TDR, make the system enter the corresponding self-locking mode.

[0102] Step 304, in the self-locking mode, the GPIOs are configured with different functions. Through GPIO function multiplexing, the requirements of DFT and SoC self-test are met.

[0103] The following specifically describes entering different locking modes according to different one-hot codes.

[0104] When the enable signal Test_en output by the enable signal interface is 0, the GPIOs generate a second test signal according to the second test requirement, and the AND gate in the enable module clamps the input to the second test signal of the test module, so that the second test signals output by all GPIO pins enter the function module, and the chip works in the normal function mode, that is, the function test state is triggered.

[0105] When the enable signal Test_en output by the enable signal interface is 1, according to the one-hot code output by the first JTAG pin, the system can enter the corresponding locked state for specific tests.

[0106] When the one-hot code is 100, FLASHLOCK outputs "0", "1", "1", and through one-hot code judgment, it controls the LPC to enter the FLASH test mode. The flashlock FF (flash lock function register) is selected; the TAP state machine enters the idle state, pulls the TMS to 0, and the taplock FF (TAP lock function register) is selected. The rest of the lock FFs are turned off. The CAT module is turned off, and the flash module is selected. The flash module can be tested according to the external signals output by the GPIOs.

[0107] When lock = 010, SCANLOCK outputs "0", "1", "0". After being judged by one - hot code, it controls LPC to enter the DFTSCAN test mode. After the input signal "1" is inverted, the scanlock FF (scan lock function register) is opened; the TAP state machine enters the idle state, pulls tms to 0, and the taplock FF (TAP lock function register) is opened. The remaining lock FFs are closed. The CAT module is selected, the flash module is turned off, and gpio is multiplexed as input signals to the channel in / out, test_clock, cat_update, and scan en pins of cat. The CAT module can be tested according to the external signals output by gpio.

[0108] When lock = 001, SOCLOCK outputs "0", "0", "1" respectively. After being judged by one - hot code, it controls LPC to enter the SoC self - test mode, which is a reserved self - test mode path. The FF of SOCTEST LOCK (function register of SoCtest) is opened; the TAP state machine enters the idle state; the taplock FF (TAP lock function register) is opened; the remaining lock FFs are closed. At this time, the debug mode of SoC is started, and the paths to other DFT - related CAT modules or flash modules are all closed.

[0109] It can be understood that the number of gpio pins can be modified, and it only needs to match the number of interfaces of the test module. When a JTAG module is set, to ensure the operation of the JTAG module, the number of gpio pins is at least 4. According to requirements, the number of test modules can be increased or decreased. At the same time, the number of bits of the one - hot code can be increased or decreased correspondingly. Figure 7 Another schematic diagram of scan LPC based on self - locking design is provided, as Figure 7 shown. The test module CAT is retained, and it can enter the dft scan test mode in the SCAN LOCK state and the self - test mode of function in the SOCTEST LOCK state respectively.

[0110] In one embodiment, a test method for a low-pin-count chip test circuit is provided, which is applied to the low-pin-count chip test circuit in any of the above embodiments. The method includes: when the enable module selects the test mode, configuring the control module and input / output pins of the low-pin-count chip test circuit according to the first test requirement, so that the control module generates a first one-hot code according to the first test requirement, and the input / output pins generate a first test signal according to the first test requirement; gating the test module based on the first one-hot code, so that the test module generates a test result in response to the first test signal; or, when the enable module selects the function mode, configuring the input / output pins of the low-pin-count chip test circuit according to the second test requirement, so that the input / output pins generate a second test signal according to the second test requirement, and the function module triggers a function test state and generates a test result in response to the second test signal.

[0111] Among them, the TDR (test data register) in the control module can be configured according to the test module that needs to be tested, so as to output the first one-hot code. Under different test modules and function modules, the input / output pins are configured with different functions to achieve GPIO function multiplexing and meet the first test requirement or the second test requirement.

[0112] Based on the same inventive concept, an embodiment of the present application also provides a chip test device for implementing the above-mentioned low-pin-count chip test circuit. The implementation solution provided by this device to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip test device provided below can refer to the limitations on the low-pin-count chip test circuit in the above text, and will not be repeated here.

[0113] In one embodiment, the chip test device includes the low-pin-count chip test circuit in each of the above embodiments. In one embodiment, the low-pin-count chip test circuit includes: input / output pins, a control module, at least two test modules, an enable module, and a function module; the control module is connected to the test module, the input / output pins are connected to the function module and the enable module, and the enable module is respectively connected to the control module and the test module for selecting the function mode and the test mode; among them, when the enable module selects the test mode, the control module generates a one-hot code according to the first test requirement to gate the test module based on the one-hot code; the input / output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or, when the enable module selects the function mode, the input / output pins generate a second test signal according to the second test requirement, and the function module triggers a function test state and generates a test result in response to the second test signal.

[0114] In one embodiment, the control module includes a first pin, a second pin, and a third pin. The first pin is connected to the test module, and the second pin is connected to the third pin. Among them, the first pin is used to generate a one-hot code; the second pin is used to generate a control signal of the control module according to the test requirements; the third pin is used to keep the control module in the current state based on the control signal after the control signal is generated by the second pin.

[0115] In one embodiment, the circuit further includes a register module. The first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module. Among them, the register module is used to control the gating of the test module according to the one-hot code and keep the control module in the current state according to the control signal.

[0116] In one embodiment, the register module includes a first shift register unit, a second shift register unit, and a first logic gate unit. Among them, the first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit; the second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit; the first output end of the first logic gate unit is further connected to the third pin, and multiple second output ends of the first logic gate unit are connected to the test module.

[0117] In one embodiment, the register module includes multiple first shift register units corresponding to multiple first pins, and the first logic gate unit includes an AND gate and a first OR gate. Among them, the input ends of each first OR gate are respectively connected to the output ends of the multiple first shift register units and the output end of the second shift register unit; the output ends of the first OR gates and the input end of the AND gate are connected, and the output end of the first OR gate is further connected to the corresponding test module; the output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0118] In one embodiment, the register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate. Among them, the first pin is connected to the input end of the third shift register unit; the input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit; the output end of the second OR gate and the input end of the AND gate are connected; the control module generates a one-hot code according to the third test requirement to turn off the test module based on the one-hot code.

[0119] In one embodiment, the enabling module includes an enabling signal interface and a second logic gate unit. One end of the second logic gate unit is connected to the enabling signal interface and the input / output pin, the other end of the second logic gate unit is connected to the test module, and the enabling signal interface is also connected to the functional module. Wherein, when the enabling signal interface outputs a first level signal to the second logic gate unit, the functional mode is selected, the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers the functional test state in response to the second test signal and generates a test result. When the enabling signal interface outputs a second level signal to the second logic gate unit, the test mode is selected, the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

[0120] In one embodiment, the control module is a JTAG module.

[0121] In the description of this specification, the descriptions referring to the terms "some embodiments", "other embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0122] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0123] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A low-pin-count chip test circuit, characterized in that Including: Input / output pins, a control module, at least two test modules, an enable module, and a function module; the control module is connected to the test module, the input / output pins are connected to the function module and the enable module, and the enable module is respectively connected to the control module and the test module for selecting a function mode and a test mode; wherein, When the enable module selects the test mode, the control module generates a one-hot code according to a first test requirement to select the test module based on the one-hot code; the input / output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or, When the enable module selects the function mode, the input / output pins generate a second test signal according to a second test requirement, and the function module triggers a function test state and generates a test result in response to the second test signal.

2. The low pin count chip test circuit according to claim 1, characterized in that The control module includes a first pin, a second pin, and a third pin, the first pin is connected to the test module, and the second pin is connected to the third pin; wherein, The first pin is used to generate the one-hot code; The second pin is used to generate a control signal of the control module according to the test requirement; The third pin is used to control the control module to maintain the current state based on the control signal after the second pin generates the control signal.

3. The low pin count chip test circuit according to claim 2, wherein The circuit further includes a register module, the first pin and the second pin are connected to an input end of the register module, and an output end of the register module is connected to the third pin and the test module; wherein, The register module is used to control the selection of the test module according to the one-hot code and control the control module to maintain the current state according to the control signal.

4. The low-pin-count chip test circuit according to claim 3, wherein The register module includes a first shift register unit, a second shift register unit, and a first logic gate unit; wherein, The first pin is connected to an input end of the first shift register unit, and an output end of the first shift register unit is connected to an input end of the first logic gate unit; The second pin and a first output end of the first logic gate unit are connected to an input end of the second shift register unit, and an output end of the second shift register unit is connected to an input end of the first logic gate unit; The first output end of the first logic gate unit is further connected to the third pin, and a plurality of second output ends of the first logic gate unit are connected to the test module.

5. The low pin-count chip test circuit according to claim 4, characterized in that, The register module includes a plurality of first shift register units respectively corresponding to a plurality of first pins, and the first logic gate unit includes an AND gate and a first OR gate; wherein, Input ends of each first OR gate are respectively connected to output ends of a plurality of the first shift register units and an output end of the second shift register unit; Output ends of each first OR gate are connected to an input end of the AND gate, and the output ends of the first OR gate are further connected to the corresponding test module; An output end of the AND gate is connected to an input end of the second shift register unit and the third pin of the control module.

6. The low-pin-count chip test circuit according to claim 5, wherein, The register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate, wherein, The first pin is connected to the input end of the third shift register unit; The input ends of the second OR gate are connected to the output end of the third shift register unit and the output end of the second shift register unit; The output end of the second OR gate is connected to the input end of the AND gate; The control module generates a one-hot code according to a third test requirement to turn off the test module based on the one-hot code.

7. The low-pin-count chip test circuit according to claim 6, wherein The enabling module includes an enabling signal interface and a second logic gate unit. One end of the second logic gate unit is connected to the enabling signal interface and the input / output pin, the other end of the second logic gate unit is connected to the test module, and the enabling signal interface is further connected to the functional module; wherein, When the enabling signal interface outputs a first level signal to the second logic gate unit, the functional mode is selected and the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers a functional test state and generates a test result in response to the second test signal; When the enabling signal interface outputs a second level signal to the second logic gate unit, the test mode is selected and the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

8. The low-pin-count chip test circuit according to claim 7, characterized in that, The second logic gate unit includes a plurality of third AND gates and a plurality of fourth AND gates. The input ends of the third AND gates are connected to the input / output pin and the enabling signal interface; the output ends of the third AND gates are connected to the input ends of the fourth AND gates, the register module is connected to the input ends of the fourth AND gates, and the fourth AND gates are connected to the test unit.

9. A test method for a test circuit of a low-pin-count chip, characterized in that, Applied to the low-pin-count chip test circuit according to any one of claims 1 to 8, the method includes: When the enabling module selects the test mode, configuring the control module and the input / output pin of the low-pin-count chip test circuit according to a first test requirement, so that the control module generates a one-hot code according to the first test requirement, and the input / output pin generates a first test signal according to the first test requirement; selecting the test module based on the one-hot code, so that the test module generates a test result in response to the first test signal; or, When the enabling module selects the functional mode, configuring the input / output pin of the low-pin-count chip test circuit according to a second test requirement, so that the input / output pin generates a second test signal according to the second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal.

10. A chip testing device, characterized in that, Including the low-pin-count chip test circuit according to any one of claims 1 to 8.

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