Low pin count chip test circuit, test method and equipment

Abstract

The present application relates to a low-pin-count chip test circuit, test method and device. The low-pin-count chip test circuit includes: a control module connected to a test module, input and output pins connected to a functional module and an enable module, and the enable module is connected to the control module and the test module respectively; wherein, when the enable module selects the test mode, the control module generates a one-hot code according to a first test requirement to select the test module based on the one-hot code; the input and output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or, when the enable module selects the functional mode, the input and output pins generate a second test signal according to a second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal, thereby solving the problem that the number of input and output pins cannot meet the chip test requirements.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a low-pin-count chip testing circuit, testing method, and equipment. Background Art

[0002] In the field of chip testing, some projects have strict restrictions on the number of GPIOs (General Purpose Input / Output). Because the project also needs to implement DFT (Design for Test) and SoC (System on Chip) self-test functions, the number of GPIOs planned for the chip testing project cannot meet the DFT design and testing requirements.

[0003] There is currently no effective solution to the problem in related technologies that the number of GPIOs cannot meet the chip testing requirements. Summary of the Invention

[0004] Based on this, it is necessary to provide a low-pin-count chip test circuit, test method and equipment to solve the problem that the number of input and output pins cannot meet the chip testing requirements.

[0005] In a first aspect, a low-pin-count chip test circuit is provided in this embodiment, comprising: input and output pins, a control module, at least two test modules, an enable module, and a functional module; the control module is connected to the test module, the input and output pins are connected to the functional module and the enable module, and the enable module is connected to the control module and the test module, respectively, for selecting a functional mode and a test mode; wherein,

[0006] When the enabling module enables the test mode, the control module generates a one-hot code according to a first test requirement to enable the test module based on the one-hot code; the input and output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or

[0007] When the enabling module selects the functional mode, the input and output pins generate a second test signal according to the second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal.

[0008] In some embodiments, the control module includes a first pin, a second pin, and a third pin, the first pin is connected to the test module, and the second pin is connected to the third pin; wherein,

[0009] The first pin is used to generate the one-hot code;

[0010] The second pin is used to generate a control signal of the control module according to the test requirement;

[0011] The third pin is used to control the control module to maintain a current state based on the control signal after the second pin generates the control signal.

[0012] In some embodiments, the circuit further includes a register module, the first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module; wherein,

[0013] The register module is used to control the gating of the test module according to the one-hot code, and to control the control module to maintain a current state according to the control signal.

[0014] In some embodiments, the register module includes a first shift register unit, a second shift register unit and a first logic gate unit; wherein,

[0015] The first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit;

[0016] The second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit;

[0017] The first output end of the first logic gate unit is also connected to the third pin, and a plurality of second output ends of the first logic gate unit are connected to the test module.

[0018] In some embodiments, the register module includes a plurality of first shift register units corresponding to a plurality of first pins respectively, and the first logic gate unit includes an AND gate and a first OR gate; wherein,

[0019] An input end of each of the first OR gates is respectively connected to the output ends of the first shift register units and the output end of the second shift register unit;

[0020] The output end of each first OR gate is connected to the input end of the AND gate, and the output end of the first OR gate is also connected to the corresponding test module;

[0021] The output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0022] In some embodiments, the register module further includes a third shift register unit, the first logic gate unit further includes a second OR gate, wherein,

[0023] The first pin is connected to the input end of the third shift register unit;

[0024] The input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit;

[0025] The output terminal of the second OR gate is connected to the input terminal of the AND gate;

[0026] The control module generates a one-hot code according to a third test requirement, so as to shut down the test module based on the one-hot code.

[0027] In some embodiments, the enable module includes an enable signal interface and a second logic gate unit, one end of the second logic gate unit is connected to the enable signal interface and the input / output pin, the other end of the second logic gate unit is connected to the test module, and the enable signal interface is also connected to the functional module; wherein,

[0028] In the case where the enable signal interface outputs a first level signal to the second logic gate unit, the functional mode is enabled, the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers a functional test state and generates a test result in response to the second test signal;

[0029] When the enable signal interface outputs a second level signal to the second logic gate unit, the test mode is selected, the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

[0030] In some embodiments, the second logic gate unit includes multiple third AND gates and multiple fourth AND gates, the input end of the third AND gate is connected to the input and output pin and the enable signal interface; the output end of the third AND gate is connected to the input end of the fourth AND gate, the register module is connected to the input end of the fourth AND gate, and the fourth AND gate is connected to the test unit.

[0031] In a second aspect, a method for testing a low-pin-count chip test circuit is provided in this embodiment, and is applied to the low-pin-count chip test circuit described in the first aspect. The method includes:

[0032] When the enabling module enables the test mode, the control module and the input / output pins of the low-pin-count chip test circuit are configured according to a first test requirement, so that the control module generates a one-hot code according to the first test requirement, and the input / output pins generate a first test signal according to the first test requirement; the test module is enabled based on the one-hot code, so that the test module generates a test result in response to the first test signal; or

[0033] When the enabling module selects the functional mode, the input and output pins of the low-pin-count chip test circuit are configured according to the second test requirement, so that the input and output pins generate a second test signal according to the second test requirement, and the functional module triggers the functional test state in response to the second test signal and generates a test result.

[0034] In a third aspect, a chip testing device is provided in this embodiment, comprising the low-pin-count chip testing circuit described in the first aspect.

[0035] The above-mentioned low-pin-count chip test circuit, test method and equipment enter the test mode or functional mode by enabling the module. In the test mode, the one-hot code generated by the control module is used to select the test module for testing. Without increasing the number of input and output pins, the needs of various chip tests are met, and the problem that the number of input and output pins cannot meet the chip testing needs is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 1 is a block diagram of a low-pin-count chip test circuit according to an embodiment;

[0038] Figure 2 1. A schematic diagram of a flow chart of a low-pin-count chip test circuit in one embodiment;

[0039] Figure 3 It is a structural block diagram of another low pin count chip test circuit in another embodiment;

[0040] Figure 4 is a structural block diagram of a register module in one embodiment;

[0041] Figure 5 A schematic diagram of a scan LPC based on a self-locking design in one embodiment;

[0042] Figure 6 A schematic diagram of one-hot code determination in one embodiment;

[0043] Figure 7 FIG. 4 is a schematic diagram of a scan LPC in an embodiment. FIG. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0046] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0047] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0048] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0049] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0050] LPC (Low Pin Count) is a low-power, highly integrated system bus standard, mainly used to connect processors and peripheral devices such as memory controllers, input and output pins, etc. It is particularly suitable for mobile devices and low-power applications to reduce the number of pins on the circuit board and improve the flexibility and efficiency of system design.

[0051] GPIO (General Purpose Input / Output) refers to the number of general-purpose input / output pins available on an integrated circuit (IC), such as a microcontroller or system-on-chip (SoC). These pins can be configured as inputs or outputs, used for communication and control with other devices or circuits. Some projects have strict GPIO limits, but require features like DFT and SoC self-test, and the GPIO limit may not meet chip testing requirements.

[0052] In one embodiment, Figure 1 A structural block diagram of a low pin count chip test circuit is provided. Figure 1 As shown, the low-pin-count chip test circuit includes: input and output pins, a control module, at least two test modules, an enable module and a functional module; the control module is connected to the test module, the input and output pins are connected to the functional module and the enable module, and the enable module is connected to the control module and the test module respectively, for selecting the functional mode and the test mode.

[0053] The low-pin-count chip test circuitry can include multiple test modules, which are used to test the chip and determine whether it functions properly after manufacturing. Functional modules, also known as function modules, are the modules on the chip responsible for executing actual application functions. By triggering the functional test state, these function modules can be verified and tested.

[0054] Input / output pins, also known as I / O interfaces, are used to transmit signals required for test mode to an enabled test module or signals required for functional mode to a functional module, as well as to transmit input signals to the test module or functional module. Low-pin-count chip test circuits may include one or more input / output pins. It will be understood that when multiple input / output pins are included, each input / output pin is connected to a control module, a functional module, and a test module, respectively.

[0055] The control module is used to output a one-hot code. The one-hot code is a coding method in which each possible value is represented by only one code bit, and only one code bit is "hot" (i.e., 1), and the rest of the code bits are "cold" (i.e., 0). The control module can output multiple one-hot codes through multiple pins, each pin corresponding to a different connected test module, so that different test modules can be controlled to be turned on or off by different one-hot codes. By increasing the length of the code bit, multiple test modes can be set accordingly. For example, a 5-bit one-hot code can support 5 independent test modes. Optionally, based on the first test requirement, a binary code is output to the control module, and the control module converts and outputs a one-hot code according to the binary input in the first test requirement. The control module can use a decoder to convert the binary input into a one-hot code output, or realize the conversion of the one-hot code through a programmable array or a programmable logic device.

[0056] The enable module is used to receive an enable signal and, based on the enable signal, adjust the validity of the output signal of the input / output pin according to the test mode. Optionally, when the enable module selects the functional mode, the level signal output by the enable module is used to make the signal output by the input / output pin to the test module an invalid signal; when the enable module selects the test mode, the level signal output by the enable module is adjusted so that the signal output by the input / output pin to the test module is a valid signal. Furthermore, according to actual needs, the input / output pin can also be connected to the functional module through the enable module, so that the enable module can be used to limit the signal output by the input / output pin to the functional module. Among them, the enabling mechanism of the enable module can be implemented by basic logic gates. For example, using logic gates such as AND gates or OR gates to perform logical calculations on the signal output by the input / output pin and the signal output by the enable module, so as to achieve the effect of enabling or shielding the validity of the signal output by the input / output pin.

[0057] Figure 2 A flow chart of a low pin count chip test circuit is provided. Figure 2 As shown, when the module is enabled in test mode, the control module generates a one-hot code according to a first test requirement to enable the test module based on the one-hot code; the input and output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal. Alternatively, when the module is enabled in functional mode, the input and output pins generate a second test signal according to a second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal.

[0058] Optionally, when the enable module selects the test mode, the enable module receives an enable signal and controls the input and output pins to output the first test signal of each test module as a valid signal according to the enable signal. The control module converts the binary input in the first test requirement into a one-hot code output. Each one-hot code is used to control a different test module, and there is only one bit in the one-hot code that is 1. Different one-hot codes correspond to the selection of different test modules. Taking a 3-bit one-hot code as an example, the one-hot code can control the selection of up to 3 different test modules.

[0059] Optionally, when the enable module selects the functional mode, the enable module receives the enable signal and controls the input and output pins to output signals to each test module as invalid signals according to the enable signal, that is, only the functional module can receive the second test signal of the input and output pins and trigger the functional test state based on the second test signal.

[0060] The first test requirement and the second test requirement can be modified according to the actual test requirements of the test module and the functional module, and are not limited here.

[0061] In this embodiment, under the test module, the control module generates a one-hot code according to the first test requirement, and the one-hot code controls the on and off of the test module. Without increasing the number of input and output pins, different test modules can be enabled and enter the test; in the functional mode, the functional test status of the functional module can still be triggered based on the input and output pins; through the multiplexing of input and output pins, various test requirements of the chip are met, and the problem that the number of input and output pins cannot meet the chip testing requirements is solved.

[0062] In one embodiment, the control module includes a first pin, a second pin and a third pin, the first pin is connected to the test module, and the second pin is connected to the third pin; wherein, the first pin is used to generate a one-hot code; the second pin is used to generate a control signal of the control module according to the test requirements; and the third pin is used to maintain the current state of the control module based on the control signal after the second pin generates the control signal.

[0063] The number of first pins is greater than or equal to the number of one-hot codes, so that each one-hot code can be connected to a corresponding test module via multiple first pins. The control signal is used to adjust the operating state of the control module. Optionally, the first pin is connected to the third pin. After the second pin generates a control signal, the control signal is input to the third pin and causes the control module to not perform a data shift operation or update the register content, that is, to maintain the current state of the control module.

[0064] Optionally, the control module can be maintained in the current state through a state machine: a state machine is provided in the control module, and when the first pin is used to generate a one-hot code, the state machine outputs a control signal through the second pin, so that the third pin receives the control signal and enters a waiting state based on the control signal.

[0065] In this embodiment, the test module receives the corresponding one-hot code respectively through the first pin, and the one-hot code output by the first pin can always be maintained at the expected value through the second pin and the third pin, thereby avoiding the chip test failure caused by the change of the one-hot code output by the first pin, and improving the anti-interference ability of the low-pin-count chip test circuit.

[0066] In one embodiment, the low-pin-count chip test circuit further includes a register module, wherein the first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module; wherein the register module is used to control the selection of the test module according to the one-hot code, and control the control module to maintain the current state according to the control signal.

[0067] The register module includes one or more registers. A clock signal generates pulses within a clock cycle, and each register performs operations such as signal writing and reading within a time period based on the pulse signal. Optionally, the register module includes multiple registers, and the first pin and the second pin are respectively connected to the input ends of different registers, thereby controlling the output of the one-hot code and the control signal through the multiple registers.

[0068] Optionally, when the module is enabled to select the test mode, the one-hot code is transmitted to the register module through the clock signal, and the register connected to the first pin is opened, thereby selecting the corresponding test module; while the control module outputs the one-hot code, the control signal is output to the third pin according to the register connected to the second pin, so that the control module maintains the current state.

[0069] Furthermore, the output of the register module is connected to the test module through the enable module. Figure 3 Another low pin count chip test circuit block diagram is provided, such as Figure 3 As shown, when the enable module selects the test mode, the register module outputs a signal to the test module through the enable module; when the enable module selects the functional mode, the signal output by the register module is not transmitted to the test module.

[0070] In this embodiment, the gating of the test module and the output of the control signal can be controlled by the register, thereby improving the stability and controllability of the low-pin-count chip test circuit.

[0071] Furthermore, in one embodiment, the register module includes a first shift register unit, a second shift register unit and a first logic gate unit; wherein, the first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit; the second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit; the first output end of the first logic gate unit is also connected to the third pin, and multiple second output ends of the first logic gate unit are connected to the test module.

[0072] The register module includes a plurality of first shift register units corresponding to the plurality of first pins, and the number of the first shift register units is consistent with the number of the first pins. In the case of providing a plurality of first pins, the first pins can be connected to the input end of each first shift register unit.

[0073] Optionally, the first shift register unit may further include a shift register and a NOT gate, wherein the output of the first pin is connected to the input of the NOT gate, the output of the NOT gate is correspondingly connected to the input of the shift register, and the output of the shift register is connected to the input of the first logic gate unit. The NOT gate regulates the signal input to the shift register.

[0074] Similarly, the second shift register unit may include a shift register, or may include an inverter, an AND gate, and a shift register connected in sequence. The structures of the first shift register unit and the second shift register unit may be adjusted according to test requirements, which will not be described in detail here.

[0075] The output ends of the first shift register unit and the second shift register unit are connected to the input end of the first logic gate unit. Therefore, the first logic gate unit can perform a logical operation on the signal output after being processed by the first shift register unit and the control signal output after being processed by the second shift register unit, ensuring that when the control module simultaneously outputs the one-hot code and the control signal, the output signal of the second output end of the first logic gate unit selects the corresponding test module, and the output signal of the first output end of the first logic gate unit keeps the control module in the current state.

[0076] In this embodiment, by setting a first logic gate unit to simultaneously receive the signal output by the first shift register unit and the control signal output by the second shift register unit, it is ensured that chip testing is achieved when the control module synchronously outputs the one-hot code and the control signal, thereby avoiding the situation where the control module only outputs the one-hot code or only outputs the control signal, resulting in unstable chip testing.

[0077] According to the different internal structures of the first shift register unit and the second shift register unit, the first logic gate unit can be adaptively adjusted according to the level of the output signal of the first shift register unit and the second shift register unit. In one embodiment, Figure 4 A structural block diagram of a register module is provided, such as Figure 4 As shown, the register module includes a plurality of first shift register units corresponding to a plurality of first pins respectively, and the first logic gate unit includes an AND gate and a first OR gate; wherein, the input end of each first OR gate is respectively connected to the output end of the plurality of first shift register units and the output end of the second shift register unit; the output end of each first OR gate is connected to the input end of the AND gate, and the output end of the first OR gate is also connected to the corresponding test module; the output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0078] The first OR gate performs a logical OR operation on the signal output after being processed by the first shift register unit and the control signal output after being processed by the second shift register unit. In the case of multiple first shift register units and one second shift register unit, the first input ends of different first OR gates are respectively connected to different first shift register units, and the first input end of each first OR gate is also connected to the second shift register unit.

[0079] In this embodiment, after the AND gate performs a logic "AND" calculation on the outputs of the plurality of first OR gates, the calculation result of the AND gate is inputted into the second shift register unit again, thereby constructing a feedback loop to improve the stability of the control signal output.

[0080] In one embodiment, the register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate, wherein the first pin is connected to the input end of the third shift register unit; the input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit; the output end of the second OR gate is connected to the input end of the AND gate; and the control module generates a one-hot code according to the third test requirement to shut down the test module based on the one-hot code.

[0081] The one-hot code generated by the control module according to the third test requirement is different from the one-hot code generated by the second test requirement. The third shift register unit includes at least a shift register.

[0082] Optionally, the third shift register unit includes a NOT gate and a shift register connected in sequence. After the control module generates a one-hot code according to the third requirement, a first pin in the control module is connected to the NOT gate in the third shift register unit. The second OR gate performs a logical OR operation on the signal processed and output by the third shift register unit and the control signal output by the second shift register unit, ensuring that when the control unit simultaneously outputs the one-hot code and the control signal, since the output end of the second OR gate is not connected to any test module, none of the test modules are selected.

[0083] In this embodiment, when the module is enabled to select the test mode, the control module generates a one-hot code according to the third test requirement, so that each test module is turned off, and a reserved self-test mode path is obtained, thereby improving the scalability of the low-pin-count chip test circuit.

[0084] In one embodiment, the enable module includes an enable signal interface and a second logic gate unit, one end of the second logic gate unit is connected to the enable signal interface and the input and output pins, the other end of the second logic gate unit is connected to the test module, and the enable signal interface is also connected to the functional module; wherein, when the enable signal interface outputs a first level signal to the second logic gate unit, the functional mode is selected, the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers the functional test state in response to the second test signal and generates a test result; when the enable signal interface outputs a second level signal to the second logic gate unit, the test mode is selected, the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

[0085] The enable signal interface is used to receive an enable signal. Optionally, the second logic gate unit includes multiple third AND gates, each of which has an input connected to the input / output pins and is also connected to the enable signal interface. The first-level signal is low, and the second-level signal is high. Depending on the second logic gate unit, the corresponding first-level signal and second-level signal may be different. For example, when the second logic gate unit includes multiple NAND gates, the first-level signal is high, and the second-level signal is low. No restrictions are imposed on the first-level signal and the second-level signal. Optionally, the second logic gate unit includes multiple third AND gates and multiple fourth AND gates, each of which has an input connected to the input / output pins and the enable signal interface; the output of the third AND gate is connected to the input of the fourth AND gate; the first OR gate in the register module is connected to the input of the fourth AND gate via an inverter; and the fourth AND gate is connected to the test unit. Thus, the second logic gate unit limits the output of the register module's signal to the test module.

[0086] Furthermore, the control module can be enabled via an enable signal: the enable signal interface is connected to the enable pin of the control module. When the enable signal interface outputs a second-level signal, the control module can output a one-hot code; when the enable signal interface outputs a first-level signal, the control module does not output a one-hot code.

[0087] Furthermore, the input of the control signal can also be limited by the enable module. The register unit can also be provided with a first AND gate and a second AND gate. The first AND gate is the logic gate connected to the output end of the first OR gate in the above embodiment. The input end of the second AND gate is respectively connected to the first AND gate and the second logic unit, and the output end of the second AND gate is connected to the third pin of the control module. When the enable signal interface outputs a first level signal, a logic "AND" calculation is performed through the second AND gate to prohibit the control signal processed by the register unit from being input to the third pin of the control module. Optionally, the other end of the second logic gate unit is connected to the clock pins of the test module and the control module, so that the clock signal input during the operation of the control module is synchronized with the test module.

[0088] In this embodiment, the enabling module is composed of the enabling signal interface and the second logic gate unit, so that the switching between the test mode and the functional mode can be realized based on a simple structure.

[0089] In one embodiment, the control module is a JTAG module.

[0090] Optionally, the JTAG (Joint Test Action Group) module includes multiple LOCK TDRs (Test Data Registers), the number of which matches the number of bits in the generated one-hot code. The LOCK TDRs are configured via ijtag (Internal JTAG) to generate corresponding one-hot codes based on the first or third test requirements. The TDRs (Test Data Registers) store test mode configuration data. By configuring the TDRs with one-hot codes, different test modules can be selected to enter different test modes, such as boundary scan testing and functional testing, to meet GPIO multiplexing requirements.

[0091] Optionally, the JTAG module includes a TAP (Test Access Port) state machine, wherein the second pin of the JTAG module is an idle pin, and the third pin is a TMS pin. The TAP state machine in the control module controls the JTAG interface as follows: after the JTAG module completes a JTAG operation to generate a one-hot code, the TAP state machine outputs a control signal from the second pin to the third pin, placing the control module in an idle state.

[0092] In one embodiment, the chip project needs to reuse pins such as JTAG pins, scan_en scan enable, TDI test data input, TDO test data output, and TCK test clock input. The number of GPIOs planned in conventional projects often cannot meet the DFT design and testing requirements. Therefore, it is difficult to complete the DFT (Design for Testability) design under the limited number of GPIOs, and to switch between function mode and DFT mode according to test requirements or functional requirements to check defects and faults generated during the chip manufacturing process. Based on this, Figure 5 A schematic diagram of the scan chain LPC based on self-locking design is provided, such as Figure 5 As shown, function refers to the functional module. CAT and flash are two different test modules. GPIOs represent input and output pins. GPIO1 is multiplexed as the function's pin input, the CAT module's test_clock, and the JTAG module's tck pin input; GPIO0 is multiplexed as the function's pin input, the CAT module's scan_in, and the JTAG module's tdi pin input; GPIO3 is multiplexed as the function's pin input, the CAT module's scan_en, and the JTAG module's tms pin input; GPIO5 is multiplexed as the cat_update signal input; GPIO4 is multiplexed as the flash's biorbit input; and GPIO2 is multiplexed as the function module's output. JTAG is the control module, including the first pins: FLASHLOCK, SOCLOCK, and SCANLOCK; the second pin is idle; and the third pin is tms. The enable module includes the enable signal interface test_en, an AND gate, and an inverter.

[0093] The register module includes a first shift register unit, a second shift register unit, a third shift register unit, and a first logic gate unit. The first shift register unit includes a NOT gate and a shift register connected in sequence. The second shift register unit includes an inverter, an AND gate, and a shift register connected in sequence. The third shift register unit includes a NOT gate and a shift register connected in sequence. The first logic gate unit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate. The input of the first OR gate is connected to the second shift register unit, the other input of the first OR gate is connected to the first shift register unit, the output of the first OR gate is connected to the input of the first AND gate and to the test module, the input of the second OR gate is connected to the output of the third shift register unit and the output of the second shift register unit, and the output of the second OR gate is connected to the input of the first AND gate. The output of the first AND gate is connected to the input of the second shift register unit and the input of the second AND gate. The input of the second AND gate is also connected to the input of the enable module, and the output of the second AND gate is connected to the third pin.

[0094] Among them, different test modes can be designed by dividing and reusing functions according to different functional modes in chip test requirements. Figure 5 As shown in the figure, four self-locking modes are designed: SCAN LOCK mode is used to perform DFT scantest (scan test) in testability design; SOCTEST LOCK mode is used to perform SoC debug test (debug test); FLASH LOCK mode is used to perform flash test, connecting the input and output pins to the flash, and the flash test is controlled by the external signals output by the input and output pins; TAP LOCK mode is used to configure the TAP state machine and ijtag in JTAG, and make the TAP state machine in idle state and the value of TDR in JTAG remain at the expected value.

[0095] Optionally, Figure 5 The JTAG network contains three 1-bit lock time delay (TDR) registers: LOCK_tdr0, LOCK_tdr1, and LOCK_tdr2. These registers are configured using IJTAG to generate one-hot codes. Different lock states are entered based on the codes, enabling GPIO function reuse and meeting the requirements of design-for-test (DFT) and SoC self-testing.

[0096] The three 1-bit LOCK TDR bits (LOCK_tdr0, LOCK_tdr1, and LOCK_tdr2) can be combined to form three possible one-hot codes: 100, 010, and 001. 100 represents FLASH LOCK. Outputting the one-hot code 100 causes the system to enter flash test mode and the LPC to enter the FLASH LOCK state. 010 represents SCAN LOCK. Outputting the one-hot code 010 causes the system to enter DFT scan test mode and the LPC to enter the SCAN LOCK state. 001 represents SOCTEST LOCK. Outputting the one-hot code 001 causes the function to enter self-test mode and the LPC to enter the SOCTEST LOCK state.

[0097] like Figure 5 As shown in the figure, after the three 1-bit LOCK TDRs output a one-hot code, the SCAN LOCK state, FLASH LOCK state, or TAP LOCK state can be determined by logic A, logic B, and logic C respectively. Taking the SCAN LOCK state as an example, Figure 6 A schematic diagram of one-hot code judgment is provided, such as Figure 6 As shown in the figure, the JTAG module includes registers 0 (tdr0), 1 (tdr1), and 2 (tdr2), each of which outputs a level signal of "0" or "1." The level signal and the constant level signal "0" output by tdr0 are input to the first XOR gate, the level signal and the constant level signal "1" output by tdr1 are input to the second XOR gate, and the level signal and the constant level signal "0" output by tdr2 are input to the third XOR gate. The outputs of the three XOR gates are connected to an OR gate. When the output code is 010, the LPC enters the SCAN LOCK state based on the output of the OR gate. When the output code is 100 or 001, the LPC does not enter the SCAN LOCK state. Similarly, according to the one-hot code corresponding to the FLASH LOCK state or TAP LOCK state, the constant level signal input to the XOR gate in Logic B and Logic C is adjusted to realize the one-hot code judgment of the FLASH LOCK state or TAP LOCK state. Logic B and Logic C are not described in detail here. It can be understood that, in addition to the Figure 5 In addition to the method shown in the figure, one-hot code determination can also be achieved through other methods such as software algorithms or FPGA (field programmable gate array).

[0098] Through the above four self-locking modes, the five GPIOs can function normally while also completing the scan test, MBIST test, flash test, and SoC self-test mode required by DFT. The specific execution logic is as follows:

[0099] Step 301 : Define and determine the self-locking mode required for the test, where the self-locking mode is one of FLASH LOCK, SCAN LOCK, SOCTEST LOCK, and TAP LOCK.

[0100] Step 302 : Configure the TDR (Test Data Register) in the JTAG according to the required self-locking mode.

[0101] Step 303: The configured TDR causes the system to enter a corresponding self-locking mode.

[0102] Step 304: In the self-locking mode, the GPIO is configured to different functions. By multiplexing the GPIO functions, the requirements of DFT and SoC self-test are met.

[0103] The following describes in detail how to enter different locking modes according to different one-hot codes.

[0104] When the enable signal Test_en output by the enable signal interface = 0, the gpio generates a second test signal according to the second test requirement, and the AND gate in the enable module clamps the second test signal input to the test module, so that the second test signals output by all gpio pins enter the function module, and the chip works in normal function mode, that is, the functional test state is triggered.

[0105] When the enable signal Test_en = 1 output by the enable signal interface, the system can enter the corresponding lock state according to the one-hot code output by the first pin of the jtag to perform specific tests.

[0106] When the one-hot code is 100, FLASHLOCK outputs "0," "1," and "1." Based on the one-hot code, the LPC enters FLASH test mode. The flashlock FF (flash lock function register) is enabled; the TAP state machine enters the idle state, pulls tms to 0, and enables the taplock FF (TAP lock function register). The remaining lock FFs are disabled. The CAT module is shut down, and the flash module is enabled. The flash module can then be tested based on the external signals output by the GPIOs.

[0107] When lock = 010, SCANLOCK outputs "0," "1," and "0," controlling the LPC to enter DFTSCAN test mode via a one-hot code. After the input signal "1" is negated, the scanlock FF (scan lock function register) is enabled. The TAP state machine enters the idle state, pulls tms to 0, and opens the taplock FF (TAP lock function register). The remaining lock FFs are disabled. The CAT module is enabled, the flash module is disabled, and the GPIOs are multiplexed as input signals to the CAT channel in / out and the test_clock, CAT_update, and scan_en pins. The CAT module can be tested based on the external signals output by the GPIOs.

[0108] When lock = 001, SOCLOCK outputs "0," "0," and "1," respectively. A one-hot code determines the LPC's entry into SoC self-test mode. This is the reserved self-test mode path. The SOCTEST LOCK FF (SoCtest function register) is enabled; the TAP state machine enters the idle state; the taplock FF (TAP lock function register) is enabled; and the remaining lock FFs are disabled. This activates the SoC's debug mode, and all other paths to the DFT-related CAT module or flash module are closed.

[0109] It is understood that the number of GPIO pins can be modified to match the number of test module interfaces. When a JTAG module is provided, a minimum of four GPIO pins is required to ensure JTAG operation. The number of test modules can be increased or decreased as needed, and the number of one-hot bits can be increased or decreased accordingly. Figure 7 A schematic diagram of another scan LPC based on self-locking design is provided, such as Figure 7 As shown, the test module CAT is retained, which can correspond to entering the dft scan test mode in the SCAN LOCK state and the function self-test mode in the SOCTEST LOCK state.

[0110] In one embodiment, a test method for a low-pin-count chip test circuit is provided, which is applied to the low-pin-count chip test circuit in any of the above embodiments. The method includes: when the module is enabled to select the test mode, configuring the control module and input-output pins of the low-pin-count chip test circuit according to a first test requirement, so that the control module generates a first one-hot code according to the first test requirement, and the input-output pins generate a first test signal according to the first test requirement; selecting the test module based on the first one-hot code, so that the test module generates a test result in response to the first test signal; or, when the module is enabled to select the functional mode, configuring the input-output pins of the low-pin-count chip test circuit according to a second test requirement, so that the input-output pins generate a second test signal according to the second test requirement, and the functional module triggers the functional test state in response to the second test signal and generates a test result.

[0111] The TDR (Test Data Register) in the control module can be configured based on the test module to output the first one-hot code. In different test modules and functional modules, the input and output pins are configured with different functions, enabling GPIO function multiplexing to meet the first or second test requirements.

[0112] Based on the same inventive concept, embodiments of the present application also provide a chip testing device for implementing the low-pin-count chip testing circuit described above. The solution provided by this device is similar to the solution described in the above-mentioned method. Therefore, the specific limitations in one or more chip testing device embodiments provided below can be found in the above-mentioned limitations on low-pin-count chip testing circuits and will not be further elaborated here.

[0113] In one embodiment, a chip testing device includes the low-pin-count chip testing circuit of each of the above embodiments. In one embodiment, the low-pin-count chip testing circuit includes: input / output pins, a control module, at least two test modules, an enable module, and a functional module; the control module is connected to the test module, the input / output pins are connected to the functional module and the enable module, and the enable module is connected to the control module and the test module, respectively, for selecting a functional mode and a test mode; wherein, when the enable module selects the test mode, the control module generates a one-hot code according to a first test requirement to select the test module based on the one-hot code; the input / output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or, when the enable module selects the functional mode, the input / output pins generate a second test signal according to a second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal.

[0114] In one embodiment, the control module includes a first pin, a second pin and a third pin, the first pin is connected to the test module, and the second pin is connected to the third pin; wherein, the first pin is used to generate a one-hot code; the second pin is used to generate a control signal of the control module according to the test requirements; and the third pin is used to maintain the current state of the control module based on the control signal after the second pin generates the control signal.

[0115] In one embodiment, the circuit further includes a register module, wherein the first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module; wherein the register module is used to control the selection of the test module according to the one-hot code, and control the control module to maintain the current state according to the control signal.

[0116] In one embodiment, the register module includes a first shift register unit, a second shift register unit and a first logic gate unit; wherein, the first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit; the second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit; the first output end of the first logic gate unit is also connected to the third pin, and multiple second output ends of the first logic gate unit are connected to the test module.

[0117] In one embodiment, the register module includes a plurality of first shift register units corresponding to a plurality of first pins respectively, and the first logic gate unit includes an AND gate and a first OR gate; wherein the input end of each first OR gate is respectively connected to the output end of the plurality of first shift register units and the output end of the second shift register unit; the output end of each first OR gate is connected to the input end of the AND gate, and the output end of the first OR gate is also connected to the corresponding test module; the output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

[0118] In one embodiment, the register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate, wherein the first pin is connected to the input end of the third shift register unit; the input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit; the output end of the second OR gate is connected to the input end of the AND gate; and the control module generates a one-hot code according to the third test requirement to shut down the test module based on the one-hot code.

[0119] In one embodiment, the enable module includes an enable signal interface and a second logic gate unit, one end of the second logic gate unit is connected to the enable signal interface and the input and output pins, the other end of the second logic gate unit is connected to the test module, and the enable signal interface is also connected to the functional module; wherein, when the enable signal interface outputs a first level signal to the second logic gate unit, the functional mode is selected, the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers the functional test state in response to the second test signal and generates a test result; when the enable signal interface outputs a second level signal to the second logic gate unit, the test mode is selected, the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

[0120] In one embodiment, the control module is a JTAG module.

[0121] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0122] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A low pin count chip test circuit, characterized in that: include: Input and output pins, a control module, at least two test modules, an enable module and a functional module; the control module is connected to the test module, the input and output pins are connected to the functional module and the enable module, and the enable module is connected to the control module and the test module respectively, for selecting a functional mode and a test mode; wherein, When the enabling module enables the test mode, the control module generates a one-hot code according to a first test requirement to enable the test module based on the one-hot code; the input and output pins generate a first test signal according to the first test requirement, and the test module generates a test result in response to the first test signal; or When the enabling module selects the functional mode, the input and output pins generate a second test signal according to a second test requirement, and the functional module triggers a functional test state and generates a test result in response to the second test signal.

2. The low pin count chip test circuit according to claim 1, characterized in that: The control module includes a first pin, a second pin and a third pin, the first pin is connected to the test module, and the second pin is connected to the third pin; wherein, The first pin is used to generate the one-hot code; The second pin is used to generate a control signal of the control module according to the test requirement; The third pin is used to control the control module to maintain a current state based on the control signal after the second pin generates the control signal.

3. The low pin count chip test circuit according to claim 2, wherein: The circuit further includes a register module, the first pin and the second pin are connected to the input end of the register module, and the output end of the register module is connected to the third pin and the test module; wherein, The register module is used to control the gating of the test module according to the one-hot code, and to control the control module to maintain a current state according to the control signal.

4. The low pin count chip test circuit according to claim 3, characterized in that: The register module includes a first shift register unit, a second shift register unit and a first logic gate unit; wherein, The first pin is connected to the input end of the first shift register unit, and the output end of the first shift register unit is connected to the input end of the first logic gate unit; The second pin and the first output end of the first logic gate unit are connected to the input end of the second shift register unit, and the output end of the second shift register unit is connected to the input end of the first logic gate unit; The first output end of the first logic gate unit is also connected to the third pin, and a plurality of second output ends of the first logic gate unit are connected to the test module.

5. The low pin count chip test circuit according to claim 4, characterized in that: The register module includes a plurality of first shift register units corresponding to a plurality of first pins respectively, and the first logic gate unit includes an AND gate and a first OR gate; wherein, An input end of each of the first OR gates is respectively connected to the output ends of the first shift register units and the output end of the second shift register unit; The output end of each first OR gate is connected to the input end of the AND gate, and the output end of the first OR gate is also connected to the corresponding test module; The output end of the AND gate is connected to the input end of the second shift register unit and the third pin of the control module.

6. The low pin count chip test circuit according to claim 5, characterized in that: The register module further includes a third shift register unit, and the first logic gate unit further includes a second OR gate, wherein: The first pin is connected to the input end of the third shift register unit; The input end of the second OR gate is connected to the output end of the third shift register unit and the output end of the second shift register unit; The output terminal of the second OR gate is connected to the input terminal of the AND gate; The control module generates a one-hot code according to a third test requirement, so as to shut down the test module based on the one-hot code.

7. The low pin count chip test circuit according to claim 6, characterized in that: The enabling module includes an enabling signal interface and a second logic gate unit, one end of the second logic gate unit is connected to the enabling signal interface and the input and output pins, the other end of the second logic gate unit is connected to the test module, and the enabling signal interface is also connected to the functional module; wherein, In the case where the enable signal interface outputs a first level signal to the second logic gate unit, the functional mode is enabled, the second logic gate unit prohibits the second test signal from being input to the test module, and the functional module triggers a functional test state and generates a test result in response to the second test signal; When the enable signal interface outputs a second level signal to the second logic gate unit, the test mode is selected, the second logic gate unit allows the first test signal to be input to the test module, and the test module generates a test result in response to the first test signal.

8. The low pin count chip test circuit according to claim 7, characterized in that: The second logic gate unit includes multiple third AND gates and multiple fourth AND gates, the input end of the third AND gate is connected to the input and output pin and the enable signal interface; the output end of the third AND gate is connected to the input end of the fourth AND gate, the register module is connected to the input end of the fourth AND gate, and the fourth AND gate is connected to the test unit.

9. A method for testing a low pin count chip test circuit, characterized in that: The low pin count chip test circuit according to any one of claims 1 to 8, wherein the method comprises: When the enabling module enables the test mode, the control module and the input / output pins of the low-pin-count chip test circuit are configured according to a first test requirement, so that the control module generates a one-hot code according to the first test requirement, and the input / output pins generate a first test signal according to the first test requirement; the test module is enabled based on the one-hot code, so that the test module generates a test result in response to the first test signal; or When the enabling module selects the functional mode, the input and output pins of the low-pin-count chip test circuit are configured according to the second test requirement, so that the input and output pins generate a second test signal according to the second test requirement, and the functional module triggers the functional test state in response to the second test signal and generates a test result.

10. A chip testing device, characterized in that: The invention comprises the low pin count chip testing circuit according to any one of claims 1 to 8.

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