Radar signal processing method and related equipment

Abstract

The invention provides a radar signal processing method and related equipment. The method is applied to a calculation module provided with a plurality of DSP chips in a radar, and each DSP chip comprises a plurality of cores. The radar signal processing method comprises the following steps: receiving a radar echo signal; performing pulse compression processing on the radar echo signal through the first DSP chip to obtain a first data volume; performing coherent accumulation processing on the first data volume through a second DSP chip to obtain a second data volume; and performing constant false alarm detection processing on the second data body through a third DSP chip to obtain message data corresponding to the radar echo signal. By using a plurality of DSP chips and a multi-core processing architecture, parallelization and modularization of radar signal processing are realized, the processing efficiency and the flexibility of the system are improved, meanwhile, by introducing a simulation test mechanism, the reliability and the stability of the system are enhanced, and the reliability and the reliability of the system are improved. The design method has the advantage of improving the flexibility, efficiency and reliability of radar signal processing.

Description

Technical Field

[0001] This application relates to the field of radar signal processing, and in particular, to a radar signal processing method and related devices. Background Art

[0002] The radar signal processing system is an important part of a radar. A suitable system construction helps the radar complete various complex tasks; with the rapid development of modern radar technology, radar systems are facing more and more challenges and requirements.

[0003] In the current complex and changeable working environment, a radar usually needs to adapt to multiple application scenarios and have multiple working modes. Under different working modes, due to differences in parameters such as working frequency and number of sampling points, different algorithm processes need to be executed; this diverse demand brings great pressure to the radar signal processing system.

[0004] Traditional radar signal processing methods are often designed for specific working modes and application scenarios, lacking necessary flexibility and generality. When it is necessary to switch the working mode or adapt to a new application scenario, it is usually necessary to redesign the program of the current system, and sometimes even to redesign the hardware solution. This method results in low reuse rate of the system and extremely high resource waste rate, and cannot meet the requirements of working effectively in diverse application scenarios.

[0005] Therefore, the current radar signal processing method has the technical problem of low reuse rate and needs to be improved. Summary of the Invention

[0006] Embodiments of this application provide a radar signal processing method and related devices, which are used to alleviate the technical problem of low reuse rate existing in the current radar signal processing method.

[0007] To solve the above technical problem, embodiments of this application provide the following technical solutions:

[0008] This application provides a radar signal processing method, which is applied to a computing module in a radar provided with multiple DSP chips, and the DSP chips include multiple cores; the radar signal processing method includes:

[0009] Receiving a radar echo signal;

[0010] Performing pulse compression processing on the radar echo signal through a first DSP chip to obtain a first data body;

[0011] Performing coherent accumulation processing on the first data body through a second DSP chip to obtain a second data body;

[0012] The third DSP chip performs a constant false alarm detection process on the second data body to obtain the message data corresponding to the radar echo signal.

[0013] In one embodiment, the step of performing pulse compression processing on the radar echo signal by the first DSP chip to obtain a first data body in the foregoing method includes:

[0014] Performing preprocessing on the radar echo signal through the first check of the first DSP chip;

[0015] Performing compression processing on the preprocessed data through the second check of the first DSP chip;

[0016] Performing packet encapsulation on the compressed data through the third check of the first DSP chip to obtain the first data body.

[0017] In one embodiment, the step of performing coherent accumulation processing on the first data body by the second DSP chip to obtain a second data body in the foregoing method includes:

[0018] Performing transpose processing on the first data body through the fourth check of the second DSP chip;

[0019] Performing accumulation processing on the transposed data through the fifth check of the second DSP chip;

[0020] Performing packet encapsulation on the accumulated data through the sixth check of the second DSP chip to obtain the second data body.

[0021] In one embodiment, the step of performing a constant false alarm detection process on the second data body by the third DSP chip to obtain the message data corresponding to the radar echo signal in the foregoing method includes:

[0022] Performing verification processing on the second data body through the seventh check of the third DSP chip;

[0023] Performing a constant false alarm detection process on the verified data through the eighth check of the third DSP chip to obtain target point track information;

[0024] Performing packet encapsulation on the target point track information through the ninth check of the third DSP chip to obtain the message data.

[0025] In one embodiment, the foregoing method further includes:

[0026] Responding to a test operation to determine the target parameters of the simulation test;

[0027] Generating a radar simulation signal based on the target parameters;

[0028] Test the computing module based on the radar simulation information.

[0029] Meanwhile, the present invention also provides a radar, which includes a computing module having multiple DSP chips, and the DSP chips include multiple cores; wherein:

[0030] The first DSP chip performs pulse compression processing on the radar echo signal to obtain a first data body;

[0031] The second DSP chip performs coherent accumulation processing on the first data body to obtain a second data body;

[0032] The third DSP chip performs constant false alarm rate detection processing on the second data body to obtain the message data corresponding to the radar echo signal.

[0033] In one embodiment, the first DSP chip includes:

[0034] The first core is used to preprocess the radar echo signal;

[0035] The second core is used to perform compression processing on the preprocessed data;

[0036] The third core is used to packetize the compressed data to obtain the first data body.

[0037] In one embodiment, the second DSP chip includes:

[0038] The fourth core is used to transpose the first data body;

[0039] The fifth core is used to perform accumulation processing on the transposed data;

[0040] The sixth core is used to packetize the accumulated data to obtain the second data body.

[0041] In one embodiment, the third DSP chip includes:

[0042] The seventh core is used to perform verification processing on the second data body;

[0043] The eighth core is used to perform constant false alarm rate detection processing on the verified data to obtain target point track information;

[0044] The ninth core is used to packetize the target point track information to obtain the message data.

[0045] Meanwhile, the present application provides a computer device, which includes a processor and a memory. The memory stores multiple instructions, and the instructions are suitable for being loaded by the processor to execute the steps in the above method.

[0046] Meanwhile, this application provides a computer-readable storage medium storing multiple instructions adapted to be loaded by a processor to execute the steps in the above method.

[0047] Meanwhile, this application provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to execute the steps in the above method.

[0048] Beneficial effects: This application provides a radar signal processing method and related devices, which are applied to a computing module with multiple DSP chips in a radar. Each DSP chip includes multiple cores. The radar signal processing method includes: receiving a radar echo signal; performing pulse compression processing on the radar echo signal through a first DSP chip to obtain a first data body; performing coherent integration processing on the first data body through a second DSP chip to obtain a second data body; performing constant false alarm rate detection processing on the second data body through a third DSP chip to obtain message data corresponding to the radar echo signal. By using multiple DSP chips and a multi-core processing architecture, the present invention realizes the parallelization and modularization of radar signal processing, improves the processing efficiency and system flexibility. At the same time, by introducing a simulation test mechanism, the reliability and stability of the system are enhanced. This design method has the advantages of improving the flexibility, efficiency, and reliability of radar signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The following will clearly show the technical solutions and their beneficial effects of this application by describing the specific embodiments of this application in detail with reference to the drawings.

[0050] Figure 1 is a schematic flowchart of the radar signal processing method provided by an embodiment of this application;

[0051] Figure 2 is a schematic structural diagram of the radar provided by an embodiment of this application;

[0052] Figure 3 is a schematic diagram of the radar signal processing system provided by an embodiment of this application;

[0053] Figure 4 is a schematic diagram of the overall structure provided by an embodiment of this application;

[0054] Figure 5 is a schematic diagram of the pulse compression module provided by an embodiment of this application;

[0055] Figure 6 is a schematic diagram of the coherent integration module provided by an embodiment of this application;

[0056] Figure 7 It is a schematic diagram of the constant false alarm detection module provided by an embodiment of the present application;

[0057] Figure 8 It is a detection map of targets in the same azimuth provided by an embodiment of the present application;

[0058] Figure 9 It is a detection map of multiple targets provided by an embodiment of the present application. Specific implementation manners

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of the present application, rather than all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0060] In the description of the embodiments of the present application, it should be understood that terms such as "first" and "second" in the specification, claims, and drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such terms may be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order different from that shown in the drawings or described content. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0061] The radar signal processing system is an important part of the radar, and a suitable system construction helps the radar to complete various complex tasks. Due to the current complex and changeable working environment, in different application scenarios, the radar usually has multiple working modes. In different working modes, due to differences in working frequency, number of sampling points, etc., the executed algorithm processing also has differences. At this time, not only the program of the current system needs to be redesigned, but even the hardware solution needs to be redesigned, resulting in low reuse rate of the system and extremely high resource waste rate, lacking necessary flexibility and generality, and being difficult to meet the requirements of effectively working in diverse application scenarios. Therefore, there is a technical problem of low reuse rate in the current radar signal processing method, which needs to be improved.

[0062] To solve the above problems, the present application provides a radar signal processing method, which is applied to a computing module provided with multiple DSP chips, and the DSP chips include multiple cores. As Figure 1 shown, the method includes:

[0063] S101: Receive radar echo signals;

[0064] S102: Perform pulse compression processing on the radar echo signal through the first DSP chip to obtain the first data volume;

[0065] S103: Perform coherent integration processing on the first data volume through the second DSP chip to obtain the second data volume;

[0066] S104: Perform constant false alarm rate detection processing on the second data volume through the third DSP chip to obtain the message data corresponding to the radar echo signal.

[0067] The reuse rate of the current radar signal processing method is low. This is mainly because in different application scenarios, the radar has diverse working modes, and parameters such as working frequency and sampling points are different, resulting in different required algorithm processing. Therefore, the existing system needs to frequently redesign the program and hardware solutions, causing problems of resource waste and insufficient system flexibility. To solve these problems, this application proposes a radar signal processing method based on multiple DSP chips. By reasonably allocating the functions of different DSP chips, efficient processing of radar signals is achieved, thereby improving the reuse rate and flexibility of the system.

[0068] In this method, the main steps of radar signal processing include pulse compression processing, coherent integration processing, and constant false alarm rate detection processing. First, after receiving the radar echo signal, perform pulse compression processing through the first DSP chip to obtain the first data volume. Then, perform coherent integration processing on the first data volume through the second DSP chip to obtain the second data volume. Finally, perform constant false alarm rate detection processing on the second data volume through the third DSP chip to obtain the message data corresponding to the radar echo signal.

[0069] Among them, the pulse compression processing is completed collaboratively by multiple cores of the first DSP chip. Specifically, the first core is responsible for preprocessing the radar echo signal, the second core is responsible for compressing the preprocessed data, and the third core is responsible for packetizing the compressed data to obtain the first data volume. The coherent integration processing is completed collaboratively by multiple cores of the second DSP chip. Specifically, the fourth core is responsible for transposing the first data volume, the fifth core is responsible for integrating the transposed data, and the sixth core is responsible for packetizing the integrated data to obtain the second data volume. The constant false alarm rate detection processing is completed collaboratively by multiple cores of the third DSP chip. Specifically, the seventh core is responsible for verifying the second data volume, the eighth core is responsible for performing constant false alarm rate detection processing on the verified data to obtain the target point track information, and the ninth core is responsible for packetizing the target point track information to obtain the message data.

[0070] In this way, the radar signal processing method of the present application can flexibly respond to different working modes in different application scenarios, avoiding the problem of frequently redesigning programs and hardware solutions, and improving the reuse rate and resource utilization efficiency of the system. Compared with the prior art, the method of the present application realizes the efficient processing of radar signals by reasonably allocating the functions of multiple DSP chips, and has higher flexibility and versatility.

[0071] The radar signal processing method of the present application realizes the efficient processing of radar signals through the collaborative work of multiple DSP chips. Specifically, after receiving the radar echo signal, first, the first DSP chip performs pulse compression processing to obtain the first data body. Then, the second DSP chip performs coherent integration processing on the first data body to obtain the second data body. Finally, the third DSP chip performs constant false alarm rate detection processing on the second data body to obtain the message data corresponding to the radar echo signal. Multiple cores inside each DSP chip are respectively responsible for specific tasks such as preprocessing, compression processing, packetizing, transposing processing, integration processing, verification processing, and constant false alarm rate detection processing. In this way, the efficient processing of radar signals is realized.

[0072] Further, in some embodiments, the process of obtaining the first data body by performing pulse compression processing on the radar echo signal through the first DSP chip includes: preprocessing the radar echo signal through the first core of the first DSP chip; performing compression processing on the preprocessed data through the second core of the first DSP chip; and packetizing the compressed data through the third core of the first DSP chip to obtain the first data body.

[0073] The technical solution of the present application solves the technical problem of low reuse rate existing in the current radar signal processing method. By distributing the processing of the radar echo signal to multiple cores of different DSP chips for processing, the processing efficiency can be improved and the flexibility and versatility of the system can be increased. Specifically, the first core of the first DSP chip preprocesses the radar echo signal, which can effectively remove noise and interference and improve the signal quality; the second core performs compression processing on the preprocessed data, which can reduce the data volume and improve the transmission and storage efficiency; the third core packetizes the compressed data to obtain the first data body, which is convenient for subsequent processing and transmission.

[0074] Specifically, the preprocessing process may include operations such as filtering and denoising, the compression processing may adopt algorithms such as fast Fourier transform (FFT), and the packetizing process may perform data packaging according to the data format requirements. As a preferred implementation manner, the preprocessing may adopt an adaptive filtering algorithm, the compression processing may adopt a wavelet transform algorithm, and the packetizing process may adopt a standard data encapsulation protocol.

[0075] Through the technical solution of this application, compared with the prior art, it has the following advantages: First, by distributing the radar signal processing process to multiple cores of different DSP chips for processing, the processing efficiency is improved and the processing time is reduced; Second, by preprocessing, compressing and packetizing the radar echo signal, the signal quality and data transmission efficiency are improved; Finally, by flexibly configuring the cores of the DSP chip, according to different application scenarios and working modes, the processing flow and algorithm can be adjusted, the flexibility and versatility of the system are improved, and it can better adapt to the complex and changeable working environment. Thus, this application effectively solves the technical problem of low reuse rate in the radar signal processing method, and improves the resource utilization rate and working efficiency of the system.

[0076] Further, in some embodiments, the second DSP chip performs coherent accumulation processing on the first data body to obtain a second data body, including:

[0077] The fourth core of the second DSP chip transposes the first data body;

[0078] The fifth core of the second DSP chip accumulates the data after transposition processing;

[0079] The sixth core of the second DSP chip packets the data after accumulation processing to obtain a second data body.

[0080] This application uses different cores of the second DSP chip to separately process the transposition, accumulation and packetizing steps of the first data body. Specifically, the fourth core is responsible for transposing the first data body. This step is to adjust the data arrangement method so that the subsequent accumulation processing can be carried out more effectively. Then, the fifth core accumulates the data after transposition processing. The purpose of this step is to coherently accumulate multiple data to enhance the signal strength. Finally, the sixth core packets the data after accumulation processing to obtain a second data body. This step is to package the processed data into a standard format for subsequent processing and transmission.

[0081] The new technical features of this solution are that the fourth core, the fifth core and the sixth core of the second DSP chip are used to perform transposition, accumulation and packetizing processing respectively. Specifically, the fourth core can implement data transposition processing through a matrix transposition algorithm, the fifth core can implement coherent accumulation processing of data through an accumulation algorithm, and the sixth core can perform standardized packetizing of the processed data through a packetizing algorithm. The implementation methods of these technical features can be adjusted according to specific requirements. For example, the transposition processing can adopt the method of interchanging rows and columns, the accumulation processing can adopt different accumulation strategies, and the packetizing processing can be flexibly designed according to the requirements of the data format.

[0082] Compared with the prior art, the solution of the present application improves the efficiency and accuracy of data processing by refining the processing steps of the second DSP chip. By separately assigning the transpose, accumulation, and packet processing to different cores, the multi-core advantages of the DSP chip can be fully utilized to achieve parallel processing, thereby shortening the processing time. In addition, this solution also has high flexibility and versatility and can be adjusted according to different application requirements to adapt to diverse radar signal processing scenarios. Thus, the solution of the present application not only improves the efficiency and effect of radar signal processing but also solves the problems of low reuse rate and serious resource waste in the prior art.

[0083] Further, in some embodiments, a constant false alarm detection process is performed on the second data body by a third DSP chip to obtain the message data corresponding to the radar echo signal, including: performing a verification process on the second data body by the seventh core of the third DSP chip; performing a constant false alarm detection process on the data after the verification process by the eighth core of the third DSP chip to obtain the target track information; and performing packetization on the target track information by the ninth core of the third DSP chip to obtain the message data.

[0084] The present application distributes the radar signal processing method to different DSP chips for processing, and each DSP chip is responsible for specific processing steps, ensuring the efficiency and accuracy of the processing. For example, the first DSP chip is responsible for performing pulse compression processing on the radar echo signal, the second DSP chip is responsible for performing coherent accumulation processing on the first data body, and the third DSP chip is responsible for performing constant false alarm detection processing on the second data body. Through this division of labor, the computing power of each DSP chip can be effectively utilized to improve the processing speed and performance of the overall system.

[0085] Specifically, the present application performs a verification process on the second data body by the seventh core of the third DSP chip to ensure the integrity and accuracy of the data. Then, a constant false alarm detection process is performed on the data after the verification process by the eighth core to identify the target track information. Finally, packetization is performed on the target track information by the ninth core to obtain the final message data. In this way, the entire processing flow is clear and the steps are well-defined, which helps to improve the stability and reliability of the system.

[0086] The technical solution proposed by the present application avoids the problem of excessive burden on a single chip in the traditional method by reasonably allocating the work tasks of the DSP chips. Through multi-core parallel processing, not only the processing speed is improved, but also the flexibility and scalability of the system are enhanced. Compared with the prior art, the present application can process radar signals more efficiently, solves the problems of low reuse rate and resource waste, and has high practical value.

[0087] Further, in some embodiments, Figure 1The method shown also includes: determining target parameters of the simulation test in response to the test operation; generating a radar simulation signal based on the target parameters; and testing the calculation module based on the radar simulation information.

[0088] In the radar signal processing method, in response to the test operation, the target parameters of the simulation test need to be determined first. These target parameters may include the radar's operating frequency, target distance, target speed, and environmental noise. After determining the target parameters, the corresponding radar simulation signal can be generated based on these parameters. The generated radar simulation signal should simulate the radar echo signal in the real environment as much as possible so that the test result has a high degree of credibility.

[0089] Specifically, the generated radar simulation signal can be generated by computer simulation software or by a dedicated signal generator. The generated simulation signal should be able to cover the operating frequency band and dynamic range of the radar. Then, based on the generated radar simulation signal, the calculation module is tested. During the test, the simulation signal can be input into the calculation module, the processing results of the module can be observed, and compared with the expected results to evaluate the performance of the calculation module.

[0090] This application adds a simulation test step so that the radar signal processing method can be fully tested and verified before actual deployment. As a result, potential problems in the system can be effectively discovered and solved, and the reliability and stability of the system can be improved. Compared with the prior art, the method of this application improves the reuse rate of the radar signal processing system, reduces resource waste, and enhances the flexibility and versatility of the system in a variety of application scenarios.

[0091] Based on the contents of the above embodiments, Figure 2 As shown, the embodiment of the present application provides a radar 2, having a computing module 20 of multiple DSP chips, and the DSP chip includes multiple cores; wherein:

[0092] The first DSP chip 201 performs pulse compression processing on the radar echo signal to obtain a first data body;

[0093] The second DSP chip 202 performs coherent accumulation processing on the first data body to obtain a second data body;

[0094] The third DSP chip 203 performs constant false alarm detection processing on the second data body to obtain message data corresponding to the radar echo signal.

[0095] In one embodiment, the first DSP chip includes:

[0096] A first core, used for preprocessing the radar echo signal;

[0097] A second core, configured to perform compression processing on the preprocessed data;

[0098] A third core, configured to packetize the compressed data to obtain the first data body.

[0099] In one embodiment, the second DSP chip includes:

[0100] A fourth core, configured to perform transpose processing on the first data body;

[0101] A fifth core, configured to perform accumulation processing on the data after transpose processing;

[0102] A sixth core, configured to packetize the data after accumulation processing to obtain the second data body.

[0103] In one embodiment, the third DSP chip includes:

[0104] A seventh core, configured to perform verification processing on the second data body;

[0105] An eighth core, configured to perform constant false alarm detection processing on the data after verification processing to obtain target point track information;

[0106] A ninth core, configured to packetize the target point track information to obtain the message data.

[0107] The present application will be further described in conjunction with specific embodiments.

[0108] The radar signal processing system is an important part of the radar. A suitable system construction helps the radar to complete various complex tasks. At present, the localization of radars in China is still in the development stage. Its hardware architecture mostly adopts a multi-core architecture of digital signal processors (DSPs) or a field programmable gate array (FPGA) + DSP architecture. However, at present, these two types of architectures mostly perform hardware integration based on foreign chips, which is likely to cause data leakage and is not conducive to information security.

[0109] Due to the current complex and changeable working environment, in different application scenarios, radars usually have multiple working modes. In different working modes, due to differences in working frequency, sampling points, etc., the executed algorithm processing also varies. At this time, not only does the program of the current system need to be redesigned, but even the hardware solution design needs to be redone, resulting in low system reuse rate and extremely high resource waste rate, lacking necessary flexibility and generality, and being difficult to meet the requirements of effectively working in diverse application scenarios. At the same time, with the continuous development of the functions and technologies of domestic radars, the requirements for the real-time performance and multi-target processing ability of domestic radar signal processing systems are also getting higher and higher; however, the current development of software and hardware of domestic radar signal processing systems is not yet mature, and it is very difficult to complete a large number of radar signal processing tasks in a very short time and provide accurate and timely radar information.

[0110] Therefore, this application fully considers the problems of low domesticization level, poor generality, and difficulty in processing large-scale multi-targets of the existing radar signal processing systems. Based on the multi-core hardware characteristics of the domestic Huari No. 2 computing module, it optimizes the current domestic radar signal processing process. At the same time, it introduces the domestic ReDe integrated development environment and VSIPL middleware for software development, and constructs a design model of a domestic radar signal processing system based on a pipeline architecture.

[0111] This application aims to improve the low processing efficiency, poor generality, and difficulty in processing large-scale multi-targets of the domestic radar signal processing system. As Figure 3 shown, first, the radar signal processing task is divided into three subtasks: pulse compression, coherent integration, and constant false alarm detection. By allocating different radar signal processing subtasks to different DSP chips of the domestic Huari No. 2 computing module, the overall pipeline design of the radar signal processing task is completed. Secondly, a pipeline design is carried out for each subtask. The functional modules of the subtask are divided into three basic processes: data reception, task execution, and data transmission, and the basic process is allocated to different cores of the DSP chip. Finally, the domestic ReDe integrated development environment and VSIPL computing middleware are introduced to carry out software development for the pulse compression module, coherent integration module, and constant false alarm detection module to realize the processing function of the radar signal processing system.

[0112] As Figure 3 shown, the technical solution adopted by the present invention is a design method of a radar signal processing system based on a pipeline architecture. The method specifically includes the following steps:

[0113] Step 1: Divide the radar signal processing task into three subtasks: pulse compression, coherent integration, and constant false alarm detection. By allocating different radar signal processing subtasks to different DSP chips of the domestic Huari No. 2 computing module, complete the overall pipeline design of the present invention;

[0114] Step 2: Construct a pipeline architecture scheme based on the pulse compression module, reasonably divide the working process of the pulse compression module, and based on the multi-core characteristics of the domestic Huari No. 2 computing module, reasonably allocate the divided working process of the pulse compression module to the DSP chip. Introduce the domestic ReDe integrated development environment and VSIPL computing middleware to conduct software development for the pulse compression module;

[0115] Step 3: Construct a pipeline architecture scheme based on the coherent integration module, reasonably divide the working process of the coherent integration module, and based on the multi-core characteristics of the domestic Huari No. 2 computing module, reasonably allocate the divided working process of the coherent integration module to the DSP chip. Introduce the domestic ReDe integrated development environment and VSIPL computing middleware to conduct software development for the coherent integration module;

[0116] Step 4: Construct a pipeline architecture scheme based on the constant false alarm detection module, reasonably divide the working process of the constant false alarm detection module, and based on the multi-core characteristics of the domestic Huari No. 2 computing module, reasonably allocate the divided working process of the constant false alarm detection module to the DSP chip. Introduce the domestic ReDe integrated development environment and VSIPL computing middleware to conduct software development for the constant false alarm detection module;

[0117] Step 5: Simulate the target information and add noise through MATLAB, simulate the actual working environment of the radar, import it into the Huari No. 2 computing module for operation, and verify the real-time performance, generality and multi-target detection ability of the present invention.

[0118] Specifically, Step 1 includes the following steps:

[0119] Divide the radar signal processing task into different subtasks. By allocating different radar signal processing subtasks to different DSP chips of the Huari No. 2 computing module, conduct pipeline design for the radar signal processing task, and divide each task cycle into 3 steps, namely pulse compression, coherent integration and constant false alarm detection. As Figure 4 shown, except for the first task cycle at the beginning, where DSP1 and DSP2 may be idle, each DSP cannot be idle in the remaining task cycles. Starting from the second task cycle, when DSP1 executes the task, DSP0 cannot be idle either and must perform pulse compression. Starting from the third task cycle, when DSP2 executes the constant false alarm detection, DSP0 cannot be idle either, and at the same time, it has to continue with pulse compression, while DSP1 needs to perform coherent integration. Starting from the fourth task cycle, each DSP module will enter a full-load working state, just like a pipeline, continuously executing each task.

[0120] Step 2 includes the following steps:

[0121] The present invention realizes pulse compression in the frequency domain, and its implementation principle is:

[0122] y(t) = IFFT{FFT{s(t)}·FFT{h(t)·w(t)}} (1)

[0124] Wherein, s(t) is the received echo signal, including target signal, noise, clutter, interference, etc.; h(t) is the pulse compression coefficient, which is pre-stored in the NAND Flash of the Huari No. 2 computing module after FFT processing and directly extracted when pulse compression operation is performed; w(t) is the window function.

[0125] According to the above pulse compression algorithm flow, its pipeline design scheme is as Figure 5 shown. The specific development process is as follows: Core 0 (i.e., the first core in the above text) is responsible for receiving the radar control packet and data packet sent by the front-end system, and then preprocessing the data, including completing data frame decoding to determine whether it is the desired data.

[0126] Core 1 (i.e., the second core in the above text) reads the parsed radar echo data, initializes it through the vsip_init() function of the VSIPL library, and completes relevant parameter settings. It calls the vsip_ccfftop_create_f() function to create 2 FFT objects, one with parameters set to VSIP FFT FWD for FFT processing, and the other with parameters set to VSIP FFTINV for IFFT processing; reads the echo data in memory, creates a block with the vsip_cblock_f() function and binds the radar echo data sent by the front-end processing system to the block, and then creates a view with the vsip_cvview_f() function and binds the block to the view; calls the vsip_ccfftop_f() function in the VSIPL library for FFT processing, multiplies the obtained FFT data by the pulse compression coefficient through the vsip_cvmul_f() function as the input data for IFFT processing; calls the vsip_ccfftop_f() function to perform IFFT processing on the radar echo data to complete pulse compression; after completing pulse compression, reversely calls the vsip_cblockrelease_f() function and the vsip_fft_destory_f() function to release the block and destroy the FFT and IFFT objects, and terminate the VSIPL library.

[0127] Core 2 (i.e., the third core in the above text) reads the memory. After the number of data pulse groups reaches 32, it packets the data and sends it to the coherent accumulation module in the form of a data frame.

[0128] Step 3 includes the following steps:

[0129] The pipeline design scheme of the coherent accumulation module is as Figure 6As shown below, the specific development process is as follows: Core 0 (i.e., the fourth core in the above text) is responsible for receiving pulse compression data, decoding the data frame, determining whether it is 32 groups of pulse compression data, and transposing the data block.

[0130] The specific development process of Core 1 (i.e., the fifth core in the above text) is as follows: Initialize the VSIPL library through the vsip_init() function, call the vsip_ccfftop_create_f() function to create an FFT object, and set the parameter to VSIP FFT FWD for FFT processing; call the vsip_cblock_f() function to create a block and bind the radar echo data sent by the pulse compression module to the block, and then call the vsip_cvview_f() function to create a view and bind the block to the view; read the cache. To improve the detection effect of weak targets, each pulse group sliding window in the present invention contains 4 groups of CPI, a total of 128 pulses, and the sliding window detection method is adopted to complete coherent accumulation; after receiving the pulse-compressed data, continuously transmit it to the cache, determine whether the CPI is 4 groups. If not, continue to receive the pulse echo data and wait for the CPI to be 4 groups. If so, move the last 3 pulse groups forward and place the latest pulse group at the end. The data after pulse compression processing is x[n], which is composed of a complex constant signal s[n]=A·e jφ and Gaussian white noise w[n] with a mean of 0 and a variance of σ2:

[0131] x[n]=s[n]+w[n]=A·e jφ +w[n] (2)

[0132] The signal-to-noise ratio (SNR) under a single pulse can be expressed as:

[0133]

[0134] Call the vsip_ccfftop_f() function in the VSIPL library to perform N coherent accumulations, and its sum Z can be expressed as:

[0135] Since the phase of the signal is consistent between the front and back pulses, in Z, the energy (power) of the signal component is: (N·A)2, and the total power of the noise is:

[0136]

[0137] From the foregoing power formulas of the signal and noise, the SNR of Z is obtained:

[0138]

[0139] After the above processing, the signal-to-noise ratio of the signal processing system can be effectively improved. After the coherent integration processing is completed, the functions vs ip_cblockrelease_f() and vs ip_fft_destory_f() are called in reverse order to release the block and destroy the FFT object, and the VSIPL library is terminated.

[0140] Core 2 (i.e., the sixth core in the above text) reads the memory, packetizes the data, and sends the data to the constant false alarm detection module in the form of data frames.

[0141] Step 4 includes the following steps:

[0142] The pipeline design scheme of the constant false alarm detection module is as Figure 7 shown. The specific development process is as follows: Core 0 (i.e., the seventh core in the above text) receives the data sent by the coherent integration module, decodes the data frame of the received data, performs a frame header check on the received data, and determines whether it is the data desired by this system. If so, continue to receive; if not, stop receiving;

[0143] Core 1 (i.e., the eighth core in the above text) transposes the data block transposed by the coherent integration module back to facilitate the subsequent constant false alarm detection; performs one-dimensional cell-averaging constant false alarm detection on the coherent integration matrix, calculates the modulus value of the matrix through the vs ip_cmmag_f() function, takes the average of the sampling values of all reference cells within the reference window starting from the first range gate, sets the window length to n = 8 data volumes, the total data length to N = 4096, the sliding window length to 1 data volume, and the signal components are 1-9, 2-10... 4088-4096 in sequence. The average values within the left and right reference windows are:

[0144]

[0145] The estimated power level Z of the background is:

[0146] Z = mean(X,Y) (9)

[0147] For a given expected false alarm probability P FA and the number of reference cells N, the corresponding threshold multiplication factor can be obtained:

[0148]

[0149] Then the detection threshold of the cell to be detected is:

[0150] T = α·Z = α·mean(X,Y) (11)

[0151] The detection unit and the threshold factor are handed over to the decision maker for decision to obtain the target point track information, and the constant false alarm detection is completed.

[0152] The core 2 (i.e., the ninth core in the above text) reads the memory, packets the data, converts the 12 - bit IP address into network bytes for subsequent inter - board transmission; and sends a message to the display control system through the UDP protocol using the sendto() function via the Fiber Channel (FC) protocol to complete the data transmission of the present invention.

[0153] Step five includes the following steps:

[0154] Use MATLAB to reasonably set the target parameters, simulate the original echo, set different sampling points, and compare the measured results of traditional single - core processing and pipeline processing. Simulate the radar echoes of various frequency bands such as high - frequency radar, ultra - high - frequency radar, L - band radar, S - band radar, and C - band radar for generality verification. Simulate 16 co - azimuth targets at 53° east - south and 525 random targets within the range of 120KM - 360KM in distance and 0 - 360° in azimuth for large - scale target detection.

[0155] Starting from the development achievements and actual engineering requirements in the current domestic radar information technology field, this application fully considers the problems of low domesticization level, poor generality, and difficulty in processing large - scale multi - targets in the current domestic radar signal processing system. Based on the multi - core hardware characteristics of the domestic Huari No. 2 chip, it reasonably divides the radar signal processing tasks, gives a design scheme for the pipeline architecture of the domestic radar signal processing system, completes the pipeline design of the overall radar signal processing system and each functional module, optimizes the current domestic radar signal processing process, improves the generality and multi - target processing ability of the domestic radar signal processing system, and has important engineering application value for ensuring national security and enhancing comprehensive competitiveness.

[0156] Application scenario

[0157] In this scenario, a pure domestic Huari No. 2 computing module is selected as the core processor, and the ReDe integrated development environment is used for engineering creation, code editing, compilation, simulation, and debugging. The domestic radar general signal processing system of the present invention is debugged and experimentally verified and analyzed through the network debugging assistant and SecureCRT tools. The functional application part mainly uses the C language to complete the software development of each radar functional module, including the pulse compression module, coherent accumulation module, and constant false alarm detection module. The radar echo data is simulated through MATLAB.

[0158] Apply the present invention to actual tests, and the specific steps are as follows:

[0159] Step 1: Before work, the Huari No. 2 computing module needs to pass debugging and testing acceptance. Check that there is no power short circuit in the module, check the working configuration of the module, insert the module into the VPX general chassis, and ensure that the connectors and backplane connectors are in close contact. Before the first power-on of the Huari No. 2 computing module, for safety reasons, a power short circuit detection needs to be done before power-on to avoid damaging the devices on the module. After determining that there is no power short circuit, power on the module and check that each power output is normal. Use a multimeter to check if there is a short circuit between each pin. Install the module software operating environment on the computer, correctly connect the network cable and serial cable, connect the network port and serial port of the module and the computer, configure the debugging instrument and emulator as needed, and establish a system debugging environment.

[0160] Step 2: Open the domestic ReDe integrated development environment, right-click on the directory to be loaded to configure the transfer path. Turn on the chassis power supply, start and load the module, and connect the serial port debugging tool SecureCRT; for convenient simulation, connect the software development platform and the general chassis in the same local area network and set their network segments to be the same. Enter the ping command in the administrator window of the software development platform to determine whether the software debugging platform and the control cabinet are connected and check the working status of the software.

[0161] Step 3: Use MATLAB to simulate the original echo, set different sampling points, and compare the measured results of traditional single-core processing and pipeline processing. Radars are divided into high-frequency radars, ultra-high-frequency radars, L-band radars, S-band radars, C-band radars, etc. according to different frequency bands. Reasonably set the target parameters through MATLAB to simulate the radar echoes of each frequency band, verify each band of radar respectively, and judge whether its processing effect meets the working requirements.

[0162] Step 4: Control the radar to work normally, simulate the radar echo of the target through MATLAB, hand it over to this system for signal processing, and display the working range detection status through the radar display console. The simulation target information is set at 53° south by east, with a distance of 132KM - 357KM, the distance between every two targets is 15KM, and there are 16 targets in total to verify its detection effect for multi-targets in the same azimuth. To detect the detection ability of this system for large-scale multi-targets, on the basis of the same azimuth detection, simulate 525 targets with distances in the range of 120KM - 360KM and azimuths of 0 - 360° through MTALAB.

[0163] The above steps are the actual test process of the present invention. In order to verify the real-time performance of the radar signal processing system design method based on the pipeline architecture, a comparative experiment of traditional single-core processing and pipeline architecture is set up. By setting different sampling points, compare the processing times of traditional single-core processing and pipeline architecture processing at different sampling points, as shown in Table 1:

[0164] Table 1 Processing Results of Traditional Single-Core Processing and Pipeline Architecture

[0165]

[0166] Through the analysis of Table 1, the processing efficiency of the pipeline architecture design has increased by 35% compared with the traditional inter-core serial processing method. Due to the relatively fine division of functions such as pulse compression, coherent integration, and constant false alarm detection in the pipeline architecture, without affecting the stability and reliability of the system, the hardware resources of Huari No. 2 are fully utilized, and the phenomenon of empty-core operation existing in traditional serial processing is greatly reduced.

[0167] To verify the generality of the design method of the radar signal processing system based on the pipeline architecture, the target parameters are reasonably set through MATLAB below, the radar echoes in each frequency band are simulated, and the generality verification is carried out. The simulation results are shown in Table 2.

[0168] Table 2 Target Detection Table for Different Frequency Bands

[0169]

[0170] It can be seen from the analysis of Table 2 that when the generality test of the present invention is carried out, the range error in different frequency bands is within the range of -0.062 KM - 0.063 KM, and the speed error is between 0.33 m / s - 2.84 m / s, meeting the requirements of the present invention. To evaluate the accuracy of the present invention for range measurement and azimuth measurement, and to measure the dispersion degree between the measured azimuth and the actual azimuth as well as the measured range and the actual range, the mean square error is introduced to calculate the range and speed. The range mean square error is 0.04, and the speed mean square error is 5.50. The error dispersion degree is small, meeting the generality requirements of the present invention.

[0171] To verify the multi-target detection ability of the design method of the radar signal processing system based on the pipeline architecture, the radar is controlled to work normally, the radar echoes of the targets are simulated through MATLAB, and handed over to the present invention for signal processing. The detection status of the working range is displayed through the radar display console. 16 co-azimuth targets are simulated at 53° south by east, and 525 random targets are simulated within the range of 120 KM - 360 KM in range and 0 - 360° in azimuth for large-scale target detection. Figure 8 Figure 23 is the azimuth map of the co-azimuth target objects detected in the radar display console. The 16 yellow dots are the target traces reported by the domestic radar general signal processing system of the present invention to the display control system. The concentric circles in the radar map represent the range, the ring distance is 120 KM, and the total mileage is 600 KM; the scales on the outermost concentric circle represent the azimuth, each small scale is 1°, and every 5 small scales form a large scale.

[0172] Table 3 Target Position Table

[0173]

[0174] From the analysis of Table 3, it can be seen that the range errors of the 16 stationary targets in the same azimuth are between -0.127 KM and -0.084 KM, and the azimuth errors are between 0.01° and 1.01°, meeting the requirements of the present invention. To evaluate the accuracy of the present invention for range measurement and azimuth measurement and to measure the dispersion between the measured azimuth and the actual azimuth as well as the measured range and the actual range, the root mean square error is introduced to calculate the range and azimuth, and the range mean square error and the azimuth mean square error are obtained as 0.073 and 0.66 respectively. The difference between the actual value and the measured value of the system is very small. Thus, it can be shown that in the normal detection mode of the radar, the present invention can detect the targets in the same azimuth in the radar echo signal. By Figure 9 From the analysis of the 525 targets shown, their range and azimuth errors are within the range of the range and azimuth errors of the targets detected in Table 3, meeting the requirements of the system for the multi-target processing ability.

[0175] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0176] Therefore, an embodiment of the present application provides a computer-readable storage medium, in which multiple instructions are stored. The instructions can be loaded by a processor and used to implement the following functions:

[0177] Receive the radar echo signal;

[0178] Perform pulse compression processing on the radar echo signal through a first DSP chip to obtain a first data body;

[0179] Perform coherent integration processing on the first data body through a second DSP chip to obtain a second data body;

[0180] Perform constant false alarm detection processing on the second data body through a third DSP chip to obtain the message data corresponding to the radar echo signal.

[0181] For the specific implementation of each of the above operations, reference can be made to the previous embodiments and will not be elaborated here.

[0182] Among them, the storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

[0183] Since the instructions stored in the storage medium can execute the steps in any of the methods provided in the embodiments of the present application, the beneficial effects achievable by any of the methods provided in the embodiments of the present application can be realized. For details, refer to the previous embodiments and will not be elaborated here.

[0184] Meanwhile, the embodiments of the present application provide a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various optional implementation manners. For example, the following functions can be realized:

[0185] Receive radar echo signals;

[0186] Perform pulse compression processing on the radar echo signals through a first DSP chip to obtain a first data volume;

[0187] Perform coherent integration processing on the first data volume through a second DSP chip to obtain a second data volume;

[0188] Perform constant false alarm rate detection processing on the second data volume through a third DSP chip to obtain the message data corresponding to the radar echo signals.

[0189] The above has introduced in detail a radar signal processing method and related devices provided in the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A radar signal processing method, characterized in that, Applied to a computing module with multiple DSP chips in a radar, the DSP chips include multiple cores; the radar signal processing method includes: Receiving radar echo signals; Performing pulse compression processing on the radar echo signals through a first DSP chip to obtain a first data body; Performing coherent integration processing on the first data body through a second DSP chip to obtain a second data body; Performing constant false alarm detection processing on the second data body through a third DSP chip to obtain the message data corresponding to the radar echo signals.

2. The radar signal processing method according to claim 1, wherein The performing pulse compression processing on the radar echo signals through the first DSP chip to obtain a first data body includes: Performing preprocessing on the radar echo signals through a first core of the first DSP chip; Performing compression processing on the preprocessed data through a second core of the first DSP chip; Performing packet encapsulation on the compressed data through a third core of the first DSP chip to obtain the first data body.

3. The radar signal processing method according to claim 1, characterized in that, The performing coherent integration processing on the first data body through the second DSP chip to obtain a second data body includes: Performing transpose processing on the first data body through a fourth core of the second DSP chip; Performing integration processing on the transposed data through a fifth core of the second DSP chip; Performing packet encapsulation on the integrated data through a sixth core of the second DSP chip to obtain the second data body.

4. The radar signal processing method according to claim 1, wherein The performing constant false alarm detection processing on the second data body through the third DSP chip to obtain the message data corresponding to the radar echo signals includes: Performing verification processing on the second data body through a seventh core of the third DSP chip; Performing constant false alarm detection processing on the verified data through an eighth core of the third DSP chip to obtain target point track information; Performing packet encapsulation on the target point track information through a ninth core of the third DSP chip to obtain the message data.

5. The radar signal processing method according to any one of claims 1 to 4, characterized in that, It further includes: Responding to a test operation to determine target parameters of a simulation test; Generating radar simulation signals based on the target parameters; Testing the computing module based on the radar simulation information.

6. A radar, characterized in that, Including a computing module with multiple DSP chips, the DSP chips include multiple cores; wherein: The first DSP chip performs pulse compression processing on radar echo signals to obtain a first data body; The second DSP chip performs coherent integration processing on the first data body to obtain a second data body; The third DSP chip performs constant false alarm detection processing on the second data body to obtain the message data corresponding to the radar echo signals.

7. The radar according to claim 6, characterized in that, The first DSP chip includes: A first core for performing preprocessing on the radar echo signals; A second core for performing compression processing on the preprocessed data; A third core for performing packet encapsulation on the compressed data to obtain the first data body.

8. The radar according to claim 6, characterized in that, The second DSP chip includes: A fourth core for performing transpose processing on the first data body; A fifth core for performing integration processing on the transposed data; A sixth core for performing packet encapsulation on the integrated data to obtain the second data body.

9. The radar according to claim 6, characterized in that The third DSP chip includes: The seventh core is used to perform a verification process on the second data body; The eighth core is used to perform a constant false alarm detection process on the data after the verification process to obtain target track information; The ninth core is used to encapsulate the target track information to obtain the message data.

10. A computer device, characterized in that, The computer device includes a processor and a memory, and the memory stores multiple instructions, and the instructions are suitable for being loaded by the processor to execute the steps in the method according to any one of claims 1 to 5.

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