Low-power-consumption band-gap reference circuit and control method thereof

Abstract

The invention discloses a low-power-consumption band-gap reference circuit and a control method thereof.The low-power-consumption band-gap reference circuit comprises a self-biasing circuit module, a voltage stabilizing circuit module and a band-gap reference generation circuit module, and the output end of the self-biasing circuit module is connected with the input end of the voltage stabilizing circuit module; the output end of the voltage stabilizing circuit module is connected with the input end of the band-gap reference generation circuit module.The control method comprises the steps that initial bias current is obtained; performing deviation detection on the initial bias current to generate an adjusting signal; and the resistor network temperature coefficient of the triode working current is adjusted according to the adjusting signal, voltage compensation is carried out, and zero-temperature-drift reference voltage is output. According to the embodiment of the invention, the stability of the output voltage can be improved, the current consumption is effectively reduced, and the energy efficiency of the circuit is improved. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a low-power bandgap reference circuit and its control method. Background Art

[0002] In traditional bandgap reference circuit designs, voltage balance at the input is achieved by relying on operational amplifiers. The use of operational amplifiers introduces the problem of input offset voltage, resulting in significant fluctuations in the output voltage between different chips. The input offset voltage is not only an uncertain variable but also affected by the amplification effect of circuit parameters, thereby introducing a greater deviation at the output. For example, in some designs, the offset voltage may be amplified several times by the resistor ratio, causing the output voltage to deviate far from the ideal value, which directly affects the accuracy and stability of the circuit.

[0003] In addition, the operational amplifier itself also faces non-ideal characteristics such as offset drift and input bias current, which will further reduce the consistency of the circuit under different temperatures and operating conditions. More importantly, the operation of the operational amplifier will significantly increase the overall power consumption of the circuit, which is particularly obvious in battery-powered or low-power application scenarios.

[0004] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0005] The main purpose of the embodiments of the present application is to propose a low-power bandgap reference circuit and its control method, which can improve the stability of the output voltage, effectively reduce current consumption, and improve the energy efficiency of the circuit.

[0006] To achieve the above object, on the one hand, an embodiment of the present application proposes a low-power bandgap reference circuit, which includes a self-biased circuit module, a voltage regulator circuit module, and a bandgap reference generation circuit module. The output end of the self-biased circuit module is connected to the input end of the voltage regulator circuit module, and the output end of the voltage regulator circuit module is connected to the input end of the bandgap reference generation circuit module, where:

[0007] The self-biased circuit module is used to generate an initial bias current;

[0008] The voltage regulator circuit module is used to detect the deviation of the initial bias current and generate an adjustment signal;

[0009] The bandgap reference generation circuit module is used to adjust the temperature coefficient of the resistor network of the transistor operating current according to the adjustment signal and perform voltage compensation, and output a zero-temperature-drift reference voltage.

[0010] In some embodiments, the self - bias circuit module adopts a cross - coupled structure. The self - bias circuit module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. Among them, the first PMOS transistor and the second PMOS transistor form a current mirror structure of the self - bias circuit module; the first NMOS transistor and the second NMOS transistor form a cross - coupled structure of the self - bias circuit module; the third NMOS transistor and the fourth NMOS transistor form a closed - loop feedback structure of the self - bias circuit module.

[0011] In some embodiments, within the self - bias circuit module, the source of the first PMOS transistor is connected to the source of the second PMOS transistor and is connected to a power signal. The gate of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, and the drain of the third NMOS transistor are connected. The drain of the first PMOS transistor, the drain of the fourth NMOS transistor, the gate of the first NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the second NMOS transistor are connected. The source of the first NMOS transistor is connected to the source of the fourth NMOS transistor and is connected to the voltage - stabilizing circuit module. The source of the second NMOS transistor is connected to the source of the third NMOS transistor and is connected to the voltage - stabilizing circuit module.

[0012] In some embodiments, the voltage - stabilizing circuit module includes a first branch module and a second branch module. The first branch module and the second branch module are symmetric with respect to the self - bias circuit module. Among them, the first branch module includes a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a third resistor. The second branch module includes a third PMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a second resistor, and a fifth resistor.

[0013] In some embodiments, in the first branch module, the source electrodes of the fifth PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and coupled to a power supply voltage. The gate electrodes of the fifth PMOS transistor, the seventh NMOS transistor, the source electrode of the first NMOS transistor, the source electrode of the fourth NMOS transistor, and the second terminal of the first resistor are connected and coupled to the bandgap reference generation circuit module. The drain electrode of the fifth PMOS transistor, the drain electrode of the sixth NMOS transistor, and the drain electrode of the seventh NMOS transistor are connected. The source electrode of the seventh NMOS transistor is connected to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the bandgap reference generation circuit module. The gate electrodes of the sixth NMOS transistor, the drain electrode of the first PMOS transistor, the drain electrode of the fourth NMOS transistor, the gate electrode of the first NMOS transistor, the gate electrode of the fourth NMOS transistor, and the drain electrode of the second NMOS transistor are connected. The source electrode of the sixth NMOS transistor is connected to the first terminal of the first resistor.

[0014] In some embodiments, in the second branch module, the source electrodes of the third PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and coupled to a power supply voltage. The gate electrodes of the third PMOS transistor, the eighth NMOS transistor, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, and the second terminal of the second resistor are connected and coupled to the bandgap reference generation circuit module. The drain electrode of the third PMOS transistor, the drain electrode of the fifth NMOS transistor, and the drain electrode of the eighth NMOS transistor are connected. The source electrode of the fifth NMOS transistor is connected to the first terminal of the second resistor. The gate electrodes of the fifth NMOS transistor, the drain electrode of the second PMOS transistor, the drain electrode of the third NMOS transistor, the gate electrode of the first PMOS transistor, the gate electrode of the second PMOS transistor, and the drain electrode of the first NMOS transistor are connected and coupled to the bandgap reference generation circuit module. The source electrode of the eighth NMOS transistor is connected to the first terminal of the fifth resistor, and the second terminal of the fifth resistor is coupled to the bandgap reference generation circuit module.

[0015] In some embodiments, it further includes generating the adjustment signal by dynamically adjusting the conduction states of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor.

[0016] In some embodiments, the bandgap reference generation circuit module includes a fourth PMOS transistor, a first triode, a second triode, a third triode, a fourth resistor, and a sixth resistor. Among them, the first triode, the second triode, and the third triode are used to generate the temperature coefficient of the resistor network according to the positive temperature coefficient voltage and the negative temperature coefficient voltage.

[0017] In some embodiments, in the bandgap reference generation circuit module, the source of the fourth PMOS transistor is connected to the power supply voltage, the emitter of the first triode is connected to the first end of the fourth resistor, the collector of the first triode, the base of the first triode, the collector of the second triode, the base of the second triode, the collector of the third triode and the base of the third triode are connected and grounded, the emitter of the second triode, the second end of the second resistor, the source of the third NMOS transistor, the source of the second NMOS transistor, the gate of the third PMOS transistor and the gate of the eighth NMOS transistor are connected, the emitter of the third triode is connected to the first end of the sixth resistor, the gate of the fourth PMOS transistor, the gate of the fifth NMOS transistor, the gate of the third NMOS transistor, the drain of the third NMOS transistor, the gate of the second PMOS transistor, the drain of the second PMOS transistor and the drain of the first NMOS transistor are connected, and the second end of the sixth resistor is connected to the drain of the fourth PMOS transistor and outputs signal V BG .

[0018] To achieve the above object, on the other hand, an embodiment of the present application proposes a control method for a low-power bandgap reference circuit, and the control method includes the following steps:

[0019] Obtain an initial bias current;

[0020] Perform deviation detection on the initial bias current to generate an adjustment signal;

[0021] Adjust the temperature coefficient of the resistor network of the triode working current according to the adjustment signal and perform voltage compensation to output a zero-temperature-drift reference voltage.

[0022] The embodiments of the present application at least include the following beneficial effects: The present application provides a low-power bandgap reference circuit and its control method. This solution generates an initial bias current through a self-bias circuit module, thereby eliminating the operational amplifier in the traditional bandgap reference circuit, reducing power consumption and improving the overall energy efficiency of the circuit. Further, the voltage regulator circuit module performs deviation detection on the initial bias current to generate an adjustment signal, and then can dynamically adjust its conduction state, improving the stability of the output voltage. It also enables the voltage regulator circuit module to quickly respond when the load changes, ensuring the constancy of the output voltage, being able to adapt to fluctuations in the input voltage, quickly adjust its own state, and achieve the dual goals of high-efficiency voltage regulation and low power consumption. Finally, the bandgap reference generation circuit module adjusts the temperature coefficient of the resistor network of the triode working current according to the adjustment signal and performs voltage compensation to output a zero-temperature-drift reference voltage, effectively reducing current consumption and improving the energy efficiency of the circuit. Description of the Drawings

[0023] Figure 1It is a schematic structural diagram of a low-power bandgap reference circuit provided by an embodiment of the present application;

[0024] Figure 2 It is a schematic step flow diagram of a control method for a low-power bandgap reference circuit provided by an embodiment of the present application;

[0025] Figure 3 It is a schematic circuit principle diagram provided by an embodiment of the present application.

[0026] Reference numerals: 1, self-biased circuit module; 2, voltage stabilizing circuit module; 3, bandgap reference generation circuit module. Detailed implementation manners

[0027] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0028] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be called the second information, and similarly, the second information can also be called the first information. Depending on the context, as used herein, the words "if", "when" can be interpreted as "when...", "when...", or "in response to a determination".

[0029] The terms "at least one", "multiple", "each", "any one", etc. used in the present application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any one refers to any one of the multiple.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0031] First of all, it should be noted that in the design of analog integrated circuits, the reference source circuit is a key circuit used to provide a stable reference voltage or current for other modules within the chip. The bandgap reference circuit is the most commonly used reference voltage generation circuit, which is favored because it can provide a relatively stable output under process variations, power supply voltage fluctuations, and temperature changes. Its basic principle is to use bipolar transistors of different sizes to generate a voltage difference with a positive temperature coefficient. This voltage difference is converted into a PTAT current through a resistor network and combined with the VBE negative temperature coefficient voltage of another transistor to form a reference voltage with a temperature coefficient close to zero.

[0032] In the related technologies, there are some deficiencies. For example, traditional bandgap reference circuits face various challenges in maintaining the stability and consistency of the output voltage, including output fluctuations caused by input offset voltage, output inconsistency between different chips, and high circuit power consumption, etc., which need to be solved.

[0033] In view of this, in the embodiments of the present application, a low-power bandgap reference circuit is provided. The circuit structure includes three parts: a self-biasing circuit module, a voltage regulation circuit module, and a bandgap reference generation circuit module. Among them, the self-biasing circuit module is connected to the voltage regulation circuit module, and through the bandgap reference generation circuit module, power supply and stable bias current are provided. Further, through a symmetric matching design method, the offset error of the system is effectively reduced, thereby improving the stability and accuracy of the circuit. Compared with the traditional bandgap reference circuit, the combination of the self-biasing circuit and the voltage regulation circuit is adopted to realize an architecture design without the assistance of an operational amplifier. This design idea not only retains high precision but also significantly reduces the overall power consumption of the circuit, meeting the requirements of low-power application scenarios. In addition, by reasonably configuring circuit elements, the self-biasing circuit module and the voltage regulation circuit module ensure the automatic adjustment and balance of current inside the circuit, further improving the temperature stability and response speed of the circuit. The embodiments of the present invention not only solve the problem of dependence on operational amplifiers in traditional bandgap reference circuits but also reduce the power consumption and complexity of the circuit while achieving high-precision reference voltage output.

[0034] Refer to Figure 1 , Figure 1 FIG. Figure 1 is a schematic structural diagram of a low-power bandgap reference circuit provided by an embodiment of the present invention. Refer to

[0035]

[0036] The self-biasing circuit module is used to generate an initial bias current;Specifically, the self - bias circuit module adopts a cross - coupled structure. The self - bias circuit module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. Among them, the first PMOS transistor and the second PMOS transistor form a current mirror structure of the self - bias circuit module, the first NMOS transistor and the second NMOS transistor form a cross - coupled structure of the self - bias circuit module, and the third NMOS transistor and the fourth NMOS transistor form a closed - loop feedback structure of the self - bias circuit module.

[0037] Among them, as Figure 3 shown, in the self - bias circuit module, the source of the first PMOS transistor is connected to the source of the second PMOS transistor and is connected to the power supply signal. The gate of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, and the drain of the third NMOS transistor are connected. The drain of the first PMOS transistor, the drain of the fourth NMOS transistor, the gate of the first NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the second NMOS transistor are connected. The source of the first NMOS transistor is connected to the source of the fourth NMOS transistor and is connected to the voltage - stabilizing circuit module. The source of the second NMOS transistor is connected to the source of the third NMOS transistor and is connected to the voltage - stabilizing circuit module.

[0038] In this embodiment, the self - bias circuit module includes MOS transistors MP1, MP2, MN1, MN2, MN3, and MN4. The source of MOS transistor MP1 and the source of MOS transistor MP2 are connected to the power supply VDD; the gate of MOS transistor MP2 is simultaneously connected to the gate of MOS transistor MP1 and the drain of MOS transistor MP2. The drains of MOS transistors MP1 and MP2 are respectively connected to the drains of MOS transistors MN4 and MN3. The gate of MOS transistor MN1 is simultaneously connected to the gate and the drain of MOS transistor MN4. The gate of MOS transistor MN2 is simultaneously connected to the gate and the drain of MOS transistor MN3. The drain of MOS transistor MN1 is connected to the drain of MOS transistor MN3. The drain of MOS transistor MN2 is connected to the drain of MOS transistor MN4. The sources of MOS transistors MN1 and MN4 are both connected to one end of resistor R4 and resistor R1. The sources of MOS transistors MN2 and MN3 are connected to one end of resistor R2 and the emitter of transistor Q2.

[0039] The voltage - stabilizing circuit module is used to detect the deviation of the initial bias current and generate an adjustment signal;

[0040] Specifically, the voltage stabilizing circuit module includes a first branch module and a second branch module. The first branch module and the second branch module are symmetric about the self - bias circuit module. Among them, the first branch module includes a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a first resistor R1, and a third resistor R3. The second branch module includes a third PMOS transistor MP3, a fifth NMOS transistor MN5, an eighth NMOS transistor MN8, a second resistor R2, and a fifth resistor R5.

[0041] The regulation signal is generated by dynamically adjusting the conduction states of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor.

[0042] Among them, as Figure 3 shown, in the first branch module, the source electrodes of the fifth PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and connected to the power supply voltage. The gate electrode of the fifth PMOS transistor, the gate electrode of the seventh NMOS transistor, the source electrode of the first NMOS transistor, the source electrode of the fourth NMOS transistor, and the second end of the first resistor are connected and connected to the band - gap reference generation circuit module. The drain electrode of the fifth PMOS transistor, the drain electrode of the sixth NMOS transistor, and the drain electrode of the seventh NMOS transistor are connected. The source electrode of the seventh NMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the band - gap reference generation circuit module. The gate electrode of the sixth NMOS transistor, the drain electrode of the first PMOS transistor, the drain electrode of the fourth NMOS transistor, the gate electrode of the first NMOS transistor, the gate electrode of the fourth NMOS transistor, and the drain electrode of the second NMOS transistor are connected. The source electrode of the sixth NMOS transistor is connected to the first end of the first resistor.

[0043] Furthermore, as Figure 3 shown, in the second branch module, the source electrodes of the third PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and connected to the power supply voltage. The gate electrode of the third PMOS transistor, the gate electrode of the eighth NMOS transistor, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, and the second end of the second resistor are connected and connected to the band - gap reference generation circuit module. The drain electrode of the third PMOS transistor, the drain electrode of the fifth NMOS transistor, and the drain electrode of the eighth NMOS transistor are connected. The source electrode of the fifth NMOS transistor is connected to the first end of the second resistor. The gate electrode of the fifth NMOS transistor, the drain electrode of the second PMOS transistor, the drain electrode of the third NMOS transistor, the gate electrode of the first PMOS transistor, the gate electrode of the second PMOS transistor, and the drain electrode of the first NMOS transistor are connected and connected to the band - gap reference generation circuit module. The source electrode of the eighth NMOS transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the band - gap reference generation circuit module.

[0044] In this embodiment, the voltage stabilizing circuit includes MOS transistor MN5, MOS transistor MN6, MOS transistor MP3, MOS transistor MP5, MOS transistor MN7, MOS transistor MN8, resistor R1, resistor R2, resistor R3, and resistor R5. The gates of MOS transistor MP5 and MOS transistor MN7 are both connected to the source of MOS transistor MN4. The gates of MOS transistor MP3 and MOS transistor MN8 are both connected to the source of MOS transistor MN3. The sources of MOS transistor MP5 and MOS transistor MP3 are both connected to power supply VDD. The drains of MOS transistor MP5 and MOS transistor MN7 are both connected to the drain of MOS transistor MN6. The drains of MOS transistor MP3 and MOS transistor MN8 are both connected to the drain of MOS transistor MN5. The gate of MOS transistor MN6 is connected to the drain of MOS transistor MN4. The gate of MOS transistor MN5 is connected to the drain of MOS transistor MN3 and the gate of MOS transistor MP4. The source of MOS transistor MN6 is connected to one end of resistor R1. The source of MOS transistor MN5 is connected to one end of resistor R2.

[0045] The bandgap reference generating circuit module is used to adjust the temperature coefficient of the resistor network of the triode operating current according to the adjustment signal and perform voltage compensation, and output a zero-temperature-drift reference voltage.

[0046] Specifically, the bandgap reference generating circuit module includes fourth PMOS transistor MP4, first triode Q1, second triode Q2, third triode Q3, fourth resistor R4, and sixth resistor R6. Among them, the first triode, the second triode, and the third triode are used to generate the temperature coefficient of the resistor network according to the positive temperature coefficient voltage and the negative temperature coefficient voltage.

[0047] Among them, as Figure 3 shown, in the bandgap reference generating circuit module, the source of the fourth PMOS transistor is connected to the power supply voltage. The emitter of the first triode is connected to the first end of the fourth resistor. The collector, base of the first triode, collector, base of the second triode, collector, and base of the third triode are connected and grounded. The emitter of the second triode, the second end of the second resistor, the source of the third NMOS transistor, the source of the second NMOS transistor, the gate of the third PMOS transistor, and the gate of the eighth NMOS transistor are connected. The emitter of the third triode is connected to the first end of the sixth resistor. The gate of the fourth PMOS transistor, the gate of the fifth NMOS transistor, the gate of the third NMOS transistor, the drain of the third NMOS transistor, the gate of the second PMOS transistor, the drain of the second PMOS transistor, and the drain of the first NMOS transistor are connected. The second end of the sixth resistor is connected to the drain of the fourth PMOS transistor and outputs signal V BG .

[0048] In this embodiment, the bandgap reference voltage generation circuit includes a triode Q1, a triode Q2, a triode Q3, a MOS transistor MP4, a resistor R4, and a resistor R6. The source of the MOS transistor MP4 is connected to the power supply VDD. The emitter of the triode Q1 is connected to one end of the resistor R4. The collector, base of the triode Q1, the collector, base of the triode Q2, the collector, base of the triode Q3 are all grounded. The emitter of the triode Q2 is connected to one end of the resistor R2, the source of the MOS transistor MN3, the source of the MOS transistor MN2, the gate of the MOS transistor MP3, and the gate of the MOS transistor MN8. The emitter of the triode Q3 is connected to one end of the resistor R6. The gate of the MOS transistor MP4 is connected to the gate of the MOS transistor MN5, the gate of the MOS transistor MN3, the drain of the MOS transistor MN3, the gate of the MOS transistor MP2, the drain of the MOS transistor MP2, and the drain of the MOS transistor MN1. The other end of the resistor R6 and the drain of the MOS transistor MP4 output the signal V BG .

[0049] In summary, the circuit of the embodiment of the present invention includes a self - biasing circuit module, a voltage - stabilizing circuit module, and a bandgap reference generation circuit module. Among them, the self - biasing circuit module is used to establish a stable bias current through the current mirror composed of the MOS transistors MP1 and MP2 and the cross - coupled feedback loop of the MOS transistors MN1, MN2, MN3, and MN4, eliminating the voltage offset error in the traditional architecture. The voltage - stabilizing circuit is used to detect the bias current deviation through the inverse ratio transistor inverter and dynamically adjust the conduction states of the MOS transistors MN5, MN6, MN7, and MN8 to maintain current balance. The bandgap reference generation circuit module is used to integrate the positive temperature coefficient voltage and the negative temperature coefficient voltage of the triodes Q1, Q2, and Q3, and generate a zero - temperature - drift reference voltage after temperature compensation by the resistor network.

[0050] Please refer to Figure 2 , the embodiment of the present application also provides a control method for a low - power bandgap reference circuit, which can implement the above - mentioned low - power bandgap reference circuit. The control method includes the following steps:

[0051] S100. Obtain an initial bias current;

[0052] In some specific embodiments, the self - bias circuit adopts a cross - coupled structure. Among them, PMOS transistors MP1 and MP2 act as a current mirror to ensure equal currents on both sides, thus achieving the balanced and stable operation of the circuit. Specifically, the drains of MP1 and MP2 share the same current through the current - mirror structure, thereby maintaining the circuit symmetry and working stability. MOS transistors MN1 and MN2 form a cross - coupled structure, jointly forming a closed - loop feedback system with MP1 and MP2. This feedback system can provide the ability of adaptive adjustment during the circuit operation, effectively improving the dynamic response characteristics of the circuit.

[0053] In the case where the drain voltages of MP1 and MP2 are mismatched, the cross - coupled MN1 and MN2 can quickly sense the voltage difference and achieve rapid current compensation by adjusting their conduction states, restoring the current balance on both sides. This design method not only improves the matching accuracy of the circuit but also ensures that the self - bias circuit module can quickly respond to voltage or current fluctuations during operation, reducing the occurrence of voltage drift, improving the stability and output accuracy of the overall circuit. In addition, while adjusting the current, the cross - coupled structure avoids the high - power - consumption problem that may be brought in traditional amplifier designs, thus achieving the goal of low power consumption.

[0054] S200. Detect the deviation of the initial bias current and generate an adjustment signal;

[0055] In some specific embodiments, in the voltage - regulation circuit part, this module includes an NMOS transistor, an inverter, and two resistors, forming an effective voltage - regulation mechanism that can cope with the impact of power - supply voltage changes on the circuit performance. Specifically, in the design of the voltage - regulation circuit module, the input terminal of the inverter is connected to the source of MOS transistor MN4 or MN3. Such a connection method can ensure that the output terminal of the inverter remains at a high level. When the input of the inverter is configured in this state, the gate - source voltage of PMOS transistors MP5 and MP3 is much larger than their drain - source voltage, causing these PMOS transistors to be in the deep linear region. In this state, the drain - source current of the PMOS transistor is extremely small, thus greatly reducing the overall power consumption of the circuit.

[0056] To further ensure the stable output of the voltage - regulation circuit module, in the design, the gates of MN5 and MN6 are used to detect the drain potentials of MP1 and MP2. Through this design, the voltage - regulation circuit module can dynamically adjust its conduction state to control the emitter currents flowing through Q1 and Q2 to be equal. This not only improves the stability of the output voltage but also enables the voltage - regulation circuit module to quickly respond when the load changes, ensuring the constancy of the output voltage. This voltage - detection and feedback - control mechanism of MN5 and MN6 enables the voltage - regulation circuit module to adapt to the fluctuations of the input voltage, quickly adjust its own state, and achieve the dual goals of high - efficiency voltage regulation and low power consumption.

[0057] Generally speaking, the overall structure of the voltage stabilizing circuit module achieves efficient voltage stabilizing performance by reasonably configuring the current path and voltage regulating unit, while reducing the power consumption of the circuit. This circuit design can maintain a stable output under different working conditions and is suitable for application scenarios with high power consumption requirements.

[0058] S300: Adjust the temperature coefficient of the resistance network for the working current of the triode according to the adjustment signal and perform voltage compensation to output a zero-temperature-drift reference voltage;

[0059] In summary, in the embodiment of the present invention, an initial bias current is established through the cross-coupled PMOS current mirror and NMOS feedback loop of the self-biased circuit module. The initial bias current deviation is detected by the inverse ratio transistor inverter of the voltage stabilizing circuit to generate an adjustment signal. The working current of the triode is dynamically balanced according to the adjustment signal by the bandgap reference generation circuit module, and a zero-temperature-drift reference voltage is generated by the resistance network temperature coefficient compensation mechanism. The embodiment of the present invention utilizes the self-biased circuit, thereby eliminating the operational amplifier in the traditional bandgap reference circuit, reducing power consumption and improving the overall energy efficiency of the circuit. Secondly, since the voltage stabilizing circuit only needs to finely adjust the current, in order to maintain the input current at a low level to reduce power consumption and maintain a stable output, an inverse ratio transistor inverter with a large channel length is used as the input of the voltage stabilizing circuit module. This design choice effectively reduces current consumption, improves the energy efficiency of the circuit, and further optimizes the overall power consumption.

[0060] It can be understood that the content in the above method embodiments is applicable to this circuit embodiment. The functions specifically implemented by this circuit embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0061] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A low-power bandgap reference circuit, characterized in that, The circuit includes a self - biasing circuit module, a voltage - stabilizing circuit module, and a bandgap reference generating circuit module. The output terminal of the self - biasing circuit module is connected to the input terminal of the voltage - stabilizing circuit module, and the output terminal of the voltage - stabilizing circuit module is connected to the input terminal of the bandgap reference generating circuit module, where: The self - biasing circuit module is used to generate an initial bias current; The voltage - stabilizing circuit module is used to detect the deviation of the initial bias current and generate an adjustment signal; The bandgap reference generating circuit module is used to adjust the temperature coefficient of the resistor network of the triode operating current according to the adjustment signal and perform voltage compensation, and output a zero - temperature - drift reference voltage.

2. The circuit according to claim 1, wherein The self - biasing circuit module adopts a cross - coupled structure. The self - biasing circuit module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. Among them, the first PMOS transistor and the second PMOS transistor form a current mirror structure of the self - biasing circuit module, the first NMOS transistor and the second NMOS transistor form a cross - coupled structure of the self - biasing circuit module, and the third NMOS transistor and the fourth NMOS transistor form a closed - loop feedback structure of the self - biasing circuit module.

3. The circuit according to claim 2, wherein In the self - biasing circuit module, the source electrodes of the first PMOS transistor and the second PMOS transistor are connected and connected to a power supply signal. The gate of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, and the drain of the third NMOS transistor are connected. The drain of the first PMOS transistor, the drain of the fourth NMOS transistor, the gate of the first NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the second NMOS transistor are connected. The source electrode of the first NMOS transistor and the source electrode of the fourth NMOS transistor are connected and connected to the voltage - stabilizing circuit module. The source electrode of the second NMOS transistor and the source electrode of the third NMOS transistor are connected and connected to the voltage - stabilizing circuit module.

4. The circuit according to claim 2, wherein The voltage - stabilizing circuit module includes a first branch module and a second branch module. The first branch module and the second branch module are symmetric with respect to the self - biasing circuit module. Among them, the first branch module includes a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a third resistor. The second branch module includes a third PMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a second resistor, and a fifth resistor.

5. The circuit according to claim 4, wherein In the first branch module, the sources of the fifth PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and connected to the power supply voltage. The gates of the fifth PMOS transistor, the seventh NMOS transistor, the source of the first NMOS transistor, the source of the fourth NMOS transistor, and the second end of the first resistor are connected and connected to the bandgap reference generation circuit module. The drains of the fifth PMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are connected. The source of the seventh NMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the bandgap reference generation circuit module. The gates of the sixth NMOS transistor, the drain of the first PMOS transistor, the drain of the fourth NMOS transistor, the gate of the first NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the second NMOS transistor are connected. The source of the sixth NMOS transistor is connected to the first end of the first resistor.

6. The circuit according to claim 4, characterized in that, In the second branch module, the sources of the third PMOS transistor, the first PMOS transistor, and the second PMOS transistor are connected and connected to the power supply voltage. The gates of the third PMOS transistor, the eighth NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor, and the second end of the second resistor are connected and connected to the bandgap reference generation circuit module. The drains of the third PMOS transistor, the fifth NMOS transistor, and the eighth NMOS transistor are connected. The source of the fifth NMOS transistor is connected to the first end of the second resistor. The gates of the fifth NMOS transistor, the drain of the second PMOS transistor, the drain of the third NMOS transistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected and connected to the bandgap reference generation circuit module. The source of the eighth NMOS transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the bandgap reference generation circuit module.

7. The circuit according to claim 4, wherein It further includes generating the adjustment signal by dynamically adjusting the conduction states of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor.

8. The circuit according to claim 4, characterized in that, The bandgap reference generation circuit module includes a fourth PMOS transistor, a first triode, a second triode, a third triode, a fourth resistor, and a sixth resistor. Among them, the first triode, the second triode, and the third triode are used to generate the resistance network temperature coefficient according to the positive temperature coefficient voltage and the negative temperature coefficient voltage.

9. The circuit according to claim 8, wherein In the bandgap reference generation circuit module, the source of the fourth PMOS transistor is connected to the power supply voltage, the emitter of the first triode is connected to the first end of the fourth resistor, the collector of the first triode, the base of the first triode, the collector of the second triode, the base of the second triode, the collector of the third triode and the base of the third triode are connected and grounded, the emitter of the second triode, the second end of the second resistor, the source of the third NMOS transistor, the source of the second NMOS transistor, the gate of the third PMOS transistor and the gate of the eighth NMOS transistor are connected, the emitter of the third triode is connected to the first end of the sixth resistor, the gate of the fourth PMOS transistor, the gate of the fifth NMOS transistor, the gate of the third NMOS transistor, the drain of the third NMOS transistor, the gate of the second PMOS transistor, the drain of the second PMOS transistor and the drain of the first NMOS transistor are connected, and the second end of the sixth resistor is connected to the drain of the fourth PMOS transistor and outputs a signal V BG .

10. A control method for a low-power bandgap reference circuit, characterized in that, The control method includes the following steps: Obtain the initial bias current; Perform deviation detection on the initial bias current to generate an adjustment signal; Adjust the resistance network temperature coefficient of the triode operating current according to the adjustment signal and perform voltage compensation to output a zero-temperature-drift reference voltage.

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